Driving compensation circuit of pixel circuit, display panel and display device

Abstract

The present disclosure discloses a driving compensation circuit of a pixel circuit, and a display panel and a display device. The driving compensation circuit of the pixel circuit comprises a comparison sub-circuit electrically connected to a first power supply signal end, a first power supply sensing end and a reset signal end or a reset sensing end and the reset signal end, configured to compare and amplify the potential of the first power supply signal end with the potential of the first power supply sensing end or compare and amplify the potential of the reset signal end with the potential of the reset sensing end, and then add the signal of the reset signal end to serve as a first reset signal for inputting into a first reset signal end of the pixel circuit. The driving compensation circuit of the present embodiment provides a comparison sub-circuit, compensates for the changes of the power supply signal or the reset signal by dynamically adjusting the potential of the first reset signal, and reduces the brightness unevenness and low-frequency flicker caused by the signal line impedance.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving compensation circuit for a pixel circuit, a display panel, and a display device. Background Technology

[0002] Current display panel display driving technology, when using a driving method that separates data writing and threshold compensation, often suffers from uneven brightness and low-frequency flicker. Summary of the Invention

[0003] To address at least one of the aforementioned problems, a first aspect of this disclosure provides a driving compensation circuit for a pixel circuit, comprising: The comparator circuit is electrically connected to the first power signal terminal, the first power sensing terminal, and the reset signal terminal, or electrically connected to the reset sensing terminal and the reset signal terminal. It is configured to compare and amplify the potential of the first power signal terminal with the potential of the first power sensing terminal, or compare and amplify the potential of the reset signal terminal with the potential of the reset sensing terminal, and then add the result to the signal of the reset signal terminal to obtain the first reset signal for connection to the first reset signal terminal of the pixel circuit.

[0004] Optionally, the comparator circuit includes: a first comparator circuit and a second comparator circuit; The first comparator circuit includes a first operational amplifier, a first input terminal of which is electrically connected to a first power signal terminal, a second input terminal of which is electrically connected to a first power sensing terminal, and an output terminal of which is electrically connected to the first input terminal of the second comparator circuit, configured to compare the potential of the first power sensing terminal with the potential of the first power signal terminal to generate a comparison value. The second comparator circuit includes a second operational amplifier. The first input terminal of the second operational amplifier is further electrically connected to the reset signal terminal, the second input terminal is electrically connected to the ground terminal, and the output terminal is electrically connected to the first reset signal terminal of the pixel circuit. It is configured to amplify the comparison value and then add it to the potential of the reset signal terminal to serve as the first reset signal input to the first reset signal terminal of the pixel circuit.

[0005] Optionally, the first comparator circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor, all with the same resistance value. The first input terminal of the first operational amplifier is electrically connected to the first power signal terminal via the first resistor and to the ground terminal via the second resistor. The second input terminal is electrically connected to the first power sensing terminal via the third resistor. The first end of the fourth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the first operational amplifier. The second comparator circuit further includes: a fifth resistor and a sixth resistor with the same resistance value, and a seventh resistor and an eighth resistor with the same resistance value. The first input terminal of the second operational amplifier is electrically connected to the reset signal terminal via the fifth resistor and electrically connected to the output terminal of the first operational amplifier via the seventh resistor. The second input terminal is electrically connected to the ground terminal via the sixth resistor. The first end of the eighth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the second operational amplifier and serves as the output terminal of the second comparator circuit.

[0006] Optionally, the transistor in the pixel circuit is a P-type transistor, the first input terminal is a non-inverting input terminal, the second input terminal is an inverting input terminal, and the potential received by the first power signal terminal is a high-level signal.

[0007] Optionally, the first comparator circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor, all with the same resistance value. The second input terminal of the first operational amplifier is electrically connected to the first power sensing terminal via the first resistor and to the ground terminal via the second resistor. The first input terminal is electrically connected to the first power signal terminal via the third resistor. The first end of the fourth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the first operational amplifier. The second comparator circuit further includes: a fifth resistor and a sixth resistor with the same resistance value, and a seventh resistor and an eighth resistor with the same resistance value. The first input terminal of the second operational amplifier is electrically connected to the reset signal terminal via the fifth resistor and electrically connected to the output terminal of the first operational amplifier via the seventh resistor. The second input terminal is electrically connected to the ground terminal via the sixth resistor. The first end of the eighth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the second operational amplifier and serves as the output terminal of the second comparator circuit.

[0008] Optionally, the transistor in the pixel circuit is an N-type transistor, the first input terminal of the first operational amplifier is an inverting input terminal, the second input terminal is a non-inverting input terminal, the first input terminal of the second operational amplifier is a non-inverting input terminal, the second input terminal is an inverting input terminal, and the potential received by the first power supply signal terminal is a low-level signal.

[0009] Optionally, the comparator circuit includes: a third operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor. The first input terminal of the third operational amplifier is electrically connected to the reset signal terminal via the ninth resistor, and the second input terminal is electrically connected to the reset sensing terminal via the eleventh resistor. The first end of the tenth resistor is electrically connected to the first input terminal, and the second end is electrically connected to the ground terminal. The first end of the twelfth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the third operational amplifier. The output terminal of the third operational amplifier is connected to the first reset signal terminal of the pixel circuit.

[0010] Optionally, the drive compensation circuit is electrically connected to the first power signal terminal, the first power sensing terminal, and the reset signal terminal, with the first power signal terminal being closer to the bonding area pin that provides the power signal than the first sensing signal terminal.

[0011] Optionally, the drive compensation circuit is electrically connected to the reset sensing terminal and the reset signal terminal, with the reset sensing terminal being closer to the bonding area pin that provides the reset signal than the reset signal terminal.

[0012] Optionally, the drive compensation circuit further includes: a first transistor and a second transistor, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor; The first electrode of the first transistor is electrically connected to the power supply threshold terminal, the second electrode is electrically connected to the first electrode of the second transistor and serves as the output terminal of the second comparator circuit, the control electrode is electrically connected to the output terminal of the second operational amplifier, the second electrode of the second transistor is electrically connected to the ground terminal, and the control electrode is electrically connected to the output terminal of the second operational amplifier.

[0013] A second aspect of this disclosure provides a display panel, including: a display area and a non-display area located around the display area, the non-display area including a driving proximal end for setting bonding area pins and a driving distal end located on a side opposite to the driving proximal end; The display panel also includes: A first power signal line extending at least partially around the display area; a plurality of first power traces and a plurality of reset signal lines extending in the direction from the drive proximal end to the drive distal end; The drive compensation circuit described above is disposed in the non-display area; and At least one sensing connection line, The comparator sub-circuit is electrically connected to a first power signal terminal, a first power sensing terminal, and a reset signal terminal. The first power sensing terminal is electrically connected via the sensing connection line to the first power signal line or the portion of the first power trace located at the far end of the drive, or The comparator circuit is electrically connected to the reset sensing terminal and the reset signal terminal, and the reset sensing terminal is electrically connected to the reset signal line via the sensing connection line.

[0014] A third aspect of this disclosure provides a display device including the display panel described above.

[0015] The beneficial effects of this disclosure are as follows: This disclosure addresses existing problems by providing a driving compensation circuit for a pixel circuit, a display panel, and a display device. By providing a comparator circuit, the potential of the first reset signal is dynamically adjusted using the change value between the sensed power supply signal or reset signal and the driving signal, thereby achieving dynamic compensation. This reduces brightness unevenness and low-frequency flicker caused by signal line impedance and has broad application prospects. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic circuit diagram showing the discrete pixel circuitry of the display panel; Figure 2 Show Figure 1 A schematic timing diagram of the discrete pixel circuit shown; Figure 3 A schematic block diagram of a drive compensation circuit for a pixel circuit according to an embodiment of the present disclosure is shown. Figure 4 A schematic circuit diagram of a drive compensation circuit for a pixel circuit according to an embodiment of the present disclosure is shown. Figure 5 A schematic circuit diagram of a drive compensation circuit for a pixel circuit according to another embodiment of the present disclosure is shown. Figure 6 A schematic block diagram of a drive compensation circuit for a pixel circuit according to another embodiment of the present disclosure is shown. Figure 7 A schematic circuit diagram of a drive compensation circuit for a pixel circuit according to another embodiment of the present disclosure is shown. Figure 8 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown; Figure 9 A schematic diagram of a display panel according to another embodiment of the present disclosure is shown. Detailed Implementation

[0018] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0020] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0021] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, exemplarily, the gate of the transistor is called the control electrode. When the transistor is an N-type transistor, the first electrode of the transistor is called the drain, and the second electrode is called the source. When the transistor is a P-type transistor, the first electrode of the transistor is called the source, and the second electrode is called the drain.

[0022] Reference Figure 1 and Figure 2 As shown, Figure 1 This diagram illustrates a schematic circuit diagram of a current discrete display driver pixel circuit. Figure 2 This is a timing diagram for the relevant ports. Combined with... Figure 1-2As can be seen, transistor T3 in the pixel circuit is a driving transistor used to generate the driving current for driving the light-emitting unit D to emit light. In the first stage S1, the signal terminal Reset_P and the control terminal AZ are at active levels, transistors T1 and T2 are turned on, and the signal at the signal terminal Vinit1 is used to reset the first node N1. In the second stage S2, the control terminals AZ and EM1 are at active levels, transistors T2, T5, T9, and T10 are turned on, the power signal Vdd of the high power signal terminal VDD is written to the fourth node N4 and the second node N2, driving transistor T3 to turn on, and the signal Vdd of the high voltage signal terminal VDD is used to charge the first node N1. When the first node N1 is charged to VN1 = Vdd + Vth, charging stops, where Vth is the threshold voltage of transistor T3. This stage can be called the threshold compensation stage. In the third stage S3, the control terminal Gate_P is at active level, transistor T4 is turned on, and the data signal at the data signal terminal Vdata is transmitted. The data is transmitted to the third node N3, whose potential is Vdata. The potential of the first node N1 is VN1 = Vdd + Vth + Vdata - Vref1. It can be seen that the data signal Vata is transmitted to the first node N1 using the coupling effect of capacitors C1 and C2; this stage can be called the data writing stage. In the fourth stage S4, the control terminal Reset_P is active, transistors T6 and T8 are turned on, and the signals Vinit2 and Vinit3 are used to reset the fifth node N5 and the sixth node N6. In the fifth stage S5, the control terminals EM1 and EM2 are active, forming a path from the high power supply signal terminal VDD through the light-emitting unit D to the low power supply terminal VSS. The driving current generated by the driving transistor T3 drives the light-emitting unit D to emit light. The driving current Ids generated by the driving transistor T3 is 0.5K × (Vgs - Vth). 2 =0.5K×(Vdd1+Vth+Vdata-Vref1-Vdd2-Vth) 2 =0.5K×(Vdd1+Vdata-Vref1-Vdd2) 2 This stage is also known as the light-emitting stage. Here, Vdd1 represents the signal transmitted to the high power supply signal terminal of node N1 during the second stage, and Vdd2 represents the signal coupled to the high power supply signal terminal of node N1 during the light-emitting stage.

[0023] As can be seen, when the high power supply signal terminal VDD experiences a voltage drop due to the influence of trace impedance during the light-emitting stage, the signal cannot be canceled out, thus affecting the driving current that drives the light emission. Because the data signal is directly driven by the display driver chip SDIC for the light-emitting unit, the data signal at different locations is relatively stable. However, since the high power supply signal terminal VDD of the pixel circuit within the entire display panel needs to be powered through the power line, there is a gradient voltage drop due to the line impedance in the power supply network. Therefore, the potential of the display panel near and far from the signal input terminal is different, resulting in different driving currents at the near and far ends, thus causing differences in brightness. Further research revealed a voltage trench effect between the reset voltage Vref1 and the high power supply signal Vdd. Specifically, when there is a difference between the power input voltage and the actual voltage in the plane, the actual reset voltage Vref1 = Vref(driving voltage) × (1 - η·ΔVdd), where η typically ranges from 0.15 to 0.3, and this parameter is related to the fabrication process. Therefore, when the high voltage signals Vdd at the near and far ends are different, the reset voltage Vref1 at the near and far ends will also be different. The coupling relationship between voltages increases the impact of the impedance voltage drop of the high voltage signal Vdd on brightness differences. Furthermore, if the potentials of the high power supply signal VDD input to different display signal terminals in the pixel circuit of the same light-emitting unit are different, flicker will occur.

[0024] To address any of the above problems, this disclosure provides a driving compensation circuit for a pixel circuit, comprising: The comparator circuit is electrically connected to the first power signal terminal, the first power sensing terminal, and the reset signal terminal, or electrically connected to the reset sensing terminal and the reset signal terminal. It is configured to compare and amplify the potential of the first power signal terminal with the potential of the first power sensing terminal, or compare and amplify the potential of the reset signal terminal with the potential of the reset sensing terminal, and then add the result to the signal of the reset signal terminal to obtain the first reset signal for connection to the first reset signal terminal of the pixel circuit.

[0025] In this embodiment, by providing a comparator circuit, the potential of the first reset signal is dynamically adjusted using the change value between the sensed power signal or reset signal and the drive signal, thereby achieving dynamic compensation and reducing the uneven brightness and low-frequency flicker caused by signal line impedance.

[0026] To illustrate the structure and function of the pixel circuits in the embodiments of this disclosure in detail, the following description is provided with reference to specific examples.

[0027] Reference Figure 3 As shown, the driving compensation circuit of the pixel circuit provided in this embodiment includes: a comparator circuit 10.

[0028] The comparator circuit 10 is electrically connected to the first power signal terminal ELVDD_PCB, the first power sensing terminal ELVDD_Sens, and the reset signal terminal Vref_SDIC. It is configured to compare and amplify the potential of the first power signal terminal ELVDD_PCB with the potential of the first power sensing terminal ELVDD_Sens, and then add the result to the signal of the reset signal terminal Vref_SDIC to obtain the first reset signal, which is used to access the first reset signal terminal Vref of the pixel circuit.

[0029] Here, the first power signal terminal ELVDD_PCB and the first power sensing terminal ELVDD_Sens represent power signal terminals located in different areas of the near and far regions of the display panel, respectively. The signal at the first power signal terminal ELVDD_PCB can represent a power signal directly from the power supply terminal of the display panel. For example, this power signal is typically provided by a power management module on a printed circuit board (PCB) flexibly connected to the display panel and introduced to the display panel through bonding area pins. The first power sensing terminal ELVDD_Sens can be a sensing signal terminal from the far region or at a certain distance from the near region; it is used to sample power signals on the power signal line located away from the near region. The reset signal terminal Vref_SDIC represents a signal terminal directly electrically connected to the display driver chip SDIC, and this signal terminal is also located in the near region.

[0030] In this article, the near-end region refers to the area in the non-display area of ​​the display panel that is close to the display driver chip SDIC or the bonding pin, while the far-end region refers to the area in the non-display area of ​​the display panel that is far from the display driver chip SDIC or the side that is close to the bonding pin.

[0031] In a specific example, refer to Figure 4 As shown, the comparator circuit includes: a first comparator circuit 101 and a second comparator circuit 102.

[0032] The first comparator circuit 101 includes a first operational amplifier A1, the first input terminal of which is electrically connected to the first power signal terminal ELVDD_PCB, the second input terminal of which is electrically connected to the first power sensing terminal ELVDD_Sens, and the output terminal of which is electrically connected to the first input terminal of the second comparator circuit 102. It is configured to compare the potential of the first power sensing terminal ELVDD_Sens with the potential of the first power signal terminal ELVDD_PCB to generate a comparison value.

[0033] In this example, the first comparator circuit 101 is used to receive the far-end potential and the near-end potential of the first power signal line, and the sensed far-end potential and the near-end potential are compared to generate a comparison value.

[0034] Specifically, the first comparator circuit 101 further includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth circuit R4 with the same resistance value. The first input terminal of the first operational amplifier A1 is electrically connected to the first power signal terminal ELVDD_PCB via the first resistor R1 and electrically connected to the ground terminal GND via the second resistor R2. The second input terminal is electrically connected to the first power sensing terminal ELVDD_Sens via the third resistor R3. The first end of the fourth resistor R4 is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the first operational amplifier A1.

[0035] In this example, the pixel circuit uses P-type transistors, with the first input being a positive input ("+") and the second input being a negative input ("-"). The signal connected to the first power signal terminal ELVDD_PCB is a high-level signal. Utilizing the virtual short and virtual open principles of operational amplifiers, since the resistances of the first resistor R1, second resistor R2, third resistor R3, and fourth resistor R4 are all equal, the first comparator circuit 101 constitutes a subtractor. The output ΔV of the first comparator circuit 101 is ΔV = ELVDD_PCB - ELVDD_Sens. That is, the first comparator circuit 101 performs the operation of subtracting the signal connected to the first power sensing terminal ELVDD_Sens from the signal connected to the first power signal terminal ELVDD_PCB. Because the signal connected to the first power signal terminal ELVDD_PCB is a high-level signal, the difference is positive. In this paper, for ease of understanding, the signals connected to the first power signal terminal ELVDD_PCB and the signals connected to the first power sensing terminal ELVDD_Sens are represented by their respective port symbols.

[0036] The second comparator circuit 102 includes a second operational amplifier A2. The first input terminal of the second operational amplifier A2 is further electrically connected to the reset signal terminal Vref_SDIC, the second input terminal is electrically connected to the ground terminal GND, and the output terminal is electrically connected to the first reset signal terminal Vref of the pixel circuit. It is configured to amplify the above comparison value and then add it to the potential of the reset signal terminal Vref_SDIC to serve as the first reset signal input to the first reset signal terminal Vref of the pixel circuit.

[0037] In this example, the difference between the far end potential and the near end potential of the first power signal line is further amplified by the second comparator circuit 102, and then used as the dynamic compensation value of the reset signal terminal Vref_SDIC of the display driver chip. The dynamic compensation value is added to the original signal from the reset signal terminal Vref_SDIC to obtain the final compensated first reset signal.

[0038] Specifically, the second comparator circuit 102 includes: a second operational amplifier A2, a fifth resistor R5 and a sixth resistor R6 with the same resistance value, and a seventh resistor R7 and an eighth resistor R8 with the same resistance value. The first input terminal of the second operational amplifier A2 is electrically connected to the reset signal terminal Vref_SDIC via the fifth resistor R5 and electrically connected to the output terminal of the first operational amplifier A1 via the seventh resistor R7. The second input terminal is electrically connected to the ground terminal GND via the sixth resistor R6. The first end of the eighth resistor R8 is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the second operational amplifier A2 and also serves as the output terminal of the second comparator circuit 102.

[0039] Since the pixel circuit uses P-type transistors, in this example, the first input terminal of the second comparator circuit 102 remains the positive input terminal "+", and the second input terminal remains the inverting input terminal "-". Utilizing the virtual short and virtual open principles of operational amplifiers, the second comparator circuit 102 amplifies and adds the signals input to the first and second input terminals proportionally. This utilizes the coupling relationship between the reset signal Vref1 and the power supply signal Vdd to establish negative feedback compensation of the reset signal Vref1 on the power supply signal Vdd.

[0040] Specifically, by setting the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 to be equal, and the resistance values ​​of the seventh resistor R7 and the eighth resistor R8 to be equal, assuming R5=R6=a and R7=R8=b, the output Vref1 of the second comparator circuit 102 is Vref1=SDIC_Vref+b / a×(RELVDD_PCB-ELVDD_Sens). In this paper, for ease of understanding, the signals connected to the first power signal terminal ELVDD_PCB, the first power sensing terminal ELVDD_Sens, and the reset signal terminal SDIC_Vref are represented by their respective port symbols.

[0041] By properly setting the scaling factor b / a, the first reset signal Vref1 output by the final comparator circuit can compensate for the coupling effect of the signal itself at the first reset signal terminal in the pixel circuit caused by the change in the power supply signal Vdd, and also cancel the effect of the difference in the change between the far and near ends of the power supply signal Vdd. The value of the scaling factor b / a depends on the material, width, and distance between the near and far ends of the first power supply signal line providing the power supply signal; its specific value can be set through simulation.

[0042] It should be noted that in this example, setting the fifth resistor R5 and the sixth resistor R6 to have equal resistance values, and the seventh resistor R7 and the eighth resistor R8 to have equal resistance values, makes it relatively easy to obtain the required scaling factor. However, this is not intended to be limiting. Other resistor relationships should also be covered by this disclosure, as long as the signal at the reset signal terminal SDIC_Vref and the ΔV amplified according to the scaling factor can be obtained. This will not be elaborated upon here.

[0043] Of course, it should be noted here that the first reset signal Vref1 output from the output terminal Vref of the drive compensation circuit replaces the signal directly output from the display driver chip SDIC and is electrically connected to the corresponding reset signal line in the pixel circuit. Furthermore, these reset signal lines are electrically connected to the first reset signal terminal in the pixel circuit, combined with... Figure 1 As shown, the signal at the first reset signal terminal is used to reset the node in the discrete pixel circuit that writes data.

[0044] In other words, the pixel circuit includes a write transistor and a first reset transistor, for Figure 1 For the pixel circuit, the write transistor corresponds to transistor T4, the first reset transistor corresponds to transistor T10, and the common electrical connection terminal of the write transistor and the first reset transistor is the node of the written data, namely the third node N3. When the write transistor is turned on, the data signal terminal Vdata is transmitted to the third node N3. When the first reset transistor is turned on, the first reset signal Vref1 of the first reset signal terminal is transmitted to the third node N3 to reset the node of the written data.

[0045] With the above settings, the comparator circuit compares the power signal in the near-end region of the bonding area pin close to the power signal input with the collected power signal in the far-end region. Based on the difference, the signal is amplified and compensated to the reset signal output by the display driver chip SDIC. This allows the reset signal to dynamically compensate for changes in the power signal, thereby achieving dynamic tracking compensation for the impact of the reset signal on the voltage drop of the power signal line and improving the brightness consistency of the pixel circuit.

[0046] Optionally, continue to refer to Figure 4 As shown, the drive compensation circuit also includes a first transistor M1 and a second transistor M2. The first transistor M1 and the second transistor M2 serve as the output units of the comparator circuit 10. The first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor. Specifically, the first electrode of the first transistor M1 is electrically connected to the power supply threshold terminal AVDD, the second electrode is electrically connected to the first electrode of the second transistor M2 and serves as the output terminal of the comparator circuit 10, the control electrode is electrically connected to the output terminal of the second operational amplifier A2, the second electrode of the second transistor M2 is electrically connected to the ground terminal GND, and the control electrode is electrically connected to the output terminal of the second operational amplifier A2.

[0047] In other words, by using the first transistor M1 and the second transistor M2 to form a "back-to-back" structure, when the signal at the output terminal of the second comparator circuit 102 is higher than the potential of the power supply threshold terminal AVDD, the first transistor M1 is turned off and the second transistor M2 is turned on, thereby pulling the output down to the ground potential; under other normal conditions, when the signal at the output terminal of the second comparator circuit 102 is less than or equal to the potential of the power supply threshold terminal AVDD, the first transistor M1 and the second transistor M2 are turned on, so that the output terminal Vref of the comparator circuit 10 can normally output the first reset signal Vref1.

[0048] It can be seen that through this setting, the threshold protection value can be set by using the potential of the power threshold terminal AVDD. In some cases, if the calculated value obtained by the operation of the second comparator circuit is too high, and the value will affect the reset effect of the node as a reset signal, the output value is pulled low by turning off the first transistor M1 and turning on the second transistor to ensure that the pixel circuit can operate normally.

[0049] Optionally, the drive compensation circuit may also include a storage capacitor C, with the first terminal of the storage capacitor C electrically connected to the output terminal of the drive compensation circuit and the second terminal electrically connected to the ground terminal GND. With this configuration, the capacitor can be used as an output filter to eliminate noise and lead interference.

[0050] It is worth mentioning that, Figure 4 The example is applied to drive compensation of pixel circuits of P-type transistors. For pixel circuits of P-type transistors, which are positive voltage drive circuits, the high-level power supply signal affects the drive current and is affected by the line resistance of the power signal line. The power signal amplitude in the far-end area is lower than that in the near-end area from the bonding area pin of the display panel. The voltage drop of the power signal can be offset by positively increasing the reset signal Vref1.

[0051] In some alternative embodiments, if the transistor in the pixel circuit is an N-type transistor and requires negative voltage drive, then the low-level power supply signal should affect the magnitude of the drive current. The signals connected to the first power supply signal terminal and the first power supply sensing terminal of the drive compensation circuit will be low-level signals, and the reset signal will be used to track and compensate for the voltage difference caused by the line resistance voltage drop of the low-level power supply signal.

[0052] Reference Figure 5As shown, the drive compensation circuit in this example is... Figure 4 The structural difference shown is that the comparator circuit includes: a first comparator circuit 101' and a second comparator circuit 102'.

[0053] Specifically, the first comparator circuit 101' includes a first operational amplifier A1, the first input terminal of the first operational amplifier A1 is electrically connected to the first power signal terminal ELVSS_PCB, the second input terminal is electrically connected to the first power sensing terminal ELVSS_Sens, and the output terminal is electrically connected to the first input terminal of the second comparator circuit A2, configured to compare the potential of the first power sensing terminal ELVSS_Sens with the potential of the first power signal terminal ELVSS_PCB to generate a comparison value.

[0054] Specifically, the first comparator circuit 101' includes: a first operational amplifier A1 and a first resistor R1, a second resistor R2, a third resistor R3 and a fourth circuit R4 with the same resistance value. The first input terminal of the first operational amplifier A1 is electrically connected to the first power signal terminal ELVSS_PCB via the first resistor R1 and electrically connected to the ground terminal GND via the second resistor R2. The second input terminal is electrically connected to the first power sensing terminal ELVSS_Sens via the third resistor R3. The first end of the fourth resistor R4 is electrically connected to the second input terminal and the second end is electrically connected to the output terminal of the first operational amplifier A1.

[0055] In this example, the pixel circuit uses N-type transistors. The first input of the first operational amplifier A1 is an inverting input "-", and the second input is a non-inverting input "+". The signal connected to the first power signal terminal ELVSS_PCB is a low-level signal, typically a negative voltage value, and its fluctuation direction is opposite to that of a high-level power signal. Based on the virtual short and virtual open principles of operational amplifiers, using the subtractor formed by the first operational amplifier A1 and the first resistors R1 to R4, the output ΔV of the first comparator circuit 101' is ΔV = ELVSS_Sens - ELVSS_PCB. That is, the first comparator circuit 101' performs the operation of subtracting the signal connected to the first power signal terminal ELVSS_PCB from the signal connected to the first power sensing terminal ELVSS_Sens. Although the signal connected to the first power signal terminal ELVSS_PCB is a low-level signal, due to the influence of the line resistance of the power signal line, the potential of the signal connected to the first power sensing terminal ELVSS_Sens should have a certain voltage drop based on the signal connected to the first power signal terminal ELVSS_PCB, therefore, the difference should be negative. In this article, for ease of understanding, the signals connected to the first power signal terminal ELVSS_PCB and the signals connected to the first power sensing terminal ELVSS_Sens are represented by their respective port symbols.

[0056] The second comparator circuit 102' includes: a second operational amplifier A2, a fifth resistor R5 and a sixth resistor R6 with the same resistance value, and a seventh resistor R7 and an eighth resistor R8 with the same resistance value. The first input terminal of the second operational amplifier A2 is electrically connected to the reset signal terminal Vref_SDIC via the fifth resistor R5 and electrically connected to the output terminal of the first operational amplifier A1 via the seventh resistor R7. The second input terminal is electrically connected to the ground terminal GND via the sixth resistor R6. The first end of the eighth resistor R8 is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the second operational amplifier A2 and serves as the output terminal of the second comparator circuit 102'.

[0057] Since the transistors in the pixel circuit are N-type transistors, in this example, the first input terminal of the second comparator circuit 102 is the positive input terminal "+", and the second input terminal is the inverting input terminal "-". Utilizing the virtual short and virtual open principles of operational amplifiers, the second comparator circuit 102' amplifies and adds the signals input to the first and second input terminals proportionally. This leverages the coupling relationship between the reset signal Vref1 and the power supply signal Vss to establish negative feedback compensation of the reset signal Vref1 on the power supply signal Vss.

[0058] Specifically, by setting the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 to be equal, and the resistance values ​​of the seventh resistor R7 and the eighth resistor R8 to be equal, assuming R5=R6=a and R7=R8=b, the output Vref1 of the first comparator circuit 101 is Vref1=SDIC_Vref+b / a×(ELVSS_Sens-RELVSS_PCB). In this paper, for ease of understanding, the signals connected to the first power signal terminal ELVSS_PCB, the first power sensing terminal ELVSS_Sens, and the reset signal terminal SDIC_Vref are represented by their respective port symbols.

[0059] By properly setting the scaling factor b / a, the first reset signal Vref1 output by the final comparator circuit can compensate for the coupling effect of the signal itself at the first reset signal terminal in the pixel circuit caused by the change in the power supply signal Vdd, and also cancel the effect of the difference in the change between the far and near ends of the power supply signal Vdd. The value of the scaling factor b / a depends on the material, width, and distance between the near and far ends of the first power supply signal line providing the power supply signal; its specific value can be set through simulation.

[0060] Of course, it should be noted here that the first reset signal Vref1 output from the output terminal Vref of the drive compensation circuit replaces the signal directly output from the display driver chip SDIC and is electrically connected to the response reset signal line in the pixel circuit. Furthermore, these reset signal lines are electrically connected to the first reset signal terminal in the pixel circuit, combined with... Figure 1As shown, the first reset signal terminal is a signal used to reset the nodes in the discrete pixel circuit that write data.

[0061] In other words, the pixel circuit includes a write transistor and a first reset transistor, for Figure 1 For the pixel circuit, the write transistor corresponds to transistor T4, the first reset transistor corresponds to transistor T10, and the common electrical connection terminal of the write transistor and the first reset transistor is the node of the written data, namely the third node N3. When the write transistor is turned on, the data signal terminal Vdata is transmitted to the third node N3. When the first reset transistor is turned on, the first reset signal Vref1 of the first reset signal terminal is transmitted to the third node N3 to reset the node of the written data.

[0062] It should be particularly noted that, through the above settings, the positive and negative input terminals of the first comparator circuit 101' and the second comparator circuit 102' can be matched with the polarity fluctuation direction of the connected first sensing signal terminal and the first power supply signal terminal, as well as the carrier characteristics of the transistor types in the pixel circuit. This allows the reset signal to be compensated in the same direction when fluctuations occur in the power supply signal line due to line resistance, making the output first reset signal value more negative. This allows the reset signal to follow the changes in the power supply signal and offset the influence of power supply signal fluctuations on the drive current. Thus, the reset signal dynamically compensates for changes in the power supply signal, thereby achieving dynamic tracking compensation for the impact of the reset signal on the line voltage drop of the power supply signal line, and improving the brightness consistency of the pixel circuit.

[0063] It should be noted that the other structures of the pixel driving circuit are consistent with those in the above embodiment, and will not be described again here.

[0064] In some alternative embodiments, considering that an important aspect of the line resistance voltage drop on the power signal line is reflected in the reset signal, namely that the voltage coupling effect of the power supply voltage drop will cause the reset signal to be different at different locations, a drive compensation circuit can be optionally used to directly and dynamically compensate in real time by dynamically following the voltage on the reset signal line of the near-end region and the far-end region.

[0065] Optionally, refer to Figure 6 and Figure 7 As shown, the driving compensation circuit of the pixel circuit provided in this embodiment includes: a comparator circuit 10'.

[0066] The comparator circuit 10' is electrically connected to the reset sensing terminal Vref_Sens and the reset signal terminal Vref_SDIC. It is configured to compare and amplify the potential of the reset signal terminal Vref_SDIC with the potential of the reset sensing terminal Vref_Sens, and then add it to the signal of the reset signal terminal to obtain the first reset signal, which is used to access the first reset signal terminal Vref of the pixel circuit.

[0067] Here, the reset sensing terminal Vref_Sens and the reset signal terminal Vref_SDIC represent the reset signal terminals located in the far-end area and the area different from the near-end area of ​​the display panel, respectively. The reset sensing terminal Vref_Sens can be a sensing signal terminal from the far-end area or a certain distance from the near-end area; it is used to sample the reset signal on the power signal line located away from the near-end area. The reset signal terminal Vref_SDIC represents a signal terminal directly electrically connected to the display driver chip SDIC, located in the near-end area.

[0068] In this article, the near-end region refers to the area in the non-display area of ​​the display panel that is close to the display driver chip SDIC or the bonding pin, while the far-end region refers to the area in the non-display area of ​​the display panel that is far from the display driver chip SDIC or the side that is close to the bonding pin.

[0069] Specifically, refer to Figure 7 As shown, the comparator circuit 10' includes: a third operational amplifier A3, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12. The first input terminal of the third operational amplifier A3 is electrically connected to the reset signal terminal Vref_SDIC via the ninth resistor R9, and the second input terminal is electrically connected to the reset sensing terminal Vref_Sens via the eleventh resistor R11. The first end of the tenth resistor R11 is electrically connected to the first input terminal, and the second end is electrically connected to the ground terminal. The first end of the twelfth resistor R12 is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the third operational amplifier A3. The output terminal of the third operational amplifier A3 is connected to the first reset signal terminal Vref of the pixel circuit.

[0070] In this example, the first input terminal of the comparator circuit 10' remains the positive input terminal "+", and the second input terminal remains the inverting input terminal "-". Utilizing the virtual short and virtual open principles of operational amplifiers, the comparator circuit 10' compares the signals input to the first and second input terminals, amplifies them proportionally, and then adds them. This leverages the coupling relationship between the reset signal Vref1 and the power supply signal Vdd to establish negative feedback compensation for the power supply signal Vdd. It should be noted that because this example directly bases the compensation on changes in the reset signal from other or remote regions, it effectively utilizes the voltage coupling effect of the power supply signal's change on the reset signal, thus achieving negative feedback compensation. This directly translates into the difference between the reset sensing terminal Vref_Sens and the reset signal terminal Vref_SDIC being reflected in the final first reset signal terminal.

[0071] Specifically, by setting the resistance values ​​of each resistor, the output Vref1 of the comparison sub-circuit 10' is compared. By appropriately setting the resistance values ​​of each resistor, the final result can be Vref1 = Vref_SDIC + (Vref_SDIC - Vref_Sens).

[0072] With the above settings, by using the comparator circuit to compare the changes in the reset signals between the near-end region and the far-end region, or other regions different from the near-end region, and then amplifying and adding them by a certain scaling factor, it is possible to use the reset signal for real-time dynamic tracking, thereby reducing the impact of changes in the reset signal in the far-end region on the drive current and improving display consistency.

[0073] It should be noted that the voltage collected by the reset sensing terminal Vref_Sens can be the voltage at the location of the reset signal line in the far-end area, or it can be collected at any location in the display area. When collecting at any location, it can realize real-time dynamic compensation for different areas of a pixel, thereby avoiding display flicker.

[0074] Based on the same inventive concept, another aspect of this disclosure provides a display panel, referring to... Figure 8 As shown, the display panel includes a display area AA and a non-display area NA located around the display area AA. The non-display area NA includes a driving proximal end for setting the bonding area pin 201 and a driving distal end located on the side opposite to the driving proximal end. The bonding area pin 201 is disposed in the bonding area 20.

[0075] The display panel also includes: a first power signal line ELVDD extending at least partially around the display area AA; a plurality of first power traces Lvdd and a plurality of reset signal lines Lvref extending in the direction from the drive proximal end to the drive distal end; The driving compensation circuit described above is located in the non-display area NA; and at least one sensing connection line Lsens.

[0076] The comparator circuit 10 is electrically connected to the first power signal terminal ELVDD_PCB, the first power sensing terminal ELVDD_Sens, and the reset signal terminal Vref_SDIC. The first power sensing terminal ELVDD_Sens is electrically connected to the portion of the first power signal line ELVDD located at the far end of the drive via the sensing connection line Lsens.

[0077] Optionally, if the power signal sampled by the first power sensing terminal ELVDD_Sens is a signal at a certain location in the display area, then the first power sensing terminal ELVDD_Sens is electrically connected via the sensing connection line Lsens to a portion of the first power trace ELVDD that is different from the near-end region or located at the far end of the drive.

[0078] It should be noted that although the first power signal line in the figure is shown as a high-level Vdd signal line, this disclosure is not limited thereto. For embodiments that utilize sampling of a low-level Vss signal line for dynamic compensation, the first power signal line should be ELVSS, and the arrangement of the signal lines is similar to this example, which will not be described in detail here.

[0079] Alternatively, refer to Figure 9 As shown, the comparator circuit 10' is electrically connected to the reset sensing terminal Vref_Sens and the reset signal terminal Vref_SDIC. The reset sensing terminal Vref_SDIC is electrically connected to the reset signal line Lvref via the sensing connection line Lsens.

[0080] By configuring the above settings, including a drive compensation circuit for pixel circuits, the reset signal can dynamically compensate for the effects of these changes on the power signal in the far region or other locations near the far region, which are different from the near region. This improves display uniformity and reduces display flicker.

[0081] Based on the same inventive concept, embodiments of this disclosure also provide the display device described above, including the display panel described above.

[0082] It should be noted that the specific structure of the display device has been described in detail above when describing the structure and function of the display panel, and will not be repeated here.

[0083] In this embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. It can improve the display consistency of the display panel and reduce flicker by using a reset signal to compensate for the influence potential in the drive current through the above-mentioned display panel.

[0084] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A driving compensation circuit for a pixel circuit, characterized in that, include: The comparator circuit is electrically connected to the first power signal terminal, the first power sensing terminal, and the reset signal terminal, or electrically connected to the reset sensing terminal and the reset signal terminal. It is configured to compare and amplify the potential of the first power signal terminal with the potential of the first power sensing terminal, or compare and amplify the potential of the reset signal terminal with the potential of the reset sensing terminal, and then add the result to the signal of the reset signal terminal to obtain the first reset signal for connection to the first reset signal terminal of the pixel circuit.

2. The drive compensation circuit according to claim 1, characterized in that, The comparator sub-circuit includes: a first comparator sub-circuit and a second comparator sub-circuit. The first comparator sub-circuit includes a first operational amplifier, with a first input terminal electrically connected to a first power supply signal terminal, a second input terminal electrically connected to a first power supply sensing terminal, and an output terminal electrically connected to the first input terminal of the second comparator sub-circuit. It is configured to compare the potential at the first power supply sensing terminal with the potential at the first power supply signal terminal to generate a comparison value. The second comparator circuit includes a second operational amplifier. The first input terminal of the second operational amplifier is further electrically connected to a reset signal terminal, the second input terminal is electrically connected to a ground terminal, and the output terminal is electrically connected to the first reset signal terminal of the pixel circuit. It is configured to amplify the comparison value and then add it to the potential of the reset signal terminal to serve as a first reset signal connected to the first reset signal terminal of the pixel circuit.

3. The drive compensation circuit according to claim 2, characterized in that, The first comparator circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor, all with the same resistance value. The first input terminal of the first operational amplifier is electrically connected to the first power signal terminal via the first resistor and electrically connected to the ground terminal via the second resistor. The second input terminal is electrically connected to the first power sensing terminal via the third resistor. The first end of the fourth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the first operational amplifier. The second comparator circuit further includes: a fifth resistor and a sixth resistor with the same resistance value, and a seventh resistor and an eighth resistor with the same resistance value. The first input terminal of the second operational amplifier is electrically connected to the reset signal terminal via the fifth resistor and electrically connected to the output terminal of the first operational amplifier via the seventh resistor. The second input terminal is electrically connected to the ground terminal via the sixth resistor. The first end of the eighth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the second operational amplifier and serves as the output terminal of the second comparator circuit.

4. The drive compensation circuit according to claim 3, characterized in that, The transistors in the pixel circuit are P-type transistors. The first input terminal is a non-inverting input terminal, and the second input terminal is an inverting input terminal. The potential received by the first power signal terminal is a high-level signal.

5. The drive compensation circuit according to claim 2, characterized in that, The first comparator circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor, all with the same resistance value. The second input terminal of the first operational amplifier is electrically connected to the first power sensing terminal via the first resistor and to the ground terminal via the second resistor. The first input terminal is electrically connected to the first power signal terminal via the third resistor. The first end of the fourth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the first operational amplifier. The second comparator circuit further includes: a fifth resistor and a sixth resistor with the same resistance value, and a seventh resistor and an eighth resistor with the same resistance value. The first input terminal of the second operational amplifier is electrically connected to the reset signal terminal via the fifth resistor and electrically connected to the output terminal of the first operational amplifier via the seventh resistor. The second input terminal is electrically connected to the ground terminal via the sixth resistor. The first end of the eighth resistor is electrically connected to the second input terminal, and the second end is electrically connected to the output terminal of the second operational amplifier and serves as the output terminal of the second comparator circuit.

6. The drive compensation circuit according to claim 5, characterized in that, The transistors in the pixel circuit are N-type transistors. The first input terminal of the first operational amplifier is an inverting input terminal, and the second input terminal is a non-inverting input terminal. The first input terminal of the second operational amplifier is a non-inverting input terminal, and the second input terminal is an inverting input terminal. The potential received by the first power signal terminal is a low-level signal.

7. The drive compensation circuit according to claim 1, characterized in that, The comparator circuit includes: a third operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor. The first input terminal of the third operational amplifier is electrically connected to the reset signal terminal via the ninth resistor, the second input terminal is electrically connected to the reset sensing terminal via the eleventh resistor, the first end of the tenth resistor is electrically connected to the first input terminal, the second end is electrically connected to the ground terminal, the first end of the twelfth resistor is electrically connected to the second input terminal, the second end is electrically connected to the output terminal of the third operational amplifier, and the output terminal of the third operational amplifier is connected to the first reset signal terminal of the pixel circuit.

8. The drive compensation circuit according to claim 2, characterized in that, The drive compensation circuit is electrically connected to a first power signal terminal, a first power sensing terminal, and a reset signal terminal. The first power signal terminal is closer to the bonding area pin that provides the power signal than the first sensing signal terminal.

9. The drive compensation circuit according to claim 7, characterized in that, The drive compensation circuit is electrically connected to the reset sensing terminal and the reset signal terminal, with the reset sensing terminal being closer to the bonding area pin that provides the reset signal than the reset signal terminal.

10. The drive compensation circuit according to claim 3 or 6, characterized in that, It also includes: a first transistor and a second transistor, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor. The first electrode of the first transistor is electrically connected to the power supply threshold terminal, the second electrode is electrically connected to the first electrode of the second transistor and serves as the output terminal of the comparator circuit, the control electrode is electrically connected to the output terminal of the second operational amplifier, the second electrode of the second transistor is electrically connected to the ground terminal, and the control electrode is electrically connected to the output terminal of the second operational amplifier.

11. A display panel, characterized in that, include: A display area and a non-display area located around the display area, the non-display area including a drive proximal end with a bonding area pin and a drive distal end located on the side opposite to the drive proximal end. The display panel also includes: A first power signal line that at least partially surrounds the display area; a plurality of first power traces and a plurality of reset signal lines extending in the direction from the drive proximal end to the drive distal end; The drive compensation circuit according to any one of claims 1-10 is disposed in the non-display area; and At least one sensing connection line, The comparator sub-circuit is electrically connected to a first power signal terminal, a first power sensing terminal, and a reset signal terminal. The first power sensing terminal is electrically connected via the sensing connection line to the first power signal line or the portion of the first power trace located at the far end of the drive, or The comparator circuit is electrically connected to the reset sensing terminal and the reset signal terminal, and the reset sensing terminal is electrically connected to the reset signal line via the sensing connection line.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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