Pixel circuit, display panel and display device

Abstract

Embodiments of the present disclosure provide a pixel circuit, a display panel and a display device, and relate to the technical field of display, so as to improve the first frame response performance of the display panel. The pixel circuit comprises a driving transistor and a first reset sub-circuit. The control electrode of the driving transistor is electrically connected with a first node, the first electrode of the driving transistor is electrically connected with a second node, and the second electrode of the driving transistor is electrically connected with a third node. The driving transistor is a low-temperature polysilicon transistor. The first reset sub-circuit is electrically connected with the first node, a first reset signal terminal and a first initialization signal terminal. The first reset sub-circuit is configured to, in a reset stage, transmit a first initialization signal from the first initialization signal terminal to the first node under the control of a first reset signal from the first reset signal terminal. The duration of the effective level of the first reset signal is greater than or equal to 5 row periods. The pixel circuit is used in the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, display panel, and display device. Background Technology

[0002] With the rapid development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, active matrix organic light-emitting diode (AMOLED) display panels are widely used in display devices such as mobile phones, televisions, and laptops due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, and high contrast.

[0003] Currently, with the widespread adoption of high refresh rate display panels, the First Frame Response (FFR) performance of these panels has become a core indicator determining the smoothness of image quality. Therefore, improving the FFR performance of display panels is a pressing issue that needs to be addressed. Summary of the Invention

[0004] The purpose of the embodiments of this disclosure is to provide a pixel circuit, a display panel, and a display device to improve the first frame response performance of the display panel.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: In a first aspect, a pixel circuit is provided for driving a light-emitting device; a data refresh cycle includes a reset phase and a light-emitting phase arranged sequentially. The pixel circuit includes a driving transistor and a first reset sub-circuit. The control electrode of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a second node, and the second electrode of the driving transistor is electrically connected to a third node; one of the second node and the third node is coupled to a first power supply signal terminal, and the other is coupled to a second power supply signal terminal; the first power supply signal terminal is configured to output a positive power supply signal, and the second power supply signal terminal is configured to output a negative power supply signal; the driving transistor is a low-temperature polysilicon transistor. The first reset sub-circuit is electrically connected to the first node, a first reset signal terminal, and a first initialization signal terminal; the first reset sub-circuit is configured to, during the reset phase, under the control of a first reset signal from the first reset signal terminal, transmit a first initialization signal from the first initialization signal terminal to the first node. The effective level of the first reset signal has a duration greater than or equal to 5 line cycles.

[0006] In this scenario, by extending the duration of the effective level of the first reset signal, the driving transistor is able to fully capture charge carriers, thereby shortening the relaxation time of the driving transistor's threshold voltage. Furthermore, this ensures that the threshold voltage of the driving transistor is nearly stable before the light-emitting phase, improving the hysteresis phenomenon of the driving transistor and enhancing the first-frame response performance of the display panel.

[0007] In some embodiments, the amplitude range of the first initialization signal is 6V to 8V.

[0008] In some embodiments, a data refresh cycle further includes a data writing phase located between the reset phase and the light emission phase; the data writing phase includes an initialization sub-phase and a data refresh sub-phase; the pixel circuit further includes a data refresh sub-circuit and a data refresh sub-circuit. The data refresh sub-circuit is electrically connected to a first scan signal terminal, a data signal terminal, and a fourth node; the data refresh sub-circuit is configured to, in the data refresh sub-phase, under the control of a first scan signal from the first scan signal terminal, transmit a data signal from the data signal terminal to the fourth node. The data writing sub-circuit is electrically connected to a second scan signal terminal, a first reference voltage signal terminal, the fourth node, and the first node; the data writing sub-circuit is configured to, in the initialization sub-phase, under the control of a second scan signal from the second scan signal terminal, transmit a first reference voltage signal from the first reference voltage signal terminal to the fourth node, and maintain the voltage between the fourth node and the first node; and, in the data refresh sub-phase, change the voltage of the first node according to the voltage change of the fourth node.

[0009] In some embodiments, the data writing sub-circuit includes a first transistor, a first storage capacitor, and a second storage capacitor. The control electrode of the first transistor is electrically connected to the second scan signal terminal, the first electrode of the first transistor is electrically connected to the first reference voltage signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node. The first plate of the first storage capacitor is electrically connected to the fourth node, and the second plate of the first storage capacitor is electrically connected to the first plate of the second storage capacitor, forming a fifth node. The second plate of the second storage capacitor is electrically connected to the first node.

[0010] In some embodiments, the pixel circuit further includes a voltage regulator circuit electrically connected to the fifth node, the third scan signal terminal, and the second reference voltage signal terminal. The voltage regulator circuit is configured to, during the reset phase, transmit a second reference voltage signal from the second reference voltage signal terminal to the fifth node under the control of a third scan signal from the third scan signal terminal. The second reference signal has the opposite polarity to the first initialization signal.

[0011] In some embodiments, the driving transistor is a P-type transistor; the second reference voltage signal terminal is electrically connected to the first power supply signal terminal.

[0012] In some embodiments, the pixel circuit further includes a compensation sub-circuit, a light emission control sub-circuit, and a second reset sub-circuit. The compensation sub-circuit is electrically connected to the first node, the third node, and a fourth scan signal terminal; the compensation sub-circuit is configured to, during the data writing phase, transmit the voltage from the third node to the first node under the control of a fourth scan signal from the fourth scan signal terminal. The light emission control sub-circuit is electrically connected to the third node, an enable signal terminal, and a sixth node, the sixth node being electrically connected to the light-emitting device; the light emission control sub-circuit is configured to, during the light emission phase, transmit the voltage from the third node to the sixth node under the control of an enable signal from the enable signal terminal. The second reset sub-circuit is electrically connected to the sixth node, a second reset signal terminal, and a second initialization signal terminal; the second reset sub-circuit is configured to, during the reset phase, during the reset phase, transmit a second initialization signal from the second initialization signal terminal to the sixth node under the control of a second reset signal from the second reset signal terminal.

[0013] In a second aspect, a display panel is provided, comprising a substrate, a pixel circuit layer, and a light-emitting device layer. The pixel circuit layer is disposed on one side of the substrate; the pixel circuit layer includes a plurality of pixel circuits as described in the first aspect. The light-emitting device layer is disposed on the side of the pixel circuit layer away from the substrate; the light-emitting device layer includes a plurality of light-emitting devices, the light-emitting devices being electrically connected to the pixel circuits.

[0014] In some embodiments, along a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting portion, and a second electrode; the light-emitting portion includes a light-emitting layer. The plurality of light-emitting devices includes a first light-emitting device, a second light-emitting device, and a third light-emitting device, wherein the first light-emitting device is configured to emit red light, the second light-emitting device is configured to emit green light, and the third light-emitting device is configured to emit blue light. The thickness of the light-emitting layer of the first light-emitting device and the thickness of the light-emitting layer of the second light-emitting device are both greater than the thickness of the light-emitting layer of the third light-emitting device.

[0015] In some embodiments, along a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting portion, and a second electrode; the light-emitting portion includes a light-emitting layer; the light-emitting layer includes a host material and a guest material. The plurality of light-emitting devices includes a first light-emitting device, a second light-emitting device, and a third light-emitting device, wherein the first light-emitting device is configured to emit red light, the second light-emitting device is configured to emit green light, and the third light-emitting device is configured to emit blue light. In the light-emitting layer of the second light-emitting device, the doping ratio of the guest material ranges from 0.4% to 1.0%.

[0016] In some embodiments, the doping ratio of the guest material in the light-emitting layer of the first light-emitting device ranges from 2.0% to 3.0%; and / or, the doping ratio of the guest material in the light-emitting layer of the third light-emitting device ranges from 1.5% to 3.0%.

[0017] Thirdly, a display device is provided. The display device includes a display panel as described in the second aspect.

[0018] The aforementioned display panel and display device have the same structure and beneficial technical effects as the pixel circuit provided in the first aspect, and will not be described in detail here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0020] Figure 1 This is a structural diagram of a display device according to some embodiments; Figure 2 This is a structural diagram of another display device according to some embodiments; Figure 3 This is a cross-sectional view of a display device according to some embodiments; Figure 4 This is a structural diagram of a display panel according to some embodiments; Figure 5 for Figure 4 A sectional view along the section line CC'. Figure 6 This is a structural diagram of a light-emitting device according to some embodiments; Figure 7This is a structural block diagram of a sub-pixel according to some embodiments; Figure 8 for Figure 7 A circuit diagram of a sub-pixel is shown; Figure 9 This is a timing diagram of a pixel circuit according to some embodiments. Detailed Implementation

[0021] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0022] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0023] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0024] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0025] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0026] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0027] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0028] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0029] In the circuit structures (e.g., pixel circuits) provided in the embodiments of this disclosure, the transistors used in the circuit structures can be thin film transistors (TFTs), metal oxidized semiconductors (MOSs), or other switching devices with the same characteristics. In the embodiments of this disclosure, thin film transistors are used as an example for illustration.

[0030] In the circuit structure provided in the embodiments of this disclosure, the first terminal of each transistor is one of the source and the drain, and the second terminal of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second terminals of the transistors in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal is the source and the second terminal is the drain; for example, when the transistor is an N-type transistor, the first terminal is the drain and the second terminal is the source.

[0031] In the circuit structure provided by the embodiments of this disclosure, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0032] The transistors included in the circuit structures provided in the embodiments of this disclosure may all be N-type transistors, or all may be P-type transistors, or a subset may be N-type transistors and a subset may be P-type transistors. In this disclosure, "effective level" refers to the level that enables the transistor to conduct. Specifically, P-type transistors can conduct under the control of a low-level signal, and N-type transistors can conduct under the control of a high-level signal.

[0033] The following is an illustrative example of the circuit structure provided in the embodiments of this disclosure, in which all transistors are P-type transistors.

[0034] In this disclosure, the P-type transistor can be turned on under the control of a low-level signal, and the N-type transistor can be turned on under the control of a high-level signal.

[0035] like Figure 1 and Figure 2 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. Exemplarily, the display device 1000 can be any product or component with display functionality, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, virtual reality (VR) device, etc.

[0036] For example, such as Figure 1 As shown, the display device 1000 can be a portable display product; for example, the display device 1000 can be... Figure 1The mobile phone shown. For example, see [link to relevant documentation]. Figure 2 The display device 1000 can be a wearable device; for example, the display device 1000 can be... Figure 2 The watch shown.

[0037] In some embodiments, see Figure 3 The display device 1000 includes a display panel 100. The display panel 100 includes a light-emitting side and a non-light-emitting side disposed opposite to each other. The light-emitting side is the side of the display panel 100 used for display. Figure 3 The upper side of the middle.

[0038] Please continue reading. Figure 3 The aforementioned display device 1000 may further include a housing 200, a cover plate 300, a circuit board 400, and other electronic components. The housing 200 may have a U-shaped longitudinal section, for example. The display panel 100 and the circuit board 400 are disposed within the housing 200, and the cover plate 300 is disposed at an opening in the housing 200. Of course, the display device 1000 may also omit the cover plate 300; this disclosure does not specifically limit this aspect.

[0039] The circuit board 400 is located on the side of the display panel 100 away from the cover plate 300, and the circuit board 400 is connected to the display panel 100 to provide the required display signals to the display panel 100.

[0040] For example, the display panel 100 described above can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc., and the embodiments disclosed herein are not specifically limited thereto. The following uses an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0041] In some embodiments, see Figure 4 The display panel 100 has a display area A and a peripheral area B located on at least one side of the display area A. Figure 4 Taking a peripheral area B surrounding a display area A as an example, display area A is the area for displaying images and is configured to have multiple sub-pixels P. Peripheral area B is the area where no images are displayed and is configured to house display driving circuitry. For example, the display driving circuitry includes a gate driving circuit 210 and a source driving circuit 220.

[0042] For example, such as Figure 4 As shown, the display panel 100 includes a substrate 11, and a plurality of sub-pixels P are disposed on the substrate 11 and located in the display area A.

[0043] The arrangement of the multiple sub-pixels P is, for example, a multi-row, multi-column configuration. Each row includes at least two sub-pixels P arranged along a first direction X, and each column includes at least two sub-pixels P arranged along a second direction Y. The first direction X intersects the second direction Y; for example, the first direction X is perpendicular to the second direction Y.

[0044] In some examples, the aforementioned plurality of sub-pixels P may include a first sub-pixel with a first emission color, a second sub-pixel with a second emission color, and a third sub-pixel with a third emission color. Here, the first, second, and third colors are the three primary colors. For example, the first color is red, the second color is blue, and the third color is green.

[0045] The substrate 11 can be of various types and can be selected according to actual needs. For example, the substrate 11 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a polymethyl methacrylate (PMMA) substrate, etc. As another example, the substrate 11 can be a flexible substrate. For example, the flexible substrate can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate, etc.

[0046] Please continue reading. Figure 4 The display panel 100 also includes a gate driving circuit 210, a source driving circuit 220, multiple gate lines GL, and multiple data lines DL. The gate driving circuit 210 and the source driving circuit 220 are disposed on the substrate 11 and located in the peripheral region B. The gate lines GL extend along a first direction X, and identical signal terminals in the same row of sub-pixels P (e.g., the enable signal terminal EM, the first reset signal terminal R1, the second reset signal terminal R2, the first scan signal terminal G1, the second scan signal terminal G2, the third scan signal terminal G3, and the fourth scan signal terminal G4 mentioned below) can be electrically connected to one gate line GL. The data lines DL extend along a second direction Y, and data signal terminals in the same row of sub-pixels P (e.g., the data signal terminal D mentioned below) can be connected to the same data line DL to scan each row of sub-pixels P row by row.

[0047] In some embodiments, see Figure 4 and Figure 5 Each sub-pixel P includes a pixel circuit 110 and a light-emitting device 120. The pixel circuit 110 and the light-emitting device 120 are connected to drive the light-emitting device 120 to emit light.

[0048] In some examples, such as Figure 5 As shown, the pixel circuit 110 includes a plurality of transistors 111 and a storage capacitor 112. For example, the pixel circuit 110 can be a "9T2C" circuit, a "7T1C" circuit, or an "8T2C" circuit, etc. The embodiments of this disclosure are not limited to these, and any other pixel circuit can be considered as long as the same technical concept is applied. Here, "T" refers to TFT, and the number before "T" indicates the number of TFTs; "C" refers to Cst, and the number before "C" indicates the number of capacitors Cst.

[0049] Among them, such as Figure 5 As shown, transistor 111 includes an active portion 1111, a first electrode 1112, a second electrode 1113, and a control electrode 1114. The first electrode 1112 and the second electrode 1113 are respectively in contact with the active portion 1111. The portion of the active portion 1111 located between the first electrode 1112 and the second electrode 1113 forms the channel 1115 of transistor 111. Storage capacitor 112 includes a first electrode plate 1121 and a second electrode plate 1122 disposed opposite to each other.

[0050] It should be noted that the first electrode 1112 can be the source of transistor 111, and the second electrode 1113 can be the drain of transistor 111. Alternatively, the first electrode 1112 can be the drain of transistor 111, and the second electrode 1113 can be the source of transistor 111. The embodiments disclosed herein do not impose specific limitations on this.

[0051] In some examples, such as Figure 7 As shown, the pixel circuit 110 includes at least one driving transistor DT, and the pixel circuit 110 includes at least a data writing stage and a light emission stage within a data refresh cycle. During the data writing stage, the pixel circuit 110 is configured to couple a data signal D to the control electrode of the driving transistor DT, thereby controlling the driving current of the driving transistor DT during the light emission stage, and thus controlling the grayscale size of the sub-pixel P (the corresponding light emission brightness of the light-emitting device 120).

[0052] It is understandable that the aforementioned driving transistor DT can be a low-temperature polysilicon (LTPS) thin-film transistor with an active component. LTPS thin-film transistors have advantages such as high mobility and fast charging, and are widely used in display panels with high-frequency driving.

[0053] In some embodiments, such as Figure 5As shown, the display panel 100 further includes a pixel circuit layer 13 and a light-emitting device layer 14 sequentially disposed on the substrate 11. The pixel circuit layer 13 includes a plurality of pixel circuits 110. The light-emitting device layer 14 includes a plurality of light-emitting devices 120. The pixel circuits 110 and the light-emitting devices 120 are electrically connected.

[0054] In some examples, such as Figure 5 As shown, along a direction perpendicular to and away from the substrate 11, the pixel circuit layer 13 includes a low-temperature polysilicon semiconductor layer ACT, an interlayer insulating layer ILD, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate conductive layer GT2, a second gate insulating layer GI2, a first source / drain conductive layer SD1, a first planarization layer PLN1, a second source / drain conductive layer SD2, and a second planarization layer PLN2, which are sequentially disposed.

[0055] In some examples, such as Figure 5 and Figure 6 As shown, along the direction away from the substrate 11, the light-emitting device 120 includes a first electrode 121, a light-emitting portion 122, and a second electrode 123. The first electrode 121 can be the anode of the light-emitting device 120, and the second electrode 123 can be the cathode of the light-emitting device 120. Alternatively, the first electrode 121 can be the cathode of the light-emitting device 120, and the second electrode 123 can be the anode of the light-emitting device 120; this embodiment does not specifically limit the specific application of this method. The following illustrative description of some embodiments of this disclosure uses the example of the first electrode 121 being the anode of the light-emitting device 120 and the second electrode 123 being the cathode of the light-emitting device 120.

[0056] For example, the light-emitting part 122 can be a single-layer structure; for instance, the light-emitting part 122 includes an emissive layer (EML) 1221. Figure 6 As shown, the light-emitting part 122 can be a stacked structure. For example, in addition to the light-emitting layer 1221, the light-emitting part 122 also includes a light-emitting functional layer 1222 to improve the luminous efficiency of the light-emitting device 120. The light-emitting functional layer 1222 is located between the light-emitting layer 1221 and the first electrode 121, and / or, the light-emitting functional layer 1222 is located between the light-emitting layer 1221 and the second electrode 123.

[0057] The light-emitting functional layer 1222 located between the light-emitting layer 1221 and the first electrode 121 includes at least one of a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). The light-emitting functional layer 1222 located between the light-emitting layer 1221 and the second electrode 123 includes at least one of an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (HBL).

[0058] Please continue reading. Figure 5 The display panel 100 also includes a pixel defining layer (PDL). The PDL is disposed on the side of the pixel circuit layer 13 away from the substrate 11 and has an opening. The light-emitting device 120 is located within the opening of the PDL.

[0059] Please continue reading. Figure 5 The display panel 100 also includes an encapsulation layer 15. The encapsulation layer 15 can be an encapsulation film or an encapsulation substrate. For example, the encapsulation layer 15 can include one encapsulation film, or it can include two or more encapsulation films stacked together. Figure 5 As shown, along a direction perpendicular to and away from the substrate 11, the encapsulation layer 15 includes a first inorganic encapsulation layer 151, an organic encapsulation layer 152, and a second inorganic encapsulation layer 153 stacked together. The materials of the first inorganic encapsulation layer 151 and the second inorganic encapsulation layer 153 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the organic encapsulation layer 152 includes a polymer resin, such as polyimide.

[0060] Currently, with the widespread adoption of high refresh rate display panels, the First Frame Response (FFR) performance of a display panel has become a core indicator determining the smoothness of its image quality. FFR performance refers to the ratio of the brightness of the first frame after a refresh to the stable steady-state brightness of the image. A higher FFR value indicates that the brightness of the first frame after a refresh is closer to the stable steady-state brightness, meaning better image quality. However, due to the hysteresis effect of the driving transistors—that is, fluctuations in the control voltage of the driving transistors cause dynamic relaxation of the threshold voltage over time—the brightness of the first frame after a refresh decreases, resulting in a decline in the FFR performance of the display panel.

[0061] Based on this, such as Figure 7 , Figure 8 and Figure 9 As shown, in a pixel circuit 110 provided in this disclosure, a data refresh cycle includes a reset phase P1 and a light emission phase P3 arranged in sequence. The pixel circuit 110 includes a driving transistor DT and a first reset sub-circuit 20.

[0062] like Figure 7 and Figure 8 As shown, the control terminal of the driving transistor DT is electrically connected to the first node N1, the first terminal of the driving transistor DT is electrically connected to the second node N2, and the second terminal of the driving transistor DT is electrically connected to the third node N3. One of the second node N2 and the third node N3 is coupled to the first power supply signal terminal VDD, and the other is coupled to the second power supply signal terminal VSS. The first power supply signal terminal VDD is configured to output a positive power supply signal, and the second power supply signal terminal VSS is configured to output a negative power supply signal. The driving transistor DT is a low-temperature polysilicon transistor.

[0063] like Figure 7 , Figure 8 and Figure 9 As shown, the first reset sub-circuit 20 is electrically connected to the first node N1, the first reset signal terminal R1, and the first initialization signal terminal VIN1. The first reset sub-circuit 20 is configured to, during the reset phase P1, transmit the first initialization signal from the first initialization signal terminal VIN1 to the first node N1 under the control of the first reset signal from the first reset signal terminal R1. The duration of the effective level of the first reset signal is greater than or equal to 5 line cycles. It should be noted that the line cycle is the ratio of a data refresh cycle to the number of scan lines of the display panel 100.

[0064] In this case, by extending the duration of the effective level of the first reset signal, the driving transistor DT is able to fully capture charge carriers, thereby shortening the relaxation time of the threshold voltage of the driving transistor DT. Furthermore, this ensures that the threshold voltage of the driving transistor DT is nearly stable before the light-emitting stage P3, improving the hysteresis phenomenon of the driving transistor DT and enhancing the first-frame response performance of the display panel 100.

[0065] For example, the duration of the effective level of the first reset signal is any one of 5 line cycles, 8 line cycles, 12 line cycles, 16 line cycles, and 20 line cycles.

[0066] In some examples, the first reset sub-circuit 20 includes a second transistor T2, the control terminal of the second transistor T2 is electrically connected to the first reset signal terminal R1, the first terminal of the second transistor T2 is electrically connected to the first initialization signal terminal VIN1, and the second terminal of the second transistor T2 is electrically connected to the first node N1, which has the advantage of simple structure.

[0067] In other examples, such as Figure 8 As shown, the first reset circuit 20 includes two second transistors T2 connected in series. The control terminals of both second transistors T2 are electrically connected to the first reset signal terminal R1. The first terminal of the first second transistor T2 is electrically connected to the first initialization signal terminal VIN1, and the second terminal of the second second transistor T2 is electrically connected to the first node N1. This reduces the risk of leakage current from the first node N1 through the first reset circuit 20, thus helping to ensure the potential stability of the first node N1.

[0068] In some embodiments, such as Figure 8 As shown, the amplitude range of the first initialization signal is 6V~8V. At this time, by applying a strong bias voltage to the control electrode of the driving transistor DT, the driving transistor DT is able to fully capture carriers, thereby further reducing the impact of the threshold voltage residue of the previous frame on the current frame and further improving the FFR performance of the display panel 100.

[0069] In some examples, the driving transistor DT is an N-type transistor, and the effective level of the first initialization signal is in the range of 6V to 8V, so that the driving transistor DT can fully capture electrons, further reducing the impact of the threshold voltage residue of the previous frame on the current frame, thereby further improving the FFR performance of the display panel 100. For example, the effective level of the first initialization signal is any one of 6V, 7V, 7.5V, and 8V.

[0070] In other examples, such as Figure 8 As shown, the driving transistor DT is a P-type transistor. The effective level of the first initialization signal is in the range of -6V to -8V, allowing the driving transistor DT to fully capture holes and further reduce the impact of the threshold voltage residue from the previous frame on the current frame, thereby further improving the FFR performance of the display panel 100. For example, the effective level of the first initialization signal can be any one of -8V, -7.5V, -7V, and 6V.

[0071] The following uses a P-type transistor as an example to illustrate some embodiments of this disclosure, but the embodiments of this disclosure are not limited thereto.

[0072] In some embodiments, such as Figure 7 , Figure 8 and Figure 9As shown, a data refresh cycle also includes a data writing phase P2, which is located between the reset phase P1 and the light emission phase P3. The data writing phase P2 includes an initialization sub-phase P21 and a data refresh sub-phase P22. The pixel circuit 110 also includes a data refresh sub-circuit 30 and a data writing sub-circuit 40.

[0073] The data refresh sub-circuit 30 is electrically connected to the first scan signal terminal G1, the data signal terminal D, and the fourth node N4. The data refresh sub-circuit 30 is configured to, during the data refresh sub-stage P22, transmit the data signal from the data signal terminal D to the fourth node N4 under the control of the first scan signal from the first scan signal terminal G1.

[0074] In some examples, such as Figure 8 As shown, the data refresh sub-circuit 30 includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first scan signal terminal G1, the first electrode of the third transistor T3 is electrically connected to the data signal terminal D, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4.

[0075] The data writing sub-circuit 40 is electrically connected to the second scan signal terminal G2, the first reference voltage signal terminal Vref1, the fourth node N4, and the first node N1. The data writing sub-circuit 40 is configured to, during the initialization sub-stage P21, under the control of the second scan signal from the second scan signal terminal G2, transmit the first reference voltage signal from the first reference voltage signal terminal Vref1 to the fourth node N4 and maintain the voltage between the fourth node N4 and the first node N1; and during the data refresh sub-stage P22, change the voltage of the first node P21 according to the voltage change of the fourth node P21.

[0076] In some examples, such as Figure 8 As shown, the data writing sub-circuit 40 includes a first transistor T1, a first storage capacitor C1, and a second storage capacitor C2. The control electrode of the first transistor T1 is electrically connected to the second scan signal terminal G2. The first electrode of the first transistor T1 is electrically connected to the first reference voltage signal terminal Vref1. The second electrode of the first transistor T1 is electrically connected to the fourth node N4. The first plate of the first storage capacitor C1 is electrically connected to the fourth node N4. The second plate of the first storage capacitor C1 is electrically connected to the first plate of the second storage capacitor C2, forming a fifth node N5. The second plate of the second storage capacitor C2 is electrically connected to the first node N1.

[0077] At this time, in the data refresh sub-stage P22, the data refresh sub-circuit 30, under the control of the first scan signal from the first scan signal terminal G1, transmits the data signal from the data signal terminal D to the fourth node N4. The data writing sub-circuit 40 changes the voltage of the first node P21 according to the voltage change of the fourth node P21, so as to write the data signal to the first node N1. This allows the control electrode of the driving transistor DT to write voltage signals with the same or different voltage values ​​in different data refresh cycles, thereby driving the light-emitting device 120 to display the same or different gray levels in different frame cycles, thus realizing dynamic image display.

[0078] In some embodiments, such as Figure 7 , Figure 8 and Figure 9 As shown, the pixel circuit 110 also includes a voltage regulator circuit 50, which is electrically connected to the fifth node N5, the third scan signal terminal G3, and the second reference voltage signal terminal Vref2. The voltage regulator circuit 50 is configured to, during the reset phase P1, under the control of the third scan signal from the third scan signal terminal G3, transmit the second reference voltage signal from the second reference voltage signal terminal Vref2 to the fifth node N5. The second reference signal has the opposite polarity to the first initialization signal.

[0079] At this time, during the reset phase P1, the first reset sub-circuit 20, under the control of the first reset signal from the first reset signal terminal R1, transmits the first initialization signal from the first initialization signal terminal VIN1 to the first node N1. The voltage regulator sub-circuit 50, under the control of the third scan signal from the third scan signal terminal G3, transmits the second reference voltage signal from the second reference voltage signal terminal Vref2 to the fifth node N5. By setting the polarity of the second reference signal to be opposite to that of the first initialization signal, the voltage difference across the second storage capacitor C2 can be increased, thereby amplifying the strong negative bias voltage of the first node N1. This ensures that the strong negative bias voltage of the first node N1 allows the driving transistor DT to fully capture holes, further reducing the impact of the threshold voltage residue from the previous frame on the current frame, thereby further improving the FFR performance of the display panel 100.

[0080] For example, the second reference voltage signal terminal Vref2 is electrically connected to the first power supply signal terminal VDD. In this case, the second reference voltage signal can be a stable positive voltage, and the signal port can be saved, reducing the design cost of the pixel circuit 110.

[0081] In some examples, the voltage regulator circuit 50 includes a fourth transistor T4, the control terminal of the fourth transistor T4 is electrically connected to the third scan signal terminal G3, the first terminal of the fourth transistor T4 is electrically connected to the second reference voltage signal terminal Vref2, and the second terminal of the fourth transistor T4 is electrically connected to the fifth node N5, which has the advantage of simple structure.

[0082] In other examples, such as Figure 8 As shown, the voltage regulator circuit 50 includes two fourth transistors T4 connected in series. The control terminals of both fourth transistors T4 are electrically connected to the third scan signal terminal G3. The first terminal of the first fourth transistor T4 is electrically connected to the second reference voltage signal terminal Vref2, and the second terminal of the second fourth transistor T4 is electrically connected to the fifth node N5. This reduces the risk of leakage current from the fifth node N5 through the voltage regulator circuit 50, thus helping to ensure the potential stability of the fifth node N5.

[0083] In some embodiments, such as Figure 7 , Figure 8 and Figure 9 As shown, the pixel circuit 110 also includes a compensation sub-circuit 60, a light emission control sub-circuit 70, and a second reset sub-circuit 80.

[0084] The compensation sub-circuit 60 is electrically connected to the first node N1, the third node N3, and the fourth scan signal terminal G4. The compensation sub-circuit 60 is configured to, during the data writing phase P2, under the control of the fourth scan signal from the fourth scan signal terminal G4, transmit the voltage from the third node N3 to the first node N1. In this way, during the data writing phase P2, the voltage of the third node N3 can be transmitted to the first node N1, thereby compensating for the threshold voltage of the driving transistor DT.

[0085] In some examples, the compensator circuit 60 includes a fifth transistor T5, the control terminal of the fifth transistor T5 is electrically connected to the fourth scan signal terminal G4, the first terminal of the fifth transistor T5 is electrically connected to the third node N3, and the second terminal of the fifth transistor T5 is electrically connected to the first node N1, which has the advantage of simple structure.

[0086] In other examples, such as Figure 8 As shown, the compensator sub-circuit 60 includes two fifth transistors T5 connected in series. The control terminals of both fifth transistors T5 are electrically connected to the fourth scan signal terminal G4. The first terminal of the first fifth transistor T5 is electrically connected to the third node N3, and the second terminal of the second fifth transistor T5 is electrically connected to the first node N1. This reduces the risk of leakage current from the first node N1 through the compensator sub-circuit 60, thus helping to ensure the potential stability of the first node N1.

[0087] Please continue reading. Figure 7 , Figure 8 and Figure 9The light-emitting control sub-circuit 70 is electrically connected to the third node N3, the enable signal terminal EM, and the sixth node N6. The sixth node N6 is electrically connected to the light-emitting device 120, which is also electrically connected to the second power supply signal terminal VSS. The light-emitting control sub-circuit 70 is configured to transmit the voltage of the third node N3 to the sixth node N6 under the control of the enable signal from the enable signal terminal EM during the light-emitting phase P3.

[0088] In some examples, such as Figure 8 As shown, the light emission control sub-circuit 70 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is electrically connected to the enable signal terminal EM. The first electrode of the sixth transistor T6 is electrically connected to the third node N3. The second electrode of the sixth transistor T6 is electrically connected to the sixth node N6.

[0089] Please continue reading. Figure 7 , Figure 8 and Figure 9 The second reset sub-circuit 80 is electrically connected to the sixth node N6, the second reset signal terminal R2, and the second initialization signal terminal VIN2. The second reset sub-circuit 80 is configured to, during the reset phase P1, transmit the second initialization signal from the second initialization signal terminal VIN2 to the sixth node N6 under the control of the second reset signal from the second reset signal terminal R2.

[0090] In some examples, such as Figure 8 As shown, the second reset sub-circuit 80 includes a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the second reset signal terminal R2, the first terminal of the seventh transistor T7 is electrically connected to the second initialization signal terminal VIN2, and the second terminal of the seventh transistor T7 is electrically connected to the sixth node N6.

[0091] The pixel circuit 110 provided in the embodiments of this disclosure can fully reset the control electrode of the driving transistor DT before the data writing stage P2, thereby enabling the driving transistor DT to fully capture charge carriers and shortening the relaxation time of the threshold voltage of the driving transistor DT. Furthermore, this ensures that the threshold voltage of the driving transistor DT is nearly stable before the light-emitting stage P3, improving the hysteresis phenomenon of the driving transistor DT and enhancing the first-frame response performance of the display panel 100. For example, when the duration of the effective level of the first reset signal is 16 line cycles, the brightness difference between the first and second frames after screen refresh is approximately 4.2%, improving the first-frame response performance of the display panel 100 and reducing the risk of screen flickering perceptible to the human eye.

[0092] In some embodiments, the plurality of light-emitting devices 120 include a first light-emitting device, a second light-emitting device, and a third light-emitting device. The first light-emitting device is configured to emit red light to form a first sub-pixel. The second light-emitting device is configured to emit green light to form a second sub-pixel. The third light-emitting device is configured to emit blue light to form a third sub-pixel. The light-emitting layer 1221 includes a host material and a guest material; the guest material is different in the light-emitting layer 1221 of different colored light-emitting devices 120.

[0093] In some examples, the host material is the same in the light-emitting layer 1221 of the light-emitting devices 120 of different colors. For example, the host material includes at least one of 4,4'-bis(N-carbazolyl)-1,1'-biphenyl (CBP) or tris(8-hydroxyquinoline)aluminum (Alq3).

[0094] In some examples, the guest material in the light-emitting layer 1221 of the first light-emitting device includes bis(1-phenylisoquinoline)iridium (acetylacetonate) (Ir(piq)2(acac)). In the light-emitting layer 1221 of the second light-emitting device, the guest material includes tris(2-phenylpyridine)iridium (Ir(ppy)3). In the light-emitting layer 1221 of the third light-emitting device, the guest material includes bis(4,6-difluorophenylpyridine-C2,N)pyridineformyliridium (FIrpic).

[0095] It is understandable that the guest material is a metal-organic complex, and its molecular structure contains polar coordinate bonds, which makes the dielectric constant of the guest material higher than that of the host material.

[0096] For example, in the light-emitting layer 1221 of the second light-emitting device, the doping ratio of the guest material ranges from 0.4% to 1.0%. Since green light accounts for approximately 70% of the brightness in white light, reducing the doping ratio of the guest material in the second light-emitting device can reduce the parasitic capacitance of the second light-emitting device, thereby increasing its charging and discharging speed. Furthermore, this can improve the FFR performance of the display panel 100 and enhance its display quality.

[0097] For example, in the light-emitting layer 1221 of the second light-emitting device, the doping ratio of the guest material is any one of 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9% and 1% to reduce the parasitic capacitance of the second light-emitting device.

[0098] For example, in the light-emitting layer 1221 of the first light-emitting device, the doping ratio of the guest material ranges from 2.0% to 3.0%; and / or, in the light-emitting layer 1221 of the third light-emitting device, the doping ratio of the guest material ranges from 1.5% to 3.0%. In this case, the FFR performance of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be improved simultaneously, thereby reducing the risk of color deviation in the displayed image.

[0099] For example, in the light-emitting layer 1221 of the first light-emitting device, the doping ratio of the guest material is any one of 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, and 3%. In the light-emitting layer 1221 of the third light-emitting device, the doping ratio of the guest material is any one of 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.3%, 2.5%, 2.8%, and 3%. In this case, the FFR performance of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be improved simultaneously, thereby reducing the risk of color deviation in the displayed image.

[0100] In the light-emitting device 120 provided in the embodiments of this disclosure, when the doping ratio of the guest material in the light-emitting layer 1221 of the first light-emitting device is 2.0%, the doping ratio of the guest material in the light-emitting layer 1221 of the second light-emitting device is 0.4%, and the doping ratio of the guest material in the light-emitting layer 1221 of the third light-emitting device is 1.5%, the parasitic capacitance of the light-emitting device 120 can be reduced by about 15% to 20%. Furthermore, the charging and discharging time of the corresponding pixel circuit 110 can be shortened by about 20%, that is, the brightness of the first frame can reach a stable value faster, thereby improving the FFR performance of the display panel 100.

[0101] In some embodiments, the thickness of the light-emitting layer 1221 of the first light-emitting device and the thickness of the light-emitting layer 1221 of the second light-emitting device are both greater than the thickness of the light-emitting layer 1221 of the third light-emitting device. In this case, since the turn-on voltage of the third light-emitting device is higher than that of the first and second light-emitting devices, the FFR performance of the third light-emitting device is superior to that of the first and second light-emitting devices. By making the thickness of the light-emitting layer 1221 of the first and second light-emitting devices both greater than that of the third light-emitting device, the parasitic capacitance of the first and second light-emitting devices can be reduced, thereby improving the FFR performance of the first and second light-emitting devices. This results in a more balanced FFR performance between the first and second light-emitting devices and the third light-emitting device, thus improving the color shift phenomenon of the display panel 100.

[0102] For example, the thickness H of the light-emitting layer 1221 in the direction perpendicular to the substrate 11 ranges from 20 nm to 50 nm. For instance, the thickness of the light-emitting layer 1221 of the first light-emitting device is 50 nm, the thickness of the light-emitting layer 1221 of the second light-emitting device is 50 nm, and the thickness of the light-emitting layer 1221 of the third light-emitting device is 30 nm.

[0103] As shown in Table 1 below, in the prior art, the FFR of white light W in the display panel is 27%, the FFR of red light R is 30%, the FFR of green light G is 22%, and the FFR of blue light B is 68%.

[0104] On the one hand, by extending the duration of the effective level of the first reset signal to 16 line cycles, the FFR of the white light W of the display panel is increased to 47%, the FFR of the red light R to 55%, the FFR of the green light G to 42%, and the FFR of the blue light B to 78%. That is, the overall FFR of the display panel 100 is improved.

[0105] On the other hand, by adjusting the doping ratio and thickness of the guest material in the light-emitting layer, the FFR of white light W in the display panel is increased to 43%, the FFR of red light R to 48%, the FFR of green light G to 39%, and the FFR of blue light B to 73%. This balances the FFR performance of the first light-emitting device R, the second light-emitting device G, and the third light-emitting device B to a certain extent, thus improving the color shift phenomenon of the display panel 100.

[0106] Furthermore, by simultaneously extending the effective level of the first reset signal and adjusting the doping ratio and thickness of the guest material in the light-emitting layer, the FFR of white light W, red light R, green light G, and blue light B in the display panel is increased to 75%, 75%, 74%, and 78%, respectively. This significantly improves the overall FFR performance of the display panel 100, reduces the FFR difference between different colors to 4%, and simultaneously improves the color shift phenomenon of the display panel 100.

[0107] Table 1

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel circuit for driving a light-emitting device; A data refresh cycle includes a reset phase and a light emission phase arranged sequentially; characterized in that, The pixel circuit includes: A driving transistor is provided, wherein the control electrode of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a second node, and the second electrode of the driving transistor is electrically connected to a third node; one of the second node and the third node is coupled to a first power signal terminal, and the other is coupled to a second power signal terminal; the first power signal terminal is configured to output a positive power signal, and the second power signal terminal is configured to output a negative power signal; the driving transistor is a low-temperature polycrystalline silicon transistor. A first reset sub-circuit is electrically connected to the first node, a first reset signal terminal, and a first initialization signal terminal; the first reset sub-circuit is configured to, during the reset phase, transmit a first initialization signal from the first initialization signal terminal to the first node under the control of a first reset signal from the first reset signal terminal. Wherein, the duration of the effective level of the first reset signal is greater than or equal to 5 line cycles.

2. The pixel circuit according to claim 1, characterized in that, The amplitude range of the first initialization signal is 6V~8V.

3. The pixel circuit according to claim 1, characterized in that, One of the data refresh cycles further includes a data writing phase, which is located between the reset phase and the light emission phase; the data writing phase includes an initialization sub-phase and a data refresh sub-phase; the pixel circuit further includes: A data refresh sub-circuit is electrically connected to a first scan signal terminal, a data signal terminal, and a fourth node; the data refresh sub-circuit is configured to, during the data refresh sub-stage, transmit a data signal from the data signal terminal to the fourth node under the control of a first scan signal from the first scan signal terminal; A data writing sub-circuit is electrically connected to the second scan signal terminal, the first reference voltage signal terminal, the fourth node, and the first node. The data writing sub-circuit is configured to, during the initialization sub-stage, under the control of the second scan signal from the second scan signal terminal, transmit the first reference voltage signal from the first reference voltage signal terminal to the fourth node and maintain the voltage between the fourth node and the first node; and, during the data refresh sub-stage, change the voltage of the first node according to the voltage change of the fourth node.

4. The pixel circuit according to claim 3, characterized in that, The data writing sub-circuit includes a first transistor, a first storage capacitor, and a second storage capacitor. The control electrode of the first transistor is electrically connected to the second scan signal terminal, the first electrode of the first transistor is electrically connected to the first reference voltage signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node. The first plate of the first storage capacitor is electrically connected to the fourth node, and the second plate of the first storage capacitor is electrically connected to the first plate of the second storage capacitor, forming a fifth node. The second plate of the second storage capacitor is electrically connected to the first node.

5. The pixel circuit according to claim 4, characterized in that, Also includes: A voltage regulator circuit is electrically connected to the fifth node, the third scan signal terminal, and the second reference voltage signal terminal; the voltage regulator circuit is configured to, during the reset phase, transmit the second reference voltage signal from the second reference voltage signal terminal to the fifth node under the control of the third scan signal from the third scan signal terminal. The second reference signal has the opposite polarity to the first initialization signal.

6. The pixel circuit according to claim 5, characterized in that, The driving transistor is a P-type transistor; the second reference voltage signal terminal is electrically connected to the first power supply signal terminal.

7. The pixel circuit according to claim 3, characterized in that, Also includes: The compensation sub-circuit is electrically connected to the first node, the third node, and the fourth scan signal terminal; The compensation sub-circuit is configured to, during the data writing phase, transmit the voltage from the third node to the first node under the control of the fourth scan signal from the fourth scan signal terminal; The light-emitting control sub-circuit is electrically connected to the third node, the enable signal terminal, and the sixth node, and the sixth node is electrically connected to the light-emitting device. The light emission control sub-circuit is configured to, during the light emission phase, transmit the voltage of the third node to the sixth node under the control of an enable signal from the enable signal terminal. The second reset sub-circuit is electrically connected to the sixth node, the second reset signal terminal, and the second initialization signal terminal; the second reset sub-circuit is configured to, during the reset phase, transmit the second initialization signal from the second initialization signal terminal to the sixth node under the control of the second reset signal from the second reset signal terminal.

8. A display panel, characterized in that, include: Substrate; A pixel circuit layer is disposed on one side of the substrate; the pixel circuit layer includes a plurality of pixel circuits as described in any one of claims 1 to 7 above; A light-emitting device layer is disposed on the side of the pixel circuit layer away from the substrate; the light-emitting device layer includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the pixel circuit.

9. The display panel according to claim 8, characterized in that, Along a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting portion, and a second electrode; the light-emitting portion includes a light-emitting layer. The plurality of light-emitting devices include a first light-emitting device, a second light-emitting device, and a third light-emitting device, wherein the first light-emitting device is configured to emit red light, the second light-emitting device is configured to emit green light, and the third light-emitting device is configured to emit blue light; The thickness of the light-emitting layer of the first light-emitting device and the thickness of the light-emitting layer of the second light-emitting device are both greater than the thickness of the light-emitting layer of the third light-emitting device.

10. The display panel according to claim 8 or 9, characterized in that, Along a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting portion, and a second electrode; the light-emitting portion includes a light-emitting layer; the light-emitting layer includes a host material and a guest material; The plurality of light-emitting devices include a first light-emitting device, a second light-emitting device, and a third light-emitting device, wherein the first light-emitting device is configured to emit red light, the second light-emitting device is configured to emit green light, and the third light-emitting device is configured to emit blue light; In the light-emitting layer of the second light-emitting device, the doping ratio of the guest material ranges from 0.4% to 1.0%.

11. The display panel according to claim 10, characterized in that, In the light-emitting layer of the first light-emitting device, the doping ratio of the guest material ranges from 2.0% to 3.0%; and / or, in the light-emitting layer of the third light-emitting device, the doping ratio of the guest material ranges from 1.5% to 3.0%.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 8 to 11.

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