Array substrate and display panel

Abstract

The embodiment of the present application discloses an array substrate and a display panel, the array substrate comprises at least one gate drive circuit, the gate drive circuit comprises a plurality of cascaded shift registers, a shielding part is arranged close to the side of the substrate of the channel region of at least part of the transistors in the shift register, the channel region of the transistor is shielded, or the electric field is shielded, or the channel region of the transistor is used as the second gate of the transistor, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for display quality.

[0003] However, the existing display panels have poor display quality and are unable to meet display requirements. Summary of the Invention

[0004] This invention provides an array substrate and a display panel to improve display performance.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate including at least one gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including a first output transistor, and the array substrate further including a substrate, an active layer and a first shielding portion.

[0006] An active layer is disposed on one side of the substrate, the channel region of the first output transistor is located in the active layer, the first terminal of the first output transistor is connected to the first signal line, and the second terminal of the first output transistor is connected to the output terminal of the shift register.

[0007] The first shielding portion is located on the active layer near the substrate side, and the orthographic projection of the first shielding portion on the substrate covers the orthographic projection of the channel region of the first output transistor on the substrate.

[0008] Optionally, the shift register further includes a first capacitor, the first plate of which is connected to the first gate of the first output transistor, and the second plate of which is connected to the first terminal of the first output transistor.

[0009] The first plate of the first capacitor is located on the side of the first shielding portion away from the substrate, and the second plate of the first capacitor is located on the side of the first plate of the first capacitor away from the substrate.

[0010] Optionally, the first plate of the first capacitor is reused as the first gate of the first output transistor.

[0011] Optionally, the orthographic projection of the first shielding portion on the substrate at least partially overlaps with the orthographic projection of the first plate of the first capacitor on the substrate, and the first shielding portion is connected to the first gate of the first output transistor.

[0012] Optionally, the first plate of the first capacitor includes a first sub-section, the orthographic projection of the first sub-section on the substrate does not overlap with the orthographic projection of the active layer on the substrate, and the orthographic projection of the first sub-section on the substrate at least partially overlaps with the orthographic projection of the first shielding portion on the substrate.

[0013] Optionally, the orthographic projection of the second plate of the first capacitor onto the substrate at least partially overlaps with the orthographic projection of the channel region of the first output transistor onto the substrate.

[0014] Optionally, along the first width direction, the size of the first blocking portion is larger than the size of the first gate of the first output transistor, wherein the first width direction is perpendicular to the extension direction of the first gate of the first output transistor.

[0015] Optionally, the shift register further includes a second output transistor, the first terminal of which is connected to a second voltage signal line, and the second terminal of which is connected to the output terminal of the shift register.

[0016] The array substrate also includes a second shielding portion, the orthographic projection of which covers the channel region of the second output transistor on the substrate.

[0017] Optionally, the second blocking portion is connected to the first gate of the second output transistor; Optionally, a clock signal or a second fixed voltage signal is transmitted on the second signal line; Optionally, a first fixed voltage signal is transmitted on the first signal line.

[0018] Optionally, the shift register further includes a second capacitor, the first plate of which is connected to the first gate of the second output transistor, and the second plate of which is connected to the second terminal of the second output transistor. The first plate of the second capacitor is located on the side of the active layer of the second output transistor away from the substrate; Optionally, the first plate of the second capacitor is disposed on the same layer as the first gate of the second output transistor, and the first plate of the second capacitor and the first gate of the second output transistor are connected as an integral structure. Optionally, the second plate of the second capacitor is connected to the second electrode of the second output transistor via the first connecting portion; Optionally, the orthographic projection of the second plate of the second capacitor onto the substrate does not overlap with the orthographic projection of the channel region of the second output transistor onto the substrate; Optionally, the orthographic projection of the second shielding portion on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.

[0019] Optionally, the channel region of the second output transistor includes a plurality of spaced sub-channel regions, and the first gate of the second output transistor includes a plurality of sub-gates, wherein the orthographic projection of the sub-gates on the substrate overlaps with the orthographic projection of a corresponding sub-channel region on the substrate. Preferably, the second shielding portion includes a plurality of spaced sub-shielding portions, and the orthographic projection of each sub-shielding portion on the substrate covers the orthographic projection of a sub-channel region on the substrate. Preferably, along the second width direction, the size of the sub-shielding portion is larger than the size of the sub-gate, wherein the second width direction is perpendicular to the extension direction of the first gate of the second output transistor.

[0020] Optionally, the active layer includes at least one of a first active layer and a second active layer, wherein the material of the first active layer includes polycrystalline silicon semiconductor and the material of the second active layer includes metal oxide semiconductor. In this case, the channel region of the transistor in the shift register is located in at least one of the first active layer and the second active layer; Optionally, the channel regions of all transistors in the shift register are located in the first active layer; or, the channel regions of all transistors in the shift register are located in the second active layer; or, the channel regions of some transistors in the shift register are located in the first active layer, and the channel regions of other transistors are located in the second active layer. Optionally, the first active layer and the second active layer are configured as separate layers; Optionally, the second active layer is located on the side of the first active layer away from the substrate; Optionally, the carrier mobility of the second active layer is greater than 20 cm⁻¹. 2 / V·s. Optionally, the material of the second active layer includes a crystalline oxide semiconductor; Optionally, the material of the second active layer includes indium gallium oxide.

[0021] Optionally, the material of the second active layer includes amorphous oxide semiconductor; Optionally, the second active layer includes a first sub-active layer and a second sub-active layer, and the carrier mobilities of the first sub-active layer and the second active layer are different; Optionally, the indium content in the first sub-active layer material is less than the indium content in the second sub-active layer material; Optionally, the material of the first sub-active layer includes indium gallium zinc oxide, and the material of the second sub-active layer includes at least one of indium zinc oxide and indium tin zinc oxide.

[0022] Optionally, the shift register further includes a first input transistor, the first terminal of which is connected to a start signal; The array substrate also includes a third shielding portion, the orthographic projection of which covers the orthographic projection of the channel region of the first input transistor on the substrate. Optionally, the third shielding portion is located on the side of the channel region of the first input transistor away from the substrate, and the third shielding portion is connected to the first gate of the first input transistor; Optionally, the shift register further includes a protection transistor connected between the first input transistor and the second output transistor, with the first terminal of the protection transistor connected to the second terminal of the first input transistor and the second terminal of the protection transistor connected to the first gate of the second output transistor. The array substrate also includes a fourth shielding portion, the orthographic projection of which covers the channel region of the transistor on the substrate. Optionally, the fourth shielding portion is located on the side of the channel region of the protection transistor away from the substrate, and the fourth shielding portion is connected to the first gate of the protection transistor.

[0023] Optionally, the shift register further includes a first switching transistor, wherein the width-to-length ratio of the channel region of the first switching transistor is smaller than the width-to-length ratio of the channel region of the first output transistor, and the channel region of the first switching transistor does not overlap with the film layer where the first shielding portion is located. Optionally, the channel region of the first switching transistor and the channel region of the first output transistor are disposed on the same layer; Optionally, the area of ​​the channel region of the first switching transistor is smaller than the area of ​​the channel region of the first output transistor.

[0024] Optionally, the array substrate further includes at least one pixel circuit, which includes a driving transistor; The array substrate also includes a first gate portion, which is located on the side of the channel region of the driving transistor close to the substrate. The orthogonal projection of the first gate portion on the substrate covers the orthogonal projection of the channel region of the driving transistor on the substrate. Optionally, the voltage applied to the first gate portion is different from the voltage applied to the first shielding portion; Optionally, the first gate portion is connected to the first power supply line.

[0025] Optionally, the active layer includes a first active layer, the channel region of the driving transistor is located in the first active layer, and the material of the first active layer includes polycrystalline silicon semiconductor material; Optionally, the channel region of the first output transistor is located in the first active layer, and the first gate portion and the first shielding portion are disposed in the same layer.

[0026] Optionally, the active layer includes a second active layer, the channel region of the driving transistor is located in the second active layer, and the material of the second active layer includes a metal oxide semiconductor material. The pixel circuit also includes a second switching transistor, the channel region of which is located in the second active layer; The array substrate also includes a second gate portion, which is located on the side of the channel region of the second switching transistor near the substrate. The orthogonal projection of the second gate portion on the substrate covers the orthogonal projection of the channel region of the second switching transistor on the substrate. Preferably, the channel region of the first output transistor is located in the second active layer, and at least one of the first gate portion and the second gate portion is disposed in the same layer as the first shielding portion.

[0027] Optionally, the active layer includes a first active layer and a second active layer, wherein the first active layer and the second active layer are configured as separate layers; The channel region of the driving transistor is located in the second active layer; The channel region of the first output transistor is located in the first active layer, and the first gate portion and the first shielding portion are disposed in different layers. Optionally, the material of the first active layer includes polycrystalline silicon semiconductor material, and the material of the second active layer includes metal oxide semiconductor material.

[0028] Optionally, the pixel circuit also includes a second switching transistor, the channel region of which is located in the second active layer; The array substrate also includes a second gate portion, which is located on the side of the channel region of the second switching transistor near the substrate. The orthogonal projection of the second gate portion on the substrate covers the orthogonal projection of the channel region of the second switching transistor on the substrate. Optionally, the second gate portion is connected to the first gate of the second switching transistor.

[0029] Optionally, the first gate portion and the second gate portion are disposed in different layers; Optionally, along the thickness direction of the array substrate, the vertical distance between the channel region of the driving transistor and the first gate portion is smaller than the vertical distance between the channel region of the second switching transistor and the second gate portion. Optionally, the shift register includes a first type of transistor and a second type of transistor, wherein the channel region of the first type of transistor is located in the first active layer, and the channel region of the second type of transistor is located in the second active layer; The array substrate includes a second type of shielding portion, which is located on the side of the channel region of the second type of transistor near the substrate. The first gate portion and the second type of shielding portion are disposed in the same layer, or the second gate portion and the second type of shielding portion are disposed in the same layer; Optionally, the shielding portion is the second gate of the corresponding transistor.

[0030] According to another aspect of the present invention, an array substrate is provided, the array substrate including at least one gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including a first input transistor, the array substrate further including: a substrate, an active layer and a third shielding portion.

[0031] An active layer is disposed on one side of the substrate, the channel region of the first input transistor is located in the active layer, and the first electrode of the first input transistor is connected to the start signal line; The third shielding portion is located on the active layer near the substrate side, and the orthographic projection of the third shielding portion on the substrate covers the orthographic projection of the channel region of the first input transistor on the substrate.

[0032] Optionally, the shift register further includes a second input transistor and a first output transistor. The first terminal of the second input transistor is connected to the second power supply line, and the second terminal of the second input transistor is connected to the first gate of the first output transistor. The channel region of the second input transistor is located in the active layer, and the channel region of the second input transistor does not overlap with the film layer where the third shielding part is located. Optionally, the channel region of the first input transistor and the channel region of the second input transistor are disposed on the same layer; Optionally, the aspect ratio of the channel region of the first input transistor is greater than the aspect ratio of the channel region of the second input transistor; Optionally, the area of ​​the channel region of the first input transistor is smaller than the area of ​​the channel region of the first output transistor, and the area of ​​the channel region of the second input transistor is smaller than the area of ​​the channel region of the first output transistor. Optionally, the area of ​​the channel region of the first input transistor is larger than the area of ​​the channel region of the second input transistor.

[0033] Optionally, the shift register includes a first switching transistor, wherein the channel region of the first switching transistor does not overlap with the film layer where the third shielding portion is located; Optionally, the channel region of the first switching transistor is disposed on the same layer as the channel region of the first input transistor; Optionally, the aspect ratio of the channel region of the first input transistor is greater than the aspect ratio of the channel region of the first switching transistor; Optionally, the area of ​​the channel region of the first input transistor is larger than the area of ​​the channel region of the first switching transistor.

[0034] According to another aspect of the present invention, an array substrate is provided, the array substrate including at least one gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including protection transistors, and the array substrate further including: a substrate, an active layer and a fourth shielding portion.

[0035] The active layer is disposed on one side of the substrate, and the channel region of the protective transistor is located in the active layer; The fourth shielding part is located on the active layer near the substrate. The orthogonal projection of the fourth shielding part on the substrate covers the orthogonal projection of the channel region of the transistor on the substrate.

[0036] Optionally, the shift register further includes a first input transistor and a second input transistor, wherein the first terminal of the first input transistor is connected to the start signal line, the second terminal of the first input transistor is connected to the first terminal of the protection transistor, and the first terminal of the second input transistor is connected to the second power supply line. The array substrate also includes a third shielding portion, which is located on the active layer near the substrate. The orthographic projection of the third shielding portion on the substrate covers the orthographic projection of the channel region of the first input transistor on the substrate. The channel region of the second input transistor is located in the active layer, and the channel region of the second input transistor does not overlap with the film layer where the third shielding part is located. Optionally, the aspect ratio of the channel region of the protection transistor is greater than the aspect ratio of the channel region of the second input transistor; Optionally, the aspect ratio of the channel region of the first input transistor is greater than the aspect ratio of the channel region of the second input transistor; Optionally, the area of ​​the channel region of the protection transistor is larger than the area of ​​the channel region of the second input transistor; Optionally, the area of ​​the channel region of the first input transistor is larger than the area of ​​the channel region of the second input transistor.

[0037] Optionally, the shift register includes a first switching transistor, wherein the channel region of the first switching transistor does not overlap with the film layer where the fourth shielding portion is located; Optionally, the channel region of the first switching transistor and the channel region of the protection transistor are disposed on the same layer; Optionally, the aspect ratio of the channel region of the protection transistor is greater than the aspect ratio of the channel region of the first switching transistor; Optionally, the area of ​​the channel region of the protection transistor is larger than the area of ​​the channel region of the first switching transistor.

[0038] According to another aspect of the present invention, an array substrate is provided. The array substrate includes at least one gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, the shift registers include a first output transistor and a first capacitor, and the array substrate further includes: a substrate, an active layer and a first shielding portion, the active layer is disposed on one side of the substrate, the channel region of the first output transistor is located in the active layer, the first electrode of the first output transistor is connected to a first signal line, and the second electrode of the first output transistor is connected to the output terminal of the shift register. The first plate of the first capacitor is located on the side of the first shielding portion away from the substrate. The first plate of the first capacitor is connected to the first gate of the first output transistor. The second plate of the first capacitor is connected to the first electrode of the first output transistor. The orthographic projection of the first shielding portion on the substrate at least partially overlaps with the orthographic projection of the first plate of the first capacitor on the substrate.

[0039] Optionally, the orthographic projection of the second plate of the first capacitor onto the substrate at least partially overlaps with the orthographic projection of the channel region of the first output transistor onto the substrate. Optionally, the first plate of the first capacitor is reused as the first gate of the first output transistor; Optionally, the first shielding portion is located on the side of the active layer closer to the substrate, and the orthographic projection of the first shielding portion on the substrate covers the orthographic projection of the channel region of the first output transistor on the substrate. Optionally, the first plate of the first capacitor includes a first sub-part, the orthographic projection of the first sub-part on the substrate does not overlap with the orthographic projection of the active layer on the substrate, and the orthographic projection of the first sub-part on the substrate at least partially overlaps with the orthographic projection of the first shielding part on the substrate. Optionally, along the first width direction, the size of the first blocking portion is larger than the size of the first gate of the first output transistor, wherein the first width direction is perpendicular to the extension direction of the first gate of the first output transistor.

[0040] Optionally, the shift register further includes a second output transistor, the first terminal of which is connected to a second signal line, and the second terminal of which is connected to the output terminal of the shift register; The array substrate also includes a second shielding portion, the orthographic projection of which covers the orthographic projection of the channel region of the second output transistor on the substrate. Optionally, the second blocking portion is connected to the first gate of the second output transistor; Optionally, a clock signal or a second fixed voltage signal is transmitted on the second signal line; Optionally, a first fixed voltage signal is transmitted on the first signal line.

[0041] Optionally, the shift register further includes a second capacitor, the first plate of which is connected to the first gate of the second output transistor, and the second plate of which is connected to the second terminal of the second output transistor. The first plate of the second capacitor is located on the side of the second shielding portion away from the substrate. Optionally, the first plate of the second capacitor is disposed on the same layer as the first gate of the second output transistor, and the first plate of the second capacitor and the first gate of the second output transistor are connected as an integral structure. Optionally, the second plate of the second capacitor is connected to the second electrode of the second output transistor via the first connecting portion; Optionally, the orthographic projection of the second plate of the second capacitor onto the substrate does not overlap with the orthographic projection of the channel region of the second output transistor onto the substrate; Optionally, the orthographic projection of the second shielding portion on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.

[0042] According to another aspect of the present invention, a display panel is provided, the display panel including the array substrate provided in any embodiment of the present invention.

[0043] The technical solution provided in this embodiment provides a shielding portion on the side of the channel region of at least some transistors in the gate driving circuit that is close to the substrate. This shields the channel region of the transistor, or provides electric field shielding, or serves as the second gate of the transistor, which is beneficial to improving the display effect.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a shift register provided in an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present invention; Figure 5 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 6 A schematic diagram of another planar structure of an array substrate provided in an embodiment of the present invention; Figure 7 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 8 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 9 A schematic diagram of another planar structure of an array substrate provided in an embodiment of the present invention; Figure 10 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 12 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 14 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 15This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 16 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 17 A cross-sectional view of another array substrate provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] Figure 1 This is a schematic diagram of a shift register provided in an embodiment of the present invention. Figure 2 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention, combined with... Figure 1 and Figure 2The array substrate provided in this embodiment includes at least one gate driving circuit. The gate driving circuit includes multiple cascaded shift registers. Each shift register includes a first input module 110, a second input module 120, and an output module 200. The input terminal of the first input module 110 is connected to a start signal SIN, and the output terminal of the first input module 110 is connected to a first control terminal of the output module 200. The input terminal of the second input module 120 is connected to a second voltage signal VGL, and the output terminal of the second input module 120 is connected to a second control terminal of the output module 200. The first input terminal of the output module 200 is connected to a first power supply signal VGH, and the second input terminal of the output module 200 is connected to either the second voltage signal VGL or a second clock signal SCK2 (here, different signals can be selected to be connected to the second input terminal of the output module 200 depending on the specific architecture of the shift register). The output terminal of the output module 200 is used to output a gate driving signal GN. Each of the first input module 110, the second input module 120, and the output module 200 includes a corresponding transistor. The first voltage signal VGH can be provided by a first signal line, and the second voltage signal VGL can be provided by a second signal line.

[0050] The array substrate also includes a substrate 101, an active layer 20, and a shielding portion 10.

[0051] The active layer 20 is disposed on one side of the substrate 101, and the channel region of the transistor is located in the active layer 20.

[0052] The shielding portion 10 is located on the side of the active layer 20 near the substrate 101. The orthographic projection of the shielding portion 10 on the substrate 101 covers the orthographic projection of at least a portion of the channel region of the transistor on the substrate 101. A first insulating layer 102 is disposed between the shielding portion 10 and the active layer 20, and a second insulating layer 103 is disposed on the side of the active layer 20 away from the substrate 101.

[0053] The technical solution provided in this embodiment provides a shielding portion 10 on the side of the channel region of at least some transistors in the gate driving circuit that is close to the substrate 101. This shields the channel region of the transistor from light or electric field, or serves as the second gate of the transistor. This reduces the influence of external factors such as ambient light or electric field from the substrate 101 side on the display driving, for example, avoiding the generation of photogenerated carriers, thereby eliminating problems such as increased leakage current in the off-state of the transistor and threshold voltage drift. This improves the display quality problems caused by ESD, copper rod friction, and external light, and is beneficial to improving the display effect.

[0054] Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 3Based on the above embodiments, optionally, the output module 200 includes a first output transistor Q1, the first terminal of the first output transistor Q1 is connected to a first signal line, and the second terminal of the first output transistor Q1 is connected to the output terminal of the shift register.

[0055] Combination Figure 2 and Figure 3 The shielding portion 10 includes a first shielding portion 11. The channel region of the first output transistor Q1 is located in the active layer 20. The first shielding portion 11 is disposed on the side of the channel region of the first output transistor Q1 near the substrate 101. The orthographic projection of the first shielding portion 11 on the substrate 101 covers the orthographic projection of the channel region of the first output transistor Q1 on the substrate 101, so that the first shielding portion 11 can completely block the influence of the light on the substrate 101 side on the channel region of the first output transistor Q1. This helps to reduce the off-state leakage current of the first output transistor Q1, effectively prevents the phenomenon of threshold voltage drift caused by light, thereby improving the waveform quality of the shift register output gate drive signal GN, and thus improving the display effect.

[0056] Figure 4 This is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present invention. Figure 5 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 4 The cross-sectional structure of the array substrate shown is obtained along the cutting line AA', combined with Figures 3 to 5 The shift register also includes a first capacitor C1. The first plate 31 of the first capacitor C1 is connected to the first gate 301 of the first output transistor Q1, and the second plate 32 of the first capacitor C1 is connected to the first terminal of the first output transistor Q1 (not shown in the figure). The first plate 31 of the first capacitor C1 is located on the side of the first shielding portion 11 away from the substrate 101, and the second plate 32 of the first capacitor C1 is located on the side of the first plate 31 of the first capacitor C1 away from the substrate 101. For example, the first plate 31 of the first capacitor C1 and the first gate 301 of the first output transistor Q1 are disposed in the same layer, which is beneficial for reducing the film thickness of the array substrate.

[0057] In one optional embodiment provided in this example, the first plate 31 of the first capacitor C1 is multiplexed as the first gate 301 of the first output transistor Q1. The orthographic projection of the first plate 31 of the first capacitor C1 on the substrate 101 overlaps with the orthographic projection of the active layer 20 on the substrate 101 to form the channel region of the first output transistor Q1. The orthographic projection of the first shielding portion 11 on the substrate 101 at least partially overlaps with the orthographic projection of the first plate 31 of the first capacitor C1 on the substrate. The first shielding portion 11 is connected to the first gate 301 of the first output transistor Q1. That is, the first shielding portion 11 and the first plate 31 of the first capacitor C1 are at the same potential, avoiding the generation of parasitic capacitance between the first shielding portion 11 and the first plate 31 of the first capacitor C1, which would affect the performance of the shift register.

[0058] Since the first plate 31 of the first capacitor C1 is multiplexed as the first gate 301 of the first output transistor Q1, and the width of the first gate 301 of the first output transistor Q1 is usually small, in order to ensure the capacitance value of the first capacitor C1, the first plate 31 of the first capacitor C1 needs to be extended to the outside of the active layer 20 to increase the overlap area between the first plate 31 and the second plate 32 of the first capacitor C1. Therefore, the orthographic projection of the first plate 31 of the first capacitor C1 on the substrate 101 and the orthographic projection of the active layer 20 on the substrate 101 have a non-overlapping portion. For example, the first plate 31 of the first capacitor C1 includes a first sub-part 311, the orthographic projection of the first sub-part 311 on the substrate 101 does not overlap with the orthographic projection of the active layer 20 on the substrate 101, and the orthographic projection of the first sub-part 311 on the substrate 101 at least partially overlaps with the orthographic projection of the first shielding part 11 on the substrate 101. In other words, the first shielding portion 11 extends below the position where the orthographic projections of the first electrode plate 31 of the first capacitor C1 and the active layer 20 on the substrate 101 do not overlap, so as to flatten the film layer below the first electrode plate 31 of the first capacitor C1 and facilitate the film formation of the first capacitor C1.

[0059] Optionally, the orthographic projection of the second plate 32 of the first capacitor C1 onto the substrate 101 at least partially overlaps with the orthographic projection of the channel region of the first output transistor Q1 onto the substrate 101. This is beneficial for increasing the overlap area between the first plate 31 and the second plate 32 of the first capacitor C1, thereby increasing the capacitance value of the first capacitor C1. Simultaneously, it also helps to reduce the area occupied by the first capacitor C1 in its own plate extension direction (e.g., the X direction). Here, the X direction can be a row direction, the Y direction can be a column direction, and the Z direction is the thickness direction of the array substrate.

[0060] In this embodiment, along the first width direction (i.e., the Y direction, which is perpendicular to the extension direction of the first gate 301 of the first output transistor Q1), the size of the first shielding portion 11 is larger than the size of the first gate 301 of the first output transistor Q1, which allows the first shielding portion 11 to completely cover the channel region of the first output transistor Q1, which is beneficial to eliminating edge optical leakage current.

[0061] In this embodiment, the active layer 20 may include a first active layer, and the material of the first active layer includes polycrystalline silicon semiconductor material.

[0062] like Figure 5 As shown, optionally, the array substrate further includes multiple conductive layers, including a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3. The first conductive layer M1 is located on the side of the first active layer 21 close to the substrate 101, the second conductive layer M2 is located on the side of the first active layer 21 away from the substrate 101, and the third conductive layer M3 is located on the side of the second conductive layer M2 away from the substrate 101.

[0063] The first shielding part 11 is located in the first conductive layer M1, the first electrode 31 of the first capacitor C1 is located in the second conductive layer M2, and the second electrode 32 of the first capacitor C1 is located in the third conductive layer M3.

[0064] Continue to refer to Figure 3 The shift register also includes a second output transistor Q2. The first terminal of the second output transistor Q2 is connected to a second signal line, and the second terminal of the second output transistor Q2 is connected to the output terminal of the shift register. The second signal line can also be used to transmit clock signals (not simultaneously transmitting a clock signal and a second fixed voltage signal; different signals can be transmitted using different second signal lines), such as the second clock signal SCK2.

[0065] A shielding portion 10 is also provided below the channel region of the second output transistor Q2. The orthographic projection of the shielding portion on the substrate 101 covers the orthographic projection of the channel region of the second output transistor Q2 on the substrate 101, so as to shield the channel region of the second output transistor Q2 and avoid adverse effects of factors such as light and electric field on the characteristics of the second output transistor Q2.

[0066] Figure 6 This is a schematic diagram of another planar structure of an array substrate provided in an embodiment of the present invention. Figure 6 Specifically, the structure is shown where the channel regions of the first output transistor Q1 and the second output transistor Q2 are arranged in the same layer, both located in the first active layer 21. Figure 7 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 6 The cross-sectional structure of the array substrate obtained along the cutting line BB' is referenced. Figure 6and Figure 7 In this embodiment, the channel region of the second output transistor Q2 includes multiple spaced sub-channel regions, which is beneficial to increasing the width-to-length ratio of the channel region of the second output transistor Q2 and increasing the driving capability of the second output transistor Q2. The first gate 302 of the second output transistor Q2 includes multiple sub-gates, and the orthographic projection of the sub-gate on the substrate 101 overlaps with the orthographic projection of a corresponding sub-channel region on the substrate.

[0067] The shielding portion 10 also includes a second shielding portion 12, which includes a plurality of spaced sub-shielding portions. The orthographic projection of each sub-shielding portion on the substrate 101 covers the orthographic projection of a sub-channel region on the substrate 101.

[0068] For example, such as Figure 7 As shown, the channel region of the second output transistor Q2 includes two spaced-apart sub-channel regions, which are disposed on the same layer. The first gate 302 of the second output transistor Q2 includes two sub-gates, namely a first sub-gate 3021 and a second sub-gate 3022. The second shielding portion 12 includes two spaced-apart sub-shielding portions, namely a first sub-shielding portion 121 and a second sub-shielding portion 122. The orthographic projection of each sub-shielding portion on the substrate 101 corresponds to the orthographic projection of a sub-channel region on the substrate 101. The two gate portions are connected together, and the two sub-shielding portions are connected together to ensure that the two gate portions are at the same potential and the two sub-shielding portions are at the same potential, thereby ensuring the stability of the characteristics of the second output transistor Q2.

[0069] In this configuration, the two sub-channel regions of the second output transistor Q2 share a common electrode. The first electrode 401 of the first output transistor Q1 is used to connect to the first voltage signal line. The second electrode 402 of the first output transistor Q1 is connected to the first electrode 403 of the second output transistor Q2 (they share a common electrode). The second electrode 404 of the second output transistor Q2 serves as the first terminal of the second output transistor Q2. The third electrode 405 of the second output transistor Q3 is connected to its first electrode 403 and together they serve as the second terminal of the second output transistor Q2.

[0070] Optionally, along the second width direction (the second width direction is perpendicular to the extension direction of the first gate 302 of the second output transistor Q2, i.e., the Y direction), the size of the sub-shielding part is larger than the size of the sub-gate, so as to ensure that the sub-shielding part can completely block the sub-gate and avoid adverse effects of factors such as light and electric field on the characteristics of the second output transistor Q2.

[0071] Figure 8 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 6 The cross-sectional structure of the array substrate obtained along the cutting line CC', reference Figure 3 , Figure 6 and Figure 8 Optionally, based on the above embodiments, the shift register further includes a second capacitor C2. The first plate 33 of the second capacitor C2 is connected to the first gate 302 of the second output transistor Q2, and the second plate 34 of the second capacitor C2 is connected to the second electrode of the second output transistor Q2. The first plate 33 of the second capacitor C2 is located on the side of the active layer 20 of the second output transistor Q2 away from the substrate 101, and the second plate 34 of the second capacitor C2 is located on the side of the first plate 33 of the second capacitor C2 away from the substrate 101. The second plate 34 of the second capacitor C2 is connected to the second electrode of the second output transistor Q2 through a first connection portion 41. This arrangement facilitates layout while ensuring the capacitance value of the second capacitor C2. The first connection portion 41 simultaneously connects the third electrode 405 and the first electrode 403 of the second output transistor Q3. The first connection portion 41 and each electrode are located in the fourth conductive layer M4.

[0072] Optionally, the first electrode plate 33 of the second capacitor C2 and the first gate 302 of the second output transistor Q2 are disposed on the same layer, which helps to reduce process steps and reduce costs; and the first electrode plate 33 of the second capacitor C2 and the first gate 302 of the second output transistor Q2 are connected as an integral structure, which helps to reduce the number of vias and improve process uniformity.

[0073] Optionally, the second capacitor C2 and the second output transistor Q2 are arranged along the X direction. The orthographic projection of the second electrode 34 of the second capacitor C2 onto the substrate 101 does not overlap with the orthographic projection of the channel region of the second output transistor Q2 onto the substrate 101. The orthographic projection of the second shielding portion 12 onto the substrate at least partially overlaps with the orthographic projection of the first electrode 33 of the second capacitor C2 onto the substrate 101. For example, the portion of the second shielding portion 12 extending to the outside of the channel region of the second output transistor Q2 overlaps with the first electrode 33 of the second capacitor C2, which helps to improve the flatness of the film layer below the second capacitor C2, thereby facilitating the film formation of the second capacitor C2.

[0074] In this embodiment, the active layer 20 may further include a second active layer, the material of which is different from that of the first active layer 21. For example, the material of the second active layer may include a metal oxide semiconductor material.

[0075] Figure 9 This is a schematic diagram of another planar structure of an array substrate provided in an embodiment of the present invention. Figure 10 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 9 The cross-sectional structure of the array substrate obtained along the cutting line DD', combined with Figure 9 and Figure 10The channel region of the first output transistor Q1 is located in the first active layer 21, and the channel region of the second output transistor Q2 is located in the second active layer 22. The first active layer 21 and the second active layer 22 are disposed in different layers, and the second active layer 22 is located on the side of the first active layer 21 away from the substrate 101. For example, the second shielding portion 12 is located in the fifth conductive layer M5 on the side of the third conductive layer M3 away from the substrate 101, the second active layer 22 is located on the side of the second shielding portion 12 away from the substrate 101, the first gate 302 of the second output transistor Q2 is located in the sixth conductive layer M6 on the side of the second active layer 22 away from the substrate 101, and the fourth conductive layer M4 is located in the sixth conductive layer M6 on the side of the sixth conductive layer M6 away from the substrate 101.

[0076] A third insulating layer 104 is disposed between the second conductive layer M2 and the third conductive layer M3; a fourth insulating layer 105 is disposed between the third conductive layer M3 and the fifth conductive layer M5; a sixth insulating layer 107 is disposed between the fifth conductive layer M5 and the second active layer 22; a seventh insulating layer 108 is disposed between the second active layer 22 and the sixth conductive layer M6; an eighth insulating layer 109 is disposed between the sixth conductive layer M6 and the fourth conductive layer M4; and a fifth insulating layer 106 is disposed on the side of the fourth conductive layer M4 away from the substrate 101.

[0077] Optionally, since the first active layer 21 and the second active layer 22 are configured in different layers, the second electrode of the first output transistor Q1 and the second electrode of the second output transistor Q2 cannot be directly connected, but need to be connected through the connection line located in the fourth conductive layer M4.

[0078] exist Figure 9 In the structure shown, the first plate 33 of the second capacitor C2 is also on the same layer as the first gate 302 of the second output transistor Q2 and is connected as an integral structure.

[0079] In this embodiment, the first blocking portion 11 is connected to the first gate 301 of the first output transistor Q1, and the second blocking portion 12 is connected to the first gate 302 of the second output transistor Q2. Here, the first blocking portion 11 can serve as the second gate of the first output transistor Q1, and the second blocking portion 12 can serve as the second gate of the second output transistor Q2. The first gate and the second gate of the transistor are short-circuited, that is, the first gate and the second gate of the transistor are at the same potential, which makes the threshold characteristics of the transistor more stable, which is beneficial to improving the driving capability of the transistor, thereby increasing the output current and improving the waveform quality of the gate drive signal GN. The first gate can be a top gate, and the second gate can be a bottom gate. Of course, in other embodiments, the first gate can also be a bottom gate, and the second gate can be a top gate.

[0080] Optionally, in this embodiment, the active layer 20 includes at least one of a first active layer 21 and a second active layer 22, and the channel regions of the transistors in the shift register are located in at least one of the first active layer 21 and the second active layer 22. For example, the channel regions of all transistors in the shift register are located in the first active layer 21; or, the channel regions of all transistors in the shift register are located in the second active layer 22; or, the channel regions of some transistors in the shift register are located in the first active layer 21, and the channel regions of other transistors are located in the second active layer 22.

[0081] Specifically, at least one of the channel regions of the first output transistor Q1 and the second output transistor Q2 is located in the first active layer 21. For example, the channel region of the first output transistor Q1 is located in the first active layer 21 and the channel region of the second output transistor Q2 is located in the second active layer 22; or, the channel region of the first output transistor Q1 is located in the second active layer 22 and the channel region of the second output transistor Q2 is located in the first active layer 21; or, the channel region of the first output transistor Q1 is located in the first active layer 21 and the channel region of the second output transistor Q2 is located in the first active layer 21.

[0082] Alternatively, at least one of the channel regions of the first output transistor Q1 and the second output transistor Q2 is located in the second active layer. For example, the channel region of the first output transistor Q1 is located in the first active layer 21, and the channel region of the second output transistor Q2 is located in the second active layer 22; or, the channel region of the first output transistor Q1 is located in the second active layer 22, and the channel region of the second output transistor Q2 is located in the first active layer 21; or, the channel region of the first output transistor Q1 is located in the second active layer 22, and the channel region of the second output transistor Q2 is located in the second active layer 22. Wherein, the carrier mobility of the second active layer is greater than 20 cm⁻¹. 2 / V·s.

[0083] Optionally, in one embodiment provided in this example, the material of the second active layer 22 includes a crystalline oxide semiconductor material. For example, the material of the second active layer 22 includes indium gallium oxide (IGO). IGO has a high proportion of In2O3, and indium provides a large number of conduction band electrons, resulting in a mobility much higher than that of traditional IGZO (Indium Gallium Zinc Oxide). It is particularly suitable for the fast charging and discharging requirements of high-resolution, high-refresh-rate panels, and can significantly improve the on-state current (Ion) of transistors and reduce pixel write time. Here, the second active layer 22 can be a single-layer active layer.

[0084] In another optional embodiment provided in this example, the material of the second active layer 22 may also include an amorphous oxide semiconductor material, such as indium gallium zinc oxide, indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). Here, the second active layer 22 can be a multilayer active layer, with at least two active layers having different carrier mobilities to improve the performance of the second active layer 22. Specifically, the second active layer 22 includes a first sub-active layer and a second sub-active layer, with different carrier mobilities. The first sub-active layer is made of indium gallium zinc oxide, and the second sub-active layer is made of at least one of indium zinc oxide and indium tin zinc oxide. For example, the second active layer 22 includes two first sub-active layers and one second sub-active layer, forming a three-layer stacked structure of IGZO / IZO / IGZO. The indium content in the first sub-active layer is lower than that in the second sub-active layer to reduce the mobility of the first sub-active layer. The top and bottom IGZO layers act as buffer layers, which helps improve transistor stability and suppress oxygen vacancy diffusion and interface traps. The middle IZO layer serves as a high-mobility core channel, providing high carrier mobility and high on-state current, ensuring the transistor's conduction capability. Through this three-layer structure of low mobility + high mobility + low mobility, the transistor achieves significantly improved stability and reduced off-state leakage current while maintaining high mobility. Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 11 The first input module 110 includes a first input transistor Q3, and the shift register also includes a protection module 130, which includes a protection transistor Q5. The first terminal of the first input transistor Q3 is connected to the start signal SIN, and the second terminal of the first input transistor Q3 is connected to the first terminal of the protection transistor Q5 (when the protection transistor Q5 is not set, the second terminal of the first input transistor Q3 is connected to the first gate of the second output transistor Q2), and the second terminal of the protection transistor Q5 is connected to the first gate of the second output transistor Q2.

[0085] The second input module 120 includes a second input transistor Q4, the first terminal of the second input transistor Q4 is connected to a second voltage signal VGL, and the second terminal of the second input transistor Q4 is connected to the first gate of the first output transistor Q1.

[0086] In this circuit, both the first input transistor Q3 and the second input transistor Q4 are turned on in response to the first clock signal SCK1, while the protection transistor Q5 is always on in response to the second voltage signal VGL.

[0087] Figure 12This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically showing the film structure of the first input transistor Q3 and the protection transistor Q5. (Refer to...) Figure 11 and 12 The channel region of the first input transistor Q3 is located in the first active layer 21. The array substrate also includes a third shielding portion 13. The orthogonal projection of the third shielding portion 13 on the substrate 101 covers the orthogonal projection of the channel region of the first input transistor Q3 on the substrate 101.

[0088] The channel region of the protection transistor Q5 is located in the first active layer 21. The array substrate also includes a fourth shielding portion 14, the orthographic projection of which covers the orthographic projection of the channel region of the protection transistor Q5 onto the substrate 101. Specifically, the third shielding portion 13 is located on the side of the channel region of the first input transistor Q3 away from the substrate 101, and the fourth shielding portion 14 is located on the side of the channel region of the protection transistor Q5 away from the substrate 101. For example, the third shielding portion 13 and the fourth shielding portion 14 are disposed in the same layer, both located in the first conductive layer. Alternatively, the channel regions of the first input transistor Q3 and the protection transistor Q5 are disposed in different layers (e.g., one is located in the first active layer 21, and the other is located in the second active layer 22), and the third shielding portion 13 and the fourth shielding portion 14 are also disposed in different layers. The third shielding portion 13 is connected to the first gate of the first input transistor Q3, and the fourth shielding portion 14 is connected to the first gate of the protection transistor Q5.

[0089] In this embodiment, at least some of the transistors in the shift register, including the first output transistor Q1, the second output transistor Q2, the first input transistor Q3, and the protection transistor Q5, are provided with corresponding shielding portions. The shielding portions serve as the second gates of the transistors and are at the same potential as the first gates, thereby achieving double-gate shielding of the transistors. This is beneficial for achieving electric field shielding, reducing off-state leakage current, and thus stabilizing the threshold characteristics of the transistors and the output waveform of the shift register.

[0090] Continue to refer to Figure 11 Optionally, the shift register further includes a first switching transistor, which can be any one of transistors Q4, Q6, Q7, and Q8 in the shift register. The first switching transistor is used to control the potential of the internal nodes of the shift register. The aspect ratio of the channel region of the first switching transistor is smaller than that of the channel region of the first output transistor Q1. Its off-state leakage current is smaller and its light sensitivity is lower. Therefore, a shielding part can be omitted on the side of the channel region of the first switching transistor near the substrate 101. That is, the channel region of the first switching transistor does not overlap with the film layer where the first shielding part 11 is located. This is beneficial for saving the area of ​​light-shielding metal, reducing capacitive coupling, improving light transmittance, and improving the panel aperture ratio and brightness.

[0091] Optionally, the channel region of the first switching transistor can be located in the first active layer 21 or the second active layer 22. In one optional embodiment, the channel region of the first switching transistor and the channel region of the first output transistor Q1 are disposed in the same layer. "Disposed in the same layer" here means that the channel regions of the first switching transistor and the first output transistor Q1 are obtained under the same film deposition process.

[0092] Optionally, since the first switching transistor is used for signal transmission and its current is relatively small, the area of ​​the channel region of the first switching transistor is set to be smaller than the area of ​​the channel region of the first output transistor Q1, so that the first switching transistor has the characteristics of high density and low parasitics, which is beneficial to reducing the layout area.

[0093] Optionally, the array substrate further includes at least one pixel circuit, wherein a gate driving circuit is connected to the pixel circuit, the gate driving circuit is used to transmit a gate driving signal GN to the pixel circuit, and the pixel circuit is used to drive the light-emitting element to emit light according to the gate driving signal GN, thereby realizing the display function. Here, the array substrate includes a display area and a non-display area disposed around the display area, the gate driving circuit is located in the non-display area, and the pixel circuit is located in the display area.

[0094] Figure 13 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 14 This is a schematic cross-sectional view of another array substrate provided in an embodiment of the present invention, with reference to... Figure 13 and Figure 14 The pixel circuit includes a driving transistor Q11. The first terminal of the driving transistor Q11 is connected to a first power supply line, and the second terminal of the driving transistor Q11 is connected to the first terminal of the light-emitting element D1. The second terminal of the light-emitting element D1 is connected to a second power supply line. The first power supply line is used to transmit a first power supply voltage VDD, and the second power supply line is used to transmit a second power supply voltage VSS.

[0095] The array substrate also includes a first gate portion 15, which is located on the side of the channel region of the driving transistor Q11 near the substrate 101. The orthographic projection of the first gate portion 15 on the substrate 101 covers the orthographic projection of the channel region of the driving transistor Q11 on the substrate 101, so as to shield the channel region of the driving transistor Q11 and prevent factors such as light and electric field from affecting the characteristics of the driving transistor Q11.

[0096] In this embodiment, the voltage connected to the first gate portion 15 is different from the voltage connected to the first shielding portion 11 and / or the second shielding portion 12. For example, both the first shielding portion 11 and the second shielding portion 12 are connected to the first gate of the corresponding transistor, while the first gate portion 15 is connected to the first terminal of the driving transistor Q11, that is, the first gate portion 15 is connected to the first power supply line. Here, the first gate portion 15 can also serve as the second gate of the driving transistor Q11. Setting the first gate portion 15 to be connected to a fixed potential (the first power supply voltage VDD) is beneficial to increasing the subthreshold swing of the driving transistor Q11 and improving the stability of the driving transistor Q11.

[0097] Optionally, refer to Figure 13 The pixel circuit also includes a second switching transistor, the channel region of which is located in the first active layer 21 or the second active layer 22. The second switching transistor can be any transistor in the pixel circuit other than the driving transistor Q11. For example, the data writing transistor Q12 is the second switching transistor. The first terminal of the data writing transistor Q12 is connected to the data signal Vdata, and the second terminal of the data writing transistor Q12 is connected to the first gate 501 of the driving transistor Q11. The data writing transistor Q12 is turned on in response to the first gate driving signal S1, transmitting the data signal Vdata to the first gate 501 of the driving transistor Q11.

[0098] The array substrate also includes a second gate portion 16, which is disposed on the side of the second switching transistor near the substrate 101. The second gate portion 16 is located on the side of the channel region of the second switching transistor near the substrate 101. The orthographic projection of the second gate portion 16 on the substrate 101 covers the orthographic projection of the channel region of the second switching transistor on the substrate 101, so as to shield the channel region of the second switching transistor.

[0099] Optionally, the second gate portion 16 is connected to the first gate of the second switching transistor, such as the second gate portion 16 being connected to the first gate 502 of the data writing transistor Q12. That is, the second gate portion 16 serves as the second gate of the data writing transistor Q12 and is connected to the first gate of the data writing transistor Q12, which helps to improve the reliability of the data writing transistor Q12 and makes the characteristics of the data writing transistor Q12 more stable.

[0100] Optionally, in one embodiment, the channel regions of the transistors in the pixel circuit and the transistors in the shift register can both be located in the first active layer 21. In this embodiment, taking the driving transistor Q11 in the pixel circuit and the first output transistor Q1 in the shift register as examples, the channel region of the driving transistor Q11 can be located in the first active layer 21, the channel region of the first output transistor Q1 is located in the first active layer 21, and the first gate portion 15 and the first shielding portion 11 are disposed in the same layer (e.g., both are located in the first conductive layer M1), which helps to reduce process steps and lower costs.

[0101] Alternatively, in another implementation, the channel regions of the transistors in the pixel circuit and the transistors in the shift register are both located in the second active layer 22. Figure 15 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 16 This is a schematic cross-sectional view of another array substrate provided in an embodiment of the present invention. Figure 16 Only the structures of some transistors in the pixel circuit and some transistors in the shift register are shown. (Refer to...) Figure 15 and Figure 16 The channel region of the driving transistor Q11 and the channel region of the second switching transistor (such as the data writing transistor Q12) are both located in the second active layer 22. The first gate portion 15 is located on the side of the channel region of the driving transistor Q11 near the substrate 101, and the orthogonal projection of the first gate portion 15 on the substrate 101 covers the orthogonal projection of the channel region of the driving transistor Q11 on the substrate 101. The second gate portion 16 is located on the side of the channel region of the second switching transistor near the substrate 101, and the orthogonal projection of the second gate portion 16 on the substrate 101 covers the orthogonal projection of the channel region of the second switching transistor on the substrate 101.

[0102] Optionally, at least one of the first gate portion 15 and the second gate portion 16 is disposed in the same layer as the first shielding portion 11.

[0103] refer to Figure 16In this embodiment, the first gate portion 15 and the second gate portion 16 are disposed in different layers. In the pixel circuit, along the thickness direction of the array substrate, the vertical distance between the channel region of the driving transistor Q11 and the first gate portion 15 is smaller than the vertical distance between the channel region of the second switching transistor and the second gate portion 16. For example, a ninth insulating layer 1091 is disposed between the first gate portion 15 and the second gate portion 16; a sixth insulating layer 107 is spaced between the channel region of the driving transistor Q11 and the first gate portion 15; and the channel region of the data writing transistor Q12 (the second switching transistor) is spaced between the sixth insulating layer 107 and the second gate portion 16, with the thickness of the sixth insulating layer 107 being less than the sum of the thicknesses of the sixth insulating layer 107 and the ninth insulating layer 1091. The purpose of this arrangement is to increase the subthreshold swing of the driving transistor Q11 while ensuring that the second switching transistor has a higher on-current and better bias temperature stress characteristics, ensuring that the characteristics of the second switching transistor do not deteriorate, and facilitating characteristic matching between the transistors.

[0104] In this embodiment, the first gate portion 15 or the second gate portion 16 is disposed on the same layer as the first shielding portion 11. That is, the first gate portion 15 and the second gate portion 16 are disposed on different layers. For the first output transistor Q1 in the shift register whose channel region is located on the second active layer 22, the first shielding portion 11 can be disposed on the same layer as the first gate portion 15 or the second gate portion 16, depending on the actual circuit characteristics.

[0105] Of course, in other embodiments, the vertical distance between the channel region of the driving transistor Q11 and the first gate portion 15 can also be equal to the vertical distance between the channel region of the second switching transistor and the second gate portion 16, that is, the first gate portion 15 and the second gate portion 16 are disposed on the same layer.

[0106] Alternatively, in another embodiment, the channel region of the transistor in the pixel circuit is located in the second active layer 22, and the channel region of the transistor in the shift register is located in the first active layer 21. Figure 17 This is a schematic cross-sectional view of another array substrate provided in an embodiment of the present invention, with reference to... Figure 17The channel region of the driving transistor Q11 is located in the second active layer 22, and the channel region of the first output transistor Q1 in the shift register is located in the first active layer 21. The first gate portion 15 and the first shielding portion 11 are disposed in different layers, such as the first gate portion 15 being located in the fifth conductive layer M5 and the first shielding portion 11 being located in the first conductive layer M1, so that the shielding portion is close to the channel region of the corresponding transistor, thereby better achieving the light-shielding effect. The first gate 501 of the driving transistor Q11 and the first gate 301 of the first output transistor Q1 are disposed in different layers, such as the first gate 301 of the first output transistor Q1 being located in the second conductive layer M2 and the first gate 501 of the driving transistor Q11 being located in the sixth conductive layer M6.

[0107] Optionally, in another embodiment, the channel regions of the transistors in the pixel circuit are located in the second active layer 22, the channel regions of some transistors in the shift register are located in the first active layer 21, and the channel regions of other transistors in the shift register are located in the second active layer 22. Exemplarily, the shift register includes a first type of transistor and a second type of transistor, with the channel regions of the first type of transistor located in the first active layer 21 and the channel regions of the second type of transistor located in the second active layer 22. The array substrate includes a first type of shielding portion and a second type of shielding portion. The first type of shielding portion is located on the side of the channel region of the first type of transistor near the substrate 101, and the second type of shielding portion is located on the side of the channel region of the second type of transistor near the substrate 101. The first gate portion 15 and the second type of shielding portion are disposed on the same layer, or the second gate portion 16 and the second type of shielding portion are disposed on the same layer, which will not be described further.

[0108] Furthermore, Figure 18 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. In this embodiment, the pixel circuit further includes a third switching transistor. The channel region of the third switching transistor is located in the first active layer 21. The channel region of the third switching transistor has no gate portion on the side near the substrate 101, which is beneficial to improving the light transmittance of the array substrate. For example, the third switching transistor may include a light-emitting control transistor Q13, which is a single-gate transistor that controls the on / off state of the current path in response to the light-emitting control signal EM. Here, the film structure of the third switching transistor can refer to the film structure of the transistor with the channel region located in the first active layer 21 in the above embodiment, and will not be described again.

[0109] Optionally, the pixel circuit further includes a storage capacitor Cst, the first terminal of which is connected to the first gate of the driving transistor Q11, and the second terminal of which is connected to the first power supply line. The first gate of the driving transistor Q11 can be reused as the first terminal of the storage capacitor Cst.

[0110] The above embodiments are only illustrated using the data writing transistor Q12 as an example, and are not intended to limit the architecture of the pixel circuit.

[0111] Optionally, the pixel circuit may also include other second switching transistors, and a second gate portion 16 may also be selectively disposed below the channel region of the other second switching transistors.

[0112] Optionally, the gate portion of the transistor in the pixel circuit whose channel region is located in the second active layer 22 is disposed in a different layer from the shielding portion of the transistor in the shift register whose channel region is located in the first active layer 21.

[0113] Optionally, at least a portion of the second active layer 22 in the pixel circuit is disposed on the same layer as the second active layer 22 in the shift register, which helps to reduce process steps, improve etching uniformity, and reduce costs.

[0114] The technical solution provided in this embodiment is that at least some transistors in the pixel circuit are second-type transistors (the channel region is located in the second active layer 22) or all transistors are first-type transistors (the channel region is located in the first active layer 21). At least some transistors in the shift register are second-type transistors (the channel region is located in the second active layer 22) or all transistors are first-type transistors (the channel region is located in the first active layer 21). By shielding or electric field-shielding the channel regions of at least some transistors (which can be second-type transistors or first-type transistors) in the pixel circuit and at least some transistors (which can be second-type transistors or first-type transistors) in the shift register, the influence of ambient light and electric field from the substrate 101 side on the display drive is reduced, avoiding the generation of photogenerated carriers. This eliminates problems such as increased leakage current in the off-state of transistors and threshold voltage drift, thereby improving the display quality problems caused by ESD, copper rod friction, and external light, which is beneficial to improving the display effect.

[0115] In one optional embodiment provided in this example, the second type of transistors (including driving transistor Q11 and at least some of the second switching transistors) in the pixel circuit are all provided with shielding portions. If all the transistors in the pixel circuit are first type transistors, then at least the driving transistor Q11 is provided with a corresponding first gate portion 15, and the first gate portion 15 is used as the second gate of the driving transistor Q11 to ensure the characteristic stability of the driving transistor Q11.

[0116] It should be understood that the shift registers and pixel circuits provided in the above embodiments are merely illustrative examples of optional structures and are not intended to limit their application. In other embodiments, the shift register can also be an architecture such as 16T2C or 13T3C, and the gate drive signal GN can be a drive signal corresponding to a P-type transistor, a drive signal corresponding to an N-type transistor, or an emission control signal (EM signal). The pixel circuit can also be an architecture such as 7T1C or 8T2C.

[0117] Optionally, in another array substrate provided in this embodiment, the array substrate includes at least one gate driving circuit, and the gate driving circuit includes multiple cascaded shift registers, such as... Figure 11 and Figure 12 As shown, the shift register includes a first input module 110, which includes a first input transistor Q3. The array substrate also includes a substrate 101, an active layer 20, and a third shielding portion 13.

[0118] An active layer is disposed on one side of the substrate 101. The channel region of the first input transistor Q3 is located in the active layer 20. The first terminal of the first input transistor Q3 is connected to the start signal line, and the second terminal of the first input transistor Q3 is connected to the first control terminal of the output module 200.

[0119] The third shielding portion 13 is located on the side of the active layer 20 near the substrate 101. The orthogonal projection of the third shielding portion 13 on the substrate 101 covers the orthogonal projection of the channel region of the first input transistor Q3 on the substrate 101.

[0120] Optionally, the shift register further includes a second input transistor Q4 and a first output transistor Q1. The first terminal of the second input transistor Q4 is connected to the second power supply line, and the second terminal of the second input transistor Q4 is connected to the first gate of the first output transistor Q1. The channel region of the second input transistor Q4 is located in the active layer 20, and the channel region of the second input transistor Q4 does not overlap with the film layer where the third shielding portion 13 is located.

[0121] Optionally, the channel region of the first input transistor Q3 and the channel region of the second input transistor Q4 are disposed in the same layer, which helps to reduce the number of film deposition process steps.

[0122] Optionally, the shift register includes a first switching transistor, the channel region of which does not overlap with the film layer containing the third shielding portion. The aspect ratio of the channel region of the first input transistor Q3 is greater than that of the channel region of the second input transistor Q4. The area of ​​the channel region of the first input transistor Q3 is smaller than the area of ​​the channel region of the first output transistor Q1, and the area of ​​the channel region of the second input transistor Q4 is smaller than the area of ​​the channel region of the first output transistor Q1. The area of ​​the channel region of the first input transistor Q3 is greater than that of the channel region of the second input transistor Q4.

[0123] In this embodiment, the channel region of the first switching transistor and the channel region of the first input transistor Q3 are disposed on the same layer. The aspect ratio of the channel region of the first input transistor Q3 is greater than that of the channel region of the first switching transistor, and the area of ​​the channel region of the first input transistor Q3 is greater than that of the channel region of the first switching transistor. The specific configuration of the technical solution provided in this embodiment can be referred to the description in the above-mentioned related embodiments. This solution also possesses the beneficial effects described in the above embodiments, and will not be repeated here.

[0124] Optionally, in another array substrate provided in this embodiment, the array substrate includes at least one gate driving circuit, and the gate driving circuit includes a plurality of cascaded shift registers, combined with Figure 11 and Figure 12 The shift register includes a first input module 110, a second input module 120, an output module 200, and a protection transistor Q5. The array substrate also includes a substrate 101, an active layer 20, and a fourth shielding portion 14.

[0125] An active layer 20 is disposed on one side of the substrate 101. The channel region of the protection transistor Q5 is located in the active layer 20. The first electrode of the protection transistor Q5 is connected to the output terminal of the first input module 110, and the second electrode of the protection transistor Q5 is connected to the first control terminal of the output module 200.

[0126] The fourth shielding portion 14 is located on the side of the active layer 20 near the substrate 101. The orthogonal projection of the fourth shielding portion 14 on the substrate 101 covers and protects the orthogonal projection of the channel region of the transistor Q5 on the substrate 101.

[0127] Optionally, the first input module 110 includes a first input transistor Q3, and the second input module 120 includes a second input transistor Q4. The first terminal of the first input transistor Q3 is connected to the start signal line, and the second terminal of the first input transistor Q3 is connected to the first terminal of the protection transistor Q5. The channel region of the first input transistor Q3 is located in the active layer 20, and a third shielding portion 13 is provided on the side of the channel region of the first input transistor Q3 near the substrate 101. The first terminal of the second input transistor Q4 is connected to the second power line, and the second terminal of the second input transistor Q4 is connected to the second control terminal of the output module 200. The channel region of the second input transistor Q4 is located in the active layer 20, and there is no shielding portion on the side of the channel region of the second input transistor Q4 near the substrate 101. The channel region of the second input transistor Q4 does not overlap with the film layer where the third shielding portion 13 is located.

[0128] Specifically, the aspect ratio of the channel region of the protection transistor Q5 is greater than that of the channel region of the second input transistor Q4, and the aspect ratio of the channel region of the first input transistor Q3 is greater than that of the channel region of the second input transistor Q4. The area of ​​the channel region of the protection transistor Q5 is greater than that of the channel region of the second input transistor Q4, and the area of ​​the channel region of the first input transistor Q3 is greater than that of the channel region of the second input transistor Q4.

[0129] Optionally, the shift register includes a first switching transistor, the channel region of which does not overlap with the film layer containing the fourth shielding portion 14. The channel region of the first switching transistor is disposed on the same layer as the channel region of the protection transistor Q5.

[0130] Optionally, the width-to-length ratio of the channel region of the protection transistor Q5 is greater than the width-to-length ratio of the channel region of the first switching transistor, and the area of ​​the channel region of the protection transistor Q5 is greater than the area of ​​the channel region of the first switching transistor.

[0131] The specific configuration of the technical solution provided in this embodiment can be referred to the description in the above related embodiments. This solution also has the beneficial effects described in the above embodiments, and will not be repeated here.

[0132] Optionally, in another array substrate provided in this embodiment, the array substrate includes at least one gate driving circuit, and the gate driving circuit includes a plurality of cascaded shift registers, combined with Figures 3-8 The shift register includes a first output transistor Q1 and a first capacitor C1, and the array substrate also includes a substrate 101, an active layer 20 and a first shielding portion 11.

[0133] An active layer 20 is disposed on one side of the substrate 101. The channel region of the first output transistor Q1 is located in the active layer 20. The first terminal of the first output transistor Q1 is connected to the first signal line, and the second terminal of the first output transistor Q1 is connected to the output terminal of the shift register.

[0134] The first plate 31 of the first capacitor C1 is located on the side of the first shielding portion 11 away from the substrate 101. The first plate of the first capacitor C1 is connected to the first gate 301 of the first output transistor Q1, and the second plate 32 of the first capacitor C1 is connected to the first terminal of the first output transistor Q1. The orthographic projection of the first shielding portion 11 on the substrate 101 at least partially overlaps with the orthographic projection of the first plate 31 of the first capacitor C1 on the substrate 101.

[0135] The first shielding portion 11 is located on the side of the active layer 20 near the substrate 101. The orthographic projection of the first shielding portion 11 on the substrate 101 covers the orthographic projection of the channel region of the first output transistor Q1 on the substrate 101. The orthographic projection of the second electrode 32 of the first capacitor C1 on the substrate 101 at least partially overlaps with the orthographic projection of the channel region of the first output transistor Q1 on the substrate 101.

[0136] Optionally, the first plate 31 of the first capacitor C1 is multiplexed as the first gate 301 of the first output transistor Q1.

[0137] Optionally, such as Figure 5 As shown, the first plate 31 of the first capacitor C1 includes a first sub-part 311. The orthographic projection of the first sub-part 311 on the substrate 101 does not overlap with the orthographic projection of the active layer 20 on the substrate 101. The orthographic projection of the first sub-part 311 on the substrate 101 at least partially overlaps with the orthographic projection of the first shielding part 11.

[0138] Optionally, along the first width direction (the first width direction is perpendicular to the extension direction of the first gate 301 of the first output transistor Q1), the size of the first blocking portion 11 is larger than the size of the first gate 301 of the first output transistor Q1.

[0139] The shift register also includes a second output transistor Q2, the first terminal of which is connected to the second signal line, and the second terminal of which is connected to the output terminal of the shift register.

[0140] The array substrate also includes a second shielding portion 12, the orthographic projection of the second shielding portion 12 on the substrate 101 covering the orthographic projection of the channel region of the second output transistor Q2 on the substrate 101.

[0141] Optionally, the second shielding portion 12 is connected to the first gate 302 of the second output transistor Q2.

[0142] The shift register also includes a second capacitor C2. The first plate 33 of the second capacitor C2 is connected to the first gate 302 of the second output transistor Q2, and the second plate 34 of the second capacitor C2 is connected to the second terminal of the second output transistor Q2. The first plate 33 of the second capacitor C2 is located on the side of the second shielding portion 12 away from the substrate 101.

[0143] Optionally, the first plate 33 of the second capacitor C2 is disposed on the same layer as the first gate 302 of the second output transistor Q2, and the first plate 33 of the second capacitor C2 and the first gate 302 of the second output transistor Q2 are connected as an integral structure.

[0144] Optionally, the second plate 34 of the second capacitor C2 is connected to the second terminal of the second output transistor Q2 through the first connection part 41.

[0145] Optionally, the orthographic projection of the second plate 34 of the second capacitor C2 onto the substrate 101 does not overlap with the orthographic projection of the channel region of the second output transistor Q2 onto the substrate 101.

[0146] Optionally, the orthographic projection of the second shielding portion 12 on the substrate 101 at least partially overlaps with the orthographic projection of the first electrode plate 33 of the second capacitor C2 on the substrate 101.

[0147] The specific configuration of the technical solution provided in this embodiment can be referred to the description in the above related embodiments. This solution also has the beneficial effects described in the above embodiments, and will not be repeated here.

[0148] Optionally, embodiments of the present invention also provide a display panel, which includes the array substrate provided in any embodiment of the present invention. Therefore, the display panel provided in this embodiment also has the beneficial effects described in any of the above embodiments. Figure 19 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 19 In this embodiment, the display panel 500 can be applied to mobile phones or any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on this.

[0149] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0150] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, The array substrate includes at least one gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, the shift registers include a first output transistor, and the array substrate further includes: Substrate; An active layer is disposed on one side of the substrate. The channel region of the first output transistor is located in the active layer. The first terminal of the first output transistor is connected to a first signal line, and the second terminal of the first output transistor is connected to the output terminal of the shift register. The first shielding portion is located on the side of the active layer near the substrate, and the orthographic projection of the first shielding portion on the substrate covers the orthographic projection of the channel region of the first output transistor on the substrate.

2. The array substrate according to claim 1, characterized in that, The shift register further includes a first capacitor, the first plate of the first capacitor being connected to the first gate of the first output transistor, and the second plate of the first capacitor being connected to the first terminal of the first output transistor. The first plate of the first capacitor is located on the side of the first shielding portion away from the substrate, and the second plate of the first capacitor is located on the side of the first plate of the first capacitor away from the substrate. Preferably, the first plate of the first capacitor is reused as the first gate of the first output transistor; Preferably, the orthographic projection of the first shielding portion on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate, and the first shielding portion is connected to the first gate of the first output transistor; Preferably, the first plate of the first capacitor includes a first sub-section, the orthographic projection of the first sub-section on the substrate does not overlap with the orthographic projection of the active layer on the substrate, and the orthographic projection of the first sub-section on the substrate at least partially overlaps with the orthographic projection of the first shielding portion on the substrate.

3. The array substrate according to claim 2, characterized in that, The orthographic projection of the second plate of the first capacitor onto the substrate at least partially overlaps with the orthographic projection of the channel region of the first output transistor onto the substrate; Preferably, along the first width direction, the size of the first blocking portion is larger than the size of the first gate of the first output transistor, wherein the first width direction is perpendicular to the extension direction of the first gate of the first output transistor.

4. The array substrate according to claim 1, characterized in that, The shift register further includes a second output transistor, the first terminal of which is connected to a second signal line, and the second terminal of which is connected to the output terminal of the shift register. The array substrate further includes a second shielding portion, the orthographic projection of the second shielding portion on the substrate covering the orthographic projection of the channel region of the second output transistor on the substrate; Preferably, the second blocking portion is connected to the first gate of the second output transistor; Preferably, a clock signal or a second fixed voltage signal is transmitted on the second signal line; Preferably, a first fixed voltage signal is transmitted on the first signal line.

5. The array substrate according to claim 4, characterized in that, The shift register further includes a second capacitor, the first plate of the second capacitor being connected to the first gate of the second output transistor, and the second plate of the second capacitor being connected to the second terminal of the second output transistor; The first plate of the second capacitor is located on the side of the channel region of the second output transistor away from the substrate; Preferably, the first plate of the second capacitor is disposed on the same layer as the first gate of the second output transistor, and the first plate of the second capacitor and the first gate of the second output transistor are connected to form an integral structure. Preferably, the second plate of the second capacitor is connected to the second electrode of the second output transistor via the first connecting portion; Preferably, the orthographic projection of the second plate of the second capacitor onto the substrate does not overlap with the orthographic projection of the channel region of the second output transistor onto the substrate; Preferably, the orthographic projection of the second shielding portion on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.

6. The array substrate according to claim 4, characterized in that, The channel region of the second output transistor includes a plurality of spaced sub-channel regions, and the first gate of the second output transistor includes a plurality of sub-gates. The orthographic projection of the sub-gates on the substrate overlaps with the orthographic projection of a corresponding sub-channel region on the substrate. Preferably, the second shielding portion includes a plurality of spaced sub-shielding portions, wherein the orthographic projection of each sub-shielding portion on the substrate covers the orthographic projection of one of the sub-channel regions on the substrate; Preferably, along the second width direction, the size of the sub-shielding portion is larger than the size of the sub-gate, wherein the second width direction is perpendicular to the extension direction of the first gate of the second output transistor.

7. The array substrate according to claim 1, characterized in that, The active layer includes at least one of a first active layer and a second active layer, wherein the material of the first active layer includes a polycrystalline silicon semiconductor material, and the material of the second active layer includes a metal oxide semiconductor material. Wherein, the channel region of the transistor in the shift register is located in at least one of the first active layer and the second active layer; Preferably, the channel regions of all transistors in the shift register are located in the first active layer; or, the channel regions of all transistors in the shift register are located in the second active layer; or, the channel regions of some transistors in the shift register are located in the first active layer, and the channel regions of other transistors are located in the second active layer. Preferably, the first active layer and the second active layer are disposed in different layers; Preferably, the second active layer is located on the side of the first active layer away from the substrate; Preferably, the carrier mobility of the second active layer is greater than 20 cm⁻¹. 2 / V·s.

8. The array substrate according to claim 7, characterized in that, The material of the second active layer includes a crystalline oxide semiconductor material; Preferably, the material of the second active layer includes indium gallium oxide.

9. The array substrate according to claim 7, characterized in that, The material of the second active layer includes amorphous oxide semiconductor; Preferably, the second active layer includes a first sub-active layer and a second sub-active layer, wherein the carrier mobilities of the first sub-active layer and the second active layer are different; Preferably, the indium content in the first sub-active layer material is less than the indium content in the second sub-active layer material; Preferably, the material of the first sub-active layer includes indium gallium zinc oxide, and the material of the second sub-active layer includes at least one of indium zinc oxide and indium tin zinc oxide.

10. The array substrate according to claim 4, characterized in that, The shift register further includes a first input transistor, the first terminal of which is connected to a start signal; The array substrate further includes a third shielding portion, the orthographic projection of which covers the orthographic projection of the channel region of the first input transistor on the substrate. Preferably, the third shielding portion is located on the side of the channel region of the first input transistor away from the substrate; Preferably, the third blocking portion is connected to the first gate of the first input transistor; Preferably, the shift register further includes a protection transistor connected between the first input transistor and the second output transistor, wherein the first terminal of the protection transistor is connected to the second terminal of the first input transistor, and the second terminal of the protection transistor is connected to the first gate of the second output transistor; The array substrate further includes a fourth shielding portion, the orthographic projection of which covers the orthographic projection of the channel region of the protective transistor on the substrate. Preferably, the fourth shielding portion is located on the side of the channel region of the protective transistor away from the substrate; Preferably, the fourth shielding portion is connected to the first gate of the protective transistor.

11. The array substrate according to claim 1, characterized in that, The shift register further includes a first switching transistor, wherein the aspect ratio of the channel region of the first switching transistor is smaller than that of the channel region of the first output transistor, and the channel region of the first switching transistor does not overlap with the film layer in which the first shielding portion is located; preferably, the channel region of the first switching transistor and the channel region of the first output transistor are disposed in the same layer. Preferably, the area of ​​the channel region of the first switching transistor is smaller than the area of ​​the channel region of the first output transistor.

12. The array substrate according to claim 1, characterized in that, The array substrate further includes at least one pixel circuit, the pixel circuit including a driving transistor; The array substrate further includes a first gate portion, which is located on the side of the channel region of the driving transistor close to the substrate. The orthographic projection of the first gate portion on the substrate covers the orthographic projection of the channel region of the driving transistor on the substrate. Preferably, the voltage applied to the first gate portion is different from the voltage applied to the first shielding portion.

13. The array substrate according to claim 12, characterized in that, The active layer includes a first active layer, the channel region of the driving transistor is located in the first active layer, and the material of the first active layer includes polycrystalline silicon semiconductor material. Preferably, the channel region of the first output transistor is located in the first active layer, and the first gate portion and the first shielding portion are disposed in the same layer. Preferably, the first gate portion is connected to the first power supply line.

14. The array substrate according to claim 12, characterized in that, The active layer includes a second active layer, the channel region of the driving transistor is located in the second active layer, and the material of the second active layer includes a metal oxide semiconductor material. The pixel circuit further includes a second switching transistor, the channel region of which is located in the second active layer; The array substrate further includes a second gate portion, which is located on the side of the channel region of the second switching transistor close to the substrate. The orthographic projection of the second gate portion on the substrate covers the orthographic projection of the channel region of the second switching transistor on the substrate. Preferably, the channel region of the first output transistor is located in the second active layer, and at least one of the first gate portion and the second gate portion is disposed in the same layer as the first shielding portion.

15. The array substrate according to claim 12, characterized in that, The active layer includes a first active layer and a second active layer, wherein the first active layer and the second active layer are configured as separate layers. The channel region of the driving transistor is located in the second active layer; Preferably, the channel region of the first output transistor is located in the first active layer, and the first gate portion and the first shielding portion are disposed in different layers; Preferably, the material of the first active layer includes a polycrystalline silicon semiconductor material, and the material of the second active layer includes a metal oxide semiconductor material.

16. The array substrate according to claim 15, characterized in that, The pixel circuit further includes a second switching transistor, the channel region of which is located in the second active layer; The array substrate further includes a second gate portion, which is located on the side of the channel region of the second switching transistor close to the substrate. The orthographic projection of the second gate portion on the substrate covers the orthographic projection of the channel region of the second switching transistor on the substrate. Preferably, the second gate portion is connected to the first gate of the second switching transistor.

17. The array substrate according to claim 16, characterized in that, The first gate portion and the second gate portion are disposed in different layers; Preferably, along the thickness direction of the array substrate, the vertical distance between the channel region of the driving transistor and the first gate portion is smaller than the vertical distance between the channel region of the second switching transistor and the second gate portion.

18. The array substrate according to claim 17, characterized in that, The shift register includes a first type of transistor and a second type of transistor, wherein the channel region of the first type of transistor is located in the first active layer, and the channel region of the second type of transistor is located in the second active layer. The array substrate includes a second type of shielding portion, which is located on the side of the channel region of the second type of transistor near the substrate. The first gate portion and the second type of shielding portion are disposed in the same layer, or the second gate portion and the second type of shielding portion are disposed in the same layer.

19. An array substrate, characterized in that, The array substrate includes at least one gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including a first input transistor, and the array substrate further includes: Substrate; An active layer is disposed on one side of the substrate, the channel region of the first input transistor is located in the active layer, and the first electrode of the first input transistor is connected to the start signal line; The third shielding portion is located on the side of the active layer near the substrate, and the orthographic projection of the third shielding portion on the substrate covers the orthographic projection of the channel region of the first input transistor on the substrate.

20. The array substrate according to claim 19, characterized in that, The shift register further includes a second input transistor and a first output transistor. The first terminal of the second input transistor is connected to a second power supply line, and the second terminal of the second input transistor is connected to the first gate of the first output transistor. The channel region of the second input transistor is located in the active layer, and the channel region of the second input transistor does not overlap with the film layer where the third shielding portion is located. Preferably, the channel region of the first input transistor and the channel region of the second input transistor are disposed on the same layer; Preferably, the aspect ratio of the channel region of the first input transistor is greater than the aspect ratio of the channel region of the second input transistor; Preferably, the area of ​​the channel region of the first input transistor is smaller than the area of ​​the channel region of the first output transistor, and the area of ​​the channel region of the second input transistor is smaller than the area of ​​the channel region of the first output transistor. Preferably, the area of ​​the channel region of the first input transistor is larger than the area of ​​the channel region of the second input transistor.

21. The array substrate according to claim 19, characterized in that, The shift register includes a first switching transistor, wherein the channel region of the first switching transistor does not overlap with the film layer in which the third shielding portion is located; Preferably, the channel region of the first switching transistor is disposed on the same layer as the channel region of the first input transistor; Preferably, the aspect ratio of the channel region of the first input transistor is greater than the aspect ratio of the channel region of the first switching transistor; Preferably, the area of ​​the channel region of the first input transistor is larger than the area of ​​the channel region of the first switching transistor.

22. An array substrate, characterized in that, The array substrate includes at least one gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers, the shift registers including protection transistors, and the array substrate further includes: Substrate; An active layer is disposed on one side of the substrate, and the channel region of the protection transistor is located in the active layer; The fourth shielding portion is located on the side of the active layer near the substrate, and the orthographic projection of the fourth shielding portion on the substrate covers the orthographic projection of the channel region of the protection transistor on the substrate.

23. The array substrate according to claim 22, characterized in that, The shift register further includes a first input transistor and a second input transistor. The first terminal of the first input transistor is connected to the start signal line, the second terminal of the first input transistor is connected to the first terminal of the protection transistor, and the first terminal of the second input transistor is connected to the second power supply line. The array substrate further includes: The third shielding portion is located on the side of the active layer near the substrate, and the orthographic projection of the third shielding portion on the substrate covers the orthographic projection of the channel region of the first input transistor on the substrate. The channel region of the second input transistor is located in the active layer, and the channel region of the second input transistor does not overlap with the film layer where the third shielding portion is located. Preferably, the aspect ratio of the channel region of the protection transistor is greater than the aspect ratio of the channel region of the second input transistor; Preferably, the aspect ratio of the channel region of the first input transistor is greater than the aspect ratio of the channel region of the second input transistor; Preferably, the area of ​​the channel region of the protection transistor is larger than the area of ​​the channel region of the second input transistor; Preferably, the area of ​​the channel region of the first input transistor is larger than the area of ​​the channel region of the second input transistor.

24. The array substrate according to claim 22, characterized in that, The shift register includes a first switching transistor, wherein the channel region of the first switching transistor does not overlap with the film layer in which the fourth shielding portion is located; Preferably, the channel region of the first switching transistor and the channel region of the protection transistor are disposed on the same layer; Preferably, the aspect ratio of the channel region of the protection transistor is greater than the aspect ratio of the channel region of the first switching transistor; Preferably, the area of ​​the channel region of the protection transistor is larger than the area of ​​the channel region of the first switching transistor.

25. An array substrate, characterized in that, The array substrate includes at least one gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, the shift registers include a first output transistor and a first capacitor, and the array substrate further includes: Substrate; An active layer is disposed on one side of the substrate. The channel region of the first output transistor is located in the active layer. The first terminal of the first output transistor is connected to a first signal line, and the second terminal of the first output transistor is connected to the output terminal of the shift register. The first shielding portion has a first electrode plate of the first capacitor located on the side of the first shielding portion away from the substrate. The first electrode plate of the first capacitor is connected to the first gate of the first output transistor. The second electrode plate of the first capacitor is connected to the first electrode of the first output transistor. The orthographic projection of the first shielding portion on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate.

26. The array substrate according to claim 25, characterized in that, The orthographic projection of the second plate of the first capacitor onto the substrate at least partially overlaps with the orthographic projection of the channel region of the first output transistor onto the substrate; Preferably, the first plate of the first capacitor is reused as the first gate of the first output transistor; Preferably, the first shielding portion is located on the side of the active layer closer to the substrate, and the orthographic projection of the first shielding portion on the substrate covers the orthographic projection of the channel region of the first output transistor on the substrate. Preferably, the first plate of the first capacitor includes a first sub-part, the orthographic projection of the first sub-part on the substrate does not overlap with the orthographic projection of the active layer on the substrate, and the orthographic projection of the first sub-part on the substrate at least partially overlaps with the orthographic projection of the first shielding part on the substrate; Preferably, along the first width direction, the size of the first blocking portion is larger than the size of the first gate of the first output transistor, wherein the first width direction is perpendicular to the extension direction of the first gate of the first output transistor.

27. The array substrate according to claim 25, characterized in that, The shift register further includes a second output transistor, the first terminal of which is connected to a second signal line, and the second terminal of which is connected to the output terminal of the shift register. The array substrate further includes a second shielding portion, the orthographic projection of the second shielding portion on the substrate covering the orthographic projection of the channel region of the second output transistor on the substrate; Preferably, the second blocking portion is connected to the first gate of the second output transistor; Preferably, a clock signal or a second fixed voltage signal is transmitted on the second signal line; Preferably, a first fixed voltage signal is transmitted on the first signal line.

28. The array substrate according to claim 27, characterized in that, The shift register further includes a second capacitor, the first plate of the second capacitor being connected to the first gate of the second output transistor, and the second plate of the second capacitor being connected to the second terminal of the second output transistor; The first plate of the second capacitor is located on the side of the second shielding portion away from the substrate; Preferably, the first plate of the second capacitor is disposed on the same layer as the first gate of the second output transistor, and the first plate of the second capacitor and the first gate of the second output transistor are connected to form an integral structure. Preferably, the second plate of the second capacitor is connected to the second electrode of the second output transistor via the first connecting portion; Preferably, the orthographic projection of the second plate of the second capacitor onto the substrate does not overlap with the orthographic projection of the channel region of the second output transistor onto the substrate; Preferably, the orthographic projection of the second shielding portion on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.

29. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-28.

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