Synchronous control circuit, synchronous control method and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a synchronous control circuit, a synchronous control method and a display panel. The synchronous control circuit comprises a controller, which is used for outputting corresponding voltage adjustment signals and first switch control signals according to the trigger voltage values of each level shifter when the power supply voltage drops to a preset threshold value; a voltage adjustment module, which is used for adjusting the drop speed of the power supply voltage in response to the voltage adjustment signals; and N switching modules, which are used for turning on the connection path between the voltage adjustment module and the level shifter in response to the first switch control signals. Therefore, the application adjusts the drop speed of the power supply voltage, so that different level shifters can obtain differentiated power-down speed compensation according to their respective trigger voltage values, thereby simultaneously reaching their respective trigger voltages and synchronously triggering the global on control function in the power-down process, and the problem of shutdown flashing screen caused by different trigger voltages of multiple cascaded level shifters is solved.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a synchronization control circuit, a synchronization control method, and a display panel. Background Technology

[0002] Currently, in order to eliminate the power-off ghosting of LCD panels, when the level converter detects that the power supply voltage has dropped to the trigger voltage, it usually forces all gate drive signals to be pulled up to the turn-on voltage of the thin-film transistors, so that all thin-film transistors in the panel are turned on at the same time, and the charge stored in the panel can be quickly discharged, thereby eliminating the power-off ghosting.

[0003] However, due to variations in the manufacturing process, the trigger voltages of different level converters exhibit individual differences. In large-size, high-resolution, and high-refresh-rate panel products, multiple level converters are often cascaded to provide sufficient gate drive capability. When multiple level converters are cascaded, the inconsistency in the trigger voltages of each level converter causes asynchronous forced pull-up of the gate drive signal during power-off, resulting in screen flickering at the moment of power-off.

[0004] Therefore, how to improve the screen flickering that occurs when multiple cascaded level converters are powered off is a current problem. Summary of the Invention

[0005] This application provides a synchronous control circuit, a synchronous control method, and a display panel. This application adjusts the rate of decrease of the power supply voltage through a voltage adjustment module, so that different level converters can obtain differentiated power-down speed compensation according to their respective trigger voltage values. Thus, during the power-down process, they simultaneously reach their respective corresponding trigger voltages and synchronously trigger the global power-on control function, solving the problem of screen flickering during shutdown caused by different trigger voltages of multiple cascaded level converters.

[0006] In a first aspect, this application provides a synchronization control circuit applied to N cascaded level converters. The synchronization control circuit includes: a controller connected to a power supply and configured to: detect the decreasing state of the power supply voltage output by the power supply in a power-off mode; when the power supply voltage drops to a preset threshold, output a corresponding voltage adjustment signal and a first switch control signal according to the trigger voltage value of each level converter; and output a second switch control signal in a normal operating mode; a voltage adjustment module connected to the power supply and the controller and configured to: adjust the decreasing rate of the power supply voltage in response to the voltage adjustment signal; and N switching modules corresponding one-to-one with the N level converters. Each switching module is connected to the controller, the voltage adjustment module, and the level converter respectively and configured to: in response to the first switch control signal, open the connection path between the voltage adjustment module and the corresponding level converter, so that the N level converters simultaneously reach their respective trigger voltages; and in response to the second switch control signal, open the connection path between the power supply and the level converter; wherein, N≥2.

[0007] Optionally, the controller is further configured to output a second switch control signal in normal operating mode; the switching module is further configured to connect the power supply and the level converter in response to the second switch control signal.

[0008] Optionally, the synchronization control circuit further includes: a plurality of synchronization compensation modules, each corresponding to a plurality of clock signal output terminals of the N level converters; wherein the synchronization compensation modules are respectively connected to the controller and the corresponding clock signal output terminal, and are configured to: maintain the level state of the clock signal output terminal before triggering the global control function in response to a first compensation control signal output by the controller; and maintain the level state of the clock signal output terminal after triggering the global control function in response to a second compensation control signal output by the controller.

[0009] Optionally, the voltage adjustment module includes: a decoder connected to the voltage adjustment output terminal of the controller, configured to convert the voltage adjustment signal into a corresponding selection signal; and multiple adjustment branches connected one-to-one with the multiple output terminals of the decoder, the adjustment branches also being connected to the power supply, configured to: in response to the selection signal, reduce the rate of decrease of the power supply voltage output by the power supply.

[0010] Optionally, the adjustment branch includes: a first transistor, the control terminal of which is connected to the output terminal of the decoder, and a first terminal of which is connected to the output terminal of the power supply; a delay resistor, the first terminal of which is connected to the second terminal of the first transistor; a delay capacitor, the first terminal of which is connected to the second terminal of the delay resistor, and the second terminal of which is grounded; and a second transistor, the control terminal of which is connected to the control terminal of the first transistor, the first terminal of which is connected to the second terminal of the delay resistor, and the second terminal of which serves as the output terminal of the voltage adjustment module.

[0011] Optionally, the switching module includes: a third transistor, the control terminal of which is connected to the controller, the first terminal of which is connected to the output terminal of the voltage adjustment module, and the second terminal of which is connected to the power supply terminal of the level converter; and a fourth transistor, the control terminal of which is connected to the control terminal of the third transistor, the first terminal of which is connected to the output terminal of the power supply, and the second terminal of which is connected to the second terminal of the third transistor; wherein the turn-on voltages of the third transistor and the fourth transistor are opposite.

[0012] Optionally, the synchronization compensation module includes: a comparator, the first input terminal of which is connected to the clock signal output terminal, and the second input terminal of which is connected to the reference signal terminal; a fifth transistor, the control terminal of which is connected to the controller, the first terminal of which is connected to the first input terminal of the comparator, and the second terminal of which serves as the output terminal of the synchronization compensation module; a sixth transistor, the control terminal of which is connected to the control terminal of the fifth transistor, and the first terminal of which is connected to the output terminal of the comparator; a flip-flop, the input terminal of which is connected to the output terminal of the comparator; and a seventh transistor, the control terminal of which is connected to the second terminal of the sixth transistor, the first terminal of which is connected to the output terminal of the flip-flop, and the second terminal of which is connected to the second terminal of the fifth transistor; wherein the turn-on voltages of the fifth transistor and the sixth transistor are opposite.

[0013] Secondly, this application provides a synchronization control method applied to a synchronization control circuit. The synchronization control method includes: acquiring the trigger voltages corresponding to N level converters; detecting the decreasing state of the power supply voltage output by the power supply in a power-off mode; when the power supply voltage drops to a preset threshold, determining the power-down speed adjustment amount corresponding to each level converter based on the trigger voltage of each level converter; switching the power supply terminal of the level converter whose power-down speed needs to be adjusted to a voltage adjustment module based on the power-down speed adjustment amount, and controlling the voltage adjustment module to adjust the decreasing speed of the power supply voltage so that each level converter reaches its corresponding trigger voltage simultaneously.

[0014] Optionally, the synchronization control method further includes: in normal operating mode, controlling the power supply output voltage of the power supply to power all level converters.

[0015] Optionally, the synchronization control circuit further includes multiple synchronization compensation modules, and the synchronization control method further includes: when some of the N level converters have triggered the global enable control function while the remaining level converters have not yet triggered, controlling the synchronization compensation module corresponding to the triggered level converter to maintain the clock signal that was originally low at the corresponding clock signal output terminal at a low level; when the remaining level converters trigger the global enable control function, controlling the synchronization compensation module to restore the clock signal to normal output.

[0016] Thirdly, this application provides a display panel, including a display area and a non-display area, wherein the display area includes a pixel array; the non-display area is provided with a gate driving circuit, a source driving circuit, N cascaded level converters and a synchronization control circuit; wherein the synchronization control circuit is connected to the N cascaded level converters respectively, the output terminals of the N cascaded level converters are connected to the gate driving circuit respectively, and the source driving circuit is connected to the pixel array.

[0017] The technical solution provided in this application has at least the following beneficial effects:

[0018] This application uses a controller to detect the drop in power supply voltage in power-off mode. When the power supply voltage drops to a preset threshold, it outputs a corresponding voltage adjustment signal and a first switch control signal based on the pre-stored trigger voltage values ​​of each level converter. Then, the voltage adjustment module responds to the voltage adjustment signal to adjust the rate of power supply voltage drop. Simultaneously, the switching module responds to the first switch control signal to switch the power supply terminal of the level converter that needs adjustment to the voltage adjustment module. This allows each level converter to obtain differentiated power-down speed compensation based on its own trigger voltage value, so that they simultaneously reach their corresponding trigger voltages during power-down and synchronously trigger the global power-on control function. This solves the power-off screen flickering problem caused by different trigger voltages of multiple cascaded level converters. Finally, by having each level converter simultaneously trigger the global power-on control function, all gate drive signals are synchronously pulled up to the power-on voltage, achieving synchronous and rapid discharge of the pixel capacitors in the panel and avoiding screen flickering abnormalities caused by inconsistent discharge timing. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 The diagram shown is a schematic diagram of a synchronous control circuit provided in an embodiment of this application.

[0021] Figure 2 The diagram shown is a normal triggering schematic of two level converters provided in an embodiment of this application.

[0022] Figure 3 The diagram shown is a triggering schematic of two level converters after voltage adjustment, according to an embodiment of this application.

[0023] Figure 4 The diagram shown is a schematic diagram of another synchronous control circuit provided in an embodiment of this application.

[0024] Figure 5 The diagram shown is a circuit diagram of a voltage adjustment module provided in an embodiment of this application.

[0025] Figure 6 The diagram shown is a circuit diagram of a switching module provided in an embodiment of this application.

[0026] Figure 7 The diagram shown is a circuit diagram of a synchronization compensation module provided in an embodiment of this application.

[0027] Figure 8 The diagram shown is a flowchart of a synchronization control method provided in an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures: 100. Synchronization control circuit; 110. Controller; 120. Voltage adjustment module; 121. Decoder; 122. Regulation branch; 130. Switching module; 140. Synchronization compensation module; 200. Power supply; 300. Level converter; 400. Gate drive circuit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; R1, delay resistor; C1, delay capacitor. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0030] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0031] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0032] In the field of liquid crystal displays (LCDs), LCDs restore images by controlling the on / off state of thin-film transistors (TFTs) to charge or discharge liquid crystal capacitors. When a TFT is on, a voltage signal on the data line is written to the pixel capacitor, charging it to the target voltage. When the TFT is off, the charge on the capacitor is retained. When the screen is turned off, because the charge accumulated in the charging capacitor may not be fully released, the liquid crystal molecules may remain in the deflected state they were in before the power-off process, resulting in a brief residual image of the previous picture on the screen, known as a power-off ghosting.

[0033] To address the aforementioned power-off ghosting, relevant technologies typically employ a global enable control function for the level converter. Specifically, when the power supply voltage of the level converter begins to drop to near a certain threshold voltage, the level converter detects the power supply voltage and triggers the global enable control function, forcibly pulling the output voltage of all gate drive signals up to the enable voltage of the thin-film transistors. At this time, all thin-film transistors in the panel are turned on, and the charge stored in the in-plane capacitors is rapidly discharged, thereby avoiding the power-off ghosting phenomenon.

[0034] However, due to variations in the manufacturing process of level converters, the detection voltage for the global enable control function is not a fixed value, but rather a voltage range with a certain width. This means that the voltage threshold for triggering the global enable control function differs between different level converters. For large-size, high-resolution, and high-refresh-rate products, more clock signals are typically required for driving, so multiple level converters are often cascaded to meet the driving requirements. In applications with multiple level converters cascaded, the inconsistent trigger voltage thresholds for the global enable control function of each level converter lead to differences in the timing of triggering the global enable control function when the device is powered off. This results in asynchronous gate drive signal actions, manifesting as screen flickering at the moment of power-off.

[0035] To address the aforementioned problems, this application provides a synchronous control circuit, specifically including the following embodiments: Figure 1 The diagram shown is a schematic representation of a synchronization control circuit provided in an embodiment of this application. Figure 1 As shown, the synchronization control circuit 100 is applied to a display panel, which includes at least N cascaded level converters 300. In this embodiment, the synchronization control circuit 100 includes a controller 110 connected to a power supply 200, configured to: detect the decrease in the power supply voltage output by the power supply 200 in a power-off mode; and when the power supply voltage drops to a preset threshold, output a corresponding voltage adjustment signal and a first switch control signal based on the trigger voltage value of each level converter 300.

[0036] It should be noted that when the supply voltage of the level converter 300 begins to drop and falls to near a certain threshold voltage, the level converter 300 triggers the global control function (Xon function), that is, the level converter 300 outputs a constant high-level clock signal, thereby forcing all gate drive signals high to the turn-on voltage. Due to process variations, the trigger voltages of different level converters 300 are different, resulting in inconsistent Xon trigger times for each level converter 300 in cascaded applications. The main function of the controller 110 is to detect the drop in supply voltage during the power-off process and initiate synchronous control operation when the supply voltage drops to a preset threshold. Specifically, the controller 110 calculates and outputs the corresponding voltage adjustment signal and the first switch control signal based on the stored trigger voltage values ​​of each level converter 300 when the supply voltage drops to the preset threshold.

[0037] To achieve the above functions, the controller 110 needs to pre-store the trigger voltage values ​​of each level converter 300. Each trigger voltage value is obtained through testing in factory mode. Specifically, multiple test voltages are set within the trigger voltage range of the level converter 300 and applied to the level converter 300 in descending order. At the same time, its gate drive signal and turn-on voltage level are monitored. When the gate drive signal level is equal to the turn-on voltage level and the turn-on voltage is less than the set value, it is determined that the level converter 300 has triggered Xon under the current test voltage. This voltage value is then used as the actual trigger voltage of the level converter 300 and stored in the controller 110.

[0038] Optionally, the controller 110 in this embodiment can be a timing controller for the display panel or an independently set microcontroller unit. By detecting the drop in the supply voltage, it actively initiates a synchronization control operation when the supply voltage drops to a preset threshold, providing an accurate start time for subsequent power-down speed adjustments and giving the synchronization control a clear time reference. Simultaneously, the controller 110 stores the actual trigger voltage values ​​of each level converter 300, enabling subsequent adjustments to be precisely controlled based on the individual differences of each level converter 300, overcoming the problem of inconsistent trigger voltages caused by process deviations.

[0039] In this embodiment, the synchronization control circuit 100 further includes a voltage adjustment module 120, which is connected to the power supply 200 and the controller 110 and is configured to adjust the rate of decrease of the power supply voltage in response to a voltage adjustment signal.

[0040] It should be noted that when the trigger voltages of the N cascaded level converters 300 are different, at the same power-down speed, the level converter 300 with the higher trigger voltage will reach its trigger voltage first and trigger Xon, while the level converter 300 with the lower trigger voltage will reach its trigger voltage later and trigger Xon; there is a time difference between the two. Combined with... Figure 2 As shown, the trigger voltage of the first level converter is V1, and the trigger voltage of the second level converter is V2, where V2 > V1. When the supply voltage drops to V2, the second level converter triggers the Xon function at time t1; when the supply voltage continues to drop to V1, the first level converter triggers the Xon function at time t2. There is a time difference between time t1 and time t2. In this embodiment, to eliminate this time difference, the power-down speed of the second level converter needs to be adjusted. The voltage adjustment module 120 is used to adjust the power-down speed of the supply voltage. Specifically, when a level converter 300 needs to adjust its power-down speed, the controller 110 informs the voltage adjustment module 120 through a voltage adjustment signal to determine the extent to which the power-down speed needs to be slowed down. Responding to the voltage adjustment signal, the voltage adjustment module 120 changes the time constant of the power supply circuit of the level converter 300, slowing down the rate of voltage drop and thus delaying the trigger time to align with the trigger time of the other level converter 300. (Continue to see...) Figure 2 As shown, the voltage adjustment module 120 adjusts the rate of decrease of the power supply voltage corresponding to the second level converter, so that both the first level converter and the second level converter reach the corresponding trigger voltage at time t2.

[0041] In one embodiment, N switching modules 130 correspond one-to-one with N level converters 300. Each switching module 130 is connected to the controller 110, the voltage adjustment module 120, and the corresponding level converter 300, and is configured to, in response to a first switch control signal, open the connection path between the voltage adjustment module 120 and the corresponding level converter 300.

[0042] It should be noted that when it is determined that a level converter 300 needs to adjust its power-down speed, the controller 110 outputs a first switch control signal to the corresponding switching module 130. The switching module 130 connects the power supply terminal of the level converter 300 to the output terminal of the voltage adjustment module 120, thus connecting the power supply circuit of the level converter 300 to the adjustment network of the voltage adjustment module 120. For level converters 300 that do not need to adjust their power-down speed, their corresponding switching module 130 does not operate, and the power supply terminal of the level converter 300 remains directly connected to the power supply 200, decreasing at its original power-down speed.

[0043] In summary, this application detects the drop in power supply voltage in power-off mode through controller 110. When the power supply voltage drops to a preset threshold, it outputs corresponding voltage adjustment signals and a first switch control signal based on the pre-stored trigger voltage values ​​of each level converter 300. Then, the voltage adjustment module 120 responds to the voltage adjustment signal to adjust the rate of power supply voltage drop. Simultaneously, the switching module 130 responds to the first switch control signal to switch the power supply terminal of the level converter 300 that needs adjustment to the voltage adjustment module 120. This allows each level converter 300 to obtain differentiated power-down speed compensation based on its own trigger voltage value, thereby simultaneously reaching its corresponding trigger voltage during power-down and synchronously triggering the global on-control function. This solves the power-off screen flickering problem caused by different trigger voltages of multiple cascaded level converters 300. Finally, by having each level converter 300 simultaneously trigger the global on-control function, all gate drive signals are synchronously pulled up to the on-voltage, achieving synchronous and rapid discharge of the pixel capacitors in the panel and avoiding screen flickering abnormalities caused by inconsistent discharge timing.

[0044] In some embodiments, the controller 110 is further configured to output a second switch control signal in normal operating mode; the switching module 130 is further configured to connect the power supply 200 and the level converter 300 in response to the second switch control signal.

[0045] It should be noted that when the display panel is operating normally, the power supply voltage output by the power supply 200 is stable at the normal operating value, and the level converter 300 outputs the gate drive signal according to the normal timing to drive the display panel to display images. At this time, the controller 110 outputs a second switch control signal in normal operating mode, which has the opposite level to the first switch control signal. After receiving the second switch control signal, each switching module 130 responds to the signal by connecting the power supply 200 and the level converter 300, while disconnecting the connection between the voltage adjustment module 120 and the level converter 300, thus ensuring the stability and reliability of the display panel during normal operation.

[0046] Figure 3 The diagram shown is a structural schematic of another synchronization control circuit provided in an embodiment of this application. Figure 3 As shown, the synchronization control circuit 100 also includes: multiple synchronization compensation modules 140, which correspond one-to-one with multiple clock signal output terminals of N level converters 300; each synchronization compensation module 140 is connected to the controller 110, the corresponding clock signal output terminal and the gate drive circuit 400 respectively, and is used to compensate the clock signal before inputting it into the gate drive circuit 400 when the trigger times of the cascaded level converters 300 are inconsistent.

[0047] It should be noted that when some level converters 300 trigger the global control function first, while the others have not yet been triggered, the clock signal at the clock signal output terminal of the first triggered level converter 300, which was originally at a low level, will be abnormally pulled high to the turn-on voltage. This abnormally pulled high clock signal will incorrectly turn on the thin-film transistor, which should be in the off state, causing screen flickering. To solve this problem, this embodiment includes a synchronization compensation module 140.

[0048] Specifically, when some of the N level converters 300 have triggered the global control function while the remaining level converters 300 have not yet been triggered, the controller 110 outputs a first compensation control signal to the synchronization compensation module 140 corresponding to the triggered level converter 300. In response to this first compensation control signal, the synchronization compensation module 140 maintains the clock signal, which was originally low at the clock signal output terminal of the level converter 300, at a low level to prevent it from being abnormally pulled high, thereby preventing screen flickering caused by abnormal clock signal transitions. For the clock signal, which was originally high, since it is already at the turn-on voltage, even if it is further pulled high, it will not have a substantial impact on the switching state of the thin-film transistor; therefore, the synchronization compensation module 140 does not need to process it.

[0049] When the remaining level converters 300 also trigger the global control function, the controller 110 outputs a second compensation control signal to the synchronization compensation module 140. In response to this second compensation control signal, the synchronization compensation module 140 restores the clock signal to normal output. At this point, all level converters 300 have triggered the global control function, and there is no imbalance state where some are triggered while others are not; the clock signal can then recover its normal waveform.

[0050] This embodiment uses a synchronization compensation module 140 at the clock signal output to maintain the originally low clock signal at a low level during the transition period when some level converters 300 have been triggered while the others have not, thus avoiding screen flickering caused by abnormally pulling the clock signal high. Simultaneously, once all level converters 300 have been triggered, the synchronization compensation module 140 automatically restores the normal output of the clock signal, without affecting the subsequent discharge process.

[0051] Figure 4 The diagram shown is a circuit schematic of a voltage adjustment module provided in an embodiment of this application. Figure 4As shown, the voltage adjustment module 120 in this embodiment includes a decoder 121 and multiple adjustment branches 122. Specifically, the decoder 121 is connected to the voltage adjustment output terminal of the controller 110 and is configured to convert the voltage adjustment signal into a corresponding selection signal; the multiple adjustment branches 122 are connected one-to-one with the multiple output terminals of the decoder 121, and the adjustment branches 122 are also connected to the power supply 200 and are configured to reduce the rate of decrease of the power supply voltage output by the power supply 200 in response to the selection signal.

[0052] In some embodiments, the regulating branch 122 includes a first transistor T1, a delay resistor R1, a delay capacitor C1, and a second transistor T2. Specifically, the control terminal of the first transistor T1 is connected to the output terminal of the decoder 121, and the first terminal of the first transistor T1 is connected to the output terminal of the power supply 200; the first terminal of the delay resistor R1 is connected to the second terminal of the first transistor T1; the first terminal of the delay capacitor C1 is connected to the second terminal of the delay resistor R1, and the second terminal of the delay capacitor C1 is grounded; the control terminal of the second transistor T2 is connected to the control terminal of the first transistor T1, the first terminal of the second transistor T2 is connected to the second terminal of the delay resistor R1, and the second terminal of the second transistor T2 serves as the output terminal of the voltage adjustment module 120.

[0053] It should be noted that after the controller 110 completes the calculation based on the trigger voltage values ​​of each level converter 300, it determines the level converter 300 whose power-down speed needs to be adjusted and its corresponding target RC time constant, and sends this information to the decoder 121 through a voltage adjustment signal. The decoder 121 decodes the voltage adjustment signal, converts it into a corresponding selection signal, and outputs it through the corresponding output terminal.

[0054] like Figure 4 As shown, taking four sets of adjustment branches 122 as an example, when the controller 110 determines that the first set of adjustment branches 122 needs to be selected, the first output terminal of the decoder 121 outputs a valid level, and the other output terminals output an invalid level. The control terminals of the first transistor T1 and the second transistor T2 in the first set of adjustment branches 122 simultaneously receive a valid level, and the first transistor T1 and the second transistor T2 are simultaneously turned on. At this time, the supply voltage output by the power supply 200 is sequentially output to the power supply terminal of the level converter 300, which needs to adjust the power-down speed, through the first transistor T1, the delay resistor R1, and the second transistor T2. At the same time, the delay capacitor C1 and the delay resistor R1 in this branch together form an RC network connected to the power supply circuit of the level converter 300. In addition, in the unselected adjustment branch 122, both transistors are in the off state, and this branch does not participate in the output of the voltage adjustment module 120.

[0055] It is worth noting that the resistance and capacitance values ​​in different regulating branches 122 are different, therefore each regulating branch 122 has a different RC time constant. When a regulating branch 122 is selected and connected to the power supply circuit of the level converter 300, the time constant of the power supply circuit of the level converter 300 changes from the original fixed RC value to the total RC value determined by the original RC value and the connected RC network. The rate of voltage drop decreases accordingly, thus delaying the moment when the level converter 300 reaches its trigger voltage. The larger the RC time constant, the slower the voltage drop rate and the greater the trigger delay; the smaller the RC time constant, the faster the voltage drop rate and the smaller the trigger delay.

[0056] Therefore, in this embodiment, the voltage regulation signal of the controller 110 is converted into a selection signal by the decoder 121, thereby realizing the selection control of multiple sets of regulation branches 122; through the regulation branches 122 with different RC time constants, the speed of power supply voltage drop is precisely adjusted in multiple levels, so that the controller 110 can select the most suitable adjustment intensity according to the actual trigger voltage difference of each level converter 300, ensuring that each level converter 300 can reach its respective trigger voltage at the same time.

[0057] Figure 5 The diagram shown is a circuit schematic of a switching module provided in an embodiment of this application. Figure 5 As shown, the switching module 130 in this embodiment includes a third transistor T3 and a fourth transistor T4. Specifically, the control terminal of the third transistor T3 is connected to the controller 110, the first terminal of the third transistor T3 is connected to the output terminal of the voltage adjustment module 120, and the second terminal of the third transistor T3 is connected to the power supply terminal of the level converter 300; the control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3, the first terminal of the fourth transistor T4 is connected to the output terminal of the power supply 200, and the second terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3; wherein, the turn-on voltages of the third transistor T3 and the fourth transistor T4 are opposite, such that the third transistor T3 is an N-type transistor and the fourth transistor T4 is a P-type transistor.

[0058] It should be noted that when the controller 110 determines that a certain level converter 300 needs to adjust its power-down speed, the controller 110 outputs a first switch control signal to the corresponding switching module 130 of that level converter 300. Since the turn-on voltages of the third transistor T3 and the fourth transistor T4 are opposite, under the control of the first switch control signal, the third transistor T3 turns on and the fourth transistor T4 turns off. At this time, the power supply terminal of the level converter 300 is connected to the output terminal of the voltage adjustment module 120 through the conducting third transistor T3, while the connection path between the level converter 300 and the power supply 200 is cut off by the fourth transistor T4. The power supply circuit of the level converter 300 is thus connected to the adjustment network of the voltage adjustment module 120, and the supply voltage decreases at the adjusted speed.

[0059] Optionally, when the controller 110 determines that a certain level converter 300 does not require adjustment of its power-down speed, the controller 110 outputs a second switch control signal to the corresponding switching module 130 of that level converter 300 (e.g., in normal operating mode, or when no adjustment is required in power-off mode). The second switch control signal has the opposite level to the first switch control signal. Under the control of the second switch control signal, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. At this time, the power supply terminal of the level converter 300 is connected to the power supply 200 through the turned-on fourth transistor T4, while the connection path between the level converter 300 and the voltage adjustment module 120 is cut off by the third transistor T3. The power supply terminal of the level converter 300 remains directly connected to the power supply 200 and decreases at its original speed.

[0060] This embodiment uses two transistors with opposite turn-on voltages to form a switching module 130, which realizes the switching of the power supply terminal of the level converter 300 between the power supply path and the voltage adjustment module path. This ensures that at any time, the power supply terminal of the level converter 300 is only connected to one of the power supply 200 and the voltage adjustment module 120, avoiding circuit logic conflicts caused by the simultaneous conduction of two paths.

[0061] Figure 6 The diagram shown is a circuit schematic of a synchronization compensation module provided in an embodiment of this application. Figure 6 As shown, the synchronization compensation module 140 in this embodiment includes a comparator, a fifth transistor T5, a sixth transistor T6, a flip-flop, and a seventh transistor T7.

[0062] Specifically, the first input terminal of the comparator is connected to the clock signal output terminal, and the second input terminal of the comparator is connected to the reference signal terminal; the control terminal of the fifth transistor T5 is connected to the controller 110, the first terminal of the fifth transistor T5 is connected to the first input terminal of the comparator, and the second terminal of the fifth transistor T5 serves as the output terminal of the synchronization compensation module 140; the control terminal of the sixth transistor T6 is connected to the control terminal of the fifth transistor T5, and the first terminal of the sixth transistor T6 is connected to the output terminal of the comparator; the clock input terminal of the flip-flop is connected to the output terminal of the comparator; the control terminal of the seventh transistor T7 is connected to the second terminal of the sixth transistor T6, the first terminal of the seventh transistor T7 is connected to the output terminal of the flip-flop, and the second terminal of the seventh transistor T7 is connected to the second terminal of the fifth transistor T5; wherein, the turn-on voltages of the fifth transistor T5 and the sixth transistor T6 are opposite.

[0063] It should be noted that the working principle of the synchronization compensation module 140 in this embodiment is as follows: (1) When some level converters have triggered the global control function while the rest of the level converters have not yet triggered: the controller 110 outputs the first compensation control signal. Since the turn-on voltages of the fifth transistor T5 and the sixth transistor T6 are opposite, under the control of the first compensation control signal, the fifth transistor T5 is turned off and the sixth transistor T6 is turned on.

[0064] At this time, the clock signal, which was originally low at the clock signal output of the triggered level converter 300, is abnormally pulled high, while the reference signal at the reference signal terminal remains at its normal low level. The first input of the comparator receives the abnormally pulled high clock signal, and the second input receives the reference signal. Since the clock signal is higher than the reference signal, the comparator output generates a rising edge signal that changes from low to high. This rising edge signal is input to the clock input of the flip-flop, triggering the flip-flop to latch the turn-off voltage of its data input terminal to the output terminal. Simultaneously, the high level output of the comparator is transmitted to the control terminal of the seventh transistor T7 via the turned-on sixth transistor T6, causing the seventh transistor T7 to turn on. After the seventh transistor T7 turns on, the turn-off voltage of the flip-flop output is transmitted to the output terminal of the synchronization compensation module 140 via the seventh transistor T7, and then output to the gate drive circuit 400.

[0065] At this time, although the clock signal output of the level converter 300 has been abnormally pulled high, the abnormally high clock signal cannot be output to the gate drive circuit 400 because the fifth transistor T5 is in the off state. The gate drive circuit 400 actually receives the shutdown voltage output by the synchronization compensation module 140, that is, the clock signal that was originally low is maintained at a low level, and the corresponding thin-film transistor remains in the off state, and will not be erroneously turned on due to abnormal clock signal jumps, thus avoiding screen flickering.

[0066] It should be noted that the clock signal, which is originally at a high level, is already at the turn-on voltage. Even if it is abnormally pulled high, it will not have a substantial impact on the switching state of the thin-film transistor. Therefore, the synchronization compensation module 140 does not need to process it.

[0067] (2) When all level converters have triggered the global control function: After the delayed-triggered level converters 300 also trigger the global control function, the controller 110 outputs a second compensation control signal. The level of the second compensation control signal is opposite to that of the first compensation control signal. Under the control of the second compensation control signal, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off.

[0068] Optionally, after the fifth transistor T5 is turned on, the clock signal output of the level converter 300 is directly connected to the output of the synchronization compensation module 140 through the turned-on fifth transistor T5, and the clock signal is output normally to the gate drive circuit 400. Simultaneously, the sixth transistor T6 is turned off, the connection between the comparator output and the control terminal of the seventh transistor T7 is severed, the control terminal of the seventh transistor T7 becomes low, and the seventh transistor T7 is turned off. The output of the trigger no longer affects the output of the synchronization compensation module 140. At this time, all level converters 300 have triggered the global control function, there is no unbalanced state of partial triggering and partial non-triggering, and the clock signal returns to normal output.

[0069] Therefore, in this embodiment, a comparator is used to detect whether the clock signal is abnormally pulled high, a trigger is used to latch the turn-off voltage, and a switching network composed of three transistors is used to switch between the compensation state and the pass-through state. During the transition period when some level converters 300 have been triggered but others have not, the clock signal, which was originally low, is kept at a low level, thus avoiding the screen flickering phenomenon caused by the clock signal being abnormally pulled high. After all level converters 300 have been triggered, the normal output of the clock signal is automatically restored.

[0070] Figure 8 The diagram shown is a flowchart illustrating a synchronization control method provided in an embodiment of this application; as follows: Figure 8 As shown, the synchronization control method in this embodiment specifically includes the following steps: Step S100: Obtain the trigger voltage corresponding to each of the N level converters.

[0071] In some embodiments, the trigger voltage values ​​of each level converter are pre-detected in factory mode. Specifically, multiple test voltages are set within the trigger voltage range of the level converters and applied to the level converters in descending order. When a level converter triggers the global control function, the current test voltage value is recorded as the actual trigger voltage of that level converter and stored in the controller. Due to process variations, the trigger voltages of different level converters may differ; for example, the trigger voltage of the first level converter may be V1, and the trigger voltage of the second level converter may be V2.

[0072] Step S200: In power-off mode, detect the drop in the power supply voltage output by the power supply.

[0073] In some embodiments, after the system is powered off, the supply voltage begins to drop. The controller continuously monitors the voltage change of the supply voltage, and when the supply voltage drops to a preset threshold, it determines that an effective power-off phase has begun and should initiate synchronization control operations.

[0074] Step S300: When the power supply voltage drops to a preset threshold, determine the power-down speed adjustment amount corresponding to each level converter according to the trigger voltage of each level converter.

[0075] This explanation uses two level shifters (a first level shifter and a second level shifter) as an example. Assume the trigger voltage of the first level shifter is V1, the trigger voltage of the second level shifter is V2, and V2 > V1, meaning the trigger voltage of the second level shifter is higher than that of the first level shifter.

[0076] The controller uses the first level converter as a reference and calculates the time t2 required for it to drop from the preset threshold Vf to the trigger voltage V1 based on the inherent RC time constant of the power supply circuit of the first level converter. The calculation formula is as follows: t2 = RC1×ln[(VDD-Vf) / (VDD-V1)](1) RC1 is the fixed time constant of the power supply circuit for the first level converter.

[0077] The controller determines the target power-down speed based on time t2 and the trigger voltage V1 of the first level converter, meaning each level converter should reach its respective trigger voltage at time t2. For the second level converter, it needs to reach the trigger voltage V2 at time t2, therefore its RC time constant RC2 should satisfy: t2 =RC2× ln[(VDD Vf) / (VDD V2)](2) After calculating t2 using formula (1), substituting it into formula (2) allows for the reverse calculation of RC2. The controller determines the power-down speed adjustment amount corresponding to the second level converter based on RC2, which means that the time constant of the power supply circuit of the second level converter needs to be adjusted from the original fixed value to the target value RC2. This adjustment amount is communicated to the voltage adjustment module through the voltage adjustment signal output by the controller.

[0078] Step S400: Based on the power-down speed adjustment amount, switch the power supply terminal of the level converter whose power-down speed needs to be adjusted to the voltage adjustment module, and control the voltage adjustment module to adjust the rate of decrease of the power supply voltage so that each level converter reaches its corresponding trigger voltage at the same time.

[0079] In this embodiment, the controller outputs a first switch control signal to the switching module corresponding to the level converter whose power-down speed needs to be adjusted, based on the power-down speed adjustment amount. In response to the signal, the switching module switches the power supply terminal of the second level converter from the power supply to the output terminal of the voltage adjustment module, so that the power supply circuit of the second level converter is connected to the adjustment network of the voltage adjustment module.

[0080] Simultaneously, the controller outputs a corresponding voltage adjustment signal to the voltage adjustment module based on the calculated RC2. Responding to this signal, the voltage adjustment module selects the power supply circuit corresponding to RC2 from multiple RC networks with different time constants, thus changing the time constant of the power supply circuit to the target value RC2. At this point, the power supply voltage to the second level converter decreases at the adjusted rate, reaching the trigger voltage V2 at time t2 and triggering the global control function.

[0081] For level converters that do not require adjustment of power-down speed, the corresponding switching module maintains the connection path between the power supply and the level converter. The first level converter drops with the original fixed time constant RC1, reaches the trigger voltage V1 at time t2, and triggers the global control function.

[0082] In summary, this method initiates synchronous control when the supply voltage drops to a preset threshold. It calculates the required power-down speed adjustment based on the actual trigger voltage of each level converter, connects the level converters that need adjustment to the voltage adjustment module through a switching module, and adjusts the rate of voltage drop of their supply voltage through the voltage adjustment module. This ensures that each level converter reaches its respective trigger voltage simultaneously and triggers the global control function synchronously, effectively solving the shutdown screen flickering problem caused by different trigger voltages of each level converter.

[0083] In one embodiment, in normal operating mode, the power supply voltage output by the control power source powers all level shifters.

[0084] In some embodiments, the synchronization control method further includes: Step S500: When some of the N level converters have triggered the global enable control function while the remaining level converters have not yet been triggered, control the synchronization compensation module corresponding to the triggered level converters to maintain the clock signal that was originally low at the corresponding clock signal output terminal at a low level.

[0085] Step S600: After the other level converters trigger the global enable control function, the control synchronization compensation module restores the clock signal to normal output.

[0086] This embodiment maintains the clock signal, which is originally low, at a low level during the transition period when some level converters have been triggered while others have not, thus avoiding screen flickering caused by the clock signal being abnormally pulled high. After all level converters have been triggered, the clock signal output is automatically restored to normal, ensuring the normal progress of the subsequent discharge process.

[0087] In some embodiments, this application provides a display panel including a display area and a non-display area. The display area includes a pixel array. The non-display area is provided with a gate driving circuit, a source driving circuit, N cascaded level converters, and a synchronization control circuit as shown in the above embodiments. The synchronization control circuit is connected to the N cascaded level converters, the output terminals of the N cascaded level converters are connected to the gate driving circuit, and the source driving circuit is connected to the pixel array.

[0088] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0089] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0090] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A synchronous control circuit, characterized in that, The synchronization control circuit, applied to N cascaded level shifters, includes: The controller, connected to the power supply, is configured to: detect the drop in the power supply voltage output by the power supply in the power-off mode; when the power supply voltage drops to a preset threshold, output a corresponding voltage adjustment signal and a first switch control signal according to the trigger voltage value of each level converter; and output a second switch control signal in the normal operation mode. A voltage regulation module, connected to the power supply and the controller, is configured to: adjust the rate of decrease of the power supply voltage in response to the voltage regulation signal; There are N switching modules, each corresponding to one of N level converters. Each switching module is connected to the controller, the voltage adjustment module, and the level converters, and is configured to: in response to a first switch control signal, establish a connection between the voltage adjustment module and the corresponding level converter, so that all N level converters simultaneously reach their respective trigger voltages; and in response to a second switch control signal, establish a connection between the power supply and the level converters; wherein N ≥ 2.

2. The synchronous control circuit according to claim 1, characterized in that, The synchronization control circuit also includes: Multiple synchronization compensation modules correspond one-to-one with the multiple clock signal output terminals of the N level converters; The synchronization compensation module is connected to the controller and the corresponding clock signal output terminal, and is configured to: maintain the level state of the clock signal output terminal before the global control function is triggered in response to the first compensation control signal output by the controller; and maintain the level state of the clock signal output terminal after the global control function is triggered in response to the second compensation control signal output by the controller.

3. The synchronous control circuit according to claim 1, characterized in that, The voltage adjustment module includes: A decoder, connected to the voltage regulation output of the controller, is configured to convert the voltage regulation signal into a corresponding selection signal. Multiple regulating branches are connected one-to-one with multiple output terminals of the decoder. The regulating branches are also connected to the power supply and are configured to: in response to the selection signal, reduce the rate of decrease of the power supply voltage output by the power supply.

4. The synchronous control circuit according to claim 3, characterized in that, The regulating branch includes: A first transistor, wherein the control terminal of the first transistor is connected to the output terminal of the decoder, and the first terminal of the first transistor is connected to the output terminal of the power supply. A delay resistor, wherein the first end of the delay resistor is connected to the second end of the first transistor; A delay capacitor, wherein the first terminal of the delay capacitor is connected to the second terminal of the delay resistor, and the second terminal of the delay capacitor is grounded; The second transistor has its control terminal connected to the control terminal of the first transistor, and its first terminal is connected to the second terminal of the delay resistor. The second terminal of the second transistor serves as the output terminal of the voltage adjustment module.

5. The synchronous control circuit according to claim 1, characterized in that, The switching module includes: The third transistor has its control terminal connected to the controller, its first terminal connected to the output terminal of the voltage adjustment module, and its second terminal connected to the power supply terminal of the level converter. The fourth transistor has its control terminal connected to the control terminal of the third transistor, its first terminal connected to the output terminal of the power supply, and its second terminal connected to the second terminal of the third transistor. The turn-on voltages of the third transistor and the fourth transistor are opposite.

6. The synchronous control circuit according to claim 2, characterized in that, The synchronization compensation module includes: The comparator has its first input terminal connected to the clock signal output terminal and its second input terminal connected to the reference signal terminal. The fifth transistor has its control terminal connected to the controller, its first terminal connected to the first input terminal of the comparator, and its second terminal serving as the output terminal of the synchronization compensation module. The sixth transistor has its control terminal connected to the control terminal of the fifth transistor, and its first terminal connected to the output terminal of the comparator. A trigger, wherein the input of the trigger is connected to the output of the comparator; The seventh transistor has its control terminal connected to the second terminal of the sixth transistor, its first terminal connected to the output terminal of the flip-flop, and its second terminal connected to the second terminal of the fifth transistor. The fifth transistor and the sixth transistor have opposite turn-on voltages.

7. A synchronization control method, characterized in that, The synchronization control method, applied to the synchronization control circuit according to any one of claims 1-6, comprises: Obtain the trigger voltage corresponding to each of the N level shifters; In power-off mode, detect the drop in the power supply voltage output by the power supply. When the power supply voltage drops to a preset threshold, the power-down speed adjustment amount corresponding to each level converter is determined according to the trigger voltage of each level converter; According to the power-down speed adjustment amount, the power supply terminal of the level converter whose power-down speed needs to be adjusted is switched to the voltage adjustment module, and the voltage adjustment module is controlled to adjust the rate of decrease of the power supply voltage so that each level converter reaches its corresponding trigger voltage at the same time.

8. The synchronization control method according to claim 7, characterized in that, The synchronization control method further includes: In normal operating mode, the power supply voltage output by the control power source powers all level converters.

9. The synchronization control method according to claim 7, characterized in that, The synchronization control circuit further includes multiple synchronization compensation modules, and the synchronization control method further includes: When some of the N level converters have triggered the global enable control function while the remaining level converters have not yet been triggered, the synchronization compensation module corresponding to the triggered level converter is controlled to maintain the clock signal, which was originally low at the corresponding clock signal output terminal, at a low level. When the remaining level converters trigger the global enable control function, they control the synchronization compensation module to restore the clock signal to normal output.

10. A display panel, comprising a display area and a non-display area, characterized in that, The display area includes a pixel array; The non-display area is provided with a gate driving circuit, a source driving circuit, N cascaded level converters, and a synchronization control circuit as described in any one of claims 1-6. The synchronization control circuit is connected to the N cascaded level converters, the output terminals of the N cascaded level converters are connected to the gate driving circuit, and the source driving circuit is connected to the pixel array.

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