Memory device and storage system for output code

Abstract

The present disclosure provides a memory device and a storage system. The memory device includes a base die and a plurality of core dies stacked on the base die and connected with the base die using a plurality of through holes and a plurality of bump pads. The base die outputs a test code as a read code through an output pad in synchronization with a first edge of a test clock signal in a normal mode, and outputs the test code as the read code through the output pad in synchronization with the first edge and a second edge of the test clock signal in an acceleration mode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0037441, filed on March 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to storage devices and storage systems for outputting code. Background Technology

[0004] Stacked memory systems, such as high-bandwidth memory (HBM) devices, are widely used in various applications due to their high bandwidth and energy efficiency. Unlike traditional memory systems that use parallel data buses, stacked memory systems consist of stacked memory devices, which include base chips and multiple memory chips interconnected via through-silicon vias (TSVs). These stacked memory devices include physical interfaces, such as a physical layer for communicating with the processor. This physical layer is designed for high-speed data transfer and efficient communication. Summary of the Invention

[0005] This disclosure describes a memory device that may include a base die and a plurality of core dies, wherein the core dies are stacked on the base die and connected to the base die using a plurality of through-holes and a plurality of bump pads. The base die can output test codes as read codes through output pads in normal mode, synchronized with a first edge of a test clock signal, and can output test codes as read codes through output pads in accelerated mode, synchronized with a first edge and a second edge of a test clock signal.

[0006] This disclosure describes a memory system that may include: an interposer stacked on a substrate; and memory devices and a processor stacked on the interposer and interconnected by wires formed in the interposer. The memory devices may include a base die and a plurality of core dies stacked on the interposer, and the base die and the plurality of core dies may be interconnected using a plurality of vias and a plurality of bump pads. The base die may output test codes as read codes through output pads in normal mode synchronized with a first edge of a test clock signal, and may output test codes as read codes through output pads in accelerated mode synchronized with a first edge and a second edge of a test clock signal.

[0007] This disclosure describes a memory device that may include: a base die; and a plurality of core dies stacked on top of the base die and connected to the base die using a plurality of vias and a plurality of bump pads. The base die is configured to: in normal mode, output a first selected clock signal through an output pad in a manner where a first edge of a first selected clock signal is synchronized only with a first edge of a test clock signal; and in accelerated mode, output a second selected clock signal through an output pad in a manner where a first edge of a second selected clock signal is synchronized with both a first edge and a second edge of the test clock signal. Attached Figure Description

[0008] Figure 1 A base die is shown according to one embodiment of the present disclosure.

[0009] Figure 2 A clock generation circuit according to an embodiment of the present disclosure is shown.

[0010] Figure 3 and Figure 4 This is a timing diagram of the operation period of a clock generation circuit according to an embodiment of the present disclosure.

[0011] Figure 5 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure. Detailed Implementation

[0012] In the following description of the embodiments, when a parameter is referred to as “predetermined,” it may be intended to mean that the value of the parameter is predetermined when the parameter is used in a certain process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during the execution of the process or algorithm.

[0013] Terms such as “first” and “second” are used to distinguish between multiple elements and do not imply the size, order, priority, number, or importance of the elements. For example, a first element may be named a second element in one example, while a second element may be named a first element in another example.

[0014] When one component is marked as "connected" to another component, these components can be directly connected or connected through an intermediate component between them. When two components are marked as "directly connected," one component is directly connected to the other, and there is no intermediate component between them.

[0015] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. Signals with a logic high level are distinguished from signals with a logic low level. For example, when a signal at a first voltage level corresponds to a logic high level signal, a signal at a second voltage level corresponds to a logic low level signal. In one embodiment, a logic high level can be a voltage level higher than a logic low level. The logic levels of signals can differ or be reversed depending on the embodiment. For example, a signal at a logic high level in one embodiment may be at a logic low level in another embodiment, and vice versa.

[0016] The term "binary bit setting" refers to a combination of logic levels of the bits included in a signal. The binary bit setting of a signal can be set differently when the logic level of each bit in the signal changes. For example, when a signal contains two bits, if the logic level of each of the two bits is "logic low, logic low", the binary bit setting of the signal can be set to the first logic bit setting; and if the logic level of each of the two bits is "logic low and logic high", the binary bit setting of the signal can be set to the second logic bit setting.

[0017] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts may be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0018] Figure 1 A base die 11 is shown according to an embodiment of the present disclosure.

[0019] like Figure 1 As shown, the base die 11 includes a test mode control circuit (TM CNT) 21, a select clock generation circuit (SCLK GEN) 23, a test code storage circuit (TSVOS STG) 25, a code output circuit (CD OUT) 27, and output pads 29. Multiple core dies (e.g.) Figure 5 The core dies 321-1 to 321-L can be disposed on the base die 11. The base die 11 and multiple core dies are perpendicularly connected to each other using microbump pads and vias to form a memory device, such as... Figure 5 Storage device 37 in the middle.

[0020] The test mode control circuit 21 generates a test clock signal TCLK and an acceleration mode signal T2-EN. The test clock signal TCLK and the acceleration mode signal T2-EN affect the output of the test code CD-OS in the test read mode, which includes a normal mode and an acceleration mode. The test mode control circuit 21 generates the test clock signal TCLK that switches between test read modes. In normal mode, the test mode control circuit 21 generates the deactivated acceleration mode signal T2-EN, and in acceleration mode, it generates the activated acceleration mode signal T2-EN. Whether the test read mode is normal or acceleration mode can be determined by the signal stored in the mode register included in the test mode control circuit 21, or by an external signal applied from outside the test mode control circuit 21.

[0021] The clock selection generation circuit 23 is electrically connected to the test mode control circuit 21 and receives the test clock signal TCLK and the acceleration mode signal T2-EN from the test mode control circuit 21. The clock selection generation circuit 23 generates a selection clock signal SCLK for the test mode based on the test clock signal TCLK and the acceleration mode signal T2-EN. When the acceleration mode signal T2-EN is deactivated, the clock selection generation circuit 23 outputs the test clock signal TCLK as the selection clock signal SCLK for the normal mode. When the acceleration mode signal T2-EN is activated, the clock selection generation circuit 23 generates the selection clock signal SCLK for the acceleration mode, which includes pulses generated at the rising and falling edges of the test clock signal TCLK.

[0022] Test code storage circuit 25 stores test code CD-OS. Test code CD-OS contains information about test results, such as the open or short circuit status of vias contained in the base die 11 and each core die. An open circuit means no current flows through the via, and a short circuit means excessive current flows through the via depending on the connection between the vias. Test code CD-OS contains multiple bits, and the binary bit settings of the multiple bits contained in test code CD-OS can correspond to at least one via determined to be open or short-circuited in each of the vias contained in the base die 11 and the multiple core dies. For example, when the vias contained in each of the base die 11 and the multiple core dies include a first column of vias and a second column of vias connected using microbump pads, a test code CD-OS containing bits with a first binary bit setting can correspond to the first column of vias, and a test code CD-OS containing bits with a second binary bit setting can correspond to the second column of vias.

[0023] The code output circuit 27 is electrically connected to the selection clock generation circuit 23 and the test code storage circuit 25. It receives the selection clock signal SCLK from the selection clock generation circuit 23 and the test code CD-OS from the test code storage circuit 25. The code output circuit 27 outputs a read code RCD to the output pad 29 based on the selection clock signal SCLK and the test code CD-OS. In normal mode, the code output circuit 27 outputs the test code CD-OS as a read code RCD through the output pad 29 according to the selection clock signal SCLK generated by the test clock signal TCLK. In accelerated mode, the code output circuit 27 outputs the test code CD-OS as a read code RCD synchronously with the rising edge of the test clock signal TCLK through the output pad 29. The selection clock signal SCLK includes pulses generated at the rising and falling edges of the test clock signal TCLK. In accelerated mode, the code output circuit 27 outputs the test code CD-OS as the read code RCD through the output pad 29 in sync with the rising and falling edges of the test clock signal TCLK.

[0024] As described above, in the test read mode of the output test code CD-OS (where the test code CD-OS contains test results such as open circuits or short circuits included in each of the base die 11 and multiple core dies), the test time can be reduced by providing an accelerated mode that generates pulses on each edge of the test clock signal TCLK to output the test code CD-OS.

[0025] Figure 2 A clock generation circuit 23 according to one embodiment of the present disclosure is shown, for example, as Figure 1 As shown.

[0026] like Figure 2 As shown, the clock generation circuit 23 includes a delay unit (DLY) 231, an accelerated clock generator 233, and a selector 235.

[0027] The delay unit 231 delays the test clock signal TCLK by a preset delay period to generate a delayed test clock signal TCLKd. The delay period is the time period used to set the pulse width of the accelerated clock signal T2CLK, and can be implemented in various ways according to the embodiments.

[0028] Accelerated clock generator 233 is electrically connected to delay unit 231 and receives delayed test clock signal TCLKd from delay unit 231. Accelerated clock generator 233 performs an XOR operation based on test clock signal TCLK and delayed test clock signal TCLKd to generate accelerated clock signal T2CLK. Accelerated clock generator 233 generates accelerated clock signal T2CLK, which contains pulses generated during a period when the phase of test clock signal TCLK and the phase of delayed test clock signal TCLKd are different. Accelerated clock generator 233 generates accelerated clock signal T2CLK, which contains pulses generated at the rising and falling edges of test clock signal TCLK. The pulse width of accelerated clock signal T2CLK is set to a preset delay period of delay unit 231. The rising edge of the test clock signal TCLK refers to the moment when the test clock signal TCLK transitions from a logic low level to a logic high level, and the falling edge of the test clock signal TCLK refers to the moment when the test clock signal TCLK transitions from a logic high level to a logic low level.

[0029] Selector 235 is electrically connected to acceleration clock generator 233 and receives acceleration clock signal T2CLK from acceleration clock generator 233. Selector 235 generates selection clock signal SCLK based on acceleration mode signal T2-EN, test clock signal TCLK, and acceleration clock signal T2CLK. When the deactivated acceleration mode signal T2-EN is received in normal mode, selector 235 outputs the test clock signal TCLK received through the first terminal "0" as selection clock signal SCLK. When the activated acceleration mode signal T2-EN is received in acceleration mode, selector 235 outputs the acceleration clock signal T2CLK received through the second terminal "1" as selection clock signal SCLK.

[0030] When the acceleration mode signal T2-EN is deactivated, the selection clock generation circuit 23 outputs the test clock signal TCLK as the selection clock signal SCLK in normal mode. When the acceleration mode signal T2-EN is activated, the selection clock generation circuit 23 generates the selection clock signal SCLK in acceleration mode, which includes pulses generated at the rising and falling edges of the test clock signal TCLK.

[0031] Figure 3 and Figure 4 This is a timing diagram of the operation of the clock generation circuit 23 according to an embodiment of the present disclosure.

[0032] like Figure 3As shown, the clock generation circuit 23 generates an accelerated clock signal T2CLK based on the delayed test clock signal TCLKd obtained by delaying the test clock TCLK by a delay period td, and also generates the test clock signal TCLK. When the accelerated mode signal T2-EN, which is deactivated at a logic low level, is received in normal mode, the clock generation circuit 23 outputs the test clock signal TCLK as the selection clock signal SCLK. Since the selection clock signal SCLK is generated from the test clock signal TCLK, the selection clock signal SCLK is generated at the times T11, T12, and T13 when the rising edge of the test clock signal TCLK occurs.

[0033] like Figure 4 As shown, the clock generation circuit 23 generates an accelerated clock signal T2CLK based on the delayed test clock signal TCLKd obtained by delaying the test clock TCLK by a delay period td, and then generates the test clock signal TCLK. When the accelerated mode signal T2-EN, which is activated at a logic high level, is received in accelerated mode, the clock generation circuit 23 outputs the accelerated clock signal T2CLK as the selection clock signal SCLK. Since the selection clock signal SCLK is generated by the accelerated clock signal T2CLK, the selection clock signal SCLK is generated at the times T21, T23, T25 when the rising edge of the test clock signal TCLK occurs, and at the times T22, T24, T26 when the falling edge of the test clock signal TCLK occurs.

[0034] Figure 5 This is a block diagram illustrating a storage system 3 according to an embodiment of the present disclosure.

[0035] like Figure 5 As shown, the storage system 3 includes a printed circuit board (PCB) 31, a substrate 33, an interposer 35, a storage device 37, and a processor 39.

[0036] Printed circuit board 31 connects various electronic components to form an electronic circuit. The electronic circuit may include a storage system 3. A copper (Cu) layer, solder mask, silkscreen, etc., are formed on the printed circuit board 31. Circuit paths for transmitting or conveying signals or electricity are formed in the copper (Cu) layer. The solder mask prevents damage to the circuit and protects specific areas of the soldered components. Silkscreen uses characters or symbols printed on the surface of the printed circuit board 31 to indicate the location or information of the electronic components.

[0037] A substrate 33 is disposed on a printed circuit board 31 and mechanically supports an interposer 35, a memory device 37, and a processor 39. Bump pads (e.g., bump pad 311) are provided between the substrate 33 and the printed circuit board 31. The substrate 33 serves as the physical foundation of the printed circuit board 31 and is an insulator. The substrate 33 may include materials such as FR4 (an insulator made of glass fiber and epoxy resin), ceramics (capable of withstanding high temperatures, possessing suitable thermal conductivity, and used in high-frequency circuits), and polyimide (used as a base material for flexible PCBs due to its flexibility).

[0038] Intermediate layer 35 is disposed on substrate 33 (with bump pads therein) and includes wires connecting electronic components (e.g., memory device 37 and processor 39) that have mismatched form factors or pin arrangements or different spacing. Intermediate layer 35 can convert signals for communication over different interfaces (such as DDR, HBM, PCIe).

[0039] A memory device 37 is disposed on an interposer layer 35, with pads (e.g., microbump pads 313) therebetween. The memory device 37 stores data received from a processor 39 or, under the control of the processor 39, outputs stored data to the processor 39. The memory device 37 includes a base die 320 and a plurality of core dies 321-1 to 321-L, where L is an integer greater than 1. The core dies 321-1 to 321-L are stacked on top of the base die 320, with microbump pads therebetween. The base die 320 and the core dies 321-1 to 321-L are perpendicularly connected to each other using vias and microbump pads. The base die 320 controls efficient data transfer between the processor 39 and the core dies 321-1 to 321-L. The base die 320 receives an input / output power supply voltage (drain voltage for I / O, also known as the output stage drain power supply voltage) VDDQ as an operating voltage used during the operation of the internal circuitry included in the base die 320. The base die 320 receives the input / output power supply voltage VDDQ from the printed circuit board 31 via the substrate 33 and the interposer 35. The input / output power supply voltage VDDQ is the voltage supplied to the buffer transmitting data and is distinct from or different from the power supply voltage VDD. Core dies 321-1 to 321-L use the peripheral voltage VPERI as their operating voltage during the operation of the internal circuitry included in core dies 321-1 to 321-L. Core dies 321-1 to 321-L generate the peripheral voltage VPERI from the power supply voltage VDD received through the base die 320. Core dies 321-1 to 321-L generate the peripheral voltage VPERI at a voltage level lower than the input / output power supply voltage VDDQ and use the peripheral voltage VPERI as their operating voltage. Each of the core dies 321-1 to 321-L includes multiple channel regions, for example, eight or sixteen independently operating channel regions. Each of the multiple channel regions is assigned an independently operating channel for receiving or transmitting data. The number L of core dies 321-1 to 321-L can be four, eight, twelve, sixteen, etc. For example, when each of core dies 321-1 to 321-12 has eight channels, core dies 321-1 to 321-4, core dies 321-5 to 321-8, and core dies 321-9 to 321-12 each include a thirty-two channel region, and data is transmitted and received from the processor 39 in units of a memory rank containing thirty-two channels.

[0040] The concepts have been disclosed in conjunction with various examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. The scope of this disclosure is not limited to these descriptions. All variations within the meaning and scope of the equivalents of the claims are included within its scope.

Claims

1. A storage device, comprising: Basic nude film; as well as Multiple core dies are stacked on top of the base die and connected to the base die using multiple vias and multiple bump pads. In normal mode, the base die outputs the test code as the read code through the output pad in sync with the first edge of the test clock signal, and in accelerated mode, it outputs the test code as the read code through the output pad in sync with the first and second edges of the test clock signal.

2. The storage device according to claim 1, wherein, The base die includes a test code storage circuit that stores the test code, which contains information about the test results regarding whether the vias contained in each of the base die and the plurality of core dies are open or short-circuited.

3. The storage device according to claim 1, wherein, The base die includes a select clock generation circuit that generates a select clock signal based on the test clock signal and the acceleration mode signal.

4. The storage device according to claim 3, wherein, The selected clock generation circuit receives the acceleration mode signal that is deactivated in the normal mode and generates the test clock signal as the selected clock signal.

5. The storage device according to claim 3, wherein, The selected clock generation circuit receives the acceleration mode signal activated in the acceleration mode and generates the selected clock signal containing pulses generated at the first and second edges of the test clock signal.

6. The storage device according to claim 3, wherein, The base die also includes a code output circuit, which outputs the test code as the read code through the output pad in sync with the selection clock signal.

7. The storage device according to claim 3, wherein, The selected clock generation circuit includes: A delay unit that delays the test clock signal by a preset delay period to generate a delayed test clock signal; An accelerated clock generator that generates an accelerated clock signal based on the test clock signal and the delayed test clock signal; and The selector generates the selection clock signal based on the acceleration mode signal, the acceleration clock signal, and the test clock signal.

8. The storage device according to claim 7, wherein, The accelerated clock generator generates the accelerated clock signal containing pulses that appear at the first and second edges of the test clock signal.

9. The storage device according to claim 7, wherein, The selector receives the acceleration mode signal that is deactivated in the normal mode and selects the test clock signal as the selected clock signal.

10. The storage device according to claim 9, wherein, The selector receives the acceleration mode signal that is activated in the acceleration mode and selects the acceleration clock signal as the selection clock signal.

11. The storage device according to claim 3, wherein, The basic die also includes a test mode control circuit, which generates the test clock signal and the acceleration mode signal in the test read mode. The test read mode includes the normal mode and the acceleration mode.

12. A storage system, comprising: Intermediate layer, which is stacked on the substrate; as well as Storage devices and processors, stacked on the interposer layer, are interconnected by wires formed in the interposer layer. The storage device includes a base die and multiple core dies stacked on the interposer layer. The base die and the plurality of core dies are interconnected using multiple vias and multiple bump pads, and In normal mode, the base die outputs the test code as the read code through the output pad in sync with the first edge of the test clock signal, and in accelerated mode, it outputs the test code as the read code through the output pad in sync with the first and second edges of the test clock signal.

13. The storage system according to claim 12, wherein, The base die includes a test code storage circuit that stores the test code, which contains information about the test results regarding whether the vias contained in each of the base die and the plurality of core dies are open or short-circuited.

14. The storage system according to claim 12, wherein, The base die includes a select clock generation circuit that generates a select clock signal based on the test clock signal and the acceleration mode signal.

15. The storage system according to claim 14, wherein, The clock selection generation circuit receives the acceleration mode signal that has been deactivated in the normal mode, and generates the test clock signal as the clock selection signal. The selected clock generation circuit receives the acceleration mode signal activated in the acceleration mode and generates the selected clock signal containing pulses generated at the first and second edges of the test clock signal.

16. The storage system according to claim 14, wherein, The base die also includes a code output circuit, which outputs the test code as the read code through the output pad in sync with the selection clock signal.

17. The storage system according to claim 14, wherein, The selected clock generation circuit includes: A delay unit that delays the test clock signal by a preset delay period to generate a delayed test clock signal; An accelerated clock generator that generates an accelerated clock signal based on the test clock signal and the delayed test clock signal; and The selector generates the selection clock signal based on the acceleration mode signal, the acceleration clock signal, and the test clock signal.

18. The storage system according to claim 17, wherein, The accelerated clock generator generates the accelerated clock signal containing pulses that appear at the first and second edges of the test clock signal.

19. The storage system according to claim 17, wherein, The selector receives the acceleration mode signal that is deactivated in the normal mode, and selects the test clock signal as the selection clock signal. The selector receives the acceleration mode signal that is activated in the acceleration mode and selects the acceleration clock signal as the selection clock signal.

20. The storage system according to claim 14, wherein, The basic die also includes a test mode control circuit, which generates the test clock signal and the acceleration mode signal in the test read mode. The test read mode includes the normal mode and the acceleration mode.

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