Apparatus and method for transmission through voltage in a memory device

Abstract

The present disclosure relates to a memory device including a memory region including a plurality of memory cells connected to a word line and a bit line, a voltage generation unit configured to generate a pass voltage and an equalization voltage, a first transmission unit configured to transmit the pass voltage or the equalization voltage between the voltage generation unit and the word line through a first path, a second transmission unit configured to transmit the pass voltage between the voltage generation unit and the word line through a second path physically separated from the first path, and an operation control unit configured to enable the first transmission unit and the second transmission unit in a pass voltage rising time period so that the pass voltage is transmitted through the first path and the second path, and to enable the first transmission unit in an equalization time period so that the equalization voltage is transmitted through the first path.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0037311, filed with the Korean Intellectual Property Office on March 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device, including but not limited to an apparatus and method for transmitting a voltage in a non-volatile memory device. Background Technology

[0003] Memory systems include storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory devices are classified as volatile memory devices or non-volatile memory devices. Volatile memory devices are those whose stored data is lost when power to the device is interrupted. Examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are those whose stored data is retained even when power to the device is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is classified as NOR memory and NAND memory.

[0004] A non-volatile memory device includes multiple memory cells connected between multiple word lines and multiple bit lines. Each of the multiple memory cells included in the non-volatile memory device is an element capable of electrical programming / erasing operations, and programming and erasing operations can be performed by changing the threshold voltage of each memory cell, since electrons are moved by a strong electric field applied to a thin oxide film. Each of the multiple memory cells included in the non-volatile memory device performs a read operation by identifying the level of the threshold voltage of each memory cell.

[0005] After a programming or reading operation begins on a plurality of memory cells included in a non-volatile memory device, a programming or reading voltage is applied to the selected word line among the plurality of word lines, and a voltage is applied to the unselected word lines among the plurality of word lines. In this example, the voltage is sufficiently high that all memory cells of the unselected word lines are turned on, so that memory cells of the unselected word lines that are not selected as programming or reading targets do not interfere with the programming or reading operation. Summary of the Invention

[0006] In an embodiment, a memory device may include: a memory region including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a voltage generation unit configured to generate a pass voltage and an equalization voltage; a first transmission unit configured to transmit the pass voltage or equalization voltage between the voltage generation unit and the plurality of word lines via a first path; a second transmission unit configured to transmit the pass voltage between the voltage generation unit and the plurality of word lines via a second path physically separate from the first path; and an operation control unit configured to enable the first transmission unit and the second transmission unit during a pass voltage rise time period, such that the pass voltage is transmitted through the first path and the second path, and to enable the first transmission unit during an equalization time period after a read operation or a programming operation begins, such that the equalization voltage is transmitted through the first path.

[0007] In an embodiment, a method of operating a memory device includes a memory region, a voltage generation unit, and a first path and a second path. The memory region includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines. The voltage generation unit is configured to generate a pass voltage and an equalization voltage. The first path and the second path are located between the voltage generation unit and the plurality of word lines and are physically separated. The method may include: a first transmission process, including transmitting the pass voltage generated by the voltage generation unit to at least one of the plurality of word lines via the first path and the second path during a pass voltage rise time period after the start of a read operation or a programming operation; and a second transmission process, including transmitting the equalization voltage generated by the voltage generation unit to the plurality of word lines via the first path during an equalization time period after the start of a read operation or a programming operation.

[0008] In an embodiment, a method may include: generating a pass voltage and an equalization voltage in a memory device by a voltage generation unit, the memory device including a plurality of memory cells connected to a plurality of word lines; transmitting the pass voltage to at least one of the plurality of word lines via a physically separated first path and second path during a pass voltage rise period after the start of a read operation or a programming operation; and transmitting the equalization voltage to the plurality of word lines via the first path during an equalization period after the start of a read operation or a programming operation. Attached Figure Description

[0009] Figure 1 A memory device in which voltage is transmitted according to an embodiment of the present disclosure is shown.

[0010] Figure 2 A voltage generation unit according to an embodiment of the present disclosure is shown.

[0011] Figures 3A to 3C A memory device is shown during the transmission of voltage and equalization voltage according to an embodiment of the present disclosure.

[0012] Figure 4A and Figure 4B This is a timing diagram of the voltage level changes of the word line according to an embodiment of the present disclosure.

[0013] Figure 5 A memory device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0014] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. The specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0015] Terms such as "first" and "second" are used to distinguish multiple elements, but do not imply the size, order, priority, quantity, importance, time, distance, or logic of the elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0016] When one element is identified as "connected" to another element, the two elements can be directly connected or connected through at least one intermediate element between them. When two elements are identified as "directly connected," one element is directly connected to the other element, and there is no intermediate element between them.

[0017] The "through voltage rise time" includes the period during which the through voltage rises from the ground voltage VSS to the level of the through voltage when it is applied to an unselected word line. Shortening the length of the through voltage rise time can reduce the time required to perform programming or reading operations.

[0018] The embodiments include a memory device capable of shortening the voltage rise time period after a read or program operation begins, and a method for operating the memory device. During the voltage rise time period, the voltage level can rapidly rise to a target level, thereby shortening the length of the voltage rise time period.

[0019] According to this specification, a memory device includes a voltage generation circuit and physically separated transmission paths located between the voltage generation circuit and multiple word lines. During an equalization period, an equalization voltage can be transmitted via a first transmission path. During a voltage rise period that does not overlap with the equalization period, a voltage rise can be transmitted via two transmission paths. Either the equalization voltage or the voltage rise can be transmitted via the first transmission path.

[0020] Figure 1 , Figure 2 , Figures 3A to 3C as well as Figure 5 A block diagram can be used based on and Figure 1 , Figure 2 , Figures 3A to 3C as well as Figure 5 The circuits or logic gates described in the associated description are used to implement the device. “Circuit” or “logic gate” includes, but is not limited to, (a) hardware-only circuit implementations such as analog and / or digital circuit implementations, and (b) combinations of circuits, software and / or firmware, including one or more processors configured to execute instructions such as software or firmware stored in one or more non-transitory computer-readable media such as memory devices to cause an electronic device to perform one or more functions.

[0021] Figure 1 A memory device in which voltage is transmitted according to an embodiment of the present disclosure is shown.

[0022] Reference Figure 1 The memory device according to an embodiment of the present disclosure includes a memory region 101, a voltage generation unit 102, a first transmission unit 103, a second transmission unit 104, an operation control unit 105, and a word line selection unit 106.

[0023] In this example, memory region 101 includes multiple memory cells connected to multiple word lines WL<1:k> and multiple bit lines BL<1:m>. For example, each of the multiple memory cells includes a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a three-level cell (TLC) storing three bits of data, or a four-level cell (QLC) storing four bits of data.

[0024] Word line selection unit 106 selects at least one word line from a plurality of word lines WL<1:k> included in memory region 101.

[0025] According to an embodiment, after a programming or reading operation begins, the word line selection unit 106 selects one word line from a plurality of word lines WL<1:k>, i.e., the "selected word line". After a programming or reading operation begins, the word line selection unit 106 selects a word line other than the selected word line from the plurality of word lines WL<1:k>, i.e., the "unselected word line". The word line selection unit 106 can select each of the plurality of word lines WL<1:k>.

[0026] The voltage generation unit 102 generates the pass voltage VPASS and the equalization voltage VEQ.

[0027] The programming operations for non-volatile memory devices will now be described.

[0028] An initial equalization operation is performed on each of the multiple word lines WL<1:k> to equalize each of them to the level of the equalization voltage VEQ. For example, during the initial equalization operation, the equalization voltage VEQ is the level of the ground voltage VSS. In this example, during the initial equalization operation period, each of the multiple word lines WL<1:k> is equalized to the level of the ground voltage VSS.

[0029] By performing a pass voltage boost operation on each of the multiple word lines WL<1:k>, the voltage at each of the multiple word lines WL<1:k> is increased to the level of the pass voltage VPASS.

[0030] By performing a pass voltage sustaining operation on the unselected word lines, the unselected word lines among the multiple word lines WL<1:k> are maintained at the level of the pass voltage VPASS. When the pass voltage sustaining operation is performed on the unselected word lines as described above, the threshold voltage level of the memory cell connected to the selected word line is changed by applying a programming voltage to the selected word line.

[0031] By performing a post-equalization operation on each of the multiple word lines WL<1:k>, each of the multiple word lines WL<1:k> is equalized to the level of the equalization voltage VEQ. In this example, during the post-equalization operation, the equalization voltage VEQ is higher than the level of the ground voltage VSS and lower than the level of the source voltage VDD. During the post-equalization operation period, each of the multiple word lines WL<1:k> is equalized to a voltage level higher than the level of the ground voltage VSS and lower than the level of the source voltage VDD.

[0032] The read operation for the memory device will now be described.

[0033] An initial equalization operation is performed on each of the multiple word lines WL<1:k>, so that each of the multiple word lines WL<1:k> is equalized to the level of the equalization voltage VEQ. In this example, during the initial equalization operation, the equalization voltage VEQ is at the level of the ground voltage VSS. During the initial equalization operation period, each of the multiple word lines WL<1:k> is equalized to the level of the ground voltage VSS.

[0034] By performing a pass voltage rise operation on each of the unselected word lines, each of the multiple word lines WL<1:k> is raised to the level of the pass voltage VPASS.

[0035] By performing a pass voltage sustaining operation on the unselected word lines, the unselected word lines among the multiple word lines WL<1:k> are maintained at the level of the pass voltage VPASS.

[0036] During the time period of performing a voltage rise operation and a voltage sustain operation on an unselected word line, the threshold voltage level of the memory cell connected to the selected word line is sensed by performing a read voltage application operation on the selected word line.

[0037] By performing a post-equalization operation on each of the multiple word lines WL<1:k>, each of the multiple word lines WL<1:k> is equalized to the level of the equalization voltage VEQ. In this example, during the post-equalization operation, the level of the equalization voltage VEQ is higher than the level of the ground voltage VSS and lower than the level of the source voltage VDD. During the post-equalization operation period, each of the multiple word lines WL<1:k> is equalized to a voltage level higher than the level of the ground voltage VSS and lower than the level of the source voltage VDD.

[0038] The difference between the initial equalization period and the subsequent equalization period lies in the fact that the level of the equalization voltage VEQ differs in each time period within both periods. However, they share the commonality that each of the multiple word lines WL<1:k> is equalized to the level of the equalization voltage VEQ. The phrase "equalization operation" without the qualifiers "initial" or "subsequent" refers to both the initial and subsequent equalization periods.

[0039] Reference Figure 1The first transmission unit 103 transmits the pass voltage VPASS or equalization voltage VEQ between the voltage generation unit 102 and the word line selection unit 106 via the first path PATH1. When enabled, the first transmission unit 103 transmits the pass voltage VPASS or equalization voltage VEQ generated by the voltage generation unit 102 via the first path PATH1 to at least one word line selected by the word line selection unit 106 from multiple word lines WL<1:k>. When disabled, the first transmission unit 103 does not transmit electrical signals from the first path PATH1, for example, by forming an open circuit with the first path PATH1.

[0040] The second transmission unit 104 transmits the pass voltage VPASS between the voltage generation unit 102 and the word line selection unit 106 via the second path PATH2. When enabled, the second transmission unit 104 transmits the pass voltage VPASS generated by the voltage generation unit 102 via the second path PATH2 to at least one word line selected by the word line selection unit 106 from a plurality of word lines WL<1:k>. When disabled, the second transmission unit 104 does not transmit electrical signals from the second path PATH2, for example, by forming an open circuit with the second path PATH2.

[0041] When the voltage VPASS generated by the voltage generation unit 102 is transmitted to at least one word line selected by the word line selection unit 106 during the voltage rise period after the start of the read operation or programming operation, the operation control unit 105 activates both the first transmission unit 103 and the second transmission unit 104 to control both the first path PATH1 and the second path PATH2.

[0042] During the balancing period following the start of a read or program operation, when the balancing voltage VEQ generated by the voltage generation unit 102 is transmitted to at least one word line selected by the word line selection unit 106, the operation control unit 105 activates the first transmission unit 103 to control the first path PATH1. The operation control unit 105 deactivates the second transmission unit 104 to keep the second path PATH2 open during the balancing period.

[0043] When, during the voltage hold-up period after the start of a read or programming operation, the voltage VPASS generated by the voltage generation unit 102 is transmitted to at least one word line selected by the word line selection unit 106, the operation control unit 105 enables the second transmission unit 104 to control the second path PATH2. The operation control unit 105 disables the first transmission unit 103 to keep the first path PATH1 open during the voltage hold-up period.

[0044] During the voltage rise period, word line selection unit 106 selects an unselected word line as the operation target. During the voltage rise period, word line selection unit 106 drives the unselected word line to the pass voltage VPASS transmitted through the first transmission unit 103 and the second transmission unit 104.

[0045] During the voltage holding period, the word line selection unit 106 selects the unselected word line as the operation target. During the voltage holding period, the word line selection unit 106 drives the unselected word line to the voltage VPASS transmitted through the second transmission unit 104.

[0046] During the balancing period, the word line selection unit 106 selects each of the multiple word lines WL<1:k> as the operation target. During the balancing period, the word line selection unit 106 drives each of the multiple word lines WL<1:k> to the balancing voltage VEQ transmitted through the first transmission unit 103.

[0047] For example, the operation control unit 105 generates a first control signal EN1, which is activated during the voltage rise period and deactivated during the voltage hold period and equalization period. The operation control unit 105 generates a second control signal EN2, which is activated during the equalization period and deactivated during the voltage rise period and voltage hold period. The operation control unit 105 generates a third control signal EN3, which is activated during the voltage hold period and deactivated during the voltage rise period and equalization period.

[0048] During the activation periods of the first control signal EN1 and the second control signal EN2, the first transmission unit 103 is enabled. During the voltage rise period or equalization period corresponding to the activation period of the first control signal EN1 or the second control signal EN2, the first transmission unit 103 is enabled, and during the voltage hold period corresponding to the deactivation period of the first control signal EN1 and the second control signal EN2, the first transmission unit 103 is deactivated.

[0049] During the activation periods of the first control signal EN1 and the third control signal EN3, the second transmission unit 104 is enabled. During the voltage rise period or voltage hold period corresponding to the activation period of the first control signal EN1 or the third control signal EN3, the second transmission unit 104 is enabled, and during the equalization period corresponding to the deactivation period of the first control signal EN1 or the third control signal EN3, the second transmission unit 104 is deactivated.

[0050] The voltage generation unit 102 generates a through voltage VPASS during the through voltage rise period or through voltage hold period corresponding to the activation period of the first control signal EN1 or the third control signal EN3, and generates an equalization voltage VEQ during the equalization period corresponding to the activation period of the second control signal EN2. In this embodiment, the voltage generation unit 102 does not generate the through voltage VPASS during the equalization period corresponding to the deactivation period of the first control signal EN1 or the third control signal EN3. Similarly, the voltage generation unit 102 does not generate the equalization voltage VEQ during the through voltage rise period or through voltage hold period corresponding to the deactivation period of the second control signal EN2.

[0051] During the voltage rise period corresponding to the activation period of the first control signal EN1, the word line selection unit 106 selects an unselected word line as the operation target. In this embodiment, during the voltage rise period corresponding to the activation period of the first control signal EN1, the word line selection unit 106 drives the unselected word line to the voltage VPASS transmitted through the first transmission unit 103 and the second transmission unit 104.

[0052] During the pass voltage holding period corresponding to the activation period of the third control signal EN3, the word line selection unit 106 selects the unselected word line as the operation target. In this embodiment, during the pass voltage holding period corresponding to the activation period of the third control signal EN3, the word line selection unit 106 drives the unselected word line to the pass voltage VPASS transmitted through the second transmission unit 104.

[0053] During the equalization period corresponding to the activation period of the second control signal EN2, the word line selection unit 106 selects each of the multiple word lines WL<1:k> as the operation target. In this embodiment, during the equalization period corresponding to the activation period of the second control signal EN2, the word line selection unit 106 drives each of the multiple word lines WL<1:k> to the equalization voltage VEQ transmitted through the first transmission unit 103.

[0054] Figure 2 A voltage generation unit is shown, for example, such as Figure 1 The voltage generation unit shown.

[0055] Reference Figure 2 The voltage generation unit 102 includes a voltage generation unit 201, a first adjustment unit 202, and a second adjustment unit 203.

[0056] In this example, the through voltage VPASS is generated by voltage generation unit 201. In this example, since the level of the through voltage VPASS is higher than the level of the source voltage VDD, the through voltage VPASS is generated by charge pumping method by voltage generation unit 201.

[0057] During the voltage rise time and voltage hold time, the voltage generation unit 201 generates the voltage VPASS by charge pumping the source voltage VDD. The voltage generation unit 201 generates the voltage VPASS in response to a first control signal EN1 generated by the operation control unit 105, which remains active during the voltage rise time. The voltage generation unit 201 also generates the voltage VPASS in response to a third control signal EN3 generated by the operation control unit 105, which remains active during the voltage hold time.

[0058] During the voltage rise period, the first regulating unit 202 stabilizes the first path PATH1 using the through voltage VPASS transmitted through the voltage generation unit 201. During the equalization period, the first regulating unit 202 internally generates an equalization voltage VEQ and uses the generated equalization voltage VEQ to stabilize the first path PATH1. In response to a first control signal EN1 generated by the operation control unit 105, which remains active during the voltage rise period, the first regulating unit 202 stabilizes the first path PATH1 using the through voltage VPASS generated by the voltage generation unit 201. In response to a second control signal EN2 generated by the operation control unit 105, which remains active during the equalization period, after internally generating the equalization voltage VEQ, the first regulating unit 202 uses the generated equalization voltage VEQ to stabilize the first path PATH1.

[0059] In this example, stabilizing the first path PATH1 includes: when the voltage level of the first path PATH1 differs from the level of the through voltage VPASS or the equalization voltage VEQ, the first adjustment unit 202 adjusts the voltage level of the first path PATH1 to maintain it at the level of the through voltage VPASS or the equalization voltage VEQ. For example, when the voltage level of the first path PATH1 is lower than the level of the through voltage VPASS, the first adjustment unit 202 raises the voltage level of the first path PATH1 to the level of the through voltage VPASS and maintains it at the level of the through voltage VPASS. For example, when the voltage level of the first path PATH1 is higher than the level of the equalization voltage VEQ, the first adjustment unit 202 lowers the voltage level of the first path PATH1 to the level of the equalization voltage VEQ and maintains it at the level of the equalization voltage VEQ.

[0060] During the voltage rise time and voltage hold time, the second regulating unit 203 stabilizes the second path PATH2 using the through voltage VPASS transmitted by the through voltage generation unit 201. In response to a first control signal EN1 generated by the operation control unit 105 that remains active during the voltage rise time, the second regulating unit 203 stabilizes the second path PATH2 using the through voltage VPASS generated by the through voltage generation unit 201. In response to a third control signal EN3 generated by the operation control unit 105 that remains active during the through voltage hold time, the second regulating unit 203 stabilizes the second path PATH2 using the through voltage VPASS generated by the through voltage generation unit 201.

[0061] In this example, "stabilizing" the second path PATH2 includes: when the voltage level of the second path PATH2 differs from the level of the through voltage VPASS, the second adjustment unit 203 adjusts the voltage level of the second path PATH2 to maintain it at the level of the through voltage VPASS. For example, when the voltage level of the second path PATH2 is lower than the level of the through voltage VPASS, the second adjustment unit 203 raises the voltage level of the second path PATH2 to the level of the through voltage VPASS and maintains it at the level of the through voltage VPASS.

[0062] According to an embodiment, the first adjustment unit 202 and the second adjustment unit 203 use a feedback control method to stabilize the first path PATH1 and the second path PATH2.

[0063] According to the embodiment, the first regulating unit 202 and the second regulating unit 203 respectively use the low differential pressure (LDO) regulator method to stabilize the first path PATH1 and the second path PATH2.

[0064] The first adjustment unit 202 and the second adjustment unit 203 may each include multiple regulators.

[0065] When the first regulating unit 202 enters an equalization period and generates an equalization voltage VEQ internally, it identifies whether this equalization period is the initial equalization period entered by the first regulating unit 202 before passing the voltage rise period, or the post-equalization period entered by the first regulating unit 202 after passing the voltage hold period. Based on the identification result, the level of the equalization voltage VEQ generated internally by the first regulating unit 202 is determined. In response to the first control signal EN1 and the second control signal EN2, during the initial equalization period entered by the first regulating unit 202 before passing the voltage rise period, the first regulating unit 202 stabilizes the first path PATH1 at the level of the equalization voltage VEQ, which is generated to be at the level of the ground voltage VSS. In response to the first control signal EN1 and the second control signal EN2, during the post-equalization period entered by the first regulating unit 202 after passing the voltage hold period, the first regulating unit 202 stabilizes the first path PATH1 at the level of the equalization voltage VEQ, which is generated to be at a level higher than the ground voltage VSS and lower than the source voltage VDD.

[0066] For example, if the first control signal EN1 is not activated after the initialization of the first adjustment unit 202, and the second control signal EN2 changes from a disabled state to an activated state, the first adjustment unit 202 will identify the equalization period as the initial equalization period it entered before the voltage rise period. When the equalization period entered by the first adjustment unit 202 is the initial equalization period, the first adjustment unit 202 generates an equalization voltage VEQ, the level of which is the level of the ground voltage VSS.

[0067] For example, when the first control signal EN1 is activated at least once after the initialization of the first adjustment unit 202, if the second control signal EN2 changes from a disabled state to an active state, the first adjustment unit 202 identifies the equalization period as a post-equalization period following the voltage holding period. When the equalization period entered by the first adjustment unit 202 is a post-equalization period, the first adjustment unit 202 generates an equalization voltage VEQ, the level of which is higher than the level of the ground voltage VSS and lower than the level of the source voltage VDD. In response to the first adjustment unit 202 exiting the post-equalization period, the first adjustment unit 202 is initialized.

[0068] For example, the operation control unit 105 generates a separate control signal (not shown). The operation control unit 105 generates a separate control signal to distinguish between the initial equalization period and the post-equalization period, for example, a control signal different from control signals EN1, EN2, and EN3. The operation control unit 105 transmits this separate control signal to the first adjustment unit 202 so that the first adjustment unit 202 adjusts the level of the equalization voltage VEQ.

[0069] Figures 3A to 3C An example is shown below: In a memory device, for example, such as Figure 1 and Figure 2 The memory device shown performs operations including transmitting through voltage and equalizing voltage.

[0070] Figures 3A to 3C It is shown, for example, when referring to Figure 1 and Figure 2 The memory device described is used during the transfer of data via voltage VPASS and equalization voltage VEQ when performing programming or reading operations.

[0071] Reference Figure 3A During the equalization period included in the programming or reading operation, the voltage generation unit 201 does not generate the through voltage VPASS. The first adjustment unit 202 generates the equalization voltage VEQ and transmits the equalization voltage VEQ to multiple word lines WL<1:k> included in the memory region 101 through the first path PATH1 and the word line selection unit 106.

[0072] For example, since the through voltage VPASS is not used during the equalization period included in the programming or reading operation, the through voltage generation unit 201 is deactivated. During the equalization period, the through voltage generation unit 201 does not generate the through voltage VPASS.

[0073] In this embodiment, since the voltage generation unit 201 does not generate a pass voltage VPASS, the second path PATH2, which only transmits the pass voltage VPASS, is not used. Therefore, the second adjustment unit 203 and the second transmission unit 104 are deactivated.

[0074] During the equalization period, an operation is performed to equalize the voltage levels of multiple word lines WL<1:k> included in memory region 101 to the level of the equalization voltage VEQ. The first adjustment unit 202 is activated to generate the equalization voltage VEQ. When the equalization period is identified as the initial equalization period entered by the first adjustment unit 202 before the voltage rise period, the first adjustment unit 202 generates the equalization voltage VEQ, the level of which is the level of the ground voltage VSS. When the equalization period is identified as the post-equalization period entered by the first adjustment unit 202 after the voltage hold period, the first adjustment unit 202 generates the equalization voltage VEQ, the level of which is higher than the level of the ground voltage VSS and lower than the level of the source voltage VDD.

[0075] According to the operation of the first transmission unit 103 activated during the equalization period, the equalization voltage VEQ generated by the first adjustment unit 202 is transmitted through the first path PATH1 and the word line selection unit 106 to multiple word lines WL<1:k> included in the memory region 101.

[0076] When the equalization period is the initial equalization period that the first adjustment unit 202 enters before the voltage rise period, since the equalization voltage VEQ is at the level of the ground voltage VSS, the first adjustment unit 202 equalizes the voltage levels of the multiple word lines WL<1:k> selected by the word line selection unit 106 to the level of the ground voltage VSS. In this example, equalizing the voltage levels of the multiple word lines WL<1:k> to the level of the ground voltage VSS includes reducing or lowering the voltage levels of the multiple word lines WL<1:k>. Therefore, in this example, the current IEQ flows out from the multiple word lines WL<1:k> and flows to the first adjustment unit 202 through the word line selection unit 106, the first transmission unit 103, and the first path PATH1.

[0077] When the equalization period is the post-equalization period entered by the first adjustment unit 202 after the voltage holding period, since the equalization voltage VEQ is in a state where its level is higher than the ground voltage VSS and lower than the source voltage VDD, the first adjustment unit 202 equalizes the voltage levels of the multiple word lines WL<1:k> selected by the word line selection unit 106 to a voltage level that is higher than the ground voltage VSS and lower than the source voltage VDD. In this example, during the voltage holding period before the first adjustment unit 202 exits the equalization period, the unselected word lines among the multiple word lines WL<1:k> are at the level of the pass voltage VPASS, and the selected word lines among the multiple word lines WL<1:k> are at the level of the programming voltage or read voltage. During the subsequent equalization period, equalizing the voltage levels of the multiple word lines WL<1:k> to a level higher than the ground voltage VSS and lower than the source voltage VDD includes lowering the voltage levels of the multiple word lines WL<1:k>. Therefore, current IEQ flows out from the multiple word lines WL<1:k> and flows to the first adjustment unit 202 through the word line selection unit 106, the first transmission unit 103, and the first path PATH1.

[0078] Reference Figure 3BDuring the voltage rise period included in the programming or reading operation, the voltage generation unit 201 generates a pass voltage VPASS. During the voltage rise period included in the programming or reading operation, the first adjustment unit 202 transmits the pass voltage VPASS generated by the voltage generation unit 201 to the first path PATH1 and the word line selection unit 106. During the voltage rise period included in the programming or reading operation, the second adjustment unit 203 transmits the pass voltage VPASS generated by the voltage generation unit 201 to the word line selection unit 106 via the second path PATH2.

[0079] For example, the through voltage generation unit 201 is activated because the through voltage VPASS is used during the through voltage rise period included in the programming or reading operation. During the through voltage rise period, the through voltage generation unit 201 generates the through voltage VPASS.

[0080] During the voltage rise period included in the read operation, the first adjustment unit 202 transmits the voltage VPASS through the first path PATH1 and the second path PATH2 to the unselected word lines among the multiple word lines WL<1:k> included in the memory region 101. During the voltage rise period included in the programming operation, the first adjustment unit 202 transmits the voltage VPASS through the first path PATH1 and the second path PATH2 to the multiple word lines WL<1:k> included in the memory region 101. The first adjustment unit 202, the first transmission unit 103, the second adjustment unit 203, and the second transmission unit 104 are enabled.

[0081] For example, the first regulation unit 202, activated during the voltage rise period, does not generate an equalization voltage VEQ. The first regulation unit 202, activated during the voltage rise period, uses the through voltage VPASS generated by the through voltage generation unit 201 to stabilize the first path PATH1. The first transmission unit 103, activated during the voltage rise period, transmits the through voltage VPASS by connecting the first path PATH1, stabilized at the level of the through voltage VPASS by the first regulation unit 202, to the word line selection unit 106. The word line selection unit 106 transmits the through voltage VPASS to each of the multiple word lines WL<1:k> after the programming operation begins, and transmits the through voltage VPASS to the unselected word lines among the multiple word lines WL<1:k> after the read operation begins.

[0082] The second regulation unit 203, activated during the voltage rise period, stabilizes the second path PATH2 using the through voltage VPASS generated by the through voltage generation unit 201. The second transmission unit 104, also activated during the voltage rise period, transmits the through voltage VPASS by connecting the second path PATH2, stabilized at the level of the through voltage VPASS by the second regulation unit 203, to the word line selection unit 106. The word line selection unit 106 transmits the through voltage VPASS to each of the multiple word lines WL<1:k> after the programming operation begins, and transmits the through voltage VPASS to the unselected word lines of the multiple word lines WL<1:k> after the read operation begins.

[0083] During the voltage rise period, the voltage VPASS is transmitted from the voltage generation unit 201 to the word line selection unit 106 via the first path PATH1 and the second path PATH2.

[0084] During the initial equalization period, which is entered by the first adjustment unit 202 and exits before the voltage rise period, the memory device is in a state where the voltage levels at multiple word lines WL<1:k> are equalized using an equalization voltage VEQ at the level of the ground voltage VSS. The operation of applying a pass voltage VPASS to the multiple word lines WL<1:k> during the voltage rise period includes raising the voltage levels of the multiple word lines WL<1:k>. Currents IPASS1 and IPASS2 flow from the first adjustment unit 202 and the second adjustment unit 203, respectively, and flow through the word line selection unit 106 to the multiple word lines WL<1:k> via the first transmission unit 103 and the first path PATH1, and the second transmission unit 104 and the second path PATH2, respectively.

[0085] Reference Figure 3C During the voltage holding period included in the programming or reading operation, the voltage generation unit 201 generates a pass voltage VPASS. The second adjustment unit 203 transmits the pass voltage VPASS generated by the voltage generation unit 201 to the word line selection unit 106 via the second path PATH2. The first adjustment unit 202 and the first transmission unit 103 are deactivated, so the pass voltage VPASS is not transmitted via the first path PATH1.

[0086] For example, during the voltage rise period included in a programming or reading operation, the voltage generation unit 201 is activated to generate the voltage VPASS. During the voltage rise period, the voltage generation unit 201 generates the voltage VPASS.

[0087] During the voltage hold-up period included in programming or reading operations, the voltage VPASS is transmitted via the second path PATH2 instead of the first path PATH1 to the unselected word lines among the multiple word lines WL<1:k> included in the memory region 101. The first adjustment unit 202 and the first transmission unit 103 are deactivated, and the second adjustment unit 203 and the second transmission unit 104 are activated. The voltage hold-up period is the period entered by the second adjustment unit 203 after the voltage rise period. Since the unselected word lines among the multiple word lines WL<1:k> are in a state where the unselected word lines are driven to the level of the voltage VPASS when entering the voltage hold-up period, the unselected word lines among the multiple word lines WL<1:k> included in the memory region 101 can be stably maintained at the level of the voltage VPASS during the voltage hold-up period even though only the second path PATH2 is used. In this embodiment, since the first path PATH1 is not used during the voltage hold-up period, the first adjustment unit 202 and the first transmission unit 103 are deactivated.

[0088] For example, the second adjustment unit 203, activated during the voltage holding period, stabilizes the second path PATH2 using the through voltage VPASS generated by the through voltage generation unit 201. The second transmission unit 104, activated during the voltage holding period, transmits the through voltage VPASS to the word line selection unit 106 by connecting the second path PATH2, stabilized at the level of the through voltage VPASS by the second adjustment unit 203, to the word line selection unit 106, thereby transmitting the through voltage VPASS to the unselected word line selected by the word line selection unit 106 from multiple word lines WL<1:k>.

[0089] In this example, during the voltage holding period, the voltage VPASS is transmitted from the voltage generation unit 201 to the word line selection unit 106 via the second path PATH2.

[0090] During the voltage rise period, which is entered by the second adjustment unit 203 and exits before the voltage hold period, the unselected word line is in a state where the unselected word line is driven to the voltage VPASS level. Although the unselected word line selected by the word line selection unit 106 is in a state where the unselected word line is driven to the voltage VPASS level during the voltage rise period, the current IPASS2 flows out from the second adjustment unit 203 and through the second transmission unit 104 and the second path PATH2 to the unselected word line, so that the unselected word line can be stably maintained at the voltage VPASS level during the voltage hold period.

[0091] Figure 4A and Figure 4BThis is, for example, in a memory device (e.g., refer to...). Figure 1 and Figure 2 Example of a timing diagram showing the voltage level changes of multiple word lines after the start of programming and reading operations of a described memory device.

[0092] Figure 4A and Figure 4B For example, when a memory device (e.g., refer to...) Figure 1 and Figure 2 Example of a timing diagram showing the voltage level changes of each of the selected word line SEL_WL and the unselected word line UNSEL_WL among a plurality of word lines WL<1:k> during programming and reading operations of the described memory device.

[0093] Figure 4A This shows the voltage level changes of each of the selected word line SEL_WL and the unselected word line UNSEL_WL among a plurality of word lines WL<1:k> when the memory device performs a programming operation.

[0094] For example, when a memory device begins programming, it enters an initial equalization period EQS1 and equalizes the voltage level of each of the multiple word lines WL<1:k> to the level of the equalization voltage VEQ. In this example, during the initial equalization period, the memory device sets the equalization voltage VEQ to the level of the ground voltage VSS. Therefore, during the initial equalization period, each of the multiple word lines WL<1:k> is equalized to the level of the ground voltage VSS.

[0095] Following the initial equalization period EQS1, the memory device enters the voltage rise period PASS_RI. During the voltage rise period PASS_RI, which includes the programming operation, the voltage levels of each of the multiple word lines WL<1:k> are raised or increased to the level of the voltage VPASS. According to an embodiment, the memory device transmits the voltage VPASS via each physically existing path from the voltage generation unit 102 to the word line selection unit 106, the first path PATH1 and the second path PATH2. Therefore, during the voltage rise period PASS_RI, which includes the programming operation of the memory device according to the embodiment, the voltage levels of the multiple word lines WL<1:k> can rise from the level of the ground voltage VSS to the level of the voltage VPASS much faster than when the voltage VPASS is transmitted via only one path, such as the second path PATH2.

[0096] After the voltage rise time period PASS_RI, the memory device enters the voltage hold time period PASS_KP. During the voltage hold time period PASS_KP included in the programming operation, the memory device continuously maintains the unselected word line UNSEL_WL among the multiple word lines WL<1:k> at the level of the voltage VPASS. According to an embodiment, during the voltage hold time period PASS_KP, the memory device transmits the voltage VPASS through at least one path in the physical path from the voltage generation unit 102 to the word line selection unit 106, for example, through the second path PATH2. Therefore, during the voltage hold time period PASS_KP included in the programming operation of the memory device according to the embodiment, the components that were not used when the unselected word line UNSEL_WL among the multiple word lines WL<1:k> was maintained at the voltage VPASS level, namely the first adjustment unit 202 and the first transmission unit 103, are deactivated.

[0097] During the voltage holding period PASS_KP included in the programming operation, the voltage level of the selected word line SEL_WL among the multiple word lines WL<1:k> rises from the level of the pass voltage VPASS to the level of the programming voltage VPGM. Therefore, the voltage level of the threshold voltage connected to the memory cell of the selected word line SEL_WL is changed. In this example, the operation of applying the programming voltage VPGM to the selected word line SEL_WL is well known in the art.

[0098] After the voltage holding period PASS_KP, the memory cell enters the post-equalization period EQS2, which equalizes the voltage level of each of the multiple word lines WL<1:k> to the level of the equalization voltage VEQ. In this example, during the post-equalization period, the level of the equalization voltage VEQ is higher than the ground voltage VSS and lower than the source voltage VDD. Therefore, during the post-equalization period, the voltage level of each of the multiple word lines WL<1:k> is equalized to a voltage level higher than the ground voltage VSS and lower than the source voltage VDD.

[0099] Figure 4B This shows the voltage level changes of the selected word line SEL_WL and the unselected word line UNSEL_WL among multiple word lines WL<1:k> when the memory device performs a read operation.

[0100] For example, when a read operation begins, the memory device enters an initial equalization period EQS1 and equalizes the voltage level of each of the multiple word lines WL<1:k> to the level of the equalization voltage VEQ. In this example, during the initial equalization period EQS1, the equalization voltage VEQ is at the level of the ground voltage VSS. Therefore, during the initial equalization period EQS1, the voltage level of each of the multiple word lines WL<1:k> is equalized to the level of the ground voltage VSS.

[0101] After the initial equalization period EQS1, the memory device enters the voltage rise period PASS_RI. During the voltage rise period PASS_RI included in the read operation, the voltage level of each of the unselected word lines UNSEL_WL among the multiple word lines WL<1:k> is raised to the level of the pass voltage VPASS. According to an embodiment, the memory device transmits the pass voltage VPASS through each of the physical paths from the voltage generation unit 102 to the word line selection unit 106, the first path PATH1 and the second path PATH2. Therefore, during the voltage rise period PASS_RI included in the read operation of the memory device according to this embodiment, the voltage level of the unselected word lines UNSEL_WL among the multiple word lines WL<1:k> rises from the ground voltage VSS level to the pass voltage VPASS level much faster than when the pass voltage VPASS is transmitted through only one path, such as the second path PATH2.

[0102] After the voltage rise time period PASS_RI, the memory device enters the voltage hold time period PASS_KP. During the voltage hold time period PASS_KP included in the read operation, the voltage level of the unselected word line UNSEL_WL among the multiple word lines WL<1:k> is continuously maintained at the level of the voltage VPASS. In this example, during the voltage hold time period PASS_KP, the memory device according to the embodiment transmits the voltage VPASS through at least one path in the physical path from the voltage generation unit 102 to the word line selection unit 106, for example, through the second path PATH2. Therefore, during the voltage hold time period PASS_KP included in the read operation of the memory device according to this embodiment, components that are not used when the unselected word line UNSEL_WL among the multiple word lines WL<1:k> is maintained at the level of the voltage VPASS, such as the first adjustment unit 202 and the first transmission unit 103, can be deactivated.

[0103] During the read operation, including the voltage rise time period PASS_RI and the voltage hold time period PASS_KP, a read voltage VREAD is applied to the selected word line SEL_WL among multiple word lines WL<1:k>. Therefore, the level of the threshold voltage connected to the memory cell of the selected word line SEL_WL can be sensed. In this example, the operation of applying the read voltage VREAD to the selected word line SEL_WL is well known in the art.

[0104] After the voltage holding period PASS_KP, the memory device enters the post-equalization period EQS2 and equalizes the voltage level of each of the multiple word lines WL<1:k> to the level of the equalization voltage VEQ. During the post-equalization period EQS2, the level of the equalization voltage VEQ is higher than the ground voltage VSS and lower than the source voltage VDD. Therefore, during the post-equalization period EQS2, the voltage level of each of the multiple word lines WL<1:k> is equalized to a voltage level higher than the ground voltage VSS and lower than the source voltage VDD.

[0105] Figure 5 A memory device according to an embodiment of the present disclosure is shown.

[0106] Reference Figure 5 The memory device includes a memory cell array 101 and a control circuit 500. The control circuit 500 includes a control logic unit 105, a page buffer unit 502, a checking unit 503, a data input / output circuit 505, a voltage supply circuit 506, and an address decoder 507. The address decoder 507 includes a reference... Figure 1 The first transmission unit 103, the second transmission unit 104, and the word line selection unit 106 are described. The voltage supply circuit 506 includes reference... Figure 1 The voltage generation unit 102 is described. The control logic unit 504 includes a reference... Figure 1 The described operation control unit 105. Although not in Figure 5 As shown, the first path PATH1 and the second path PATH2 are located between the voltage supply circuit 506 and the address decoder 507.

[0107] The memory cell array 101 includes multiple memory blocks <1:6>. The multiple memory blocks <1:6> are connected to the address decoder 507 via row lines RL. The multiple memory blocks <1:6> are connected to the page buffer unit 502 via bit lines BL1 to BLm. Each of the memory blocks <1:6> includes multiple memory cells.

[0108] The control circuit 500 is configured to perform programming, reading, or erasing operations on selected regions of the memory cell array 101. The control circuit 500 controls the memory cell array 101. For example, the control circuit 500 applies various operating voltages to the row lines RL and bit lines BL1 to BLm and discharges the applied voltages.

[0109] The address decoder 507 of the control circuit 500 is connected to the memory cell array 101 via row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and common source lines.

[0110] Address decoder 507 is configured to operate in response to control by control logic unit 504. Address decoder 507 receives address RADD from control logic unit 504.

[0111] Address decoder 507 is configured to decode the block address of the received address RADD. Address decoder 507 selects at least one memory block from the memory blocks MEMORY BLOCK<1:6> based on the decoded block address. Address decoder 507 is configured to decode the row address of the received address RADD. Address decoder 507 selects at least one word line from the word lines of the selected memory block based on the decoded row address. Word line selection unit 106 included in address decoder 507 selects one word line from the multiple word lines WL<1:k> included in the selected memory block as the target of a programming operation or a read operation, and selects word lines other than the selected word line as unselected word lines. First transmission unit 103 included in address decoder 507 transmits a voltage VPASS or equalization voltage VEQ through a first path PATH1 to word line selection unit 106, which is received from voltage generation unit 102 included in voltage supply circuit 506. The second transmission unit 104 included in the address decoder 507 transmits via voltage VPASS through the second path PATH2 to the word line selection unit 106, which is received from the voltage generation unit 102 included in the voltage supply circuit 506.

[0112] The voltage supply circuit 506 of the control circuit 500 is configured to generate multiple operating voltages VRD, VPGM, VPASS, VERS, and VEQ using an external power supply voltage. The voltage supply circuit 506 operates in response to the control of the control logic unit 504.

[0113] In this embodiment, the voltage supply circuit 506 regulates the external power supply voltage and generates the internal power supply voltage.

[0114] In this embodiment, the voltage supply circuit 506 generates multiple operating voltages VRD, VPGM, VPASS, VERS, and VEQ using an external or internal power supply voltage. For example, the voltage supply circuit 506 generates multiple erase voltages VERS, multiple programming voltages VPGM, multiple pass voltages VPASS, multiple selective read voltages, and multiple non-selective read voltages.

[0115] The generated operating voltages VRD, VPGM, VPASS, VERS, and VEQ are supplied to the memory cell array 101 by the address decoder 507.

[0116] Page buffer unit 502 includes multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm are respectively connected to memory cell array 101 via multiple bit lines BL1 to BLm. The multiple page buffers PB1 to PBm operate in response to the control of control logic unit 504.

[0117] Multiple page buffers PB1 to PBm communicate data DATA with the data input / output circuit 505. During programming operations, the multiple page buffers PB1 to PBm receive the data DATA to be stored through the data input / output circuit 505 and the data line DL.

[0118] The data input / output circuit 505 includes multiple input / output buffers (not shown) for receiving data DATA. During programming operations, the data input / output circuit 505 receives data DATA to be stored from an external device. During reading operations, the data input / output circuit 505 outputs data DATA transferred from multiple page buffers PB1 to PBm included in the page buffer unit 502 to an external device.

[0119] The control logic unit 504 is connected to the address decoder 507, voltage supply circuit 506, page buffer unit 502, data input / output circuit 505, and checking unit 503 included in the control circuit 500. The control logic unit 504 is configured to control all operations of the memory device. The control logic unit 504 operates in response to commands (CMD) from an external device.

[0120] Control logic unit 504 controls control circuit 500 by generating various signals in response to command CMD and address ADDR. For example, control logic unit 504 generates operation signal OPSIG, address RADD, read and write control signals PBSIGNALS, and reference information REF_INFO in response to command CMD and address ADDR. Control logic unit 504 outputs operation signal OPSIG to voltage supply circuit 506, address RADD to address decoder 507, read and write control signals PBSIGNALS to page buffer unit 502, and reference information REF_INFO to checking unit 503. Control logic unit 504 determines whether the verification operation passes or fails in response to pass / fail signals PASS / FAIL output by checking unit 503.

[0121] The relevant concepts have been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than restrictive perspective. Therefore, the scope of this disclosure is not limited to the foregoing description. All changes within the meaning and equivalents of the claims are included within the scope of the claims.

Claims

1. A memory device, comprising: The memory region includes multiple memory cells connected to multiple word lines and multiple bit lines; The voltage generation unit generates the pass voltage and the equalization voltage; The first transmission unit transmits the through voltage or the equalization voltage between the voltage generation unit and the multiple word lines via a first path; The second transmission unit transmits the through voltage between the voltage generation unit and the multiple word lines via a second path, wherein the second path is physically separated from the first path; as well as The operation control unit activates the first transmission unit and the second transmission unit during the voltage rise period, so that the voltage is transmitted through the first path and the second path, and activates the first transmission unit during the equalization period after the start of the read operation or programming operation, so that the equalized voltage is transmitted through the first path.

2. The memory device according to claim 1, wherein, During the pass voltage holding period that the second transmission unit enters after the pass voltage rise period, the operation control unit activates the second transmission unit, causing the second transmission unit to transmit the pass voltage through the second path.

3. The memory device according to claim 2, wherein, The operation control unit generates a first control signal, a second control signal, and a third control signal. The first control signal is activated during the through voltage rise time period and deactivated during the through voltage hold time period and the equalization time period. The second control signal is activated during the equalization time period and deactivated during the through voltage rise time period and the through voltage hold time period. The third control signal is activated during the through voltage hold time period and deactivated during the through voltage rise time period and the equalization time period. The first transmission unit is activated during the activation period of the first control signal and the second control signal; as well as The second transmission unit is activated during the activation period of the first control signal and the third control signal.

4. The memory device according to claim 2, further comprising a word line selection unit, wherein during the activation time period of the first control signal and the third control signal, the word line selection unit connects unselected word lines that are not selected as read operation targets or programming operation targets among the plurality of word lines to the first transmission unit and the second transmission unit, and during the activation time period of the second control signal, the word line selection unit connects the plurality of word lines to the first transmission unit and the second transmission unit.

5. The memory device according to claim 3, wherein, The voltage generation unit includes: During the activation time period of the first control signal and the third control signal, the through voltage is generated by charge pumping the source voltage through the voltage generation unit. The first adjustment unit, during the activation period of the second control signal, stabilizes the first path at the level of the equalization voltage, and during the activation period of the first control signal, stabilizes the first path at the voltage level of the through voltage generated by the through voltage generation unit; and The second adjustment unit stabilizes the second path at the voltage level of the through voltage generated by the through voltage generation unit during the activation time period of the first control signal and the third control signal.

6. The memory device according to claim 5, wherein, The first adjustment unit responds to the first control signal and the second control signal, and during the equalization period that the first adjustment unit enters before the voltage rise period, stabilizes the first path at the level of the equalization voltage, wherein the equalization voltage is generated at the level of the ground voltage.

7. The memory device according to claim 5, wherein, The first adjustment unit responds to the first control signal and the second control signal, and during the equalization period that the first adjustment unit enters after the voltage holding period, stabilizes the first path at the level of the equalization voltage, wherein the equalization voltage is generated at a level higher than the ground voltage and lower than the source voltage.

8. A method of operating a memory device, the memory device including a memory region, a voltage generation unit, and a first path and a second path, the memory region including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, the voltage generation unit generating a pass voltage and an equalization voltage, the first path and the second path being located between the voltage generation unit and the plurality of word lines and physically separated, the method comprising: The first transmission process includes transmitting the through voltage generated by the voltage generation unit through the first path and the second path to at least one of the plurality of word lines during the through voltage rise time period after the start of the read operation or programming operation. as well as The second transmission process includes transmitting the equalized voltage generated by the voltage generation unit to the multiple word lines through the first path during an equalization period after the start of the read operation or the programming operation.

9. The method of claim 8, further comprising: The third transmission process includes transmitting the through voltage to the at least one word line via the second path after the start of the read operation or the programming operation, during the through voltage holding period following the through voltage rise period.

10. The method according to claim 9, wherein, In the first transmission process and the third transmission process, the at least one word line includes the unselected word line among the plurality of word lines that was not selected as the target of a read operation or a programming operation.

11. The method of claim 9, further comprising: During the voltage rise time period and the voltage hold time period, the voltage is generated by the voltage generation unit using a charge pumping method. The first path and the second path are stabilized by utilizing the through voltage generated during the through voltage rise time period; as well as The second path is stabilized by utilizing the through voltage generated during the through voltage holding period.

12. The method of claim 11, further comprising: When the first path enters the equalization period before the voltage rise period, the first path is stabilized during the equalization period by using an equalization voltage generated by the voltage generation unit with a level of ground voltage.

13. The method of claim 11, further comprising, when entering the equalization period after the voltage holding period, stabilizing the first path during the equalization period using an equalization voltage generated by the voltage generation unit, having a level higher than the ground voltage and lower than the source voltage.

14. A method comprising: A voltage generation unit generates a pass voltage and an equalization voltage in a memory device, the memory device comprising multiple memory cells connected to multiple word lines; During the voltage rise period after the start of a read or program operation, the voltage is transmitted to at least one of the plurality of word lines via a physically separated first and second path. as well as During the equalization period following the start of the read operation or the programming operation, the equalization voltage is transmitted to the multiple word lines via the first path.

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