An oxide-based memory cell array and a multi-terminal read method

Abstract

The application relates to an oxide-based memory cell array and a multi-terminal reading method, and relates to the technical field of microelectronics, and solves the technical problems of insufficient DRAM reading bandwidth and incapability of realizing simultaneous sequential parallel reading. The memory cell of the memory cell array comprises one writing transistor, multiple reading transistors and one common storage node; the writing transistor is controlled by a writing word line and a writing bit line; the multiple reading transistors are controlled by multiple sets of reading word lines and reading bit lines which are independent of each other; the common storage node is connected to the gates of the multiple reading transistors respectively; and one of the source-drain electrodes of the writing transistor is connected to the common storage node.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to an oxide-based memory cell array and a multi-terminal readout method. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and cloud computing technologies, the demand for high-bandwidth, low-latency data storage in computing systems is growing exponentially. Memory (especially dynamic random-access memory (DRAM)) is the core hub for data interaction in computing systems, facing the triple challenges of increasing integration density, reducing power consumption, and breaking through read bandwidth limitations. Traditional memory technologies (such as DRAM) are gradually approaching their physical limits in terms of scalability, access speed, and energy efficiency, while the parallel read capabilities required by emerging architectures such as AI accelerators and in-memory computing are difficult for traditional architectures to meet.

[0003] Traditional DRAM consists of one transistor and one capacitor (1T1C), using the capacitor's charging and discharging to store binary data. However, with the continuous miniaturization of manufacturing processes and the increasing density of storage, this traditional architecture faces fundamental physical limitations: 1. In terms of unit transistors, as the process node advances, the off-state leakage current of silicon-based MOSFETs increases exponentially, leading to a sharp deterioration in data retention characteristics. This forces the system to significantly shorten the refresh cycle, resulting in refresh power consumption accounting for more than 30% of the total DRAM power consumption.

[0004] 2. In terms of unit capacitors, in order to maintain a sufficient signal-to-noise ratio, storage capacitors are difficult to scale down proportionally. Manufacturers have to adopt three-dimensional capacitor structures with high aspect ratios, which leads to a sharp increase in process complexity and manufacturing costs.

[0005] 3. Under the general trend of monolithic 3D (M3D) integration, the presence of capacitors makes the process of stacking traditional DRAM in the vertical direction extremely difficult, which seriously hinders the flexible deployment of DRAM in emerging architectures such as chiplets, near-memory computing and in-memory computing.

[0006] To address the structural limitations of traditional 1T1C DRAM, the capacitor-free 2-transistor 0-capacitor (2T0C) DRAM architecture has garnered significant attention from academia and industry in recent years. This architecture completely eliminates traditional storage capacitors, storing data through the parasitic gate capacitance of the transistors themselves, thus fundamentally eliminating the challenge of capacitor miniaturization.

[0007] However, in traditional (2T0C) DRAM, the write transistor and read transistor are connected in series, and its architecture uses a single gate control. Furthermore, read and write operations share the same set of word line / bit line signal paths, which leads to the following drawbacks: 1. Single-channel read limitation: Only one read operation can be performed on the same memory array within one clock cycle, and the data read bandwidth is limited by the clock frequency.

[0008] Second, it cannot achieve simultaneous dual reads: it cannot perform two independent read operations on the same storage array within a single time period, making it difficult to meet the requirements of parallel reading of weight data and activation data in the in-memory computing architecture.

[0009] The aforementioned defects have become a key obstacle restricting the large-scale deployment of memory (especially DRAM) in high-bandwidth application scenarios. Summary of the Invention

[0010] In view of the above analysis, the present invention aims to provide an oxide-based memory cell array and a multi-end read method to solve the above-mentioned defects of traditional memory.

[0011] In a first aspect, embodiments of the present invention provide an oxide-based memory cell array, which is applied to a dynamic random access memory. The memory cell array includes multiple memory cells, wherein memory cells in the same row share a word line and memory cells in the same column share a bit line. The memory cells include: One write transistor, multiple read transistors, and a common memory node; The write transistor is controlled by write word lines and write bit lines, the plurality of read transistors are controlled by multiple sets of read word lines and read bit lines that are independent of each other, the common memory node is connected to the gate of the plurality of read transistors respectively, and one of the source and drain terminals of the write transistor is connected to the common memory node.

[0012] Based on the further improvement of the above-mentioned memory cell array, both the write transistor and the read transistor are oxide thin-film transistors.

[0013] Based on the further improvement of the above-mentioned memory cell array, the oxide thin film transistor is an N-type indium gallium zinc oxide thin film transistor, and the substrate of the N-type indium gallium zinc oxide thin film transistor is grounded.

[0014] Based on the further improvement of the above-mentioned memory cell array, the gate of the write transistor is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the common memory node.

[0015] Based on the further improvement of the above-mentioned memory cell array, the source of each read transistor is connected to the corresponding read word line, and the drain is connected to the corresponding read bit line.

[0016] Based on the further improvement of the above-mentioned storage cell array, the storage cell is configured to include a multi-port read phase, which is obtained through the following configuration: Set the write line to a low level to turn off the write transistor; A read voltage is applied to each of the plurality of read word lines and the current on each of the plurality of read bit lines is read, wherein the voltage of the common memory node simultaneously controls the turn-off and turn-on of the plurality of read transistors.

[0017] Based on the further improvement of the above-mentioned storage cell array, the storage cell is configured to also include a single-port read phase, which is obtained through the following configuration: Set the write line to a low level to turn off the write transistor; A read voltage is applied to the target read word line among the plurality of read word lines, and the other read word lines are set to a low level to turn off the other read transistors; Read the current on the read bit line associated with the target read word line, wherein the voltage of the common memory node controls the turn-off and turn-on of the target read transistor.

[0018] Based on the further improvement of the above-mentioned storage cell array, the storage cell is configured to include a data writing stage, which is obtained through the following configuration: Set the write line to a high level to turn on the write transistor; Set the plurality of read word lines to a low level to turn off the plurality of read transistors; Apply the voltage corresponding to the data to the write bit line.

[0019] Based on the further improvement of the above-mentioned storage cell array, the storage cell is configured to include a data retention phase, which is obtained through the following configuration: Set the write line to a low level to turn off the write transistor; Set the plurality of read word lines to a low level to turn off the plurality of read transistors.

[0020] Secondly, embodiments of the present invention provide a multi-terminal reading method based on a memory cell array, wherein the memory cell array is applied to a dynamic random access memory, and memory cells in the same row share a word line, and memory cells in the same column share a bit line. The memory cells of the memory cell array include: One write transistor, multiple read transistors, and a common memory node; The write transistor is controlled by write word lines and write bit lines, the plurality of read transistors are controlled by multiple sets of read word lines and read bit lines that are independent of each other, the common memory node is connected to the gate of the plurality of read transistors respectively, and one of the source and drain terminals of the write transistor is connected to the common memory node; The multi-terminal reading method includes: Set the write line to a low level to turn off the write transistor; A read voltage is applied to each of the plurality of read word lines and the current on each of the plurality of read bit lines is read, wherein the voltage of the common memory node simultaneously controls the turn-off and turn-on of the plurality of read transistors.

[0021] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: 1. In the storage cell of the storage cell array provided in the embodiment of the present invention, two read transistors share the same common storage node, and one copy of stored data can be read by two independent ports at the same time without repeated storage. The storage density is increased by 100% compared with two single-port cells.

[0022] Second, in the storage cell of the storage cell array provided in the embodiment of the present invention, the write path and the two read paths are completely physically separated, the write operation and the read operation do not interfere with each other, the read-write crosstalk problem is completely eliminated, and there is no mutual interference between the two read operations.

[0023] Third, in the memory cells of the memory cell array provided in this embodiment of the invention, all transistors are indium gallium zinc oxide thin-film transistors, which have extremely low off-state leakage current (~10). - The 2²A / μm level means that adding a read transistor does not significantly increase the leakage current path of the common memory node, and the data retention time is comparable to that of a traditional 2T0C memory cell.

[0024] Fourth, in the storage unit of the storage unit array provided in the embodiments of the present invention, each read port is equipped with an independent read word line and read bit line. The two read ports can be controlled completely independently, supporting multiple working modes such as single-port reading and dual-port simultaneous reading, which is extremely flexible.

[0025] V. The storage cell array provided in this embodiment of the invention adopts a capacitor-free design, completely eliminating the traditional storage capacitor, fundamentally eliminating the problem of capacitor miniaturization, simplifying the manufacturing process, and naturally compatible with monolithic 3D (M3D) integration.

[0026] VI. The storage cell array provided in the embodiments of the present invention utilizes the characteristics of indium gallium zinc oxide devices to store multiple bits of data, thereby effectively increasing storage density.

[0027] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0028] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Figure 1 This is a basic structural diagram of the storage cells of a storage cell array according to an embodiment of the present invention.

[0029] Figure 2 It shows Figure 1 This is a schematic diagram illustrating the working principle of the storage unit in the data retention phase.

[0030] Figure 3 It shows Figure 1 The diagram illustrates the working principle of the storage unit in the data writing stage.

[0031] Figures 4(a) and 4(b) show Figure 1 The diagram illustrates the working principle of the storage unit in the single-port independent read stage.

[0032] Figure 5 It shows Figure 1 The diagram illustrates the working principle of the storage unit in the dual-port simultaneous reading stage.

[0033] Figure 6 It shows Figure 1 The diagram shows the waveform of the storage unit in the data writing stage.

[0034] Figure 7 It shows Figure 1 The diagram shows the waveform of the storage unit in the data reading stage.

[0035] Figure 8 This is a flowchart illustrating a multi-terminal reading method based on a storage cell array according to an embodiment of the present invention. Detailed Implementation

[0036] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0037] Figure 1 This is a basic structural diagram of a memory cell in a memory cell array applied to a dynamic random access memory according to an embodiment of the present invention.

[0038] The following is combined Figure 1 An embodiment of the present invention will be described.

[0039] like Figure 1As shown, this memory cell uses a capacitor-free structure with one write transistor and two read transistors, for a total of three transistors. The write transistor is denoted as WTr, the first read transistor as RTr1, and the second read transistor as RTr2. The gate of WTr is connected to the write word line WWL, the source of WTr is connected to the write bit line WBL, and the drain of WTr is connected to the common memory node SN. The gate of RTr1 is directly connected to the common memory node, the source of RTr1 is connected to the first read word line RWL1, and the drain of RTr1 is connected to the first read bit line RBL1. The gate of RTr2 is directly connected to the common memory node, the source of RTr2 is connected to the second read word line RWL2, and the drain of RTr2 is connected to the second read bit line RBL2.

[0040] Figure 1 The storage unit has four working stages: data retention stage, data writing stage, single-port independent read stage, and dual-port simultaneous read stage.

[0041] Figure 2 It shows Figure 1 This is a schematic diagram illustrating the working principle of a storage unit in the data retention phase. (See diagram for example.) Figure 2 As shown, during the data retention phase, the write word line WWL, the first read word line RWL1, and the second read word line RWL2 are all at low levels, and WTr, RTr1, and RTr2 are all turned off. Data is stored as charge in the parasitic gate capacitance of the common memory node SN. In some embodiments, all transistors are N-type indium gallium zinc oxide (IGZO) thin-film transistors. Due to the extremely low off-state leakage current of IGZO transistors, the charge leakage rate of the common memory node SN is extremely slow, allowing data to be retained for milliseconds or even seconds, significantly reducing the refresh rate and system power consumption.

[0042] Figure 3 It shows Figure 1 This is a schematic diagram illustrating the working principle of a storage unit during the data writing phase. (See diagram for example.) Figure 3 As shown, during the data writing phase, a high level is applied to the write word line WWL, turning on the write transistor WTr. The first read word line RWL1 and the second read word line RWL2 remain low, and both read transistors remain off. The write bit line WBL is applied with the voltage corresponding to the data. After writing is complete, the write word line WWL returns to a low level, WTr turns off, and the data enters a hold state.

[0043] Figures 4(a) and 4(b) show Figure 1The diagram illustrates the working principle of a storage cell in the single-port independent read phase. As shown in Figure 4(a), to perform an independent read operation on the first read port, the write word line WWL is kept low, and the write transistor WTr is turned off. A read voltage is applied to the first read word line RWL1, and the second read word line RWL2 is kept low. The voltage of the common storage node SN controls the conduction level of the first read transistor RTr1: when SN is high, RTr1 is turned on, and a read current is generated on the first read bit line RBL1; when SN is low, RTr1 is turned off, and there is no significant current on RBL1. By detecting the magnitude of the current on RBL1, the data status stored in the SN node can be determined. After the read is completed, the first read word line RWL1 returns to low, and RTr1 is turned off.

[0044] As shown in Figure 4(b), to perform an independent read operation on the second read port, the write word line WWL is kept low, and the write transistor WTr is turned off. A read voltage is applied to the second read word line RWL2, while the first read word line RWL1 remains low. The voltage of the common memory node SN controls the conduction level of the second read transistor RTr2: when SN is high, RTr2 is on, and a read current is generated on the second read bit line RBL2; when SN is low, RTr2 is off, and there is no significant current on RBL2. By detecting the current on RBL2, the data status stored in the SN node can be determined. After the read operation is completed, the second read word line RWL2 returns to low, and RTr2 is turned off.

[0045] Figure 5 It shows Figure 1 The diagram illustrates the working principle of the storage unit in the dual-port simultaneous read phase. (See diagram for example.) Figure 5 As shown, during the dual-port simultaneous read phase, the write word line WWL remains low, and the write transistor WTr is turned off; the first read word line RWL1 and the second read word line RWL2 are simultaneously subjected to read voltages. The same voltage of the common memory node SN simultaneously controls the conduction state of the two read transistors RTr1 and RTr2: when SN is high, both read transistors are turned on simultaneously, and the first read bit line RBL1 and the second read bit line RBL2 simultaneously generate read currents; when SN is low, both read transistors are turned off simultaneously, and there is no significant current on either read bit line. Two identical data outputs can be obtained simultaneously through two independent detection circuits. After the read is completed, both read word lines simultaneously return to low level, and both read transistors simultaneously turn off.

[0046] It should be noted that, although Figures 1 to 5 The storage unit shown employs a two-read-port design, but the scope of protection of this invention is not limited to this. Other numbers of read ports are also included in the scope of protection of this invention, such as three, five, or other numbers of read ports, as long as they employ the same design as the storage unit. Figure 1The illustrated memory cells have the same or similar connection method (e.g., the gates of multiple read transistors are connected to the same common memory node), and achieve the same level of connectivity as... Figure 1 The storage units shown have the same or similar effects (e.g., simultaneously reading data stored in a common storage node SN).

[0047] Figure 6 It shows Figure 1 The diagram shows the waveform of the storage unit in the data writing stage. Figure 7 It shows Figure 1 The diagram illustrates the waveform of a storage unit during the data reading phase. Figure 6 In the middle, V WWL V represents the voltage on the writing line. WBL V represents the voltage on the write bit line. SN This represents the voltage at the common storage node SN. Figure 7 In the middle, V RWLx This represents the voltage on the corresponding reading line (x=1 represents V). RWL1 The voltage across, x=2 represents V RWL2 (voltage on) V OUT This represents the output current. This has already been discussed above. Figures 3 to 5 The working states of the storage unit during the data writing and data reading stages have been explained separately, and will not be repeated here.

[0048] It should be noted that the memory structure of "one write transistor and multiple read transistors" proposed in this invention has significant technical advantages when applied to dynamic random access memory (DRAM) and is not easily conceived by those skilled in the art, for the following reasons: I. Industry Technological Inertia. For the past half-century, all iterations of DRAM have been built on silicon-based devices. Those skilled in the art have reached the following unbreakable industry consensus: DRAM is inherently unsuitable for multiple read ports; to increase bandwidth, static random access memory (SRAM) or high-bandwidth memory (HBM) stacking is used. This conclusion is entirely correct within the silicon-based framework, because the multiple leakage currents of silicon-based multi-port DRAM are sufficient to affect data retention time. For a long time, the vast majority of designers have focused on using system-level solutions (increasing bit width, stacking chips) to solve bandwidth problems, never attempting a "cell-level, read port-adding" approach.

[0049] II. Limitations of Indium Gallium Zinc Oxide (IGZO) Device Research. IGZO DRAM is a relatively new technology, and global research has focused on two main areas: 1. Improving data retention time and reducing refresh power consumption using the low leakage current of IGZO; 2. Enhancing storage density through 3D integration using capacitor-free and back-to-offline (BEOL) compatible characteristics. Everyone is pursuing a path of "replacing traditional DRAM," assuming that IGZO's 2T0C is simply a "material-upgraded single-port DRAM." However, during research, inventors creatively discovered that the ultra-low off-state leakage current of IGZO can completely resolve the core contradiction of "multiple ports = leakage current explosion." The increase in leakage current caused by multiple read transistors connected in parallel is negligible within the IGZO range and has almost no impact on data retention time.

[0050] III. Predicting the Limits of Silicon-Based DRAM Processes. With the rapid development of AI technology, most industry professionals are focusing their research on high-bandwidth DRAM on HBM (High-bandwidth Machine Model), aiming to increase capacity and bandwidth by stacking more layers. However, silicon-based DRAM inevitably has a power consumption limit, and multi-layer stacking leads to explosive heat dissipation requirements. By applying a "one write transistor, multiple read transistors" memory structure to Dynamic Random Access Memory (DRAM), the multiple read transistors work in parallel without interference, effectively increasing capacity and bandwidth, thus breaking the perception that increasing storage capacity relies on stacking more layers.

[0051] Figure 8 This is a schematic flowchart of a multi-terminal read method based on a memory cell array according to an embodiment of the present invention. The memory cell array includes: a write transistor, multiple read transistors, and a common memory node. The write transistor is controlled by write word lines and write bit lines, the multiple read transistors are controlled by multiple independent sets of read word lines and read bit lines, the common memory node is connected to the gates of the multiple read transistors, and one of the source and drain terminals of the write transistor is connected to the common memory node. Figure 1 An example of a storage cell in this storage cell array is shown. (This has already been combined with...) Figures 1 to 7 The structure and working principle of the storage unit have been explained, and will not be repeated here.

[0052] like Figure 8 As shown, this multi-terminal read method based on a storage cell array includes: Step 801: Set the write line to low level to turn off the write transistor.

[0053] Step 802: Apply reading voltage to each of the multiple read word lines and read the current on each of the multiple read bit lines.

[0054] In this embodiment, the write word line WWL remains low, and the write transistor WTr is turned off; the first read word line RWL1 and the second read word line RWL2 are simultaneously subjected to read voltages. The same voltage of the common memory node SN simultaneously controls the conduction state of the two read transistors RTr1 and RTr2: when SN is high, both read transistors are turned on simultaneously, and the first read bit line RBL1 and the second read bit line RBL2 simultaneously generate read current; when SN is low, both read transistors are turned off simultaneously, and there is no significant current on either read bit line. Two identical data outputs can be obtained simultaneously through two independent detection circuits. After reading is completed, both read word lines simultaneously return to low level, and both read transistors are turned off simultaneously. The voltage of the common memory node SN simultaneously controls the turn-on and turn-off of multiple read transistors.

[0055] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: 1. In the storage cell of the storage cell array provided in the embodiment of the present invention, two read transistors share the same common storage node, and one copy of stored data can be read by two independent ports at the same time without repeated storage. The storage density is increased by 100% compared with two single-port cells.

[0056] Second, in the storage cell of the storage cell array provided in the embodiment of the present invention, the write path and the two read paths are completely physically separated, the write operation and the read operation do not interfere with each other, the read-write crosstalk problem is completely eliminated, and there is no mutual interference between the two read operations.

[0057] Third, in the memory cells of the memory cell array provided in this embodiment of the invention, all transistors are indium gallium zinc oxide thin-film transistors, which have extremely low off-state leakage current (~10). - The 2²A / μm level means that adding a read transistor does not significantly increase the leakage current path of the common memory node, and the data retention time is comparable to that of a traditional 2T0C memory cell.

[0058] Fourth, in the storage unit of the storage unit array provided in the embodiments of the present invention, each read port is equipped with an independent read word line and read bit line. The two read ports can be controlled completely independently, supporting multiple working modes such as single-port reading and dual-port simultaneous reading, which is extremely flexible.

[0059] V. The storage cell array provided in this embodiment of the invention adopts a capacitor-free design, completely eliminating the traditional storage capacitor, fundamentally eliminating the problem of capacitor miniaturization, simplifying the manufacturing process, and naturally compatible with monolithic 3D (M3D) integration.

[0060] VI. The storage cell array provided in the embodiments of the present invention utilizes the characteristics of indium gallium zinc oxide devices to store multiple bits of data, thereby effectively increasing storage density.

[0061] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An oxide-based memory cell array, characterized in that, The memory cell array is applied to a dynamic random access memory. The memory cell array includes multiple memory cells. Memory cells in the same row share a word line, and memory cells in the same column share a bit line. Each memory cell includes: One write transistor, multiple read transistors, and a common memory node; The write transistor is controlled by write word lines and write bit lines, the plurality of read transistors are controlled by multiple sets of read word lines and read bit lines that are independent of each other, the common memory node is connected to the gate of the plurality of read transistors respectively, and one of the source and drain terminals of the write transistor is connected to the common memory node.

2. The storage cell array according to claim 1, characterized in that, Both the write transistor and the read transistor are oxide thin-film transistors.

3. The storage cell array according to claim 2, characterized in that, The oxide thin-film transistor is an N-type indium gallium zinc oxide thin-film transistor, and the substrates of the N-type indium gallium zinc oxide thin-film transistor are all grounded.

4. The storage cell array according to claim 3, characterized in that, The gate of the write transistor is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the common memory node.

5. The storage cell array according to claim 3, characterized in that, The source of each read transistor is connected to the corresponding read word line, and the drain is connected to the corresponding read bit line.

6. The storage cell array according to claim 1, characterized in that, The storage unit is configured to include a multi-port read phase, which is configured as follows: Set the write line to a low level to turn off the write transistor; A read voltage is applied to each of the plurality of read word lines and the current on each of the plurality of read bit lines is read, wherein the voltage of the common memory node simultaneously controls the turn-off and turn-on of the plurality of read transistors.

7. The storage cell array according to claim 1, characterized in that, The storage unit is configured to further include a single-port read phase, which is configured as follows: Set the write line to a low level to turn off the write transistor; A read voltage is applied to the target read word line among the plurality of read word lines, and the other read word lines are set to a low level to turn off the other read transistors; Read the current on the read bit line associated with the target read word line, wherein the voltage of the common memory node controls the turn-off and turn-on of the target read transistor.

8. The storage cell array according to claim 1, characterized in that, The storage unit is configured to include a data writing phase, which is configured as follows: Set the write line to a high level to turn on the write transistor; Set the plurality of read word lines to a low level to turn off the plurality of read transistors; Apply the voltage corresponding to the data to the write bit line.

9. The storage cell array according to claim 1, characterized in that, The storage unit is configured to include a data retention phase, which is configured as follows: Set the write line to a low level to turn off the write transistor; Set the plurality of read word lines to a low level to turn off the plurality of read transistors.

10. A multi-terminal reading method based on a storage cell array, characterized in that, The memory cell array is applied to a dynamic random access memory. Memory cells in the same row share a word line, and memory cells in the same column share a bit line. The memory cells in the memory cell array include: One write transistor, multiple read transistors, and a common memory node; The write transistor is controlled by write word lines and write bit lines, the plurality of read transistors are controlled by multiple sets of read word lines and read bit lines that are independent of each other, the common memory node is connected to the gate of the plurality of read transistors respectively, and one of the source and drain terminals of the write transistor is connected to the common memory node; The multi-terminal reading method includes: Set the write line to a low level to turn off the write transistor; A read voltage is applied to each of the plurality of read word lines and the current on each of the plurality of read bit lines is read, wherein the voltage of the common memory node simultaneously controls the turn-off and turn-on of the plurality of read transistors.

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