storage device

Abstract

The present invention relates to a storage device. In the present invention, a plurality of transistors supply a first potential to first and second inputs of a sense amplifier circuit based on a first signal. A first wiring is connected to the first input. A second wiring is connected to the second input. A first storage unit includes a first cell transistor and a first cell capacitor connected in series. A first selection transistor is connected between the first wiring and the first storage unit. A second storage unit includes a second cell transistor and a second cell capacitor connected in series. A second selection transistor is connected between the second wiring and the second storage unit. A first operation of raising a potential of a gate of the first selection transistor is performed. A second operation of lowering a potential of the first signal is performed after the first operation. After the second operation, a third operation of raising a potential of a gate of the first cell transistor and raising a potential of a gate of the second selection transistor is performed.

Description

Technical Field

[0001] The implementation generally relates to a storage device. Background Technology

[0002] As a storage device, DRAM (Dynamic Random Access Memory) is known. DRAM storage cells contain capacitors and transistors. The storage cells store data based on the charge stored in the capacitors. A sense amplifier amplifies the voltage corresponding to the data to be read, i.e., the data in the storage cell, thereby identifying the stored data. Summary of the Invention

[0003] The present invention provides a high-speed storage device.

[0004] A storage device according to one embodiment includes a sense amplifier circuit, a plurality of transistors, a first wiring, a second wiring, a first storage cell, a first selection transistor, a second storage cell, and a second selection transistor. The sense amplifier circuit has a first input and a second input. The plurality of transistors supply a first potential to the first input and the second input based on a first signal. The first wiring is connected to the first input. The second wiring is connected to the second input. The first storage cell includes a first unit transistor and a first unit capacitor connected in series. The first selection transistor is connected between the first wiring and the first storage cell. The second storage cell includes a second unit transistor and a second unit capacitor connected in series. The second selection transistor is connected between the second wiring and the second storage cell. A first operation is performed to increase the potential of the gate of the first selection transistor. After the first operation, a second operation is performed to decrease the potential of the first signal. After the second action, a third action is performed, which is to increase the potential of the gate of the first unit transistor and the potential of the gate of the second selection transistor. Attached Figure Description

[0005] Figure 1 This shows the functional blocks and related constituent elements of the storage device in the first embodiment.

[0006] Figure 2 This shows a portion of the constituent elements of the storage device according to the first embodiment and the connections between the constituent elements.

[0007] Figure 3 This shows a portion of the constituent elements of the sensing amplifier of the storage device according to the first embodiment, and the connections of the constituent elements.

[0008] Figure 4This describes a portion of the constituent elements and their connections during the data readout period of the storage device in the first embodiment.

[0009] Figure 5 It represents several states during the data readout period of the storage device in the first embodiment according to time.

[0010] Figure 6 It represents the potential of several wirings and signals during the data readout period of the storage device in the first embodiment, according to time.

[0011] Figure 7 This describes a portion of the constituent elements of the storage device and the connections of the constituent elements in a first variation of the first embodiment.

[0012] Figure 8 This indicates the state of the storage device during data readout in the first variation of the first embodiment.

[0013] Figure 9 It represents the potentials of several wirings and signals during the data readout period of the storage device in the first variation of the first embodiment, according to time.

[0014] Figure 10 It represents the potential of several wirings and signals during the data readout period of the storage device in the second variation of the first embodiment, according to time.

[0015] Figure 11 This describes a portion of the constituent elements and their connections during the data readout period of the storage device in the third variation of the first embodiment.

[0016] Figure 12 It represents the potential of several wirings and signals during the data readout period of the storage device in the third variation of the first embodiment, according to time.

[0017] Figure 13 This describes a portion of the constituent elements and their connections during the data readout period of the storage device in the second embodiment.

[0018] Figure 14 It represents the potential of several wirings and signals during the data readout period of the storage device in the second embodiment, according to time.

[0019] Figure 15 It represents the potentials of several wirings and signals during the data readout period of the storage device in the first variation of the second embodiment, according to time.

[0020] Figure 16 It represents the potential of several wirings and signals during the data readout period of the storage device in the second variation of the second embodiment, according to time.

[0021] Figure 17 This describes a portion of the constituent elements and their connections during the data readout period of the storage device in the third variation of the second embodiment.

[0022] Figure 18 It represents the potential of several wirings and signals during the data readout period of the storage device in the third variation of the second embodiment, according to time.

[0023] Figure 19 It represents the potential of several wirings and signals during the data readout period of the storage device in the third embodiment, according to time.

[0024] Figure 20 It represents the potential of several wirings and signals during the data readout period of the storage device in the first variation of the third embodiment, according to time. Detailed Implementation

[0025] Hereinafter, embodiments will be described with reference to the accompanying drawings. For multiple constituent elements having substantially the same function and structure in a particular embodiment or different embodiments, numbers or letters may be added to the end of the reference numerals to distinguish them. In subsequent embodiments of a previously described embodiment, the differences from the previously described embodiment will be mainly described. The description of a particular embodiment, unless explicitly or clearly excluded, applies in its entirety to the description of other embodiments.

[0026] Each functional block can be implemented using either hardware, computer software, or a combination of both. Some functions can be executed by functional blocks different from the exemplified functional block, or they can be divided into smaller functional sub-blocks.

[0027] In this specification and claims, a first element is "connected" to another second element, including the first element being directly connected to the second element, or being connected to the second element via an element that is always or selectively conductive.

[0028] 1. First Implementation Method

[0029] 1.1. Structure (Composition)

[0030] Figure 1 The functional blocks of the storage device in the first embodiment are shown. The storage device 1 is a device for storing data. The storage device 1 includes a storage cell array 11, an input / output circuit 12, a row control circuit 13, a column control circuit 14, a read / write circuit 15, and a control circuit 16.

[0031] Storage cell array 11 is a functional block for storing data. Storage cell array 11 contains multiple storage cells (MCs). Each storage cell (MC) stores data. Each storage cell (MC) corresponds to a row and a column. Multiple storage cell (MCs) corresponding to the same row are connected to one word line (WL). Multiple storage cell (MCs) corresponding to the same column are connected to one bit line (BL).

[0032] Input / output circuit 12 is a circuit for inputting and outputting data and signals. Input / output circuit 12 receives control signals CNT, instructions CMD, address information ADD, and data DAT from the external storage device 1. Input / output circuit 12 outputs data DAT. When data is written to storage device 1, data DAT represents the written data. When data is read from storage device 1, data DAT represents the read data.

[0033] The row control circuit 13 controls the word lines WL. The row control circuit 13 receives address information ADD from the input / output circuit 12. The row control circuit 13 selects one word line WL associated with the row specified by the received address information ADD. Additionally, based on the received address information ADD, the row control circuit 13 deselects other word lines WL.

[0034] Column control circuit 14 controls bit line BL. Column control circuit 14 receives address information ADD from input / output circuit 12. Column control circuit 14 includes multiple sense amplifier circuits 14A. When reading data, the sense amplifier circuit 14A amplifies the potential appearing on bit line BL based on the data stored in the memory cell MC, generating a read signal (voltage or current). Column control circuit 14 supplies the read signal related to bit line BL specified by address information ADD to read / write circuit 15. When writing data, column control circuit 14 supplies a write signal (voltage or current) based on the data being written to bit line BL specified by address information ADD.

[0035] The read / write circuit 15 controls the writing of data to and from the memory cell MC. The read / write circuit 15 receives write data from the input / output circuit 12. The read / write circuit 15 supplies a write signal (voltage or current) based on the write data to the column control circuit 14. When reading data, the read / write circuit 15 receives a read signal (voltage or current) from the column control circuit 14, the read signal (voltage or current) being determined by the state of the data stored in the memory cell MC to be read. The read / write circuit 15 generates read data based on the read signal and supplies the read data to the input / output circuit 12.

[0036] Control circuit 16 is a circuit that controls the operation of storage device 1. Control circuit 16 receives instruction CMD and control signal CNT from input / output circuit 12. Based on the control indicated by instruction CMD and control signal CNT, control circuit 16 controls row control circuit 13, column control circuit 14, and read / write circuit 15.

[0037] Figure 2 This shows some of the constituent elements of the storage device according to the first embodiment and the connections between these constituent elements. For example... Figure 2 As shown, the storage device 1 includes at least two global bit lines GBL (GBL_0 and GBL_1) and multiple cell groups CS. Hereinafter, one of the source and drain of a transistor will sometimes be referred to as one end of the transistor, and the other as the other end of the transistor.

[0038] Each cell group CS is connected to a global bit line GBL. Figure 2 This example illustrates a global bit line (GBL) connecting three cell groups (CS). Each cell group (CS) contains one bit line select transistor (TrB), multiple memory cells (MC), and one bit line (BL).

[0039] Bit line select transistor TrB is connected between one global bit line GBL and one bit line BL. In one example, TrB is an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). TrB receives a bit line select signal BS at its gate. Different TrBs may each receive different bit line select signals BS. Two or more TrBs may each receive a common bit line select signal BS at multiple gates. In one example, TrB is included in column control circuitry 14. In another example, the bit line select signal BS is supplied from circuitry in column control circuitry 14 and is based on control signals and address information ADD from control circuitry 16.

[0040] Multiple memory cells MC are each connected to a bit line BL at one end. Each memory cell MC contains a cell transistor CT and a cell capacitor CC. The cell transistor CT and the cell capacitor CC are connected in series. The node of the cell transistor CT opposite to that of the cell capacitor CC is connected to the bit line BL. The node of the cell capacitor CC opposite to that of the cell transistor CT is connected to a board line PL (not shown). Different cell transistors CT are connected to different word lines WL. Alternatively, two or more cell transistors CT can be connected to a common word line WL at multiple gates.

[0041] A unit transistor CT has a group of shapes, configurations, and (or) dimensions that are substantially the same as or similar to those of a bit line select transistor TrB. "Substantially the same" means that although the goal is the same, unexpected errors may occur due to limitations in manufacturing and / or measurement techniques. A unit transistor CT may also have a group of shapes, configurations, and (or) dimensions that differ from those of a bit line select transistor TrB. In one example, the unit transistor CT and the bit line select transistor TrB are formed through a common manufacturing process (a group of manufacturing steps).

[0042] The cell capacitor CC stores data by utilizing the charge (amount of charge) accumulated at the node connected to the cell transistor CT. The state of whether the node of the cell capacitor CC connected to the cell transistor CT has accumulated charge corresponds to the state of the storage cell MC storing data "1" or storing data "0".

[0043] Storage device 1 does not need to include a reference cell for determining what kind of data is stored in the data read object, i.e., the storage cell MC. In one example, storage device 1 does not include a reference cell. In another example, storage device 1 uses all storage cells MC except for virtual cells as storage cells for storing data, instead of reference cells. Virtual cells are formed to create storage cells MC with substantially uniform characteristics (size), and in one example, they are located at the outermost edge of the region where storage cells MC are formed.

[0044] All memory cells (MCs) except for virtual cells have substantially the same characteristics. More specifically, in one example, all memory cells (MCs) except for virtual cells are groups of substantially the same shape, construction (or) size.

[0045] The memory cell array 11, row control circuit 13, and column control circuit 14 are configured such that by selecting one word line WL and one bit line BL, only one memory cell MC is selected. With this configuration, as described above, either two or more bit line selection transistors TrB can receive a common bit line selection signal BS at multiple gates, or (or) two or more cell transistors CT can be connected to the common word line WL at multiple gates.

[0046] Figure 3 This shows some constituent elements of the sensing amplifier in the storage device of the first embodiment, and the connections of these constituent elements. For example... Figure 3 As shown, the sense amplifier circuit 14A includes inputs IN0 and IN1, and nodes (wiring) SAN0 and SAN1. Although Figure 3Not shown in the diagram, but in order to amplify the potential appearing on the bit line BL based on the data stored in the memory cell MC, the sense amplifier circuit 14A includes a flip-flop. That is, in one example, it includes an inverter circuit with an output connected to node SAN0 and an inverter circuit with an output connected to node SAN1. The input and output of one of the two inverter circuits are connected to the output and input of the other inverter circuit, respectively.

[0047] The sense amplifier circuit 14A receives the internal power supply voltage Vcc and a reference voltage. In one example, the reference voltage is the ground voltage Vss, and the following description is based on this example. The sense amplifier circuit 14A receives an enable signal SEN. During the period when the sense amplifier circuit 14A receives the valid (or active) enable signal SEN, it is in an operational state. During the operational state, the sense amplifier circuit 14A raises the higher potential of nodes SAN0 and SAN1 to a high potential and lowers the lower potential to a low potential. In one example, the high potential has a magnitude equal to the internal power supply voltage Vcc, and the low potential has a magnitude equal to the ground voltage Vss. In one example, the valid logic for the enable signal SEN is high.

[0048] Connect IN0 to node SAN0. Connect IN1 to node SAN1.

[0049] The sense amplifier circuit 14A also has a configuration that allows nodes SAN0 and SAN1 to be selectively connected to node NBP. For example, such as... Figure 3 As shown, the sense amplifier circuit 14A includes n-type MOSFETs TN1, TN2, and TN3. Transistor TN1 is connected between node SAN0 and node NBP. Node NBP receives a pre-charge voltage Vpc. The pre-charge voltage Vpc, for example, has half the difference between the internal supply voltage Vcc and the ground voltage Vss, i.e., voltage Vcc / 2. Transistor TN1 receives the signal PRE at its gate. In one example, the signal PRE is supplied from the read / write circuit 15.

[0050] Transistor TN2 is connected between node SAN1 and node NBP. Transistor TN2 receives the PRE signal at its gate.

[0051] Transistor TN3 is connected between node SAN0 and node SAN1. Transistor TN3 receives the PRE signal at its gate.

[0052] Either transistor TN1 or TN2 can be omitted. Transistor TN3 can also be omitted. Transistors TN1, TN2, and TN3 can be included in the column control circuit 14, or they can be included outside the sense amplifier circuit 14A.

[0053] 1.2. Actions

[0054] Figure 4 This describes a portion of the constituent elements and their connections during the data readout period of the storage device in the first embodiment. Figure 4 This indicates the state during data reading from a specific data read object, i.e., memory cell MC. Hereinafter, the data read object, i.e., memory cell MC, is sometimes referred to as the selected memory cell MCsel. The word line WL connected to the selected memory cell MCsel is sometimes referred to as the selected word line WLsel. The cell group CS containing the selected memory cell MCsel is sometimes referred to as the selected cell group CSsel. The bit line selection transistor TrB in the selected cell group CSsel is sometimes referred to as the selected bit line selection transistor TrBsel. The bit line selection signal BS received using the selected bit line selection transistor TrBsel is sometimes referred to as the selected bit line selection signal BSsel. The bit line BL in the selected cell group CSsel is sometimes referred to as the selected bit line BLsel.

[0055] Figure 4 This represents an example of connecting the selected cell group CSsel to the global bit line GBL_0.

[0056] During data read from the selected memory cell MCsel, one cell group CS connected to the global bit line GBL_1 is used for auxiliary data readout. Either cell group CS connected to the global bit line GBL_1 can also be used. Hereinafter, the auxiliary cell group CS is sometimes referred to as the reference cell group CSref. The bit line selection transistor TrB in the reference cell group CSref is sometimes referred to as the reference bit line selection transistor TrBref. The bit line selection signal BS received using the reference bit line selection transistor TrBref is sometimes referred to as the reference bit line selection signal BSref. The bit line BL in the reference cell group CSref is sometimes referred to as the reference bit line BLref.

[0057] Each bit line BL, including the select bit line BLsel and the reference bit line BLref, remains at the precharge potential Vpc when it is not accessed, including when data is read from the memory cell MC connected to it. The precharge potential Vpc has a value that is substantially the same as the precharge voltage Vpc, which is Vcc / 2.

[0058] Figure 5 It represents several states during the data readout period of the storage device in the first embodiment, according to time. For example... Figure 5As shown, each time data is read, a different cell group CS than the one used as the reference cell group CSref in the previous data read can be used as the reference cell group CSref. In the next data read following the previous one, there are cases where a different bit line selection transistor TrB is used as the selected bit line selection transistor TrBsel and is turned on, and cases where the same bit line selection transistor TrB is used as the selected bit line selection transistor TrBsel and is turned on. Furthermore, when the same bit line selection transistor TrB is turned on, there are cases where a different word line WL is used as the selected word line WLsel, and cases where the same word line WL continues to be the selected word line WLsel. In either case, a different cell group CS than the one used as the reference cell group CSref in the previous data read can be used as the reference cell group CSref. However, it is not necessary to use a different cell group CS as the reference cell group CSref for every data read. In one example, during two or more consecutive data readouts, one cell group CS can be used as the reference cell group CSref, and during the next two or more consecutive data readouts, the next cell group CS can be used as the reference cell group CSref.

[0059] Figure 6 This refers to the potentials of several wirings and signals during the data readout period of the storage device in the first embodiment, expressed in terms of time. In one example, when storage device 1 determines that data will be read from the selected storage unit MCsel based on the instruction CMD, it begins... Figure 6 The data shown is read out. Figure 6 The data readout shown was performed during Figure 4 This is performed under the connected state shown.

[0060] like Figure 6 As shown, in Figure 6 At the start of the period shown, the wiring and signals have the potentials described below. The select bit line select signal BSsel, the select word line WLsel, the reference bit line select signal BSref, and the enable signal SEN are at a low ("L") level or a low potential. In one example, the low level or low potential has a magnitude substantially the same as the ground voltage Vss, which is 0V. The signal PRE is at a high ("H") level.

[0061] exist Figure 6 Throughout the period shown, the potential of word line WL, except for the select word line WLsel, remains low. Therefore, in Figure 6 Throughout the period shown, all memory cells MC except for the selected memory cell MCsel, including the memory cell MC in the reference cell group CSref, remain disconnected.

[0062] exist Figure 6 Throughout the period shown, the bit line select signal BS, except for the select bit line select signal BSsel and the reference bit line select signal BSref, remains at a low level. Therefore, in Figure 6 Throughout the entire period shown, the bit line selection transistor TrB, except for the selection bit line selection transistor TrBsel and the reference bit line selection transistor TrBref, remains in the off state.

[0063] When the select bit line select signal BSsel is low, the select bit line select transistor TrBsel is off. When the select word line WLsel is low, the cell transistor CT for selecting the memory cell MCsel is off. When the reference bit line select signal BSref is low, the reference bit line select transistor TrBref is off.

[0064] Since the signal PRE is high, transistors TN1 and TN2 of the sensing amplifier circuit 14A are in the on state, and nodes SAN0 and SAN1 are precharged to the precharge potential Vpc (=Vcc / 2).

[0065] Because the enable signal SEN is low, the sense amplifier circuit 14A is inoperable, meaning it cannot change the potentials of nodes SAN0 and SAN1 to the internal power supply potential Vcc and ground potential Vss, respectively. The internal power supply potential Vcc is the potential of the wiring receiving the internal power supply voltage Vcc, and has a substantially the same magnitude as the internal power supply voltage Vcc. The ground potential Vss is the potential of the wiring receiving the ground voltage Vss, and has a substantially the same magnitude as the ground voltage Vss.

[0066] For reference Figure 4 The bit line BL is maintained at a precharge potential (=Vcc / 2) during periods when there is no access to the memory cell MC connected to the bit line BL. Therefore, in Figure 6 At the start of the period shown, the selected bit line BLsel and the reference bit line BLref have a precharge potential Vpc.

[0067] At time t1, the select bit line select signal BSsel is set to high. Therefore, the select bit line BLsel is connected to the global bit line GBL_0 and node SAN0 of the sense amplifier circuit 14A. The potential of the high level of the bit line select signal BS, which includes the select bit line select signal BSsel (the difference between the low and high levels), has a magnitude V1.

[0068] There is capacitance between the gate of the select bit line select transistor TrBsel and the select bit line BLsel. Therefore, setting the select bit line select signal BSsel high may cause the potential of the select bit line BLsel, and consequently the global bit line GBL_0, to rise. This rise in potential manifests as noise on the global bit line GBL_0. However, at time t1, nodes SAN0 (global bit line GBL_0) and SAN1 (global bit line GBL_1) are pre-charged, thus suppressing the noise effect.

[0069] At time t2, the potential of signal PRE is set to low. Thus, pre-charging ends, and the potentials of nodes SAN0 and SAN1 in the sense amplifier circuit 14A become independent.

[0070] At time t3, the potential of the select word line WLsel is set to a high level. Consequently, the cell transistor CT of the select memory cell MCsel becomes on. As a result, the potential of the select bit line BLsel, through charge sharing, has a value based on the amount of charge stored in the cell capacitor CC of the select memory cell MCsel, which contains the data stored therein. Figure 6 This represents a case where the select memory cell MCsel does not hold charge in its cell capacitor CC. The select bit line BLsel has a potential lower than the pre-charge potential Vpc. The node SAN0 connected to the select bit line BLsel also has the same potential as the select bit line BLsel. As a result of charge sharing, the cell capacitor CC of the select memory cell MCsel loses the stored charge. The high-level potential (the difference between the low-level and high-level potentials) of the select word line WLsel has a magnitude of V2.

[0071] On the other hand, the reference bit line BLref and node SAN1 are not connected to any unit capacitor CC, but are electrically floating. Therefore, at time t3, charge sharing does not occur as it does on the select bit line BLsel. Consequently, the reference bit line BLref and node SAN1 maintain the same potential after time t3. However, the reference bit line BLref and node SAN1 may be affected by noise (the potential from other wirings caused by parasitic capacitance).

[0072] There is capacitance between the select word line WLsel and the select bit line BLsel. Therefore, when the potential of the select word line WLsel is set to a high level, the potential of the select bit line BLsel rises.

[0073] At time t3, the reference bit line selection signal BSref is set high. Therefore, the reference bit line BLref is connected to the global bit line GBL_1 and node SAN1 of the sense amplifier circuit 14A. In one example, size V1 and size V2 are essentially the same. Size V1 can also be different from size V2.

[0074] Setting the reference bit line select signal BSref high is to suppress the effect of the potential rise in the select bit line BLsel caused by setting the select word line WLsel high. Therefore, as long as the effect of the potential rise in the select bit line BLsel caused by setting the select word line WLsel high can be suppressed, the timing of setting the reference bit line select signal BSref high does not have to be exactly the same as the timing of setting the select word line WLsel high. In one example, the reference bit line select signal BSref is set to high synchronously with the timing of the potential rise in the select bit line BLsel caused by setting the select word line WLsel high.

[0075] At time t4, the enable signal SEN is set to high. This enables the sense amplifier circuit 14A to operate. Consequently, the higher potential of nodes SAN0 and SAN1 rises to the internal power supply potential Vcc, and the lower potential of nodes SAN0 and SAN1 falls to the ground potential Vss. Figure 6 In the example shown, the potential of node SAN0 is lowered to ground potential Vss, and the potential of node SAN1 is raised to internal power supply potential Vcc. The select bit line BLsel connected to node SAN0 will also have ground potential Vss. Additionally, the reference bit line BLref connected to node SAN1 will also have internal power supply potential Vcc.

[0076] In the case where the selected memory cell MCsel does not store charge in the cell capacitor CC, node SAN1 and the reference bit line BLref will have internal power supply potential Vcc, and node SAN0 and the selected bit line BLsel will also have ground potential Vss. Because the selected bit line BLsel has ground potential Vss, it does not store charge in the cell capacitor CC of the selected memory cell MCsel, i.e., it recovers the state before the data was read.

[0077] In the case where the select memory cell MCsel stores charge in the cell capacitor CC, the select bit line BLsel has an internal power supply potential Vcc, therefore, charge is stored in the cell capacitor CC of the select memory cell MCsel. This restores the select memory cell MCsel to its state before data readout.

[0078] At time t5, the potential of the select word line WLsel is set to low. Consequently, the cell transistor CT of the select memory cell MCsel becomes off.

[0079] At time t6, the enable signal SEN is set to a low level. As a result, the sense amplifier circuit 14A becomes inoperable.

[0080] At time t7, the potential of signal PRE is set to high. Consequently, transistors TN1 and TN2 of the sense amplifier circuit 14A become active, and nodes SAN0 and SAN1 are pre-charged to the pre-charge potential Vpc. Additionally, the potential of the select bit line BLsel connected to node SAN0 and the potential of the reference bit line BLref connected to node SAN1 also become the pre-charge potential Vpc.

[0081] At time t8, the select bit line select signal BSSel is set to low. Therefore, the select bit line select transistor TrBsel is turned off.

[0082] At time t8, the reference bit line select signal BSref is set to a low level. Consequently, the reference bit line select transistor TrBref is turned off.

[0083] 1.3. Advantages

[0084] For reference Figure 6 As stated above, when the potential of the select word line WLsel is set to a high level, the potential of the select bit line BLsel rises. During data readout, this manifests as noise on node SAN0 of the sense amplifier circuit 14A, thereby reducing the accuracy of data readout. To address this, consider the following comparative example. In this comparative example, a cell group CS connected to the global bit line GBL_1 is used as a dedicated cell group for reference (hereinafter referred to as the reference dedicated cell group) CS. The memory cell MC in the reference dedicated cell group CS is not used to store data, and the cell capacitor CC stores a charge of a pre-charge potential Vpc (=Vcc / 2). Furthermore, when the potential of the select word line WLsel is set to a high level, the potential of any word line (hereinafter referred to as the reference dedicated word line) WL in the reference dedicated cell group CS is also set to a high level. As a result, the capacitance of the memory cell (hereinafter referred to as the reference dedicated memory cell) MC connected to the reference dedicated word line WL causes the potential of the bit line BL in the reference dedicated cell group CS to rise. Therefore, the effect of the potential rise of the select bit line BLsel is suppressed.

[0085] However, since the potential of the reference dedicated word line WL is set to a high level, when the potential of the bit line BL in the reference dedicated cell group CS is made to the internal power supply potential Vcc or the ground potential Vss by the sense amplifier circuit 14A, the potential of the cell capacitor CC of the reference dedicated memory cell MC deviates from the precharge potential Vpc. Therefore, a precharge is set at the start of precharge (equivalent to the first embodiment). Figure 6 After time t7), during the period when pre-charging occurs, the potential of the reference dedicated word line WL is high. This period causes the cell capacitor CC of the reference dedicated memory cell MC to retain a charge of the pre-charge potential Vpc again, that is, it causes the reference dedicated memory cell MC to recover. However, this recovery period reduces the speed at which data is read from the selected memory cell MCsel. In addition, the comparative example memory device is larger in size because space is required to set up the reference dedicated cell group CS.

[0086] According to the first embodiment, when the potential of the select word line WLsel is set to a high level, the reference bit line select signal BSref is also set to a high level. A capacitance exists between the wiring transmitting the reference bit line select signal BSref (the gate of the reference bit line select transistor TrBref) and the reference bit line BLref. Therefore, by setting the reference bit line select signal BSref to a high level, the potential of the reference bit line BLref rises. As a result, the potential of node SAN1 of the sense amplifier circuit 14A rises. The potential change (rise) of node SAN1 is of the same polarity as the potential change (rise) of node SAN0 of the sense amplifier circuit 14A based on the high potential of the select word line WLsel. Thus, the rise in the potential of the reference bit line BLref mitigates or cancels the effect on the operation of the sense amplifier circuit 14A caused by the rise in the potential of the select bit line BLsel due to the rise in the potential of the select word line WLsel. Therefore, the reduction in data readout accuracy is suppressed. Furthermore, regarding suppressing the reduction in data readout accuracy of the memory device of the first embodiment, a dedicated reference cell group and its control are not required, unlike in the comparative example. Therefore, data can be read in a short time.

[0087] The amount of potential rise in the select bit line BLsel caused by the potential rise of the select word line WLsel depends on the capacitance between the gate of the unit transistor CT and the bit line BL (the end of the unit transistor CT connected to the bit line BL). Similarly, the amount of potential rise in the reference bit line BLref caused by the potential rise of the reference bit line select signal BSref depends on the capacitance between the gate of the bit line select transistor TrB and the bit line BL (the end of the bit line select transistor TrB connected to the reference bit line BLref). Therefore, the closer the shape, construction, and (or) size of the bit line select transistor TrB is to the shape, construction, and (or) size of the unit transistor CT, the closer the capacitance of the bit line select transistor TrB is to the capacitance of the unit transistor CT. Consequently, the closer the shape, construction, and (or) size of the bit line select transistor TrB is to the shape, construction, and (or) size of the unit transistor CT, the better the potential rise of the reference bit line BLref based on the potential rise of the reference bit line select signal BSref will suppress the effect of the potential rise of the select bit line BLsel based on the potential rise of the select word line WLsel.

[0088] Furthermore, the amount of potential rise in the select bit line BLsel caused by the potential rise of the select word line WLsel depends on the amount of potential rise in the word line WL. Similarly, the amount of potential rise in the reference bit line BLref caused by the potential rise of the reference bit line select signal BSref depends on the amount of potential rise in the bit line select signal BS. Therefore, the closer the amount of potential rise in the select word line WLsel (magnitude V2) is to the amount of potential rise in the reference bit line select signal BSref (magnitude V1), the better the potential rise in the reference bit line BLref caused by the potential rise in the reference bit line select signal BSref will suppress the effect of the potential rise in the select bit line BLsel caused by the potential rise in the select word line WLsel.

[0089] Furthermore, the storage device 1 of the first embodiment does not require a dedicated reference cell group, nor does it require space for the dedicated reference cell group. As a result, the storage device 1 is smaller.

[0090] Furthermore, according to the first embodiment, the memory device 1 can achieve stable operation, thereby suppressing the reduction of data readout accuracy. Each bit line BL remains at the precharge potential Vpc when it is not accessed, including when reading data from the memory cell MC connected to it, and the bit line selection transistor TrB connected to it remains in the off state, thus causing electrical fluctuation. Therefore, the potential of the bit line BL may unexpectedly change from the precharge potential Vpc. According to the first embodiment, the cell group CS sequentially functions as the reference cell group CSref. Each cell group CS receives the precharge voltage Vpc during the period it functions as the reference cell group CSref. Therefore, the electrical fluctuation state of each cell group CS is periodically eliminated. Thus, the memory device 1 can operate stably, thereby enabling data readout with high accuracy.

[0091] 1.4. Variation Example

[0092] 1.4.1. First Variation Example

[0093] Figure 7 This describes a portion of the constituent elements of the storage device and the connections of the constituent elements in a first variation of the first embodiment. Figure 7 This describes the constituent elements of the cell group CS of the storage device 1 in the first variation example, and the connections between these constituent elements. For example... Figure 7 As shown, cell group CS contains two bit line selection transistors, TrB_a and TrB_b. TrB_a and TrB_b are connected in parallel between a global bit line GBL and a bit line BL. Bit line selection transistor TrB_a receives the bit line selection signal BS_a at its gate. Bit line selection transistor TrB_b receives the bit line selection signal BS_b at its gate.

[0094] Figure 8 This indicates the state of the storage device during data readout in the first variation of the first embodiment. Preferably, when the cell group CS functions as the selection cell group CSsel, the on-resistance of the bit line selection transistor TrB is low. This is because the speed of accessing the selection memory cell MCsel (the potential rise or fall of the selection bit line BLsel) is faster.

[0095] On the other hand, when cell group CS functions as reference cell group CSref, bit line select transistor TrB only needs to suppress the effect caused by the rise of select word line WLsel, and does not need to have a low on-resistance.

[0096] Based on these requirements, such as Figure 8As shown, in the selection cell group CSsel, both bit line selection transistors TrB_a and TrB_b are set to the on state. On the other hand, in the reference cell group CSref, when the potential of the selection word line WLsel is set to high, only one of the bit line selection transistors TrB_a and TrB_b is set to the on state. Figure 8 The example shown is a bit line select transistor TrB_a. Bit line select transistors TrB_a and TrB_b in the on state are surrounded by solid lines.

[0097] Figure 9 This refers to the potentials of several wirings and signals during the data readout period of the storage device in the first variation of the first embodiment, expressed in terms of time. For example... Figure 9 As shown, the select bit line select signals BSsel_a and BSsel_b are set to high at time t1 and low at time t8. The reference bit line select signal BSref_a is set to high at time t3 and low at time t8. Other bit line select signals BS besides the select bit line select signals BSsel_a and BSsel_b, and the reference bit line select signal BSref_a, are set to high at time t3 and low at time t8. Figure 9 The entire period shown remains at a low level.

[0098] By adjusting the on-resistance and capacitance of the bit line selection transistors TrB_a and TrB_b, the operational characteristics of the selection cell group CSsel and the reference cell group CSref can be individually adjusted. Specifically, the magnitude of the potential rise in the reference bit line BLref caused by the potential rise of the reference bit line selection signal BSref, and the magnitude of the on-resistance of the selection bit line selection transistor TrBsel, can be individually adjusted. Thus, in the reference cell group CSref, the effects caused by the potential rise of the selection bit line BLsel are optimally suppressed by the bit line selection transistors TrB_a or TrB_b, while simultaneously achieving the optimal resistance between the global bit line GBL_0 and the selection memory cell MCsel in the selection cell group CSsel.

[0099] Each unit group CS can contain more than three bit line selection transistors TrB connected in parallel.

[0100] 1.4.2. Second variation example

[0101] Figure 10 It represents the potential of several wirings and signals during the data readout period of the storage device in the second variation of the first embodiment, according to time.

[0102] like Figure 10As shown, the high-level potential (the difference between the low-level and high-level potentials) of the select bit line select signal BSsel has a magnitude of V3. Magnitude V3 is greater than magnitude V1. Therefore, the on-resistance of the select bit line select transistor TrBsel is lower than when magnitude V1 is used.

[0103] According to the second variation, the magnitude of the potential rise of the reference bit line BLref caused by the potential rise of the reference bit line selection signal BSref, and the magnitude of the on-resistance of the selection bit line selection transistor TrBsel, can also be adjusted individually. Thus, the same advantages as in the first variation can be obtained.

[0104] 1.4.3. Third Variation Example

[0105] Figure 11 This describes a portion of the constituent elements and their connections during the data readout period of the storage device in the third variation of the first embodiment.

[0106] like Figure 11 As shown, during data reading from the select memory cell MCsel, two reference cell groups, CSref_0 and CSref_1, are used. Furthermore, when the select word line WLsel is set to a high level, the respective reference bit line select signals BSref_0 and BSref_1 for the reference cell groups CSref_0 and CSref_1 are also set to a high level.

[0107] Figure 12 This refers to the potentials of several wirings and signals during the data readout period of the storage device in the third variation of the first embodiment, expressed in terms of time. For example... Figure 12 As shown, the reference bit line select signals BSref_0 and BSref_1 are set to high at time t3 and low at time t8. The bit line select signals BS other than the select bit line select signal BSsel and the reference bit line select signals BSref_0 and BSref_1 are... Figure 12 The entire period shown remains at a low level.

[0108] The potential rise of the reference bit line BLref caused by the high-level changes of multiple reference bit line select signals BSref accumulates. Therefore, the amount of potential rise of the reference bit line BLref depends on the number of reference bit line select signals BSref that are set to high level during data readout. Thus, by adjusting the number of reference bit line select signals BSref that are set to high level during data readout, the amount of potential rise of the reference bit line BLref can be adjusted. Therefore, according to the third variation, the magnitude of the potential rise of the reference bit line BLref caused by the potential rise of the reference bit line select signal BSref, and the magnitude of the on-resistance of the select bit line select transistor TrBsel, can also be adjusted individually. Thus, the same advantages as in the first variation can be obtained.

[0109] Furthermore, according to the third variation, during a single data read (reading data from one selected memory cell MCsel), the electrical float of the bit lines BL of two or more cell groups CS is eliminated. Thus, the electrical float of multiple bit lines BL can be eliminated efficiently.

[0110] Two or more of the first, second and third variations can be combined.

[0111] 2. Second Implementation Method

[0112] Figure 13 This illustrates a portion of the constituent elements and their connections during the data readout process of the storage device in the second embodiment. For example... Figure 13 As shown, a cell group CS connected to the global bit line GBL_0 functions as the selection cell group CSsel. Another cell group CS connected to the global bit line GBL_0 functions as the auxiliary cell group CSass. The auxiliary cell group CSass performs the function of suppressing the potential rise of the global bit line GBL_0 caused by the potential rise of the selection word line WLsel, which is performed by the reference cell group CSref in the first embodiment. Regarding the auxiliary cell group CSass, it functions as the reference cell group CSref. Figure 5 The content described for the reference cell group CSref is the same. During multiple data readouts, a cell group CS that is different from the cell group CS used as the auxiliary cell group CSass in the previous data readout can be used as the auxiliary cell group CSass. Hereinafter, the bit line selection transistor TrB in the auxiliary cell group CSass is sometimes referred to as the auxiliary bit line selection transistor TrBass. The bit line selection signal BS received through the auxiliary bit line selection transistor TrBass is sometimes referred to as the auxiliary bit line selection signal BSass.

[0113] A cell group CS connected to the global bit line GBL_1 functions as a reference cell group CSref.

[0114] Figure 14 It represents the potential of several wirings and signals during the data readout period of the storage device in the second embodiment, according to time. Figure 14 The constituent elements connected to the global bit line GBL_1 are not shown. Arbitrary control can be performed on the reference cell group CSref. In one example, the reference bit line select signal BSref is maintained at a low level. In different examples, the reference bit line select signal BSref only needs to be set to a high level before time t3. The state in which the reference bit line select signal BSref is set to a high level at time t3 corresponds to a combination of the second and first embodiments.

[0115] like Figure 14 As shown, at time t1, the auxiliary bit line selection signal BSass is set to a high level. It only needs to go high before time t2.

[0116] At time t3, the auxiliary bit line select signal BSass is set to low. Setting BSass low suppresses the potential rise of the select bit line BLsel caused by setting the select word line WLsel high. Therefore, as long as the potential rise of the select bit line BLsel caused by setting WLsel high can be suppressed, setting BSass low does not need to be at exactly the same time as setting WLsel high. In one example, BSass is set low synchronously with the potential rise of the select bit line BLsel caused by setting WLsel high.

[0117] According to the second embodiment, the cell group CS connected to the selection cell group CSsel on the same global bit line GBL_0 functions as an auxiliary cell group CSass. When the potential of the selection word line WLsel is set to a high level, the auxiliary bit line selection signal BSass is set to a low level. The low level of the auxiliary bit line selection signal BSass causes a change in the potential of the global bit line GBL_0. This change in the potential of the global bit line GBL_0 has the opposite polarity to the noise on the potential of the global bit line GBL_0 caused by the high level of the selection word line WLsel. Therefore, the noise on the potential of the global bit line GBL_0 caused by the high level of the selection word line WLsel can be suppressed or canceled. As a result, the reduction in data readout accuracy can be suppressed.

[0118] Furthermore, similar to the first embodiment, the second embodiment does not require a dedicated reference cell group and its control to suppress the decrease in data readout accuracy. Therefore, like the first embodiment, data can be read out in a short time.

[0119] 2.1. First Variation Example

[0120] In the first variation, the bit line selection transistor TrB is always kept in the on state. Moreover, during data readout, the bit line selection transistor TrB of the selection cell group CSsel is kept in the on state, and the bit line selection transistor TrB of the cell group CS other than the selection cell group CSsel is set to the off state.

[0121] Figure 15 This refers to the potentials of several wirings and signals during the data readout period of the storage device in the first variation of the second embodiment, expressed in terms of time. For example... Figure 15 As shown, in Figure 15 At the start of the period shown, the bit line selection signal BS, including the selected bit line selection signal BSsel and the auxiliary bit line selection signal BSass, is at a high level.

[0122] exist Figure 15 Throughout the entire period shown, the select bit line select signal BSSel remains at a high level.

[0123] At time t1, the bit line selection signal BS, except for the selected bit line selection signal BSsel and the auxiliary bit line selection signal BSass, is set to low level.

[0124] At time t3, the auxiliary bit line selection signal BSass is set to low.

[0125] At time t8, the potential of the bit line select signal BS, except for the bit line select signal BSeI, is set to high.

[0126] According to the first variation, even if the bit line select signal BS is always high, the potential change of the auxiliary bit line select signal BSass causes noise with the opposite polarity to the noise generated on the global bit line GBL_0 due to the potential change of the select word line WLsel. Therefore, the same advantages as the basic form of the second embodiment can be obtained.

[0127] 2.2. Second variation example

[0128] The second variation is equivalent to the application of the first variation of the first embodiment to the second embodiment. That is, the unit group CS has Figure 7The constituent elements and their connections shown include bit line selection transistors TrB_a and Tr_b. Furthermore, in the selection cell group CSBsel, both the selection bit line selection signals BSBsel_a and BSBsel_b of the selection bit line selection transistors TrBsel_a and TrBsel_b are set to a high level, thus enabling both transistors to be in a conducting state. On the other hand, in the auxiliary cell group CSass, when the potential of the selection word line WLsel is set to a high level, only one of the auxiliary bit line selection signals BSass_a and BSass_b (e.g., BSass_a) is set to a low level.

[0129] Figure 16 This refers to the potentials of several wirings and signals during the data readout period of the storage device in the second variation of the second embodiment, expressed in terms of time. For example... Figure 16 As shown, the select bit line select signals BSBsel_a and BSBsel_b are set to high at time t1 and low at time t8. The auxiliary bit line select signal BSass_a is set to high at time t1 and low at time t3. Other bit line select signals BS besides the select bit line select signals BSBsel_a and BSBsel_b and the auxiliary bit line select signal BSass_a are set to high at time t1 and low at time t3. Figure 16 The entire period shown remains at a low level.

[0130] According to the second variation, it is possible to obtain the same additional advantages as the first variation of the first embodiment.

[0131] 2.3. Third variation example

[0132] The third variation is equivalent to the application of the third variation of the first embodiment to the second embodiment.

[0133] Figure 17 This describes a portion of the constituent elements and their connections during the data readout period of the storage device in the third variation of the second embodiment.

[0134] like Figure 17 As shown, during data reading from the select memory cell MCsel, two auxiliary cell groups CSass_0 and CSass_1 are used. Furthermore, when the select word line WLsel is set to a high level, the auxiliary bit line select signals BSBass_0 and BSBass_1 for each of the auxiliary cell groups CSass_0 and CSass_1 are set to a low level.

[0135] Figure 18This refers to the potentials of several wirings and signals during the data readout period of the storage device in the third variation of the second embodiment, expressed in terms of time. For example... Figure 18 As shown, the auxiliary bit line selection signals BSass_0 and BSass_1 are set to high at time t1 and low at time t3. The bit line selection signals BS other than the main bit line selection signal BSsel and the auxiliary bit line selection signals BSass_0 and BSass_1 are... Figure 18 The entire period shown remains at a low level.

[0136] According to the third variation, it is possible to obtain the same additional advantages as the third variation of the first embodiment.

[0137] Two or more of the first, second, and third variations can be combined. The second variation of the first embodiment can also be applied to the second embodiment.

[0138] 3. Third Implementation Method

[0139] The third embodiment is an excerpt from a portion of the first and second embodiments. That is, the third embodiment is equivalent to a configuration that does not include the control of the reference cell group CSref (especially the reference bit line selection transistor TrBref) in the first embodiment, or the control of the auxiliary cell group (especially the auxiliary bit line selection transistor TrBass) in the second embodiment.

[0140] The data readout process of the storage device in the third embodiment includes some constituent elements and connections that are connected to those in the first embodiment. Figure 4 The same applies. However, arbitrary control can be performed on the reference cell group CSref. In one example, the reference bit line select signal BSref is maintained at a low level. In different examples, the reference bit line select signal BSref only needs to be set to a high level before time t3, for example, set to a high level at time t1. The form in which the reference bit line select signal BSref is set to a high level at time t3 is equivalent to the first embodiment.

[0141] Alternatively, during data readout of the storage device in the third embodiment, a portion of the constituent elements and connections are connected to those in the second embodiment. Figure 13 Same. However, no control is performed on the auxiliary unit group CSass. The form in which control is performed on the auxiliary unit group CSass is equivalent to the second embodiment.

[0142] Figure 19 This refers to the potentials of several wirings and signals during the data readout period of the storage device in the third embodiment, expressed in terms of time. For example... Figure 19 As shown, and as referenced Figure 6 The signal PRE is described as follows: Figure 19The period shown is set to high level from the start of time t2.

[0143] At time t1, that is, during the period when the signal PRE is high, the select bit line select signal BSsel is set to high.

[0144] At time t3, that is, while the signal PRE is low, the potential of the select word line WLsel is set to high.

[0145] According to the third embodiment, as described below, the impact of noise on data readout is suppressed.

[0146] There is capacitance between the gate of the bit line select transistor TrB and the global bit line GBL. Therefore, when the select bit line select signal BSsel on the gate of the bit line select transistor TrB is set to a high level, the potential of the global bit line GBL can rise, and this rise in potential manifests as noise to the global bit line GBL.

[0147] According to the third embodiment, during the period when the signal PRE is high, i.e., during pre-charging, the select bit line selection signal BSsel is controlled to be high. Therefore, when the select bit line selection signal BSsel is controlled to be high, the global bit line GBL_0 receives the pre-charging voltage Vpc. Thus, the noise caused by the potential rise of the global bit line GBL_0 is suppressed.

[0148] As described in the first embodiment, each bit line BL is electrically floating when not accessed, and the potential of the bit line BL may vary from the precharge potential Vpc. According to the third embodiment, during precharge, the select bit line select signal BSsel is set high, i.e., the global bit line GBL_0 is connected to the select bit line BLsel. Therefore, the select bit line BLsel receives the precharge voltage Vpc at the beginning of data readout, thus eliminating the potential variation during the electrical floating of the select bit line BLsel. This allows data to be read out with higher accuracy.

[0149] 3.1. First Variation Example

[0150] The first variation is the same as the first variation of the second embodiment, in that the bit line selection transistor TrB is always kept in the on state. That is, the first variation is an excerpt of a portion of the first variation of the second embodiment.

[0151] Figure 20 This refers to the potentials of several wirings and signals during the data readout period of the storage device in the first variation of the third embodiment, expressed in terms of time. For example... Figure 20 As shown, in Figure 20 At the start time of the period shown, the bit line select signal BS, including the bit line select signal BSsel, is at a high level.

[0152] exist Figure 20 Throughout the entire period shown, the select bit line select signal BSSel remains at a high level.

[0153] At time t1, that is, during the period when signal PRE is high, the bit line select signal BS, including the reference bit line select signal BSref, except for the select bit line select signal BSsel, is set to low.

[0154] When the bit line select signal BS (excluding the bit line select signal BSsel) on the gate of the bit line select transistor TrB is set to a low level due to the capacitance between the gate of the bit line select transistor TrB and the global bit line GBL, the potential of the global bit line GBL may drop. This drop in potential manifests as noise on the global bit line GBL_0.

[0155] According to the first variation, during the period when the signal PRE is high, i.e., during pre-charging, the bit line selection signal BS, except for the selection bit line selection signal BSsel, is controlled to a low level. Based on the same principle as in the basic form of the third embodiment for suppressing the noise caused by controlling the selection bit line selection signal BSsel to a high level, the noise caused by the potential drop of the global bit line GBL_0 and the potential fluctuation of the selection bit line BLsel are eliminated. Therefore, even if the bit line selection signal BS is always high, data can be read with high accuracy.

[0156] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, as well as within the scope of the invention as described in the claims and their equivalents.

[0157] [Symbol Explanation]

[0158] 1: Storage device

[0159] 11: Memory Cell Array

[0160] 12: Input / output circuit

[0161] 13: Line control circuit

[0162] 14: Column control circuit

[0163] 15: Read / Write Circuit

[0164] 16: Control Circuit

[0165] MC: Storage Unit

[0166] WL: Word Line

[0167] BL: Bitline

[0168] PL: Board Line

[0169] CS: Unit Group

[0170] CT: Unit Transistor

[0171] CC: Unit capacitor

[0172] TrB: Bit Line Select Transistor

[0173] BS: Bit line select signal.

Claims

1. A storage device comprising: The sensing amplifier circuit has a first input and a second input; Multiple transistors supply a first potential to the first input and the second input based on a first signal; The first wiring is connected to the first input; The second wiring is connected to the second input; The first memory cell includes a first cell transistor and a first cell capacitor connected in series; A first selection transistor is connected between the first wiring and the first memory cell; The second memory cell includes a second unit transistor and a second unit capacitor connected in series; and A second selection transistor is connected between the second wiring and the second memory cell; and Perform a first action of raising the potential of the gate of the first selection transistor. Following the first action, a second action is performed to lower the potential of the first signal. After the second action, a third action is performed, which is to increase the potential of the gate of the first unit transistor and the potential of the gate of the second selection transistor.

2. The storage device according to claim 1, wherein Following the third action, a fourth action is performed, which involves lowering the potential of the gate of the first selection transistor and lowering the potential of the gate of the second selection transistor. From the start of the first action to the end of the fourth action, the gate potential of the second unit transistor remains at a low level.

3. The storage device according to claim 2, further comprising: A third selection transistor is connected between the first wiring and the first memory cell; and The fourth selection transistor is connected between the second wiring and the second memory cell; In the first operation, the potential of the gate of the third selection transistor is increased. From the start of the first action to the end of the fourth action, the potential of the gate of the fourth selection transistor remains low.

4. The storage device according to claim 1, wherein In the first operation, the potential of the gate of the first selection transistor is increased by a first magnitude. In the third operation, the potential of the gate of the second selection transistor is increased by a second magnitude. The first size is greater than the second size.

5. The storage device according to claim 1, further comprising: The third memory cell includes a third unit transistor and a third unit capacitor connected in series; and The third selection transistor is connected between the second wiring and the third memory cell; In the third operation, the potential of the gate of the third selection transistor is increased.

6. The storage device according to claim 1, wherein The first unit capacitor stores one of the following: a first amount of charge and a second amount of charge, determined based on the data stored in the first storage unit. The second unit capacitor stores one of the third and fourth amounts of charge, determined based on the data stored in the second storage unit.

7. The storage device according to claim 1, comprising: The fourth memory cell includes a fourth cell transistor and a fourth cell capacitor connected in series; The fifth selection transistor is connected between the first wiring and the fourth memory cell; The fifth memory cell includes a fifth cell transistor and a fifth cell capacitor connected in series; and The sixth selection transistor is connected between the second wiring and the fifth memory cell; After the third action, a fifth action is performed, which is to increase the potential of the gate of the fourth unit transistor and the potential of the gate of the sixth selection transistor.

8. The storage device according to claim 1, comprising: The fourth memory cell includes a fourth cell transistor and a fourth cell capacitor connected in series and connected to the first wiring via the first selection transistor; The fifth memory cell includes a fifth cell transistor and a fifth cell capacitor connected in series; and The fifth selection transistor is connected between the second wiring and the fifth memory cell; Following the third action, a fifth action is performed, which involves raising the gate potential of either the first or fourth unit transistor. Increase the potential of the gate of the fifth selection transistor.

9. A storage device comprising: The sensing amplifier circuit has a first input and a second input; The first wiring is connected to the first input; The second wiring is connected to the second input; The first memory cell includes a first cell transistor and a first cell capacitor connected in series; A first selection transistor is connected between the first wiring and the first memory cell; The second memory cell includes a second unit transistor and a second unit capacitor connected in series; and A second selection transistor is connected between the first wiring and the second memory cell; and Perform the first action, which is to increase the potential of the gate of the first unit transistor and decrease the potential of the gate of the second selection transistor.

10. The storage device according to claim 9, wherein Prior to the first action, a second action is performed to increase the potential of the gate of the first selection transistor, and a third action is performed to increase the potential of the gate of the second selection transistor.

11. The storage device according to claim 10, wherein Following the first action, a fourth action is performed to lower the potential of the gate of the first selection transistor. From the second action to the fourth action, the gate potential of the second unit transistor remains at a low level.

12. The storage device according to claim 11, further comprising: A third selection transistor is connected between the first wiring and the first memory cell; and A fourth selection transistor is connected between the first wiring and the second memory cell; In the second action, the potential of the gate of the third selection transistor is increased. From the start of the second action to the end of the fourth action, the potential of the gate of the fourth selection transistor remains low.

13. The storage device according to claim 9, further comprising: The third memory cell includes a third unit transistor and a third unit capacitor connected in series; and A third selection transistor is connected between the first wiring and the third memory cell; and In the first action, the potential of the gate of the third selection transistor is reduced.

14. The storage device according to claim 9, wherein The first unit capacitor stores one of the following: a first amount of charge and a second amount of charge, determined based on the data stored in the first storage unit. The second unit capacitor stores one of the third and fourth amounts of charge, determined based on the data stored in the second storage unit.

15. The storage device according to claim 9, comprising: The fourth memory cell includes a fourth cell transistor and a fourth cell capacitor connected in series; The fifth selection transistor is connected between the first wiring and the fourth memory cell; The fifth memory cell includes a fifth cell transistor and a fifth cell capacitor connected in series; and A sixth selection transistor is connected between the first wiring and the fifth memory cell; and After the first action, the fifth action is performed, which is to increase the potential of the gate of the fourth unit transistor and decrease the potential of the gate of the sixth selection transistor.

16. The storage device according to claim 9, comprising: The fourth memory cell includes a fourth cell transistor and a fourth cell capacitor connected in series and connected to the first wiring via the first selection transistor; The fifth memory cell includes a fifth cell transistor and a fifth cell capacitor connected in series; and A fifth selection transistor is connected between the first wiring and the fifth memory cell; and After the first action, a fifth action is performed, which is to increase the potential of the gate of the first unit transistor or the fourth unit transistor and decrease the potential of the gate of the fifth selection transistor.

17. The storage device according to claim 9, further comprising: The sixth memory cell includes a sixth cell transistor and a sixth cell capacitor connected in series; and The seventh selection transistor is connected between the first wiring and the sixth memory cell; and Prior to the first action, a sixth action is performed to lower the potential of the gate of the seventh selection transistor. After the first action, a seventh action is performed, which is to increase the potential of the gate of the second selection transistor and the potential of the gate of the seventh selection transistor.

18. The storage device according to claim 17, wherein From the start of the sixth operation to the end of the seventh operation, the potential of the gate of the first selection transistor remains high.

19. A storage device comprising: The sensing amplifier circuit has a first input and a second input; Multiple transistors supply a first potential to the first input and the second input; The first wiring is connected to the first input; The second wiring is connected to the second input; The first memory cell includes a first cell transistor and a first cell capacitor connected in series; A first selection transistor is connected between the first wiring and the first memory cell; The second memory cell includes a second unit transistor and a second unit capacitor connected in series; and A second selection transistor is connected between the second wiring and the second memory cell; and The gate potentials of the respective transistors remain high throughout the first period. At the first moment during the first period, the gate potential of the first selection transistor is high. At a second moment following the first period, the potential of the gate of the first unit transistor is increased.

20. The storage device according to claim 19, wherein At the first moment, the potential of the gate of the first selection transistor is set to a high level.

21. The storage device according to claim 19, wherein The potential of the gate of the first selection transistor is maintained at a high level until the third time point after the second time point.

22. The storage device according to claim 19, wherein The gates of the plurality of transistors receive the first signal. At the fourth time point following the second time point, the potential of the first signal is increased. After the fourth time point, the potential of the gate of the first selection transistor is reduced.

23. The storage device according to claim 19, comprising: The third memory cell includes a third unit transistor and a third unit capacitor connected in series; and A third selection transistor is connected between the first wiring and the third memory cell; and At time 5 during the first period, the potential of the gate of the third selection transistor is reduced.

24. The storage device according to claim 23, wherein The gates of the plurality of transistors receive the first signal. At the sixth time point following the second time point, the potential of the first signal is increased. After the sixth time point, the potential of the gate of the third selection transistor is increased.

Images