A read amplifier circuit for an eFuse memory array

Abstract

The application provides a read amplification circuit of an eFuse memory array, the eFuse memory array comprising a plurality of eFuse branches to be read, the read amplification circuit comprising a latch, a reference branch and a current source unit. The latch is powered by a first power supply, and the latch comprises a first inverting branch and a second inverting branch; the outputs of the first inverting branch and the second inverting branch serve as two output terminals of the latch; wherein the first inverting branch is connected in series with the eFuse memory array. The reference branch is connected in series with the second inverting branch; the current source unit is arranged between the two output terminals of the latch and is powered by a second power supply, and the current source comprises a fifth switch tube, a sixth switch tube and a seventh switch tube, one end of the seventh switch tube is connected to the second power supply, and the fifth switch tube and the sixth switch tube are symmetrically arranged between the two output terminals with respect to the seventh switch tube; the fifth switch tube, the sixth switch tube and the seventh switch tube are controlled by the same clock signal.

Description

Technical Field

[0001] This application relates to the field of semiconductor storage technology, and in particular to a read amplifier circuit for an eFuse storage array. Background Technology

[0002] eFuse (electronic fuse) memory, as a typical one-time programmable non-volatile memory cell, has been widely used. In the unprogrammed state, the connection of the eFuse cell remains intact, exhibiting a low initial resistance value. When data needs to be written, by applying a sufficiently large programming current to a specific eFuse cell, the electromigration and thermal effects cause the silicide to partially melt or structurally break down, resulting in an irreversible and drastic increase in its resistance value, exhibiting an extremely high resistive state.

[0003] To accurately convert the physical resistance state stored in the eFuse cell into a logic level that can be processed by subsequent digital circuits, a read amplification circuit must be configured in the read path. The core function of the read amplification circuit is to detect the slight difference in electrical signals generated by the eFuse cell before and after programming and quickly amplify them to a full-swing digital logic level.

[0004] However, in existing eFuse memory array read amplifier circuits, as the capacity of the eFuse memory array increases, a large number of unselected eFuse cells inevitably generate significant parallel leakage current at the same time. This leakage current is superimposed on the current of the target read cell, severely interfering with and weakening the effective read signal, resulting in the inability to correctly determine the logic state. This problem is particularly prominent under high temperature and low voltage conditions, severely restricting the reliability of eFuse memory applications in high-capacity, low-voltage scenarios. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a read amplifier circuit for an eFuse memory array, so as to improve the problem of misjudgment caused by the inability to suppress the parallel subthreshold leakage current generated by a large number of unselected eFuse cells in low power supply voltage and large capacity array scenarios.

[0006] To achieve the above and other related objectives, this application provides a read amplification circuit for an eFuse memory array. The eFuse memory array includes multiple eFuse read branches connected in parallel. The read amplification circuit includes a latch, a reference branch, and a current source unit. The latch is powered by a first power supply and includes two cross-coupled inverter branches: a first inverter branch and a second inverter branch. The outputs of the first and second inverter branches serve as the two output terminals of the latch. The first inverter branch is connected in series with the eFuse memory array. The reference branch is connected in series with the second inverter branch. The current source unit is located between the two output terminals of the latch and is powered by a second power supply. The current source includes at least three switching transistors: a fifth switching transistor, a sixth switching transistor, and a seventh switching transistor. One end of the seventh switching transistor is connected to the second power supply. The fifth and sixth switching transistors are symmetrically arranged between the two output terminals relative to the seventh switching transistor. The fifth, sixth, and seventh switching transistors are controlled by the same clock signal. During the read preparation phase, the current source unit is turned on by the clock signal, and the current in the reference branch and the branch to be read in the eFuse array is provided by the current source unit; during the read phase, the current source unit is turned off by the clock signal, the positive feedback mechanism of the latch is activated, and logic levels are output at the two output terminals.

[0007] In one embodiment of the readout amplifier circuit of the present invention, the first power supply and the second power supply are the same power supply.

[0008] In one embodiment of the readout amplifier circuit of the present invention, the fifth, sixth and seventh switching transistors are PMOS transistors; when the clock signal is low, the current source unit is working, and when the clock signal is high, the current source unit is off.

[0009] In one embodiment of the read amplifier circuit of the present invention, if the clock signal turns high, the parasitic capacitance between the two output terminals maintains the initial voltage difference between the two output terminals and triggers positive feedback of the latch, outputting logic level at the two output terminals.

[0010] In one embodiment of the readout amplifier circuit of the present invention, the readout amplifier circuit further includes an output buffer unit, which is connected to the two output terminals and is used to output complementary logic signals.

[0011] In one embodiment of the readout amplifier circuit of the present invention, the output buffer unit includes two inverters, which are respectively connected to the two output terminals and shape the voltages of the two output terminals into standard digital complementary signals.

[0012] In one embodiment of the readout amplifier circuit of the present invention, the reference branch includes a precision reference resistor and an NMOS transistor. One end of the precision reference resistor is connected in series with the second inverting branch, and the other end of the precision reference resistor is connected to one end of the NMOS transistor, and the other end of the NMOS transistor is grounded.

[0013] In one embodiment of the read amplifier circuit of the present invention, each of the branches to be read includes an eFuse fuse and an NMOS transistor. One end of the eFuse fuse is connected to the input terminal of the first inverting branch, and the other end of the fuse is connected to one end of the NMOS transistor, and the other end of the NMOS transistor is grounded.

[0014] As described above, the read amplification circuit of the eFuse memory array provided in this application achieves timing separation and physical path separation between the branch current injection process and the latch positive feedback read process by setting up a current source unit composed of a fifth, sixth, and seventh switch transistor, which are synchronously controlled by the same clock signal and arranged symmetrically. During the read preparation stage, the clock signal turns on the current source unit, and the second power supply provides the working current to the eFuse branch to be read and the reference branch, completing the establishment of the differential current signals of the two branches. During this stage, the current supply to the branch path is undertaken by the current source unit, and the path voltage drop consists only of the on-state voltage drop of the current source unit switch transistor, the voltage drop of the latch inverting branch device, and the voltage drop of the eFuse branch itself. This avoids the unnecessary loss of additional threshold voltage caused by the latch positive feedback start-up, saves circuit voltage drop margin, and improves the effective working voltage of the eFuse branch to be read. During the read phase, the clock signal synchronously shuts down the current source unit, cutting off the external current supply and activating the latch positive feedback mechanism formed by the cross-coupled inverter branch. Relying on the stable differential current established by the two branches, a stable logic level is quickly output. Simultaneously, the symmetrical arrangement of the fifth and sixth switches relative to the seventh switch ensures the consistency of current supply to the eFuse's read branch and reference branch, reducing branch current deviation. The external independent clock controls the current source unit, allowing for on-demand adjustment of the branch operating current. By increasing the branch read operating current, leakage current interference from unselected eFuse branches in a parallel multi-branch structure is offset, optimizing the array read signal-to-noise ratio under low-voltage conditions. This adapts to low-voltage read scenarios for large-capacity parallel eFuse storage arrays, effectively improving the accuracy and stability of logic reads in eFuse fuse / non-fuse states. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the read amplifier circuit of an eFuse memory array provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a system chip provided in an embodiment of this application.

[0016] Reference numerals: 100, latch; 101, first power supply; 102, second power supply; 103, first inverting branch; 104, second inverting branch; 110, current source unit; 200, eFuse memory array; 300, reference branch; 400, output buffer unit; 401, inverter; 10, system chip; 20, non-volatile memory; 21, decoder; 22, eFuse memory array; 23, read amplifier circuit; M1, first PMOS transistor; M2, second PMOS transistor; M3, first NMOS transistor; M4, second NMOS transistor; M5, third PMOS transistor; M6, fourth PMOS transistor; M7, fifth PMOS transistor; M8, third NMOS transistor; M9, fourth NMOS transistor; A, first output terminal; B, second output terminal. Detailed Implementation

[0017] The technical solution of this application will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0018] In the description of this application, it should be understood that the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0019] In the description of this application, the references to terms such as "in some embodiments," "in other embodiments," and "in a particular example" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0020] Through long-term research and in-depth technical analysis, the inventors of this application discovered that with the evolution of semiconductor manufacturing processes and the continuous reduction of power supply voltage, while the capacity of eFuse memory arrays has expanded to hundreds of columns or even larger, traditional read amplifier circuits have encountered a serious contradiction between leakage current and voltage drop. Specifically, in the traditional voltage-type latch amplifier architecture, hundreds of unselected bit lines share the same read path, and their subthreshold leakage current will converge into a severe voltage drift at the reference node. Because the series resistance of the eFuse read branch is relatively large, the circuit cannot "trade current for signal-to-noise ratio" like low-impedance solutions; once the power supply voltage drops to an extremely low level, the effective signal window is only a few millivolts, and the drift induced by leakage current can easily overwhelm it, causing the latch amplifier to misjudge. In addition, existing traditional latch amplifiers are still hard-connected to the eFuse read branch during the sampling stage, and their input transistors will also draw a small amount of DC, forming a second leakage current path, further distorting the sampling node potential and introducing a new source of error into the judgment result.

[0021] On the other hand, in traditional current-mode latch amplifier architectures, the subthreshold leakage problem of unselected bit lines still exists. The voltage drop across the entire path to ground originates from the threshold voltage of the latch cross-coupled transistor, the overdrive voltage, and the voltage drop of the eFuse unit itself. This leads to a fundamental physical contradiction: on the one hand, to suppress the effects of subthreshold leakage, the read current of the circuit needs to be significantly increased; on the other hand, the low supply voltage strictly limits the current increase margin because the large threshold voltage consumes most of the voltage margin. This contradiction cannot be reconciled in traditional architectures, making it difficult to avoid misreading of the sensitive amplifier under low supply voltage. At the same time, traditional current-mode architectures often require complementary multiphase clock signals for control, resulting in complex timing logic and a high susceptibility to low fault tolerance due to clock skew.

[0022] Based on the aforementioned deficiencies in related technologies, this application provides a read amplification circuit for an eFuse memory array. This circuit aims to separate the current source injection mechanism from the latch activation process through circuit innovation, thereby releasing sufficient voltage margin at lower power supply voltages and making it possible to suppress subthreshold leakage current by increasing the circuit current.

[0023] Please see Figure 1The first aspect of this application is to provide a read amplification circuit for an eFuse storage array 200, which is a non-volatile storage structure in which storage cells represent different data bits by either being fused or remaining fused. The eFuse storage array 200 typically consists of multiple eFuse cells used to store data such as configuration information, security keys, or identity identifiers. In this invention, the eFuse storage array 200 includes multiple eFuse read branches arranged in parallel, which refer to the current paths in the eFuse storage array 200 used to carry the eFuse cells to be read. Each eFuse read branch typically includes an eFuse fuse, the resistance of which reflects the stored data.

[0024] As a basic embodiment, the read amplification circuit includes a latch 100, a reference branch 300, and a current source unit 110. The latch 100 is powered by a first power supply 101 and is a differential amplifier structure with a positive feedback mechanism, which amplifies small input voltage or current differences into a stable logic level output. The latch 100 includes two cross-coupled inverter branches, namely a first inverter branch 103 and a second inverter branch 104; the outputs of the first inverter branch 103 and the second inverter branch 104 serve as the two output terminals of the latch, labeled as first output terminal A and second output terminal B, respectively; wherein, the first inverter branch 103 is connected in series with the eFuse memory array 22. The reference branch 300 is connected in series with the second inverting branch 104; the current source unit 110 is disposed between the two output terminals of the latch 100 and is powered by the second power supply 102. The current source unit 110 includes at least three switching transistors: a fifth switching transistor M5, a sixth switching transistor M6, and a seventh switching transistor M7. One end of the seventh switching transistor M7 is connected to the second power supply 102. The fifth switching transistor M5 and the sixth switching transistor M6 are symmetrically disposed between the two output terminals relative to the seventh switching transistor M7. The gates of the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 are connected to the same clock signal and are controlled by the same clock signal. During the read preparation phase, the current source unit 110 is turned on by the clock signal, and the current in the reference branch 300 and the branch to be read in the eFuse array 200 is provided by the current source unit 110. During the read phase, the current source unit 110 is turned off by the clock signal, the positive feedback mechanism of the latch 100 is activated, and logic levels are output at the two output terminals.

[0025] Specifically, in this embodiment, the first inverting branch 103 includes a first PMOS transistor M1 and a first NMOS transistor M3, and the second inverting branch 104 includes a second NMOS transistor M4 and a second PMOS transistor M2. The sources of the first PMOS transistor M1 and the second PMOS transistor M2 are both electrically connected to a first power supply 101. The first power supply 101 provides operating voltage to the two PMOS transistors in the latch 100, ensuring that they can be normally turned on or off under specific operating conditions. The drain of the first PMOS transistor M1 is electrically connected to the drain of the first NMOS transistor M3 to form a first output terminal A, and the drain of the second PMOS transistor M2 is electrically connected to the drain of the second NMOS transistor M4 to form a second output terminal B. The gates of the first PMOS transistor M1 and the first NMOS transistor M3 are both electrically connected to the second output terminal B, and the gates of the second PMOS transistor M2 and the second NMOS transistor M4 are both electrically connected to the first output terminal A. The source of the first NMOS transistor M3 is electrically connected to multiple eFuse branches to be read.

[0026] One end of reference branch 300 is connected to the source of the second NMOS transistor M4, and the other end is grounded. Reference branch 300 provides a reference current or voltage path for the read amplifier circuit. By comparing the current or voltage of the eFuse branch to be read with reference branch 300, the fuse state of the eFuse cell can be accurately determined.

[0027] In one embodiment of the readout amplifier circuit of the present invention, the fifth switch M5, the sixth switch M6, and the seventh switch M7 are all PMOS transistors. When the clock signal is low, the current source unit operates; when the clock signal is high, the current source unit is turned off. Specifically, the source of the seventh switch M7 is electrically connected to the second power supply 102, which provides the operating voltage to the current source unit 110, used to provide current to the circuit nodes during the pre-charging phase and establish an initial voltage difference. The drain of the seventh switch M7 is connected to the sources of the fifth switch M5 and the sixth switch M6, respectively. The drain of the fifth switch M5 is connected to the first output terminal A, and the drain of the sixth switch M6 is connected to the second output terminal B. The gates of the fifth switch M5, the sixth switch M6, and the seventh switch M7 are all connected to the same clock signal. The clock signal is a periodically changing electrical signal used to synchronize and control the timing of the modules in the circuit. By varying the level of the clock signal, the current source unit 110 can be precisely controlled to turn on and off, thereby enabling phased operation of the circuit. In one embodiment, for example, the clock signal can be a square wave signal, whose high or low level states control the on and off states of these PMOS transistors.

[0028] The read amplifier circuit of the eFuse memory array 200 provided in this application physically separates the current source injection mechanism from the activation process of the latch 100 by introducing a current source unit 110 composed of a fifth switch M5, a sixth switch M6, and a seventh switch M7. During the establishment of the differential current signal, the voltage across the entire current path is provided by the second power supply 102. In the circuit connecting the eFuse memory array 200, the voltage drop mainly comes from the overdrive voltage of the seventh switch M7, the overdrive voltage of the fifth switch M5, the threshold voltage and overdrive voltage of the first NMOS transistor M3, and the voltage drop of the eFuse cell itself. In this process, since the overdrive voltages of the fifth switch M5, the sixth switch M6, and the seventh switch M7 are typically only tens of millivolts, far less than the threshold voltage of conventional transistors which are hundreds of millivolts, the read amplifier circuit of this application can save the threshold voltage drop that would otherwise be wasted and convert it into an effective voltage margin for the eFuse cell. This reallocation of microscopic parameters allows the macroscopic circuit to maintain sufficient voltage headroom to significantly increase the operating current of branches even at extremely low supply voltages. The injection of large current directly overwhelms the subthreshold leakage current generated by the unselected bit lines, improving the signal-to-noise ratio degradation problem in low-voltage, high-capacity array scenarios and enhancing the reliability of high-precision status readings.

[0029] Furthermore, the read amplification circuit of this application uses PMOS transistors in the current source unit 110 and injects current into the first output terminal A and the second output terminal B during the preparation phase, causing the potentials of these two nodes to be strongly pulled up to near the voltage of the second power supply 102. When the voltages provided by the first power supply and the second power supply are close to or the same, the voltage difference between the gate and source of the first PMOS transistor M1 and the second PMOS transistor M2, which are both PMOS transistors, is small or close to zero, much smaller than their turn-on threshold. Therefore, the first PMOS transistor M1 and the second PMOS transistor M2 are naturally and physically forced into a deep cutoff state during the preparation phase. This design isolates the current source injection process from the activation process of the latch 100, reduces the discrimination error sources introduced thereby, and improves the purity of the potentials of the first output terminal A and the second output terminal B and the sampling accuracy.

[0030] In one embodiment of the readout amplifier circuit of the present invention, the first power supply 101 and the second power supply 102 are the same power supply. In other embodiments, the first power supply 101 and the second power supply 102 may be different power supplies.

[0031] In this embodiment, the current source unit 110 is controlled by a single clock signal. During the preparation phase, this single clock signal controls the seventh switch M7 to turn on, establishing an initial current difference. During the comparison phase, the current source is instantly cut off by switching the level of this single clock signal. At this time, the voltages of the first output terminal A and the second output terminal B, deprived of current source replenishment, begin to decrease as the branch discharges. When the potentials of the nodes on both sides form a difference due to the branch resistance difference, and the potential of one node decreases, the gate voltage of the PMOS transistor on that side decreases. When the absolute value of its gate-source voltage exceeds the absolute value of the threshold voltage, the cross-coupled transistors naturally turn on, thereby instantly activating the positive feedback mechanism. This single-clock combined with potential-triggered soft-start logic eliminates the need for complex multi-phase clock control, reduces the risk of timing errors caused by clock skew and clock overlap, and improves the timing fault tolerance and system stability under high-speed read conditions.

[0032] Furthermore, in this embodiment, the seventh switch M7 serves as the overall current source, with its drain acting as a current shunt point. It is simultaneously connected to the sources of both the fifth switch M5 and the sixth switch M6, forming a symmetrical current distribution network. This symmetrical topology, with one source and two shunts, ensures that, in the initial state, the current references injected into the reference branch 300 and the bit line branch are completely from the same source, minimizing common-mode interference caused by process variations in different current source devices. Simultaneously, the series connection of the fifth switch M5 and the sixth switch M6 adds a level of physical isolation between the seventh switch M7 and the sensitive sampling node (first output terminal A or second output terminal B). The gates of the fifth switch M5, the sixth switch M6, and the seventh switch M7 are connected to the same clock signal and are synchronously turned off during the comparison phase. At this time, the source nodes of M5 and M6 (i.e., the drain nodes of M7) are in a high-impedance floating state due to the lack of a discharge path. The high-impedance state of M5 and M6 cuts off the DC path between the power supply and the sampling node, which can effectively block the noise feedthrough and charge injection effect of the power supply, ensuring that the small differential voltage signals established on the first output terminal A and the second output terminal B are not destroyed, thus laying a solid hardware foundation for the high-precision discrimination of the subsequent latch 100.

[0033] Furthermore, in this embodiment, the latch 100 utilizes the gate-drain cross-interconnection of the first PMOS transistor M1 and the second PMOS transistor M2 to construct a closed-loop positive feedback system with extremely positive gain in the circuit. When the circuit enters the comparison phase, a small voltage difference begins to form between the first output terminal A and the second output terminal B due to the difference in branch resistance. This small voltage difference directly acts on the gates of the first PMOS transistor M1 and the second PMOS transistor M2, causing a difference in their conduction levels. On the side with weaker conduction (corresponding to faster node discharge and lower potential), the gate of its PMOS transistor receives a lower potential from the opposite node, increasing the absolute value of the gate-source voltage and enhancing its conduction level. After the PMOS transistor's conduction level is enhanced, more current is injected into the corresponding node, pulling the node potential up to the power supply voltage. This increased node potential, in turn, increases the gate voltage of the other PMOS transistor, decreasing the absolute value of the gate-source voltage, thereby further turning off the other PMOS transistor.

[0034] Taking the example where the potential of the first output terminal A is lower than that of the second output terminal B: the low potential of the first output terminal A directly affects the gate of the second PMOS transistor M2, increasing the absolute value of the gate-source voltage of the second PMOS transistor M2 and enhancing its conduction. After the enhanced conduction of the second PMOS transistor M2, more current is injected into the second output terminal B, pulling up its potential. The increased potential of the second output terminal B, in turn, affects the gate of the first PMOS transistor M1, decreasing the absolute value of its gate-source voltage and deepening its turn-off. After the first PMOS transistor M1 turns off, the first output terminal A loses its pull-up current, and its potential drops further, further reducing the gate voltage of the second PMOS transistor M2, forming a positive feedback loop. Once this positive feedback process is triggered, it rapidly amplifies the originally small differential signal and locks it to a full-swing digital logic level within a very short time, improving the voltage gain and response speed of the sensitive amplifier and effectively reducing the probability of metastability.

[0035] In one embodiment of the read amplifier circuit of the present invention, the current source unit 110 is turned on when the clock signal is low and turned off when the clock signal is high. The single clock signal is simultaneously connected to the gates of the seventh switch M7, the fifth switch M5, and the sixth switch M6. When the clock signal is low, the gate-source voltage of the seventh switch M7 is the difference between the low level and the power supply voltage, and its absolute value is greater than the absolute value of the threshold voltage, so the seventh switch M7 is turned on. At the same time, the gate-source voltages of the fifth switch M5 and the sixth switch M6 are also the difference between the low level and their respective source potentials, and their absolute values ​​are greater than the absolute value of the threshold voltage, so the fifth switch M5 and the sixth switch M6 are turned on, and the current source unit 110 provides current to the reference branch 300 and the bit line branch. When the clock signal is high, the gate-source voltages of the seventh switch M7, the fifth switch M5, and the sixth switch M6 all approach zero, so the seventh switch M7, the fifth switch M5, and the sixth switch M6 are turned off synchronously, and the current source unit 110 stops providing current to the reference branch 300 and the bit line branch.

[0036] This application clarifies the correspondence between the clock signal level and the state of the current source unit 110, optimizing the timing control of the circuit. Specifically, when the clock signal is low, the current source unit 110 is turned on, ensuring that the second power supply 102 can stably provide voltage during the preparation phase and forming a precise initial voltage difference between the first output terminal A and the second output terminal B, effectively avoiding interference from leakage current on circuit stability. When the clock signal turns high, the current source unit 110 is turned off, cutting off the power supply, allowing the parasitic capacitances of the first output terminal A and the second output terminal B to reliably maintain the initial voltage difference and trigger the positive feedback mechanism of the latch 100, thereby outputting an accurate logic level during the comparison phase. This precise timing control significantly improves the accuracy and anti-interference capability of the eFuse memory array 200 read amplifier circuit, especially in low power supply voltage and large-scale array applications, effectively preventing misjudgments and ensuring accurate reading of the eFuse fuse state.

[0037] In one embodiment of the read amplifier circuit of the present invention, if the clock signal is low, the first PMOS transistor M1 and the second PMOS transistor M2 are in the off state, and the voltage is provided by the second power supply 102, forming an initial voltage difference between the first output terminal A and the second output terminal B. During the preparation stage when the clock signal is low, the first PMOS transistor M1 and the second PMOS transistor M2 in the latch 100 are reliably in the off state. This effectively avoids leakage current and interference that may be introduced during the initial setup process, ensuring that the first output terminal A and the second output terminal B can establish a pure and accurate initial voltage difference determined by the current difference between the branch to be read and the reference branch 300 under the stable power supply of the second power supply 102. This precise initial voltage difference provides a stable and accurate starting condition for the subsequent positive feedback comparison of the latch 100, significantly improving the accuracy and stability of the eFuse memory array 200 read under low power supply voltage, thereby effectively suppressing the misjudgment problem caused by leakage current and ensuring the reliability of the circuit under harsh operating conditions.

[0038] In one embodiment of the read amplifier circuit of the present invention, if the clock signal turns high, the read amplifier circuit enters the comparison stage from the preparation stage. The parasitic capacitances of the first output terminal A and the second output terminal B maintain the initial voltage difference, that is, the parasitic capacitances of the first output terminal A and the second output terminal B slow down the rate of node potential change, so that the initial voltage difference formed by the difference in resistance between the two branches in the preparation stage can be maintained before the positive feedback of the latch is triggered, thereby avoiding the initial voltage difference from rapidly decaying or drifting due to leakage current or environmental noise after the external power supply is disconnected. This ensures that the latch 100 can receive an accurate and stable differential input before amplification begins. Subsequently, the positive feedback mechanism of the latch unit is reliably triggered, rapidly amplifying the small voltage difference to a stable logic level. This allows the fuse-broken state of the eFuse to be read accurately and reliably, effectively solving the misjudgment problem caused by the initial voltage difference drift, and significantly improving the robustness and accuracy of the read amplifier circuit in low power supply voltage, large-scale eFuse arrays, and environments with leakage current interference. The entire process requires no additional components, simplifying circuit design and improving reliability in low voltage environments.

[0039] In one embodiment of the read amplifier circuit of the present invention, the read amplifier circuit further includes an output buffer unit 400, which is connected to the first output terminal A and the second output terminal B, and is used to output complementary logic signals. By introducing the output buffer unit 400 and connecting it to the first output terminal A and the second output terminal B to output complementary logic signals, this application effectively solves the problem that the voltage signals output by the latch 100 at the first output terminal A and the second output terminal B may be unstable or non-standard digital signals. After the latch 100 completes the latching operation and establishes a stable logic level difference between the first output terminal A and the second output terminal B, the output buffer unit 400 can receive and process these signals. The output buffer unit 400, with its signal shaping and driving capabilities, converts the differential voltage signal from the latch 100 into a standard complementary logic signal with sufficient driving capability. This conversion process not only stabilizes the level of the output signal, making it conform to the input specifications of subsequent digital circuits, but also enhances the signal's anti-interference capability and transmission reliability by providing complementary outputs.

[0040] In one embodiment of the readout amplifier circuit of the present invention, the output buffer unit 400 includes two inverters 401, respectively connected to the first output terminal A and the second output terminal B, and shaping the voltages of the first output terminal A and the second output terminal B into standard digital complementary signals. As a basic digital logic gate circuit, the inverter 401's core function is to invert the logic level of the input signal, that is, to convert a high-level input to a low-level output, and vice versa. Besides the basic logic inversion function, the inverter 401 also plays a crucial role in signal buffering, enhancing drive capability, and shaping the signal. In practical implementation, inverters can employ various technologies. For example, they can be constructed using complementary metal-oxide-semiconductor (CMOS) technology, consisting of a PMOS transistor and an NMOS transistor connected in series. This structure is widely used due to its low power consumption, high noise margin, and excellent switching characteristics. Alternatively, they can be implemented using transistor-transistor logic (TTL) technology, using a combination of multiple bipolar transistors to complete the inversion function, typically used in scenarios requiring a large drive current.

[0041] In one embodiment of the readout amplifier circuit of the present invention, the reference branch 300 includes a precision reference resistor R. ref With the third NMOS transistor M8, and the precision reference resistor R ref One end is connected to the source of the second NMOS transistor M4, and the precision reference resistor R ref The other end is connected to the drain of the third NMOS transistor M8, and the source of the third NMOS transistor M8 is grounded. This precision reference resistor R... ref It is a resistor element with high precision and good stability, whose resistance remains relatively constant under different temperature and voltage conditions. Precision reference resistor R refProviding accurate and stable resistance values ​​ensures the accuracy of the reference current or voltage, effectively avoiding misjudgments caused by resistance deviations. Simultaneously, the third NMOS transistor M8, as a control element, has its source directly grounded, forming a low-impedance grounding path, which effectively suppresses the accumulation of leakage current in the reference branch 300 and reduces voltage drift. The gate control method of the third NMOS transistor M8 can refer to existing control methods. In one embodiment, the gate of the third NMOS transistor M8 is connected to the reference voltage V. ref Furthermore, the switching of the third NMOS transistor M8 is controlled by two sets of timing mechanisms: precharge / equalization and latch enable. It is cut off during precharge, turned on during read amplification, and held during latching. Utilizing the switching characteristics of the third NMOS transistor M8, current flow can be optimized, enhancing current control capabilities at low voltages. Overall, these features collectively improve the noise immunity of the reference branch 300, ensuring stable reference values ​​in low supply voltages and large-scale arrays, thereby significantly improving the accuracy and reliability of the eFuse memory array 200 read amplification circuit.

[0042] In one embodiment of the read amplifier circuit of the present invention, each branch to be read includes an eFuse fuse and a fourth NMOS transistor. One end of the eFuse fuse is connected to the source of the first NMOS transistor M3, and the other end of the eFuse fuse is connected to the drain of the fourth NMOS transistor M9. The source of the fourth NMOS transistor is grounded. The gates of all the fourth NMOS transistors M9 in the eFuse memory array 200 are controlled by the word line WL (row decoding output). When WL is high (≥Vth), it is turned on. The selected row is turned on during reading to establish a read current path, and the unselected row remains off to suppress leakage current.

[0043] Please see Figure 1 During the differential current signal establishment period, the clock signal clk is low, and the seventh switch M7 is turned on. Its current flows through the fifth switch M5 and the sixth switch M6 to the first NMOS transistor M3 and the second NMOS transistor M4, respectively. If the eFuse of the selected branch is not blown, that is, the resistance R of the branch to be read... fuse Less than the reference resistance R ref If the current flowing through the first NMOS transistor M3 is greater than that through the second NMOS transistor M4, then the current flowing through the second NMOS transistor M4 will be greater; conversely, if the eFuse has blown, the resistance R of the branch to be read will be less than that of the first NMOS transistor M4. fuse Greater than R refThe current of the first NMOS transistor M3 is less than that of the second NMOS transistor M4. At this time, the voltage between the first output terminal A and the second output terminal B is approximately the voltage of the second power supply 102 minus twice the overdrive voltage (i.e., the sum of the overdrive voltages of M7 and M5, or the sum of the overdrive voltages of M7 and M6). This value is very close to the voltage of the second power supply 102, which means that the first PMOS transistor M1 and the second PMOS transistor M2 are in the off state, and all the current in the circuit is provided by the seventh switch transistor M7. It should be noted that the markings of the first power supply and the second power supply in this invention are only used for distinction. The first power supply and the second power supply can be the same power supply or different power supplies. In this embodiment, the first power supply and the second power supply are independent of each other, but provide the same power supply voltage.

[0044] When the clock signal clk switches to a high level, the current source unit composed of the fifth switch M5, the sixth switch M6, and the seventh switch M7 turns off, and the circuit enters the comparison phase. Because the latch structure composed of the first PMOS transistor M1, the second PMOS transistor M2, the first NMOS transistor M3, and the second NMOS transistor M4 is symmetrical, and in the early stages of the comparison phase, the parasitic capacitances on the first output terminal A and the second output terminal B maintain the node potential, ensuring that the gate-source voltages of the first NMOS transistor M3 and the second NMOS transistor M4 maintain the relationship established in the preparation phase. This maintains the magnitude relationship of the currents in the two branches, so a voltage difference gradually builds up between the first output terminal A and the second output terminal B. Simultaneously, the outflow of current causes the voltages at the first output terminal A and the second output terminal B to continuously decrease, thereby turning on the first PMOS transistor M1 and the second PMOS transistor M2. As the voltage difference continues to increase, the positive feedback mechanism of the latch 100 is activated, ultimately outputting stable logic levels at the first output terminal A and the second output terminal B.

[0045] Please see Figure 2 A second aspect of the present invention is to provide a system-on-a-chip (SoC) 10, which includes a non-volatile memory 20. The non-volatile memory 20 includes an eFuse memory array 22, a read amplifier circuit 23, and a decoder 21. The read amplifier circuit 23 can be the read amplifier circuit of any of the above embodiments. For example, the read amplifier circuit 23 can be used to read configuration information, security keys, or identity identifiers of the eFuse memory array 22.

[0046] Specifically, in one embodiment, the read amplifier circuit 23 is used to read the configuration and calibration of the system chip 10. Its function is to store configuration information, such as CPU / GPU frequency and voltage parameters, by melting specific eFuses after the system chip 10 has undergone factory testing, or to activate redundant units to replace manufacturing defective parts. In specific usage, each time the chip is powered on, the read amplifier circuit automatically reads these eFuse arrays and loads the configuration information into the corresponding modules, realizing personalized customization of the chip and improving yield.

[0047] In another embodiment, the read amplifier circuit is used to read the security key and ID storage by permanently burning the encryption key or unique chip identity (ID) into the eFuse. Specifically, when the system needs to perform authentication or data encryption / decryption, the read amplifier circuit is triggered to read the stored key or ID. Due to its low-voltage operating characteristics, it effectively reduces the risk of side-channel attacks (such as power consumption analysis) during the reading process.

[0048] In another embodiment, the read amplification circuit is used to read low-power IoT devices, enabling stable reading of the chip's configuration status even at extremely low supply voltages (e.g., battery-powered devices). Specifically, it is integrated into various low-power microcontrollers and system-on-a-chip 10 to ensure that the device can reliably read startup code and configuration data across the entire battery voltage operating range, without misreading due to voltage fluctuations.

[0049] The system-on-a-chip provided in this application integrates the aforementioned high-precision read amplifier circuit with an independent current source injection architecture at the system architecture level. This architecture breaks the dependence of circuits on high power supply voltage in related technologies, enabling the memory to maintain strong read current and extremely high signal-to-noise ratio even at extremely low near-threshold voltages.

[0050] As described above, in the read amplifier circuit of this invention, the introduction of a current source unit significantly increases the branch current, thereby effectively suppressing the interference of subthreshold leakage current on the latch output. This design not only improves the circuit's noise immunity but also, by increasing voltage margin, enables the circuit to operate stably under low power supply voltage, achieving simultaneous enhancement of performance and reliability. Compared to the traditional inherent structure, this circuit optimizes the voltage drop path from the power supply to the eFuse resistor, reducing the voltage drop from the power supply to the eFuse resistor during differential current signal establishment (the reduction is approximately the difference between the threshold voltage and the overdrive voltage). Thanks to this, the minimum power supply voltage required for stable reading can be effectively extended towards lower voltages, thus giving this design a better low-voltage tolerance margin compared to traditional structures.

[0051] To verify the effectiveness of the above mechanism under actual process fluctuations, this study simulated the readout function of the circuit under low-voltage conditions using the Monte Carlo method. The simulation conditions covered the worst-case combination of power supply voltage fluctuations (±10%), temperature range (-40°C to 125°C), and global process variation (3σ) to ensure coverage of all extreme edge cases in mass production scenarios. Simulation results show that under all the above extreme combinations, the circuit in this study did not experience any readout failure events; while the conventional structure in comparison exhibited varying degrees of probabilistic failure under the same constraints. Based on the quantitative evaluation of this statistical data, the effective lower limit of the circuit in this study shows a significant statistical shift compared to the control circuit. This result fully demonstrates the stability advantage of this design in the near-threshold and subthreshold regions, and its strong robustness to process, voltage, and temperature (PVT) fluctuations.

[0052] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability. The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A read amplification circuit for an eFuse memory array, the eFuse memory array comprising multiple eFuse read branches arranged in parallel, characterized in that, The readout amplifier circuit includes: A latch, powered by a first power supply, includes two cross-coupled inverter branches: a first inverter branch and a second inverter branch; the outputs of the first inverter branch and the second inverter branch serve as the two output terminals of the latch; wherein, the first inverter branch is connected in series with the eFuse memory array. A reference branch, wherein the reference branch is connected in series with the second anti-phase branch; A current source unit is disposed between the two output terminals of the latch and powered by a second power supply. The current source includes at least three switching transistors: a fifth switching transistor, a sixth switching transistor, and a seventh switching transistor. One end of the seventh switching transistor is connected to the second power supply. The fifth and sixth switching transistors are symmetrically disposed between the two output terminals relative to the seventh switching transistor. The fifth, sixth, and seventh switching transistors are controlled by the same clock signal. During the read preparation phase, the current source unit is turned on by the clock signal, and the current in the reference branch and the branch to be read in the eFuse array is provided by the current source unit. During the reading phase, the current source unit is turned off by the clock signal, the positive feedback mechanism of the latch is activated, and logic levels are output at the two output terminals.

2. The readout amplifier circuit according to claim 1, characterized in that, The first power supply and the second power supply are the same power supply.

3. The readout amplifier circuit according to claim 1, characterized in that, The fifth, sixth, and seventh switching transistors are PMOS transistors; the current source unit operates when the clock signal is low and is turned off when the clock signal is high.

4. The readout amplifier circuit according to claim 3, characterized in that, If the clock signal goes high, the parasitic capacitance between the two output terminals maintains the initial voltage difference between the two output terminals and triggers positive feedback of the latch, outputting logic levels at the two output terminals.

5. The readout amplifier circuit according to claim 1, characterized in that, The readout amplifier circuit also includes an output buffer unit, which is connected to the two output terminals and is used to output complementary logic signals.

6. The readout amplifier circuit according to claim 5, characterized in that, The output buffer unit includes two inverters, which are respectively connected to the two output terminals and shape the voltages of the two output terminals into standard digital complementary signals.

7. The readout amplifier circuit according to claim 1, characterized in that, The reference branch includes a precision reference resistor and an NMOS transistor. One end of the precision reference resistor is connected in series with the second inverting branch, and the other end of the precision reference resistor is connected to one end of the NMOS transistor. The other end of the NMOS transistor is grounded.

8. The readout amplifier circuit according to claim 1, characterized in that, Each of the branches to be read includes an eFuse fuse and an NMOS transistor. One end of the eFuse fuse is connected to the input terminal of the first inverting branch, and the other end of the fuse is connected to one end of the NMOS transistor, with the other end of the NMOS transistor grounded.

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