Control method, system, circuit and device for reducing lpddr power consumption and storage medium

Abstract

The application provides a control method, system, circuit, device and storage medium for reducing LPDDR power consumption. The method comprises the following steps: acquiring a current write command type, a DBI enabling state and a DM enabling state; when the current write command type is a WR command, the DBI enabling state is disabled and the DM enabling state is enabled, or when the DBI enabling state and the DM enabling state are both disabled, determining that a DMI signal is an invalid signal and generating a DMI receiver shutdown enabling signal; and controlling the DMI receiver to enter a low-power shutdown state according to the DMI receiver shutdown enabling signal. The application identifies the invalid signal on the DMI interface, and shuts down the DMI receiver from the physical layer when the invalid signal is determined, so as to reduce the power consumption of the chip during the invalid operation process and realize the low-power operation of the chip.

Description

Technical Field

[0001] This application belongs to the field of dynamic random access memory technology, and particularly relates to a control method, system, circuit, device and storage medium for reducing LPDDR power consumption. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that uses capacitors to store electrical charge to store data. Low Power Double Data Rate Dynamic Random Access Memory (LPDDR) is a low-power DRAM primarily used in mobile devices such as smartphones and tablets. Its characteristics include low power consumption and small size. Therefore, reducing the power consumption of LPDDR is crucial for extending the battery life of mobile devices.

[0003] The LPDDR design specification requires the chip to have a DMI interface for inputting DMI signals. The DMI signal serves two purposes: first, it's used for data masking (DM), where the chip removes unwanted data based on the mask information on the DMI; second, it's used for data bus inversion (DBI), where the chip inverts the data according to the information on the DMI and writes it internally. The DMI signal is input to the chip interface simultaneously with the data signal.

[0004] According to the LPDDR design specifications, there are two types of input for write commands: the Write command (WR command) and the Mask Write command (MWR command). When a WR command is sent, the information on the DMI can only be used for DBI functions; while when a MWR command is sent, the information on the DMI can be used for both DBI and DM functions. The chip can configure the DBI and DM signals to allow the MWR / WR commands to identify whether the signals on the DMI are specifically used for DBI or DM functions.

[0005] However, in some operating scenarios, signals on the DMI are invalid for the current command. For example, when the chip only issues a DM signal and sends a WR command, any signals on the DMI are meaningless for the WR command—because according to the LPDDR specification, when sending a WR command, the information on the DMI can only be used for the DBI function, not the DM function. But in this scenario, the chip will still receive and process the invalid signals on the DMI normally, causing unnecessary dynamic power consumption in the DMI receiver and increasing the overall power consumption of the chip.

[0006] Therefore, how to identify and filter invalid signals on the DMI interface to reduce the power consumption of the chip under specific operating conditions, thereby achieving the low-power design goal of LPDDR, is a technical problem that urgently needs to be solved in this field.

[0007] The foregoing statements are for informational purposes only and are not intended to provide background information in connection with this application. Unless otherwise stated herein, the content described in this section is not prior art to the rest of this application. Summary of the Invention

[0008] This invention proposes a control method, system, circuit, device, and storage medium for reducing LPDDR power consumption. By identifying invalid signals on the DMI interface and physically shutting down the DMI receiver when invalidity is determined, the power consumption of the chip during invalid operation is reduced, thereby achieving low-power operation of the chip.

[0009] According to a first aspect of the embodiments of this application, a control method for reducing LPDDR power consumption is provided, comprising:

[0010] Get the current write command type, DBI enable status, and DM enable status; When the current write command type is WR command, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, the DMI signal is determined to be an invalid signal and a DMI receiver shutdown enable signal is generated. The DMI receiver is controlled to enter a low-power shutdown state based on the DMI receiver shutdown enable signal.

[0011] In some embodiments of this application, determining that the DMI signal is an invalid signal and generating a DMI receiver shutdown enable signal further includes: Statistical analysis of the duration of invalid DMI signals within a preset time window; The shutdown benefit value ΔP is calculated based on the duration of the ineffective shutdown operation. The formula for calculating the shutdown benefit value ΔP is as follows: ; in, P active This refers to the power consumption of the DMI receiver during normal operation. P off This represents the residual leakage power consumption after the DMI receiver is turned off. T invalid This represents the total duration of the DMI signal being in an invalid state. P wake_up This refers to the surge power consumption of the DMI receiver from shutdown to restart. T wake_upRecovery time required to restart the DMI receiver. P transition This refers to the short-circuit power consumption caused by level switching. T trans This refers to the level switching time; When the turn-off benefit value ΔP is greater than zero, a DMI receiver turn-off enable signal is generated.

[0012] In some embodiments of this application, before determining that the DMI signal is an invalid signal, the method further includes: The stable duration of the WR command, DBI enabled state, and DM enabled state is timed; When the stable duration reaches the preset first time threshold, the process is then performed to determine whether the DMI signal is invalid.

[0013] In some embodiments of this application, generating a DMI receiver turn-off enable signal includes: The percentage of invalid DMI signals within a predetermined time window is statistically analyzed. When the percentage exceeds the first preset threshold, the DMI receiver is controlled to enter a deep shutdown state. When the percentage is less than or equal to the first preset threshold and greater than the second preset threshold, the DMI receiver is controlled to enter the weak bias hold state. When the percentage is less than or equal to the second preset threshold, the DMI receiver is kept on.

[0014] In some embodiments of this application, before controlling the DMI receiver to enter a low-power shutdown state, the method further includes: Obtain the junction temperature parameters of the current chip; The temperature compensation factor is determined based on the junction temperature parameters. The first and second preset thresholds are corrected based on the temperature compensation factor.

[0015] According to a second aspect of the embodiments of this application, a control system for reducing LPDDR power consumption is provided, comprising: The command parsing module is used to obtain the type of the current write command; The status detection module is used to obtain the DBI enable status and DM enable status; The enable signal generation module is used to determine that the DMI signal is invalid and generate a DMI receiver shutdown enable signal when the current write command type is WR command, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled. The DMI receiver is used to control the DMI receiver to enter a low-power shutdown state based on the DMI receiver shutdown enable signal.

[0016] In some embodiments of this application, the enable signal generation module includes: The power consumption evaluation unit is used to determine the invalid duration of the DMI signal within a preset time window when the DMI signal is invalid; and to calculate the shutdown benefit value of this shutdown operation based on the invalid duration; when the shutdown benefit value is greater than zero, a DMI receiver shutdown enable signal is generated.

[0017] According to a third aspect of the embodiments of this application, a control circuit for reducing LPDDR power consumption is provided, the circuit comprising: The WR command input terminal is used to receive WR command signals; The MWR command input terminal is used to receive MWR command signals. The DBI enable input is used to receive the DBI enable signal. The DM enable input is used to receive the DM enable signal. Enable signal output terminal is used to output the DMI receiver shutdown enable signal; The logic gate combination unit includes a first OR gate, a first AND gate, a second AND gate, and a second OR gate; The input of the first OR gate is connected to the DBI enable input and the DM enable input, and the output of the first OR gate outputs the first signal. The input of the first AND gate is connected to the DBI enable input and the WR command input, and the output of the first AND gate is the third signal; The input of the second AND gate is connected to the MWR command input and the first signal, and the output of the second AND gate outputs the second signal. The input of the second OR gate is connected to the second signal and the third signal, and the output of the second OR gate is used as the enable signal output. When the WR command signal is valid, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, the DMI signal is determined to be invalid. The logic gate combination unit outputs the DMI receiver shutdown enable signal, which is used to indicate that the DMI receiver enters the low-power shutdown state.

[0018] According to a fourth aspect of the embodiments of this application, a control device for reducing LPDDR power consumption is provided, comprising: DMI receiver, used to receive DMI signals and DMI receiver turn-off enable signals; The logic control circuit, connected to the DMI receiver, is used to execute the above control method and output a DMI receiver turn-off enable signal to the DMI receiver to control the DMI receiver to enter a low-power turn-off state.

[0019] According to a fifth aspect of the present application, a computer-readable storage medium is provided having a computer program stored thereon; the computer program is executed by a processor to implement a control method for reducing LPDDR power consumption.

[0020] This application discloses a control method, system, circuit, device, and storage medium for reducing LPDDR power consumption. The method includes acquiring the current write command type, DBI enable state, and DM enable state; when the current write command type is a WR command, the DBI enable state is disabled, and the DM enable state is enabled, or when both the DBI and DM enable states are disabled, the DMI signal is determined to be invalid, and a DMI receiver shutdown enable signal is generated; based on the DMI receiver shutdown enable signal, the DMI receiver is controlled to enter a low-power shutdown state. This application reduces chip power consumption during invalid operations by identifying invalid signals on the DMI interface and physically shutting down the DMI receiver when invalidity is determined, thereby achieving low-power operation of the chip.

[0021] Compared with the prior art, the present invention has the following advantages: (1) It can accurately identify invalid DMI signals under specific operating conditions of LPDDR and avoid accidentally turning off valid signals; (2) It reduces power consumption by turning off the physical layer (cutting off the bias current or disconnecting the power supply), which is significantly better than signal shielding at the logic layer; (3) By introducing a turn-off benefit calculation mechanism, it ensures that the system performance is not affected while reducing power consumption; (4) It is implemented by pure combinational logic circuits, which has fast response speed, small area overhead and is easy to integrate. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 The diagram illustrates the steps of a control method for reducing LPDDR power consumption according to an embodiment of this application. Figure 2 The diagram illustrates the steps for determining an invalid signal according to an embodiment of this application. Figure 3 The diagram illustrates the steps of generating a DMI receiver shutdown enable signal according to an embodiment of this application. Figure 4 A simplified structural diagram of a DMI receiver according to an embodiment of this application is shown in the figure; Figure 5 This is a waveform diagram of the DMI receiver when the shutdown enable signal is high, provided in an embodiment of the present invention. Figure 6This is a waveform diagram of the DMI receiver when the power-off enable signal is low, provided in an embodiment of the present invention. Figure 7 A schematic diagram of a control circuit for reducing LPDDR power consumption according to an embodiment of this application is shown; Figure 8 The waveform diagram shown is displayed when the DBI function is not enabled and the DM function is enabled under the WR command. Figure 9 The waveform diagrams under the WR command are shown when the DBI function is enabled and the DM function is not enabled. Figure 10 The waveform diagram under the MWR command is shown when the DBI function is not started and the DM function is started. Figure 11 The waveform diagram under the MWR command is shown when the DBI function is not started and the DM function is not started. Figure 12 The diagram shows a schematic representation of a control system for reducing LPDDR power consumption according to an embodiment of this application. Figure 13 The diagram shows a step-by-step schematic of a control device for reducing LPDDR power consumption according to an embodiment of this application; Figure 14 The diagram shows a schematic representation of an electronic device according to an embodiment of this application. Detailed Implementation

[0023] This application aims to identify and filter invalid signals on the DMI interface, thereby reducing the chip's power consumption under specific operating conditions and achieving the low-power design goal of LPDDR. While various DRAM power management schemes exist in the prior art, none have solved the aforementioned technical problem.

[0024] For example, some solutions reduce wake-up latency by waking up DRAM RANK in advance when DRAM read / write commands are detected, but these solutions do not involve signal reception control of the DMI interface; some solutions reduce CPU load by replacing CPU storage / recovery register configuration parameters with hardware control units, but these solutions do not involve DMI signal validity judgment and receiver shutdown control; some solutions improve bus utilization by optimizing the scheduling order of DDR read / write commands through multi-level arbitration, but do not involve power management at the signal receiver; and some solutions convert XDR command format to DDR command format using a conversion chip and discard some XDR column commands at the protocol layer, but these solutions only perform logical discarding at the command decoding layer and do not involve shutdown control at the receiver physical layer.

[0025] The present application discloses a control method, system, circuit, device, and storage medium for reducing LPDDR power consumption. The method includes obtaining the current write command type and the DBI enable state and DM enable state; when the current write command type is a WR command, the DBI enable state is disabled, and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, determining that the DMI signal is an invalid signal and generating a DMI receiver shutdown enable signal; and controlling the DMI receiver to enter a low-power shutdown state according to the DMI receiver shutdown enable signal.

[0026] This application identifies the characteristic of an invalid DMI signal in an LPDDR chip under specific operating conditions (WR command, DBI disabled, and DM enabled). Upon determining invalidity, it physically shuts down the analog front-end circuitry of the DMI receiver, thereby blocking the input and processing of invalid signals at the signal reception source and avoiding unnecessary power consumption by the DMI receiver during periods of invalid signals. Compared with existing technologies, this invention has at least the following advantages: First, by introducing a quantitative calculation formula for the shutdown benefit value, the net power consumption benefit brought by shutting down the DMI receiver can be accurately assessed, and the decision on whether to perform the shutdown operation can be made based on the judgment condition △P>0, avoiding the power consumption inversion problem caused by frequent shutdown / wake-up, thus realizing refined and intelligent power consumption management.

[0027] Secondly, by introducing dynamic toggle rate detection and dynamic power consumption calculation formula for DMI signal, the shutdown judgment threshold can be adaptively adjusted according to the actual signal activity on the DMI signal line, making power management decisions more in line with actual operating conditions and further improving the effectiveness of power optimization.

[0028] Third, by introducing temperature compensation and hysteresis control mechanisms, different turn-off depths (deep turn-off or weak bias retention turn-off) can be adaptively selected according to the current junction temperature of the chip. This solves the problem of increased turn-off leakage current under high temperature environment and the additional power consumption caused by frequent receiver switching (ping-pong effect) under critical state, thus improving the engineering reliability and environmental adaptability of the solution.

[0029] Fourth, by implementing the combinational logic circuit at the gate level, setting up the clock synchronization latch and the anti-jitter delay unit, not only is a clear hardware implementation path provided, but also the problems of false shutdown caused by combinational logic glitches and signal instability during command transitions in high-speed signal transmission are solved, ensuring the timing reliability and signal integrity of the solution.

[0030] Fifth, for the MWR command scenario, this invention provides an independent shutdown scheme for DMI receiver sub-circuits at the byte level, which enables fine-grained control of partial shutdown and partial retention in mixed operating conditions where some bytes are masked and some bytes are not masked under the MWR command, further expanding the coverage of power consumption optimization scenarios.

[0031] Sixth, this invention differs fundamentally from existing technologies such as "discarding protocol layer commands," "command scheduling optimization," and "hardware storage of register parameters" in terms of inventive concept, technical problems, and implementation principles. It provides a novel solution for power management of LPDDR chips that starts from the physical receiver layer.

[0032] It should be noted that the 'low-power shutdown state' in this application does not refer to a single power-off state, but rather a set of states with multiple shutdown depths. In practical engineering applications, deep shutdown (complete power-off) or shallow shutdown (preserving bias) can be dynamically selected based on the chip junction temperature and predicted sleep duration to achieve optimal energy efficiency. Deep shutdown is only a preferred embodiment of the low-power shutdown state in this application and should not be considered as a limitation on the scope of protection of this application.

[0033] Quantitative modeling revealed that at high temperatures (e.g., 85°C), leakage power consumption increases exponentially. In this case, even if the duration of the invalid signal is short (R value is small), "deep shutdown" should be initiated immediately. However, at low temperatures (e.g., -40°C), leakage is extremely low. If the duration of the invalid signal is not long enough, it is preferable to maintain "shallow shutdown" or "no shutdown" because the power loss caused by wake-up may be greater than that caused by leakage.

[0034] This invention achieves the following significant effects by introducing junction temperature parameters as a decision variable for turn-off depth: 1. Resolved the nonlinear contradiction between high-temperature leakage and shutdown benefits: By using a temperature compensation coefficient to correct the hysteresis threshold, the DMI receiver can trigger deep shutdown with a lower proportion of invalid signals in high-temperature environments, effectively curbing the surge in power consumption caused by high-temperature leakage. 2. Avoids performance waste in low-temperature environments: In low-temperature environments, the shutdown trigger threshold is automatically raised to prevent the extra power consumption caused by frequent wake-ups from exceeding the power saving benefits, achieving the optimal energy efficiency ratio across the entire temperature range (-40℃~105℃). 3. Improved system environmental adaptability: Since LPDDR chips are widely used in smartphones, automotive electronics and outdoor equipment, this invention can dynamically adjust the control strategy based on real-time junction temperature, which significantly reduces the impact of ambient temperature changes on chip power consumption consistency.

[0035] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0036] Example 1 Figure 1 The diagram illustrates the steps of a control method for reducing LPDDR power consumption according to an embodiment of this application.

[0037] like Figure 1 As shown, a method for reducing LPDDR power consumption in this embodiment includes: S1: Get the current write command type, DBI enable status, and DM enable status; S2: When the current write command type is WR command, DBI enable state is disabled and DM enable state is enabled, or when both DBI enable state and DM enable state are disabled, the DMI signal is determined to be an invalid signal and a DMI receiver shutdown enable signal is generated. S3: Control the DMI receiver to enter the low-power shutdown state according to the DMI receiver shutdown enable signal.

[0038] In the preferred implementation process, before S2 determines that the DMI signal is invalid and generates the DMI receiver turn-off enable signal, it also includes: The stable duration of the WR command, DBI enabled state, and DM enabled state is timed; when the stable duration reaches the preset time threshold, the determination of whether the DMI signal is invalid is then performed.

[0039] This application considers shutting down the DMI receiver, which can reduce the receiver's operating power consumption. The main principle behind this power reduction is that after a conventional DMI receiver receives a signal, it outputs the signal. The output signal will consume power when it reaches other functional modules. If the DMI is shut down, the receiver will stabilize the DMI output signal at 1 or 0, which can ensure that the DMI signal can maintain the lowest power consumption in other functional modules.

[0040] Figure 2 The diagram illustrates the steps for determining an invalid signal according to an embodiment of this application.

[0041] like Figure 2 As shown, S2 determines that the DMI signal is invalid and generates a DMI receiver shutdown enable signal, including: S21: Statistically determine the duration of invalid DMI signals within a preset time window; S23: Calculate the shutdown benefit value ΔP for this shutdown operation based on the ineffective duration. The formula for calculating the shutdown benefit value ΔP is as follows: ; in, P active This refers to the power consumption of the DMI receiver during normal operation. P off This represents the residual leakage power consumption after the DMI receiver is turned off.T invalid This represents the total duration of the DMI signal being in an invalid state. P wake_up This refers to the surge power consumption of the DMI receiver from shutdown to restart. T wake_up Recovery time required to restart the DMI receiver. P transition This refers to the short-circuit power consumption caused by level switching. T trans This refers to the level switching time; S23: When the turn-off revenue value ΔP is greater than zero, generate the DMI receiver turn-off enable signal.

[0042] Figure 3 The diagram illustrates the steps of generating a DMI receiver turn-off enable signal according to an embodiment of this application.

[0043] like Figure 3 As shown, S2 generates a DMI receiver shutdown enable signal, including: S24: Statistically determine the percentage of invalid DMI signals within a predetermined time window; S25: When the percentage is greater than the first preset threshold, control the DMI receiver to enter the deep shutdown state; when the percentage is less than or equal to the first preset threshold and greater than the second preset threshold, control the DMI receiver to enter the weak bias hold state; when the percentage is less than or equal to the second preset threshold, control the DMI receiver to remain on.

[0044] Further optimization of the implementation also includes: obtaining the junction temperature parameters of the current chip; determining a temperature compensation factor based on the junction temperature parameters; wherein the temperature compensation factor increases as the junction temperature parameters increase; and correcting the first preset threshold and the second preset threshold based on the temperature compensation factor.

[0045] Other preferred implementations include: obtaining the process corner information of the current chip; and adaptively adjusting the time threshold used to determine the invalidity of the DMI signal based on the process corner information.

[0046] In the preferred implementation process, the following steps are also included: when the DBI enable state is detected to be enabled, or the current write command type is switched to MWR command, the DMI signal is determined to be restored to a valid signal; a DMI receiver enable signal is generated; and then, based on the DMI receiver enable signal, the DMI receiver is controlled to power on within a preset recovery time.

[0047] During the preferred implementation process, when the current write command type is an MWR command, it also includes: The DM mask status of the DMI sub-signal corresponding to each data byte is detected. When the DM mask status corresponding to the target byte is a full mask, that is, the DMI status is 1, the DMI receiver receives the signal with DMI 1. When the DM mask status corresponding to the target byte is not a full mask, the sub-DMI receiver corresponding to the target byte remains on.

[0048] Other preferred embodiments include: reading the command queue pre-stored in the LPDDR controller to obtain command information to be executed in a future predetermined period; when it is determined from the command information that there is a valid read / write operation for a non-current DRAM RANK in the future predetermined period, the step of shutting down the DMI receiver is prohibited.

[0049] Table 1 shows the truth table of the control logic of the control method for reducing LPDDR power consumption in the embodiments of this application.

[0050]

[0051] Table 1 Truth Table of Control Logic The "DMI off" option means that the DMI receiver enable signal is turned off, meaning that the DMI signal is meaningless at this time and can be turned off.

[0052] Figure 4 A simplified structural diagram of a DMI receiver according to an embodiment of this application is shown.

[0053] Figure 5 This is a waveform diagram of the DMI receiver when the shutdown enable signal is high, provided in an embodiment of the present invention. Figure 6 The waveform diagram of the DMI receiver when the turn-off enable signal is low is provided in the embodiment of the present invention.

[0054] like Figure 4 As shown, after the DMI signal is input to the DMI receiver, when the DMI receiver enable signal is high, it will output the DMI input signal to the DMI output port. The signal waveform is shown below. Figure 5 As shown; if the DMI receiver enable signal is low, the DMI input signal will not be output, and the signal waveform is shown in the figure. Figure 6 As shown.

[0055] Preferably, the analog front-end module includes a differential amplifier and a bias current source. The DMI differential signal is amplified by the differential amplifier and then output to the DMI output port. The operation of the differential amplifier depends on a stable bias current provided by the bias current source.

[0056] Preferably, the enable control switch is connected to the power supply terminal (VDD power supply line or ground terminal) of the bias current source. The control terminal of this enable control switch is connected to the DMI receiver enable control signal (EN signal). When the EN signal is high, the enable control switch is closed, the bias current source is powered, the differential amplifier operates normally, the DMI input signal is amplified and output to the DMI output port. When the EN signal is low, the enable control switch is open, the bias current source is cut off, the differential amplifier stops working, and the DMI receiver enters a low-power shutdown state.

[0057] like Figure 5 As shown, when the enable signal EN is high, the DMI input signal is transmitted normally to the DMI output. Figure 6 As shown, when the enable signal EN is low (i.e., during the off period), the output is the default 1 or 0 and does not respond to changes in the DMI input signal.

[0058] This application provides a detailed description of the control method for reducing LPDDR power consumption in its embodiments.

[0059] 1) First, obtain the current write command type, DBI enable status, and DM enable status.

[0060] The chip's internal command parsing unit decodes the received write command to identify whether it is a WR or MWR command. Simultaneously, it reads the relevant configuration bits of the chip's internal Mode Register (MR) to obtain status information indicating whether the DBI and DM functions are enabled.

[0061] 2) Then, when the current write command type is WR command, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled; the invalid duration of the DMI signal within the preset time window is statistically analyzed, and the shutdown benefit value of the DMI receiver corresponding to the DMI signal is calculated based on the invalid duration.

[0062] According to the LPDDR design specification, when a WR command is sent, the information on the DMI can only be used for the DBI function. Therefore, when DBI is disabled but DM is enabled, the DM signal carried on the DMI is completely invalid for the WR command. Under this condition, the power consumption evaluation process is initiated.

[0063] The timer inside the power consumption evaluation module counts the duration for which the DMI signal is in an invalid state within a preset time window (e.g., 1μs). T invalid An invalid state refers to a period in which DM information, rather than DBI information, is transmitted on the DMI signal.

[0064] Then, it is determined whether the shutdown benefit value meets the preset shutdown condition. If it does, a DMI receiver shutdown enable signal is generated; if it does not, the current state is maintained and monitoring continues.

[0065] Based on the determination result of the power consumption evaluation module, the enable signal generation module outputs a valid level (e.g., low level) DMI receiver shutdown enable signal.

[0066] 3) Finally, based on the DMI receiver turn-off enable signal, control the DMI receiver to enter the low-power turn-off state.

[0067] The enable control switch of the DMI receiver operates according to the shutdown enable signal, cutting off the bias current or power supply of the receiver's analog front-end circuit, so that the receiver enters a low-power shutdown state.

[0068] When a valid DBI signal is subsequently detected or the command type changes, the enable signal generation module outputs an invalid level (e.g., a high level) to control the DMI receiver to quickly wake up and return to normal operation.

[0069] To prevent the DMI receiver from frequently switching between valid and invalid signals, embodiments of this application introduce a hysteresis control mechanism.

[0070] The percentage R of invalid DMI signals within a predetermined time window (e.g., 1 microsecond) is statistically analyzed. invalid = T invalid / T total T invalid T is the total duration during which DMI signals are deemed invalid within the statistical window. total This represents the total duration of the statistics window.

[0071] Based on the proportion, the following three-state decision is executed: Deep shutdown state: when the proportion is greater than the first preset threshold η high When (e.g., 60%), control the DMI receiver to enter a deep shutdown state (complete power-off, including cutting off the bias current and disconnecting the power supply). Weak bias hold state: when the proportion is less than or equal to η high And greater than the second preset threshold η low When the current is 30% (e.g., 30%), the DMI receiver is controlled to enter a weak bias hold state (retaining a portion of the bias current to keep the receiver in a "standby" state, which can be restored to the working state in a short time). Forced on state: when the percentage is less than or equal to η low At this time, the DMI receiver is kept on (no shutdown operation is performed).

[0072] Where, ηhigh >η low η high and η low The specific value can be configured through the mode register.

[0073] By setting the hysteresis interval [η] high η low This design ensures that when the proportion of invalid signals fluctuates around a critical value, the DMI receiver will not frequently switch between on and off, thus avoiding the additional power consumption and timing uncertainties caused by frequent switching.

[0074] To ensure that shutting down the DMI receiver results in a positive power consumption benefit (i.e., the power saved by shutting down is greater than the additional power consumed by shutting down and restarting), this application introduces a shutdown benefit calculation model.

[0075] Before generating the DMI receiver shutdown signal, the logic control circuit or a processor connected to the logic control circuit (such as an LPDDR controller) calculates the shutdown benefit value ΔP for this shutdown operation.

[0076] The formula for calculating the turn-off revenue ΔP is: ; in, P active This refers to the power consumption of the DMI receiver during normal operation. P off This represents the residual leakage power consumption after the DMI receiver is turned off. T invalid This represents the total duration of the DMI signal being in an invalid state. P wake_up This refers to the surge power consumption of the DMI receiver from shutdown to restart. T wake_up Recovery time required to restart the DMI receiver. P transition This refers to the short-circuit power consumption caused by level switching. T trans This represents the level switching time.

[0077] When ΔP > 0, the logic control circuit executes the step of generating a DMI receiver shutdown signal. When ΔP ≤ 0, the DMI receiver is not shut down even if the current DMI signal is invalid, so as to keep the receiver in the on state.

[0078] By introducing the above-mentioned formula for calculating the shutdown benefit value, this application upgrades the shutdown decision of the DMI receiver from "qualitative judgment" to "quantitative decision", ensuring that every shutdown operation brings real power saving and avoiding the power management failure problem of "losing big gains for small gains".

[0079] Optionally, T can be dynamically predicted based on historical statistics and the current command queue depth. invalid The value of T. For example, when the command queue is empty or contains only WR commands and the invalid condition is met. invalid It can be predicted to be a large value; when there are consecutive read and write commands interleaved in the command queue, T invalid It can be predicted to be a small value.

[0080] When the DMI receiver is in the off state, continuously monitor changes in the current write command type, DBI enable state, and DM enable state.

[0081] The DMI signal is considered to have recovered to a valid signal when any of the following conditions are met: The current write command type is switched to MWR command (MWR=1); DBI enable state is switched to enabled (DBI_EN=1); The DM enable state is switched to disabled (DM_EN=0).

[0082] When the DMI signal is determined to be restored to a valid signal, the logic control circuit generates a DMI receiver enable signal (that is, the enable control signal EN is flipped to a high level) and sends the DMI receiver enable signal to the enable control terminal of the DMI receiver.

[0083] The DMI receiver powers on within a preset recovery time based on the DMI receiver activation signal, restoring it to normal operating status.

[0084] Optionally, the recovery time can be a fixed value (defined by the LPDDR datasheet) or a programmable value configured via the mode register. The recovery time value must be at least longer than the setup time of the analog front-end bias current source of the DMI receiver to ensure that the receiver is fully stable before a valid DMI signal arrives.

[0085] Figure 7 A schematic diagram of a control circuit for reducing LPDDR power consumption according to an embodiment of this application is shown.

[0086] like Figure 7 As shown, the circuit includes: a WR command input terminal for receiving the WR command signal; a MWR command input terminal for receiving the MWR command signal; a DBI enable input terminal for receiving the DBI enable signal; a DM enable input terminal for receiving the DM enable signal; and an enable signal output terminal for outputting the DMI receiver shutdown enable signal.

[0087] The logic gate combination unit includes a first OR gate H1, a first AND gate Y1, a second AND gate Y2, and a second OR gate H2; The input of the first OR gate H1 is connected to the DBI enable input and the DM enable input, and the output of the first OR gate H1 outputs the first signal. The input of the first AND gate Y1 is connected to the DBI enable input and the WR command input, and the output of the first AND gate Y1 is the third signal. The input of the second AND gate Y2 is connected to the MWR command input and the first signal, and the output of the second AND gate Y2 outputs the second signal; The input of the second OR gate H2 is connected to the second signal and the third signal, and the output of the second OR gate H2 is used as the enable signal output. When the WR command signal is valid, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, the DMI signal is determined to be invalid. The logic gate combination unit outputs the DMI receiver shutdown enable signal, which is used to indicate that the DMI receiver enters the low-power shutdown state.

[0088] Please see Figures 8 to 11 , Figures 8 to 11 The waveforms of the DMI receiver enable control signal are shown in different operating modes.

[0089] Figure 8 The diagram shows the waveform under the WR command when the DBI function is not enabled and the DM function is enabled. As can be seen from the diagram, during the period when the WR command is active, since DBI is not enabled and DM is enabled, the DMI signal is invalid, the DMI receiver enable signal is pulled low, and the receiver is turned off.

[0090] Figure 9 The diagram shows the waveforms under the WR command when the DBI function is enabled and the DM function is disabled. As can be seen from the diagram, although the current command is WR, since DBI is enabled, the DMI signal is used for the DBI function and is a valid signal. The DMI receiver enable signal remains high, and the receiver is turned on.

[0091] Figure 10 The diagram shows the waveform under the MWR command when the DBI function is not enabled and the DM function is enabled. As can be seen from the diagram, although DBI is not enabled and DM is enabled, the current command is the MWR command (under the MWR command, DMI can be used for the DM function), the DMI signal is valid, the DMI receiver enable signal remains high, and the receiver is turned on.

[0092] Figure 11 The waveform diagram shown is displayed under the MWR command when the DBI and DM functions are not enabled. As can be seen from the diagram, even if both DBI and DM are disabled under the MWR command, the DMI receiver enable signal is pulled low, and the receiver is turned off.

[0093] A control method for reducing LPDDR power consumption according to an embodiment of this application includes obtaining the current write command type and the DBI enable state and DM enable state; when the current write command type is a WR command, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, the DMI signal is determined to be an invalid signal and a DMI receiver shutdown enable signal is generated; the DMI receiver is controlled to enter a low-power shutdown state according to the DMI receiver shutdown enable signal.

[0094] This application identifies the characteristics of invalid DMI signals in LPDDR chips under specific operating conditions (e.g., WR command, DBI disabled and DM enabled). Upon determining invalidity, it physically shuts down the analog front-end circuitry of the DMI receiver, thereby blocking the input and processing of invalid signals at the signal reception source and avoiding unnecessary power consumption by the DMI receiver during periods of invalid signals. Compared with existing technologies, this invention has at least the following advantages: First, by introducing a quantitative calculation formula for shutdown benefit value, the shutdown benefit brought by shutting down the DMI receiver can be accurately evaluated, and a decision on whether to perform a shutdown operation can be made based on the judgment conditions, avoiding the power consumption inversion problem caused by frequent shutdown / wake-up, thus realizing refined and intelligent power consumption management.

[0095] Secondly, by introducing a dynamic power consumption calculation formula, the shutdown decision threshold can be adaptively adjusted according to the actual signal activity on the DMI signal line, making power management decisions more in line with actual operating conditions and further improving the effectiveness of power consumption optimization.

[0096] Third, by introducing temperature compensation and hysteresis control mechanisms, different turn-off depths (deep turn-off or weak bias retention turn-off) can be adaptively selected according to the current junction temperature of the chip. This solves the problem of increased turn-off leakage current under high temperature environment and the additional power consumption caused by frequent receiver switching (ping-pong effect) under critical state, thus improving the engineering reliability and environmental adaptability of the solution.

[0097] Fourth, by implementing the combinational logic circuit at the gate level, setting up the clock synchronization latch and the anti-jitter delay unit, not only is a clear hardware implementation path provided, but also the problems of false shutdown caused by combinational logic glitches and signal instability during command transitions in high-speed signal transmission are solved, ensuring the timing reliability and signal integrity of the solution.

[0098] Fifth, for the MWR command scenario, this invention provides an independent shutdown scheme for DMI receiver sub-circuits at the byte level, which enables fine-grained control of partial shutdown and partial retention in mixed operating conditions where some bytes are masked and some bytes are not masked under the MWR command, further expanding the coverage of power consumption optimization scenarios.

[0099] The methods, systems, circuits, devices, and chips for reducing LPDDR power consumption provided in this application can be widely applied to various mobile terminals and embedded systems using LPDDR memory. Significant power reduction can be achieved by adding a small number of combinational logic gates within the chip. Simulation results show that in typical LPDDR5 operating scenarios (WR commands account for over 60% of all write commands, and the operating mode with DBI disabled and DM enabled accounts for approximately 40%), the power consumption of the DMI receiver can be reduced by approximately 30%–50%, and the overall chip power consumption can be reduced by approximately 5%–15%, demonstrating significant practical value in extending the battery life of mobile devices.

[0100] In summary, the LPDDR power consumption control method of this application includes obtaining the current write command type and the DBI and DM enable states; when the current write command type is a WR command, the DBI enable state is disabled, and the DM enable state is enabled, or when both the DBI and DM enable states are disabled, the DMI signal is determined to be invalid, and a DMI receiver shutdown enable signal is generated; the DMI receiver is controlled to enter a low-power shutdown state based on the DMI receiver shutdown enable signal. This application reduces the chip's power consumption during invalid operations by identifying invalid signals on the DMI interface and physically shutting down the DMI receiver when invalidity is determined, thereby achieving low-power operation of the chip.

[0101] Example 2 This application also provides a control system for reducing LPDDR power consumption. For details not disclosed in the control system for reducing LPDDR power consumption in this embodiment, please refer to the specific implementation of the control method and circuit for reducing LPDDR power consumption in other embodiments.

[0102] Figure 12 The diagram shows a schematic of a control system for reducing LPDDR power consumption according to an embodiment of this application.

[0103] like Figure 12 As shown, a control system for reducing LPDDR power consumption includes: Command parsing module 10 is used to obtain the type of the current write command; The status detection module 20 is used to obtain the DBI enable status and DM enable status; The enable signal generation module 30 is used to determine that the DMI signal is invalid and generate a DMI receiver shutdown enable signal when the current write command type is WR command, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled. DMI receiver 1 is used to control the DMI receiver to enter a low-power shutdown state according to the DMI receiver shutdown enable signal.

[0104] In the preferred implementation process, the enable signal generation module 30 includes: The power consumption evaluation unit is used to determine the invalid duration of the DMI signal within a preset time window when the DMI signal is invalid; and to calculate the shutdown benefit value of this shutdown operation based on the invalid duration; when the shutdown benefit value is greater than zero, a DMI receiver shutdown enable signal is generated.

[0105] In the preferred implementation, the DMI receiver includes an analog front-end module and an enable control switch; the analog front-end module includes a differential amplifier and a bias current source; the enable control switch is connected to the power supply terminal of the bias current source; the DMI receiver controls the enable control switch to open according to the DMI receiver turn-off enable signal, so as to cut off the power supply to the bias current source.

[0106] In the preferred implementation, the power consumption evaluation module includes a timer; the timer is used to evaluate the invalid duration T within a preset time window. invalid Count the invalid duration T. invalid Compare with the preset minimum shutdown time threshold; when the invalid duration T invalid The power consumption assessment module only triggers the calculation of the shutdown benefit value when the power consumption exceeds the preset minimum shutdown time threshold.

[0107] This application discloses a control method for reducing LPDDR power consumption, which includes obtaining the current write command type, DBI enable state, and DM enable state; when the current write command type is a WR command, the DBI enable state is disabled, and the DM enable state is enabled, or when both the DBI and DM enable states are disabled, the DMI signal is determined to be invalid, and a DMI receiver shutdown enable signal is generated; the DMI receiver is controlled to enter a low-power shutdown state based on the DMI receiver shutdown enable signal. This application reduces the chip's power consumption during invalid operations by identifying invalid signals on the DMI interface and physically shutting down the DMI receiver when invalidity is determined, thereby achieving low-power operation of the chip.

[0108] Compared with the prior art, the embodiments of this application have the following beneficial effects: (1) It can accurately identify invalid DMI signals under specific operating conditions of LPDDR and avoid accidentally turning off valid signals; (2) It reduces power consumption by turning off at the physical layer (cutting off bias current or disconnecting power supply), which is significantly better than signal shielding at the logic layer; (3) By introducing a turn-off benefit calculation mechanism, it ensures that system performance is not affected while reducing power consumption; (4) It is implemented using pure combinational logic circuits, which has fast response speed, small area overhead and is easy to integrate.

[0109] Example 3 This embodiment provides an electronic device. For details not disclosed in the electronic device of this embodiment, please refer to the specific implementation of the control system or method for reducing LPDDR power consumption in other embodiments.

[0110] Figure 13 The diagram illustrates the steps of a control device for reducing LPDDR power consumption according to an embodiment of this application.

[0111] like Figure 13 As shown, this application embodiment provides a control device for reducing LPDDR power consumption, including: DMI receiver 1 is used to receive DMI signals and DMI receiver turn-off enable signals; The logic control circuit 2 is connected to the DMI receiver 1 and is used to execute the control method of embodiment 1, outputting a DMI receiver turn-off enable signal to the DMI receiver 1 to control the DMI receiver to enter a low-power turn-off state.

[0112] Example 4 This embodiment provides an electronic device. For details not disclosed in the electronic device of this embodiment, please refer to the specific implementation of the control system or method for reducing LPDDR power consumption in other embodiments.

[0113] Figure 14 The diagram shows a schematic representation of an electronic device according to an embodiment of this application.

[0114] like Figure 14 As shown, the electronic device 410 includes: a storage unit 402 for storing executable instructions; and a processing unit 401 for connecting to the storage unit 402 to execute the executable instructions, thereby completing a control method for reducing LPDDR power consumption.

[0115] Those skilled in the art will understand that the illustration Figure 14 This is merely an example of electronic device 410 and does not constitute a limitation on electronic device 410. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 410 may also include input / output devices, network access devices, buses, etc.

[0116] The processing unit 401 (Central Processing Unit, CPU) can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processing unit 401 can be any conventional processor. The processing unit 401 is the control center of the electronic device 410, connecting all parts of the electronic device 410 via various interfaces and lines.

[0117] Storage unit 402 can be used to store computer-readable instructions. Processing unit 401 implements various functions of electronic device 410 by running or executing computer-readable instructions or modules stored in storage unit 402 and calling data stored in storage unit 402. Storage unit 402 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of electronic device 410, etc. In addition, storage unit 402 may include hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, read-only memory (ROM), random access memory (RAM), or other non-volatile / volatile storage devices.

[0118] If the modules integrated in electronic device 410 are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by instructing related hardware through computer-readable instructions. The computer-readable instructions can be stored in a computer-readable storage medium, and when executed by a processor, the computer-readable instructions can implement the steps of the various method embodiments described above.

[0119] Example 4 This embodiment provides a computer-readable storage medium having a computer program stored thereon; the computer program is executed by a processor to implement the control method for reducing LPDDR power consumption in other embodiments.

[0120] In summary, the electronic device and storage medium using this application include obtaining the current write command type and the DBI enable state and DM enable state; when the current write command type is a WR command, the DBI enable state is disabled, and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, the DMI signal is determined to be an invalid signal and a DMI receiver shutdown enable signal is generated; the DMI receiver is controlled to enter a low-power shutdown state based on the DMI receiver shutdown enable signal. This application reduces the chip's power consumption during invalid operations by identifying invalid signals on the DMI interface and physically shutting down the DMI receiver when invalidity is determined, thereby achieving low-power operation of the chip.

[0121] Those skilled in the art will understand that the terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms “a,” “an,” and “the” as used in this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0122] It should be understood that although the terms first, second, third, etc., may be used in this invention to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of this invention, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0123] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0124] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A control method for reducing LPDDR power consumption, characterized in that, include: Get the current write command type, DBI enable status, and DM enable status; When the current write command type is WR command, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, the DMI signal is determined to be an invalid signal and a DMI receiver shutdown enable signal is generated. The DMI receiver is controlled to enter a low-power shutdown state according to the DMI receiver shutdown enable signal.

2. The method according to claim 1, characterized in that, Before determining that the DMI signal is invalid, the method further includes: The stable duration of the WR command, the DBI enabled state, and the DM enabled state is timed; When the stable duration reaches a preset first time threshold, the process of determining whether the DMI signal is invalid is then performed.

3. The control method according to claim 1, characterized in that, The process of determining that the DMI signal is invalid and generating a DMI receiver shutdown enable signal further includes: Statistical analysis of the duration of invalid DMI signals within a preset time window; The shutdown benefit value ΔP of this shutdown operation is calculated based on the ineffective duration. The formula for calculating the shutdown benefit value ΔP is as follows: ； in, P active This refers to the power consumption of the DMI receiver during normal operation. P off The residual leakage power consumption after the DMI receiver is turned off. T invalid The total duration of the invalid state of the DMI signal. P wake_up This refers to the surge power consumption of the DMI receiver from shutdown to restart. T wake_up The recovery time required for the DMI receiver to be restarted. P transition This refers to the short-circuit power consumption caused by level switching. T trans This refers to the level switching time; When the shutdown benefit value ΔP is greater than zero, a DMI receiver shutdown enable signal is generated.

4. The control method according to claim 1, characterized in that, The generation of the DMI receiver turn-off enable signal includes: The percentage of invalid DMI signals within a predetermined time window is statistically analyzed. When the percentage is greater than the first preset threshold, the DMI receiver is controlled to enter a deep shutdown state; When the percentage is less than or equal to the first preset threshold and greater than the second preset threshold, the DMI receiver is controlled to enter a weak bias hold state. When the percentage is less than or equal to the second preset threshold, the DMI receiver is kept on.

5. The method according to claim 4, characterized in that, Before controlling the DMI receiver to enter a low-power shutdown state, the method further includes: Obtain the junction temperature parameters of the current chip; Based on the junction temperature parameters, a temperature compensation factor is determined. The first preset threshold and the second preset threshold are corrected according to the temperature compensation factor.

6. A control system for reducing LPDDR power consumption, characterized in that, include: The command parsing module is used to obtain the type of the current write command; The status detection module is used to obtain the DBI enable status and DM enable status; The enable signal generation module is used to determine that the DMI signal is an invalid signal and generate a DMI receiver shutdown enable signal when the current write command type is a WR command, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled. A DMI receiver is configured to control the DMI receiver to enter a low-power shutdown state based on the DMI receiver shutdown enable signal.

7. The control system according to claim 6, characterized in that, The enable signal generation module includes: The power consumption evaluation unit is used to determine that when the DMI signal is invalid, to count the invalid duration of the DMI invalid signal within a preset time window; and to calculate the shutdown benefit value of this shutdown operation based on the invalid duration; when the shutdown benefit value is greater than zero, to generate a DMI receiver shutdown enable signal.

8. A control circuit for reducing LPDDR power consumption, characterized in that, The circuit includes: The WR command input terminal is used to receive WR command signals; The MWR command input terminal is used to receive MWR command signals. The DBI enable input is used to receive the DBI enable signal. The DM enable input is used to receive the DM enable signal. Enable signal output terminal is used to output the DMI receiver shutdown enable signal; The logic gate combination unit includes a first OR gate, a first AND gate, a second AND gate, and a second OR gate; The input terminal of the first OR gate is connected to the DBI enable input terminal and the DM enable input terminal, and the output terminal of the first OR gate outputs a first signal; The input of the first AND gate is connected to the DBI enable input and the WR command input, and the output of the first AND gate is the third signal; The input of the second AND gate is connected to the MWR command input and the first signal, and the output of the second AND gate outputs the second signal; The input of the second OR gate is connected to the second signal and the third signal, and the output of the second OR gate is used as an enable signal output. When the WR command signal is valid, the DBI enable state is disabled and the DM enable state is enabled, or when both the DBI enable state and the DM enable state are disabled, the DMI signal is determined to be invalid. The logic gate combination unit outputs a DMI receiver shutdown enable signal, which is used to indicate that the DMI receiver enters a low-power shutdown state.

9. A control device for reducing LPDDR power consumption, characterized in that, include: DMI receiver, used to receive DMI signals and DMI receiver turn-off enable signals; A logic control circuit, connected to the DMI receiver, is used to execute the method as described in any one of claims 1 to 5, and output a DMI receiver turn-off enable signal to the DMI receiver to control the DMI receiver to enter a low-power turn-off state.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program is executed by the processor to implement the control method for reducing LPDDR power consumption as described in any one of claims 1 to 5.

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