Resistive random access memory compatibility tuning system and method based on adaptive parameter iteration

Abstract

This invention belongs to the field of computer storage technology and relates to an adaptive parameter iterative resistive random access memory (RRAM) compatibility tuning system and method. The system includes: a host interface protocol mapper for resolving the desired target conductance value; an adaptive iterative control engine for outputting the optimal pulse voltage amplitude and optimal pulse width; a dynamic pulse generator for synthesizing physically simulated pulses; an RRAM cross-memory array; a dynamic reference sensitive amplifier array for quantizing weak analog currents that do not reach a preset threshold into digital signals and returning them to the adaptive iterative control engine to update the initial conductance value and recalculate the error gradient; and a compatibility physical layer tuning module for determining whether there is an insulation drift risk in the array region. Its beneficial effect is the prediction of the optimal pulse voltage amplitude V. k And optimal time pulse width T k On average, it only takes 1 to 3 attempts to accurately fall into the tiny target tolerance band, greatly improving the write speed.

Description

Technical Field

[0001] This invention relates to the field of computer storage technology, and specifically to a system and method for optimizing the compatibility of resistive random access memory (RRAM) based on adaptive parameter iteration. Background Technology

[0002] Traditional von Neumann architectures are facing insurmountable bottlenecks in terms of the "memory wall" and "power wall." Among numerous novel non-volatile memory technologies, resistive random access memory (RRAM) stands out due to its superior physical characteristics, becoming a key candidate technology for in-memory computing and next-generation high-performance embedded memory chips. The basic physical structure of RRAM is a simple metal-insulator-metal sandwich stack architecture. In typical transition metal oxide-based RRAM devices, data storage depends on the formation and breakage of microscopic conductive filaments within the insulating layer. When a specific programming voltage is applied between the top and bottom electrodes, the electric field and Joule heating jointly drive oxygen ion migration, leaving oxygen vacancies to accumulate and form conductive pathways, allowing the device to switch from a high-resistivity state to a low-resistivity state—a process known as the SET operation. Conversely, applying a reverse voltage (in bipolar devices) or voltages of varying magnitudes in the same direction (in unipolar devices) causes oxygen ions to recombine with oxygen vacancies, breaking the conductive filaments and restoring the device to its HRS (High Resistance State), i.e., the RESET operation.

[0003] Compared to traditional NAND Flash or DRAM, RRAM offers significant advantages: its read / write speeds can reach nanosecond levels, it supports 3D cross-arrays for extremely high storage density, and its manufacturing process is highly compatible with standard CMOS front-end and back-end processes, allowing direct integration onto logic chips without significantly increasing manufacturing costs. More importantly, RRAM's conductivity is not limited to switching between two discrete states. By precisely modulating the energy of programming pulses (voltage amplitude, current limit, or pulse duration), RRAM can exhibit rich analog multi-value storage characteristics. This ability to simulate gradual changes in biological synaptic weights through conductivity variations provides a perfect physical mapping mechanism for building hardware accelerators for artificial neural networks. Despite RRAM's enormous potential at the device level, its transition from a single laboratory device to a system-level commercial array faces extremely severe control and compatibility challenges. Among these, achieving precise control of RRAM's resistance state with extremely low power consumption and latency in complex system environments, while ensuring seamless compatibility with existing high-speed digital bus interfaces, has become a core problem urgently needing to be solved by both academia and industry.

[0004] In MLC or QLC RRAM programming, to overcome the physical limitation that a single open-loop write pulse cannot precisely lock the device within the target resistance state range, the most mainstream technology currently is the Incremental Step Pulse Programming with Verify Algorithm (ISPVA or M-ISPVA) and its derived advanced Write-and-Verify (WV) schemes. However, the traditional M-ISPVA algorithm heavily relies on a fixed voltage step size. Since the RRAM conductance exhibits highly nonlinear behavior with the integral of the applied electric field, such as the exponential or logarithmic switching law revealed by the TEAM physical model, this fixed step size strategy appears extremely rigid. When the initial state is far from the target state, the small fixed step size requires the algorithm to perform dozens or even hundreds of pulse iterations to approach the target; while when the state is close to the target, due to the nonlinear amplification effect of the filamentary abrupt change, the fixed pulse width and amplitude easily lead to state skipping, i.e., producing the so-called over-set or over-reset phenomenon. Once an overshoot occurs, traditional controllers can only apply pulses of opposite polarity to pull it back to its original state and restart the incremental iteration. This repeated friction not only significantly slows down programming speed—a single RRAM write-verify cycle often takes hundreds of nanoseconds—but also causes devastating delays of several seconds for deep neural networks with tens of millions of parameters, such as ResNet-50, with a single full array weight update. Furthermore, it places enormous write stress on the physical structure of the RRAM. High-frequency write-verify directly accelerates the generation of redundant defects in the insulating layer and thermal damage to the lattice, drastically reducing the RRAM's originally considerable erase / write lifetime to around 10⁵ cycles, severely hindering its application in learning-based neuromorphic computing and high-frequency caching that require frequent parameter updates.

[0005] Furthermore, due to the unique physical mechanism of RRAM, its resistive states are not absolutely static. Due to thermal diffusion of atoms on the conductive filament surface, stress relaxation mechanisms, and charge recapture / release processes, the conductivity of RRAM will spontaneously drift or decay over time after programming. Especially in the case of multi-value storage, the tolerance window between adjacent resistive states is extremely small; even slight conductivity relaxation can cause the distribution of adjacent logic states to overlap, leading to catastrophic read errors. Existing system-level memory interface physical layer calibration is primarily designed for DRAM or SRAM, typically performing static or quasi-static calibration only once during system power-on initialization or a very small number of sleep / wake cycles. Once the RRAM array experiences a collective shift in resistive state distribution due to temperature rise or internal relaxation during operation, the fixed Vref decision threshold in the DDR controller will not be able to adaptively adjust. The sampling point originally calibrated at the center of the eye diagram will fall directly on the drifted signal edge, causing the physical layer read error rate to increase exponentially. Summary of the Invention

[0006] Technical problems to be solved

[0007] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a resistive random access memory (RRAM) compatibility tuning system and method based on adaptive parameter iteration, which solves the technical problems faced by the prior art, such as high write latency, large lifespan loss, interface mismatch caused by analog drift, and lack of closed-loop compensation mechanism.

[0008] Technical solution To achieve the above objectives, the main technical solutions adopted by the present invention include: In a first aspect, this invention proposes a resistive switching memory compatibility tuning system based on adaptive parameter iteration, comprising: The host interface protocol mapper is used to receive standard memory bus protocol instructions from the host computer processor, perform pre-read operations on the target RRAM, extract its target logical address, and parse out the expected target conductance value. The adaptive iterative control engine, upon receiving a write task, directs the dynamic reference sensitive amplifier array to obtain the current initial conductance value of the RRAM, calculates the error gradient between the current conductance state and the target conductance state, and adaptively updates the optimal parameter combination required for the next round of programming. A dynamic pulse generator is used to receive digital instructions from an adaptive iterative control engine and synthesize physical simulation pulses on selected word lines or bit lines. The RRAM cross-memory array receives the physical simulation pulses applied by the dynamic pulse generator and the shaping circuit; A dynamic reference sensitive amplifier array is used to sense the weak analog current flowing through the RRAM cell and compare it with an internal reference threshold. Analog currents that do not reach the preset threshold are quantized into digital signals and returned to the adaptive iterative control engine to update the initial conductance value and recalculate the error gradient. The compatibility physical layer tuning module is used to determine whether there is insulation drift in the area where the target RRAM cell is located; and to generate physical layer compensation instructions for areas with insulation drift risk, dynamically adjusting the reference voltage offset of the corresponding sensitive amplifier and / or the clock phase of the data strobe signal.

[0009] As a further improvement of the present invention, the reference voltage input terminal of the dynamic reference sensitive amplifier array is connected to a dynamic reference network that supports multi-tap fine-tuning.

[0010] As a further improvement of the present invention, the weak analog current flowing through the RRAM cell is sensed in real time through a self-terminating dynamic tracking circuit throughout the entire system operation.

[0011] As a further improvement of the present invention, the self-terminating dynamic tracking circuit includes: A pulse width modulator based on a variable RC network is used to control a set of wide-channel PMOS switch arrays to connect parasitic capacitance branches of different capacitance values ​​into a constant current source charging and discharging network according to the time pulse width digital control word. The voltage across the capacitor is used as the clock enable signal of the flip-flop. When the capacitor charging crosses the logic inversion threshold, the flip-flop flips and physically cuts off the pulse signal sent to the RRAM array. A current mirroring and self-terminating clamp includes: a current mirroring circuit connected to the bit line of the target RRAM cell for mapping transient programming current flowing through the RRAM device to an auxiliary bypass; and a high-speed dynamic analog voltage comparator disposed on the auxiliary bypass, the inverting input of which is connected to a target conductance value. The mapped reference source allows the high-speed comparator to react immediately when the current flowing through the device touches the reference threshold, and output a toggle signal within hundreds of picoseconds; and a large-size clamping NMOS transistor connected in parallel between the bit line and ground, whose gate is connected to the output of the high-speed comparator, is used to pull the bit line voltage down to zero when the toggle signal is received, hard blocking programming stress to remove the unacceptable clock delay in the digital feedback loop; The micro-bias reference injector is a miniature digital-to-analog converter composed of a switched capacitor network connected in series outside the global reference voltage input node. After receiving the bias offset command issued by the compatibility physical layer tuning module, it performs fine-grained compensation of the local reference voltage through the switched capacitor array and injects a micro-charge into the local reference input node of the dynamic reference sensitive amplifier array. It works with the sensitive amplifier to complete the verification reading and data output, and superimposes a DC bias on the global reference level.

[0012] As a further improvement of the present invention, the mirror ratio of the current mirror circuit is 1:1 or scaled proportionally.

[0013] Secondly, the present invention provides a method for optimizing the compatibility of resistive random access memory (RANM) based on adaptive parameter iteration, comprising the following steps: Step 1: Receive the multi-value write command from the host computer, perform a pre-read operation on the target RRAM cell, extract its target logical address, and parse out the expected target conductance value G. target ; Step 2: Apply a weak bias prefetch to the addressed RRAM cell and read the current initial conductance value G0 of the RRAM cell; Step 3: Calculate the error gradient between the current conductance state and the target conductance state. Based on the error gradient Determine if the RRAM cell status has converged; if yes, end the write process directly; otherwise, proceed to the next step. Step 4: Calculate the rate of change of the current RRAM cell's conductivity and adaptively update the optimal parameter combination required for the next round of programming. ; Step 5: Based on the optimal parameter combination Generate physical simulation pulses to apply physical simulation pulses to selected word lines or bit lines of the RRAM array; Step 6: Real-time sensing of the weak analog current I flowing through the RRAM cell current ; Step 7: Based on the updated error gradient, re-determine whether the RRAM cell state has converged; if yes, proceed to the insulation drift determination step; if no, proceed to the next step. Step 8: Check if the maximum number of iterations has been reached; if not, increase the number of iterations and return to Step 4 to continue dynamically approximating the maximum number of iterations; if the maximum number of iterations has been reached, proceed to the next step. Step 9: Determine if there is insulation drift in the array region where the target RRAM cell is located; if so, generate a physical layer compensation instruction; if not, terminate directly. Step 10: Generate physical layer compensation instructions to dynamically adjust the reference voltage offset of the corresponding sensitive amplifier and / or the clock phase of the data strobe signal.

[0014] As a further improvement of the present invention, the calculation of the conductivity change rate includes: If it is the first iteration, the rate of change of conductivity γ is taken as a preset empirical value; If it is not the first iteration, then γ is calculated according to the following formula:

[0015] In the formula, k represents the number of iterations, V represents the voltage amplitude of the pulse, and T represents the pulse width.

[0016] As a further improvement of the present invention, the optimal parameter combination includes the optimal pulse voltage amplitude V. k And optimal time pulse width T k This is obtained by synchronous iterative calculation using an adaptive decay function based on the conductivity rate gradient. The iterative calculation formula is as follows:

[0017]

[0018] In the formula, , , , Both indicate configurable weights. Indicates the amplitude of the pulse base voltage. Indicates the minimum time pulse width. and These represent the error gradient and the rate of change of conductivity, respectively, during the iteration process.

[0019] As a further improvement of the present invention, during the application of the physical simulation pulse, the weak analog current flowing through the RRAM cell is sensed in real time by a self-terminating dynamic tracking circuit. If the conductive path is connected and I current If the preset threshold is not reached, a verification read operation is performed to update the initial conductance value G of the RRAM cell. k And recalculate the error gradient E k .

[0020] As a further improvement of the present invention, in step 9, the underlying parameter stress characteristics of each RRAM write process are extracted to determine whether there is an insulation drift risk in the array region where the target RRAM cell is located. The underlying parameters are the number of iterations, cumulative energy integral, and cell spatial position accumulated during the current writing process, extracted after the writing process is completed. The stress index for extracting the underlying parameters is calculated according to the following formula:

[0021] In the formula, The pulse width indicating the time of a successful write.

[0022] Beneficial effects The beneficial effects of this invention are: Traditional fixed-step M-ISPVA is prone to oscillations or slow ramp-ups when storing multiple values, requiring an average of 15 to 20 iterations for each cell write, resulting in a total latency as high as 2. ~5 This invention predicts the optimal pulse voltage amplitude V using nonlinear gradient descent. k And optimal time pulse width T k On average, it only requires 1-3 attempts to accurately fall into the tiny target tolerance band, significantly improving write speed. This is a decisive generational advantage for edge AI acceleration chips that need to update millions of parameter matrices in milliseconds.

[0023] Irreversible damage caused by resistive switching layer defects mainly stems from prolonged high-voltage overshoot. This invention introduces a sub-nanosecond-level hardware combination of a self-terminating comparator and a powerful clamping transistor. Regardless of the initial pulse width allocated by the algorithm, the destructive energy is interrupted as soon as the conductive filament is formed. This extreme on-demand energy allocation mechanism reduces the invalid write stress experienced by RRAM devices by more than 90%, resulting in a significant extension of their stable erase / write cycle life. Attached Figure Description

[0024] Figure 1 This is a structural diagram of a resistive switching memory compatibility optimization system based on adaptive parameter iteration provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a self-terminating dynamic tracking circuit for resistive random access memory provided in an embodiment of the present invention; Figure 3 This is a flowchart of a resistive switching memory compatibility optimization method based on adaptive parameter iteration provided in an embodiment of the present invention. Detailed Implementation

[0025] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention can be understood more clearly and thoroughly, and that the scope of the present invention can be fully conveyed to those skilled in the art.

[0026] Firstly, such as Figure 1As shown, this embodiment of the invention provides a resistive random access memory (RRAM) compatibility tuning system based on adaptive parameter iteration, comprising: The Host Interface & Protocol Mapper, acting as the system front-end, receives standard memory bus protocol instructions from the host computer (CPU / GPU or NPU accelerator), performs pre-fetch operations on the target RRAM, and parses its digitized logical address, data, and read / write enable signals into a target logical address and target conductance value G that the RRAM array can directly process. target The output is sent to the adaptive iterative control engine.

[0027] The Adaptive Iteration Control Engine (AICE) integrates parameter calculation operators based on ultra-lightweight, physically compact models (such as those extracted from TEAM models or simplified artificial neural network predictors). Connected to the host interface protocol mapper, it directs the dynamic reference sensitive amplifier array to acquire the current initial conductance value G of the RRAM upon receiving a write task. current The engine calculates the error gradient between the current state and the target electrical state using a nonlinear iterative algorithm, and adaptively updates the optimal parameter combination required for the next round of programming. .

[0028] The Dynamic Pulse Generator (DPG), controlled by the adaptive iterative control engine, integrates a high-precision digital-to-analog converter (DAC) for voltage regulation output, and a programmable delay phase-locked loop or charge-discharge tracking network for generating finely time-width modulated signals. It receives digital instructions from the adaptive iterative control engine and synthesizes dynamically adjustable physical analog pulses in both shape and duration on selected word lines or bit lines.

[0029] An RRAM crossbar array is the physical entity that stores data, consisting of word lines and bit lines arranged in an orthogonal grid. At each crossbar, a 1T1R basic cell consisting of a gating transistor and a resistive switching device is deployed to suppress creeping leakage current in the large array. It receives physically simulated pulses applied by the dynamic pulse generator.

[0030] A dynamic reference and sense amplifier array (DV-SA) is used to sense the weak analog current I flowing through the RRAM cell during verification reads or standard address reads.current It compares the current with an internal reference threshold, quantizes the analog current that does not reach the preset threshold into a digital signal and returns it to the adaptive iterative control engine to update the initial conductance value and recalculate the error gradient.

[0031] Throughout the system's operation, the underlying hardware, namely the self-terminating dynamic tracking circuit, synchronously senses the analog current of the RRAM cells. Furthermore, in this system, the reference voltage input of the DV-SA is not connected to a fixed static reference source, but rather to a dynamic reference network that supports multi-tap fine-tuning.

[0032] The Compatibility PHY Tuning Module (CPTM), coupled with the adaptive iterative control engine, determines whether there is a risk of insulation drift in the array region where the target RRAM cell is located due to IR voltage drop or severe insulation by extracting the stress characteristics of the underlying parameters during each RRAM write process. Then, it sends a dynamic reference voltage to the physical layer reference voltage generator through the system side channel to compensate for the bias offset, and schedules the phase fine-tuning of the DQS sampling clock when necessary.

[0033] Specifically, sending the compensation command to reset the DQS delay phase of the corresponding data pin is executed when at least one of the following conditions is met: The stress index is higher than the reference threshold of the target array region, and the calculated local voltage compensation offset Vref has reached or is close to the preset compensation limit, but it still cannot restore the verification read result to the preset read margin.

[0034] If the number of consecutive read failures, edge sampling errors, or bit error rate exceeds a preset threshold within the same data pin, the same DQ / DQS group, or adjacent bit line regions, it indicates that the read failures are mainly caused by sampling window offset or data strobe signal phase mismatch.

[0035] Based on the RRAM cell spatial location, bit line length, IR voltage drop estimate, and write energy integration parameters, it is determined that the data arrival time skewness relative to DQS exceeds the preset phase margin; fourth, after completing If the remaining read error still shows a directional shift related to the DQS phase after Vref is written and then read again, it is determined that adjusting the reference voltage alone is insufficient to eliminate the drift risk, and the compensation command is sent to reset or fine-tune the DQS delay phase of the corresponding data pin.

[0036] like Figure 2As shown, the self-terminating dynamic tracking programming circuit includes an adaptive iterative control engine interface and the following three coupled sub-networks: A variable RC tracking pulse width modulator (RCPWM) based on an adaptive iterative control engine controls a wide-channel PMOS switch array to connect parasitic capacitance branches of different values ​​to a constant current source charging and discharging network. This causes the capacitor voltage to gradually rise, generating a clock enable signal upon reaching a threshold. This, in turn, controls a write pulse generator to output a programming pulse with the target pulse width. This write pulse is applied to selected RRAM bit lines, word lines, and 1T1R memory cells to drive the formation or adjustment of the conductive filaments in the resistive switching device. The voltage across the capacitor serves as the clock enable signal (ClockEnable) for the flip-flop. When the capacitor charging crosses the logic inversion threshold, the flip-flop toggles, physically truncating the pulse signal sent to the RRAM array. By changing the number of capacitors connected in parallel, it achieves adaptive scaling of the analog pulse width, highly compatible with the requirements of resistive switching memory compatibility tuning systems, and can achieve picosecond-level adaptive pulse widths (T). k It does not rely on a power-intensive multi-megahertz digital clock counter.

[0037] A mirror current sensing and self-limiting clamp includes: a current mirror circuit connected to the bit line terminal of the target RRAM cell, used to map the transient programming current flowing through the RRAM device to an auxiliary bypass; wherein the mirror ratio of the current mirror circuit is 1:1 or scaled proportionally. A high-speed dynamic analog voltage comparator is disposed on the auxiliary bypass, the inverting input of which is connected to a value determined by the target conductance. The mapped reference source allows the high-speed comparator to react immediately when the current flowing through the device reaches the reference threshold, and output a toggle signal within hundreds of picoseconds; and a large-size clamping NMOS transistor connected in parallel between the bit line and ground, with its gate connected to the output of the high-speed comparator, is used to pull the bit line voltage down to zero when the toggle signal is received, hard blocking programming stress, thereby removing the intolerable clock delay in the digital feedback loop and achieving hardware-level safety braking.

[0038] The micro-bias Vref Injector supports local compensation. This micro-bias Vref Injector is a miniature digital-to-analog converter (DAC) consisting of a switched-capacitor network connected in series outside the global reference voltage input node. After receiving bias offset commands from the compatibility physical layer tuning module, it performs fine-grained compensation of the local reference voltage through the switched-capacitor array and injects a small amount of charge into the local reference input node of the dynamic reference sensitive amplifier array. This, in conjunction with the sensitive amplifier, completes verification reading and data output, and superimposes a DC bias above the global reference level. Therefore, even when the absolute resistance of the RRAM drifts due to ambient temperature, the sensing front end can still adaptively adjust the judgment balance to the optimal data identification center. The offset command on the PHY controller side can dynamically calibrate the reference voltage and sensing threshold based on stress integration during the writing process, array position, and possible IR voltage drop or resistance drift.

[0039] The aforementioned self-terminating dynamic tracking circuit for resistive random access memory (RRAM) bypasses a current mirror circuit and a dynamic high-speed comparator on the bit line. During the duration of a single write pulse, once a surge in current caused by the conductive filament being connected is detected and reaches a safety threshold, the hardware circuit directly triggers a large-size clamping transistor to forcibly drain the bit line voltage and truncate the pulse within hundreds of picoseconds, achieving zero-delay physical-level loss prevention.

[0040] As an alternative, in some low-cost applications, the target chip, due to manufacturing cost constraints, cannot integrate a high-precision micro-digital-to-analog converter within the read channel to physically fine-tune the reference voltage Vref. To address this, drawing inspiration from Low-Rank Adaptation (LoRA) in large language model fine-tuning, the compensation amounts for resistive random access memory (RRAM) characteristic variations and conductance drift calculated by the system are converted into a low-dimensional digital error correction matrix. This compensation does not directly implement physical voltage bias in the analog domain; instead, a very small amount of high-precision compensation features are stored in a high-speed SRAM sidebar that works in conjunction with the RRAM array. During high-speed read operations, the digital processor performs hardware-level arithmetic summation of the initial digital quantity with drift or noise read from the RRAM array and the digital compensation amount synchronously read from the SRAM sidebar, thereby achieving read compatibility tuning effects equivalent to analog domain reference voltage fine-tuning in a purely digital form.

[0041] This invention provides a resistive random access memory (RRAM) compatibility tuning system based on adaptive parameter iteration. Before writing, it pre-reads the initial resistive state assessment error and, based on the device conductance differential gradient extracted using a combination of hyperbolic tangent and exponential nonlinear mapping models, synchronously and adaptively derives and updates the voltage amplitude and time pulse width of the next programming pulse in each iteration cycle. This achieves accurate approximation of the multi-valued target resistive state with the fewest possible pulses. Furthermore, it can actively extract the accumulated stress integral and IR voltage drop spatial characteristics consumed by the underlying RRAM cells during programming and report these prior physical characteristics via a sideband bus. Upon receiving these characteristics, the physical layer controls the internal micro-switched capacitor network to dynamically inject an offset into the reference voltage input of a specific sensitive amplifier and coordinately adjust the DQS clock phase. This proactively adapts to and counteracts the analog resistive state drift phenomenon caused by time or temperature in the RRAM.

[0042] Secondly, such as Figure 3 As shown, this embodiment of the invention provides a method for optimizing the compatibility of resistive random access memory (RANM) based on adaptive parameter iteration, including the following steps: Step 1: Receive the multi-value (MLC / QLC) write command from the host computer, perform a pre-read operation on the target RRAM, extract its target logical address, and parse the expected target conductance value G. target .

[0043] Step 2: Apply a non-destructive weak bias read-ahead to the addressed RRAM cell and read the current initial conductance value G0 of the RRAM cell.

[0044] In this embodiment, the applied weak bias pre-read is an extremely low bias of 0.1V.

[0045] Step 3: Calculate the error gradient between the current conductance state and the target conductance state. And based on the error gradient Determine if the RRAM cell status has converged, i.e., if the error is within the tolerance range. If yes, end the write process directly; otherwise, proceed to the next step.

[0046] Specifically, if the absolute value of the error gradient |E0| is less than the preset compatibility tolerance band limit ε, the storage bit is determined to be in an ideal state, and the process is terminated directly to avoid unnecessary wear caused by writing the same value overwrite. If the absolute value of the error gradient |E0| exceeds the preset compatibility tolerance band limit ε, then proceed to the next step of judgment.

[0047] Where the error gradient Calculate according to the following formula: .

[0048] Step 4: Calculate the rate of change of the current RRAM cell's conductivity and adaptively update the optimal parameter combination required for the next round of programming. .

[0049] In the first iteration, the rate of change of conductivity γ is taken as a preset empirical value; in other iterations, γ is calculated according to the following formula:

[0050] In the formula, k represents the number of iterations, V represents the voltage amplitude of the pulse, and T represents the pulse width.

[0051] Based on the aforementioned conductivity rate gradient, the optimal parameter combination for the next round of programming, i.e., the optimal pulse voltage amplitude V, is calculated synchronously and iteratively using an adaptive decay function. k And optimal time pulse width T k .

[0052] The iterative calculation formula is:

[0053]

[0054] In the formula, , , , Both indicate configurable weights. Indicates the amplitude of the pulse base voltage. Indicates the minimum time pulse width. and These represent the error gradient and the rate of change of conductivity, respectively, during the iteration process.

[0055] Among them, the hyperbolic tangent function The introduction of this ensures that when the error is extremely large, the voltage increment is nonlinearly clamped within the safe physical limit to prevent breakdown; while when the error is extremely small, the amplitude adjustment becomes an extremely fine linear approximation to achieve accurate approximation of the multi-value target resistance state with the fewest number of pulses.

[0056] Exponential mapping This endows the time pulse width with a strong adaptive scaling capability, providing long pulses in the early stage to accelerate filament growth, and rapidly shrinking the time pulse width at the end to prevent overshoot.

[0057] Step 5: Based on the optimal parameter combination Generate physical simulation pulses to apply physical simulation pulses to selected word lines or bit lines of the RRAM array.

[0058] Step 6: Real-time sensing of the weak analog current I flowing through the RRAM cell current .

[0059] During the application of the physical simulation pulse, the weak analog current flowing through the RRAM cell is sensed in real time by a self-terminating dynamic tracking circuit. If the conductive path is connected and I current If the preset threshold is reached, the high-speed clamping circuit is triggered to immediately cut off the pulse to prevent overwrite and protect the device. If the conductive path is connected and I current If the preset threshold is not reached, a verification read operation is performed to update the initial conductance value G of the RRAM cell. k And recalculate the error gradient E k .

[0060] Step 7: Based on the updated error gradient, re-determine whether the RRAM cell state has converged; if yes, proceed to the insulation drift determination step; if no, proceed to the next step.

[0061] Step 8: Check if the maximum number of iterations has been reached; if not, increase the number of iterations and return to step 4 to continue dynamically approaching the maximum number of iterations; if it has been reached, proceed to the next step.

[0062] Step 9: Determine whether there is insulation drift in the array region where the target memory cell is located; if so, generate a physical layer compensation instruction; if not, end directly.

[0063] Specifically, by extracting the stress characteristics of the underlying parameters during each RRAM write process, it is determined whether there is a risk of insulation drift in the array region where the target RRAM cell is located.

[0064] The underlying parameters include: the number of iterations required for each RRAM write, the final applied energy integral parameter, and the cell space location.

[0065] The extracted stress index is calculated according to the following formula:

[0066] In the formula, The pulse width indicating the time of a successful write.

[0067] If the determination result is that the array region where the RRAM cell is located is deep within the array and its The value is much higher than the baseline threshold for this sector, indicating that the physical location faces a severe IR voltage drop (signal attenuation).

[0068] Step 10: Generate physical layer compensation instructions to dynamically adjust the reference voltage offset of the corresponding sensitive amplifier and / or the clock phase of the data strobe signal.

[0069] Based on the above judgment results, the compatibility correction sequence is initiated, and the corresponding local voltage compensation offset is calculated through the internal bus. Vref is written into the dynamic reference sensitive amplifier array for that bit line and used as a compensation instruction to reset the DQS delay phase of the corresponding data pin when necessary.

[0070] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0071] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, then this invention should also include these modifications and variations.

[0072] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A compatibility tuning system for resistive random access memory (RANM) based on adaptive parameter iteration, characterized in that, include: The host interface protocol mapper is used to receive standard memory bus protocol instructions from the host computer processor, perform pre-read operations on the target RRAM, extract its target logical address, and parse out the expected target conductance value. The adaptive iterative control engine, upon receiving a write task, directs the dynamic reference sensitive amplifier array to obtain the current initial conductance value of the RRAM, calculates the error gradient between the current conductance state and the target conductance state, and adaptively updates the optimal parameter combination required for the next round of programming. A dynamic pulse generator is used to receive digital instructions from an adaptive iterative control engine and synthesize physical simulation pulses on selected word lines or bit lines. The RRAM cross-memory array receives the physical simulation pulses applied by the dynamic pulse generator and the shaping circuit; A dynamic reference sensitive amplifier array is used to sense the weak analog current flowing through the RRAM cell and compare it with an internal reference threshold. Analog currents that do not reach the preset threshold are quantized into digital signals and returned to the adaptive iterative control engine to update the initial conductance value and recalculate the error gradient. The compatibility physical layer tuning module is used to determine whether there is insulation drift in the area where the target RRAM cell is located; and to generate physical layer compensation instructions for areas with insulation drift risk, dynamically adjusting the reference voltage offset of the corresponding sensitive amplifier and / or the clock phase of the data strobe signal.

2. The adaptive parameter iteration-based resistive random access memory compatibility tuning system according to claim 1, characterized in that, The reference voltage input of the dynamic reference sensitive amplifier array is connected to a dynamic reference network that supports multi-tap fine-tuning.

3. The adaptive parameter iteration-based resistive random access memory compatibility optimization system according to claim 1, characterized in that, Throughout the entire system operation, the weak analog current flowing through the RRAM cell is sensed in real time through a self-terminating dynamic tracking circuit.

4. The adaptive parameter iteration-based resistive random access memory compatibility optimization system according to claim 3, characterized in that, The self-terminating dynamic tracking circuit includes: A pulse width modulator based on a variable RC network is used to control a set of wide-channel PMOS switch arrays to connect parasitic capacitance branches of different capacitance values ​​into a constant current source charging and discharging network according to the time pulse width digital control word. The voltage across the capacitor is used as the clock enable signal of the flip-flop. When the capacitor charging crosses the logic inversion threshold, the flip-flop flips and physically cuts off the pulse signal sent to the RRAM array. A current mirroring and self-terminating clamp includes: a current mirroring circuit connected to the bit line of the target RRAM cell for mapping transient programming current flowing through the RRAM device to an auxiliary bypass; and a high-speed dynamic analog voltage comparator disposed on the auxiliary bypass, the inverting input of which is connected to a target conductance value. The mapped reference source allows the high-speed comparator to react immediately when the current flowing through the device touches the reference threshold, and output a toggle signal within hundreds of picoseconds; and a large-size clamping NMOS transistor connected in parallel between the bit line and ground, whose gate is connected to the output of the high-speed comparator, is used to pull the bit line voltage down to zero when the toggle signal is received, hard blocking programming stress to remove the unacceptable clock delay in the digital feedback loop; The micro-bias reference injector is a miniature digital-to-analog converter composed of a switched capacitor network connected in series outside the global reference voltage input node. After receiving the bias offset command issued by the compatibility physical layer tuning module, it performs fine-grained compensation of the local reference voltage through the switched capacitor array and injects a micro-charge into the local reference input node of the dynamic reference sensitive amplifier array. It works with the sensitive amplifier to complete the verification reading and data output, and superimposes a DC bias on the global reference level.

5. The adaptive parameter iteration-based resistive random access memory compatibility optimization system according to claim 4, characterized in that, The current mirror circuit has a mirror ratio of 1:1 or is scaled proportionally.

6. A method for optimizing the compatibility of resistive random access memory (RANM) based on adaptive parameter iteration, characterized in that, Includes the following steps: Step 1: Receive the multi-value write command from the host computer, perform a pre-read operation on the target RRAM cell, extract its target logical address, and parse out the expected target conductance value G. target ; Step 2: Apply a weak bias prefetch to the addressed RRAM cell and read the current initial conductance value G0 of the RRAM cell; Step 3: Calculate the error gradient between the current conductance state and the target conductance state. And based on the error gradient Determine if the RRAM cell status has converged; if so, terminate the write process directly. Otherwise, proceed to the next step; Step 4: Calculate the rate of change of the current RRAM cell's conductivity and adaptively update the optimal parameter combination required for the next round of programming. ; Step 5: Based on the optimal parameter combination Generate physical simulation pulses to apply physical simulation pulses to selected word lines or bit lines of the RRAM array; Step 6: Real-time sensing of the weak analog current I flowing through the RRAM cell current ; Step 7: Based on the updated error gradient, re-determine whether the RRAM cell state has converged; if yes, proceed to the insulation drift determination step; if no, proceed to the next step. Step 8: Check if the maximum number of iterations has been reached; if not, increase the number of iterations and return to Step 4 to continue dynamically approximating the maximum number of iterations; if the maximum number of iterations has been reached, proceed to the next step. Step 9: Determine if there is insulation drift in the array region where the target RRAM cell is located; if so, generate a physical layer compensation instruction; if not, terminate directly. Step 10: Generate physical layer compensation instructions to dynamically adjust the reference voltage offset of the corresponding sensitive amplifier and / or the clock phase of the data strobe signal.

7. The method for compatibility optimization of resistive random access memory based on adaptive parameter iteration according to claim 6, characterized in that, The calculation of the rate of change of conductivity includes: If it is the first iteration, the rate of change of conductivity γ is taken as a preset empirical value; If it is not the first iteration, then γ is calculated according to the following formula: In the formula, k represents the number of iterations, V represents the voltage amplitude of the pulse, and T represents the pulse width.

8. The method for optimizing the compatibility of resistive random access memory according to claim 6, characterized in that, The optimal parameter combination includes the optimal pulse voltage amplitude V. k And optimal time pulse width T k This is obtained by synchronous iterative calculation using an adaptive decay function based on the conductivity rate gradient. The iterative calculation formula is as follows: In the formula, , , , Both indicate configurable weights. Indicates the amplitude of the pulse base voltage. Indicates the minimum time pulse width. and These represent the error gradient and the rate of change of conductivity, respectively, during the iteration process.

9. The method for compatibility optimization of resistive random access memory based on adaptive parameter iteration according to claim 6, characterized in that, During the application of the physical simulation pulse, the weak analog current flowing through the RRAM cell is sensed in real time by a self-terminating dynamic tracking circuit. If the conductive path is connected and I current If the preset threshold is not reached, a verification read operation is performed to update the initial conductance value G of the RRAM cell. k And recalculate the error gradient E k .

10. The method for optimizing the compatibility of resistive random access memory according to claim 6, characterized in that, In step 9, the underlying parameter stress characteristics of each RRAM write process are extracted to determine whether there is a risk of insulation drift in the array region where the target RRAM cell is located. The underlying parameters are the number of iterations, cumulative energy integral, and cell spatial position accumulated during the current writing process, extracted after the writing process is completed. The stress index for extracting the underlying parameters is calculated according to the following formula: In the formula, The pulse width indicating the time of a successful write.

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