Extending the stop refinement mode to improve performance and power by reducing verification and scan operations

Abstract

A memory device includes memory cells connected to word lines and configured to hold threshold voltages corresponding to data states. The data states include a highest data state in which the threshold voltage of the memory cells associated with the highest data state is higher than the threshold voltages for other data states in the data states. A control component is configured to apply, during each program loop of a plurality of program loops of a program operation, each program pulse of a series of program pulses of a program voltage to selected ones of the word lines followed by a verify pulse of a verify voltage associated with a respective one of the data states to program and verify the memory cells connected to the selected word lines. The control component is further configured to skip verification of the memory cells targeted with at least one of the other data states in the data states in at least one program loop of the plurality of program loops.

Description

Technical Field

[0001] This application relates to the operation of non-volatile memory devices. Background Technology

[0002] This section provides background information relating to the technology associated with this disclosure and is therefore not necessarily prior art.

[0003] In some programming techniques used to program multi-bit data into each of multiple memory cells in a selected word line, the programming operation comprises multiple programming loops (or iterations), where each programming loop includes a programming step and a verification step. Programming continues until the memory cell is programmed to a corresponding data state associated with an increasing threshold voltage level. To reduce programming time (i.e., reduce tProg), in some programming operations, the final verification step for verifying the last data state is skipped, and programming is completed without verification. Summary of the Invention

[0004] This section provides a general overview of this disclosure and is not a full disclosure of its entire scope or all its features and advantages.

[0005] The purpose of this disclosure is to provide a memory device and a method of operating the memory device, which address and overcome the disadvantages discussed herein.

[0006] Therefore, one aspect of this disclosure is to provide a memory device including memory cells, each memory cell being connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The plurality of data states includes a highest data state, in which the threshold voltage of the memory cell associated with the highest data state is higher than the threshold voltage for the other data states among the plurality of data states. A control unit is configured to apply each of a series of programming pulses of a programming voltage to a selected word line among the plurality of word lines during each programming cycle of a plurality of programming cycles of a programming operation, followed by verification pulses of a plurality of programming verification voltages each associated with one of the data states among the plurality of data states, to program and verify the memory cell connected to the selected word line. The control unit is also configured to skip verification of the memory cell targeting at least one of the other data states among the plurality of data states in at least one programming cycle of the plurality of programming cycles.

[0007] According to another aspect of this disclosure, a controller for communicating with a memory device is also provided. The memory device includes memory cells, each connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The plurality of data states includes a highest data state, in which the threshold voltage of the memory cell associated with the highest data state is higher than the threshold voltage for the other data states among the plurality of data states. The controller is configured to instruct the memory device to apply each of a series of programming pulses of a programming voltage to a selected word line among the plurality of word lines during each programming cycle of a plurality of programming cycles of a programming operation, followed by verification pulses of a plurality of programming verification voltages each associated with one of the data states among the plurality of data states, to program and verify the memory cell connected to the selected word line. The controller is further configured to instruct the memory device to skip verification of the memory cell targeting at least one of the other data states among the plurality of data states in at least one programming cycle of the plurality of programming cycles.

[0008] According to an additional aspect of this disclosure, a method of operating a memory device is provided. The memory device includes memory cells, each memory cell being connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The plurality of data states includes a highest data state, in which the threshold voltage of the memory cell associated with the highest data state is higher than the threshold voltage for other data states among the plurality of data states. The method includes the steps of: applying each of a series of programming pulses of a programming voltage to a selected word line among the plurality of word lines during each programming cycle of a plurality of programming cycles of programming operation, followed by verification pulses of a plurality of programming verification voltages each associated with one of the data states among the plurality of data states, to program and verify the memory cell connected to the selected word line. The method further includes the step of: skipping verification of the memory cell targeting at least one of the other data states among the plurality of data states in at least one programming cycle of the plurality of programming cycles.

[0009] Further applicable fields will become apparent from the description provided herein. The descriptions and specific examples in this invention are intended for illustrative purposes only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0010] The accompanying drawings described herein are for illustrative purposes only, representing selected embodiments rather than all possible specific implementations, and are not intended to limit the scope of this disclosure.

[0011] Figure 1A These are block diagrams of example memory devices based on various aspects of this disclosure;

[0012] Figure 1B It is a block diagram of an example control circuit according to various aspects of this disclosure;

[0013] Figure 2 The various aspects described in this disclosure are as follows. Figure 1A A block of memory cells in an example two-dimensional configuration of a memory array;

[0014] Figure 3A and Figure 3B A cross-sectional view of an example floating gate memory cell in a NAND string according to various aspects of this disclosure is depicted.

[0015] Figure 4A and Figure 4B A cross-sectional view of an example charge-trapping memory cell in a NAND string according to various aspects of this disclosure is depicted.

[0016] Figure 5 The various aspects described in this disclosure are as follows. Figure 1A Example block diagram of sensing block SB1;

[0017] Figure 6A Based on all aspects of this disclosure Figure 1A A perspective view of a set of blocks in an example three-dimensional configuration of a memory array;

[0018] Figure 6B The various aspects described in this disclosure are as follows. Figure 6A An example cross-sectional view of a portion of one of the blocks;

[0019] Figure 6C The various aspects described in this disclosure are as follows. Figure 6B A diagram showing the diameter of the storage holes in the stack;

[0020] Figure 6D The various aspects described in this disclosure are as follows. Figure 6B A close-up view of the stacked area 722;

[0021] Figure 7A The various aspects described in this disclosure are as follows. Figure 6B A top view of the stacked example wordline layer WLL0;

[0022] Figure 7B The various aspects described in this disclosure are as follows. Figure 6B A top view of the stacked example top dielectric layer DL19;

[0023] Figure 8A The various aspects described in this disclosure are as follows. Figure 7A Example NAND strings in sub-blocks SBa to SBd;

[0024] Figure 8B Another example view depicting a NAND string in a sub-block according to various aspects of this disclosure;

[0025] Figure 9 The distribution of Vth of data states in an MLC memory system according to various aspects of this disclosure is illustrated;

[0026] Figure 10 The distribution of Vth of data states in a TLC memory system according to various aspects of this disclosure is illustrated;

[0027] Figure 11 The distribution of Vth of data states in a QLC memory system according to various aspects of this disclosure is illustrated;

[0028] Figure 12 An example is illustrated by the Vth distribution of the data state in a faulty memory block of a TLC memory system that has been programmed prior to verification, according to various aspects of this disclosure;

[0029] Figure 13 The voltage versus time of the control gate of a selected word line applied to a good memory block during programming is depicted according to various aspects of this disclosure.

[0030] Figure 14 The voltage versus time of the control gate of a selected word line applied to a faulty memory block during programming is depicted according to various aspects of this disclosure.

[0031] Figure 15 A flowchart illustrating the steps of programming a memory cell for a selected word line according to various aspects of this disclosure is provided.

[0032] Figure 16A and Figure 16B The sequence of parts of the programming operations, including those that skipped and those that did not skip the highest data state verification, is shown according to various aspects of this disclosure;

[0033] Figure 17A and Figure 17B The sequence of parts of the programming operations, including those that skip and do not skip B data state verification, is shown according to various aspects of this disclosure;

[0034] Figure 18 The following three modes are shown according to various aspects of this disclosure: the prior art that skips only the verification of the highest data state, the first mode that skips the verification of the two lower data states, and the second mode that skips the verification of the four lower data states.

[0035] Figure 19 The diagram shows the relationship between the number of programming loops required to complete programming of the initial data state N, the second-level data state N+1, and the third-level data state N+2, and the bit scan through the failure bits, according to various aspects of this disclosure.

[0036] Figure 20 It is a diagram of the threshold voltage distribution of the three-layer cell for different bit scans through the failure bit, according to various aspects of this disclosure;

[0037] Figure 21 This is a comparison made according to various aspects of this disclosure between relaxed bit scanning through failure bits and using stop refinement when the predetermined number is set to two; and

[0038] Figure 22 The steps of a method for operating a memory device according to various aspects of this disclosure are illustrated.

[0039] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the figures. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0040] In the following description, details are set forth to provide an understanding of this disclosure. In some instances, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure this disclosure.

[0041] Generally, this disclosure relates to a type of nonvolatile memory device well suited for use in many applications. The nonvolatile memory devices and associated methods of operation of this disclosure will be described in conjunction with one or more example embodiments. However, the specific example embodiments disclosed are provided only to sufficiently clearly describe the inventive concepts, features, advantages, and purposes to allow those skilled in the art to understand and practice this disclosure. Specifically, example embodiments are provided so that this disclosure will be comprehensive and will fully communicate the scope to those skilled in the art. Numerous specific details (such as examples of specific components, apparatus, and methods) are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that specific details are not required, example embodiments may be embodied in many different forms, and should not be construed as limiting the scope of this disclosure. In some example embodiments, well-known processes, well-known apparatus structures, and well-known technologies are not described in detail.

[0042] In some memory devices or apparatuses, memory cells are joined together in NAND strings, such as in blocks or sub-blocks. Each NAND string comprises a plurality of memory cells connected in series between one or more drain-side selected-gate SG transistors (SGD transistors) connected in series on the drain side of the NAND string's connection bit line and one or more source-side selected-gate SG transistors (SGS transistors) connected in series on the source side of the NAND string's connection bit line. Furthermore, the memory cells may be arranged with a common control gate line (e.g., a word line) that acts as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells may be connected in other types of strings and in other ways.

[0043] In a 3D memory architecture, memory cells can be arranged in a vertical string in a stack, wherein the stack includes alternating conductive and dielectric layers. The conductive layers act as word lines connecting to the memory cells. Memory cells may include data memory cells eligible to store user data, and dummy or non-data memory cells ineligible to store user data.

[0044] Before programming certain non-volatile memory devices, memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gate of the memory cell being erased. Alternatively, the erase operation removes electrons from the charge trapping layer.

[0045] Each memory cell can be associated with a data state based on the data written in the programming command. Based on its data state, the memory cell will remain in an erase state or be programmed to a programmed data state. For example, in a three-bit memory device, there are eight data states, including erase and programmed states.

[0046] During the programming operation, memory cells are programmed according to the word line programming order. For example, programming may begin at the word line on the source side of the block and proceed to the word line on the drain side of the block. In one approach, each word line is fully programmed before the next word line is programmed. For example, the first word line WL0 is programmed using one or more programming pulses until programming is complete. Next, the second word line WL1 is programmed using one or more programming pulses until programming is complete, and so on. The programming pulses may include a set of increasing programming voltages applied to the word lines in corresponding programming cycles or program-verify iterations. A verification operation or verification phase may be performed after each programming voltage to determine whether the memory cell has been fully programmed. When programming of a memory cell is complete, further programming of it may be prevented, while programming of other memory cells continues in subsequent programming cycles. The final verification step for verifying the last data state may be skipped, and programming may be completed even if verification fails. However, typically only verification of the last data state or the highest data state is skipped.

[0047] Figure 1A This is a block diagram of an example memory device. Memory device 100 may include one or more memory dies 108. Memory die 108 includes a memory structure 126 of memory cells (such as a memory cell array), control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable by word lines via row decoder 124 and by bit lines via column decoder 132. Read / write circuitry 128 includes multiple sensing blocks SB1, SB2…SBp (sensing circuitry) and allows parallel reading or programming of a page of memory cells. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0048] Memory structure 126 can be two-dimensional or three-dimensional. Memory structure 126 may include one or more memory cell arrays comprising a three-dimensional array. Memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory stages are formed on (rather than in) a single substrate (such as a wafer), without intermediate substrates. Memory structure 126 may include any type of non-volatile memory monolithically formed in one or more physical stages of a memory cell array having active regions disposed above a silicon substrate. Memory structure 126 may reside in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is above or within the substrate.

[0049] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0050] Storage region 113 may be provided, for example, for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, and / or verification voltage, etc. Location parameters may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, and / or the location of the memory cell on a specific plane, etc. Contact connector thickness parameters may indicate the thickness of the contact connector and / or the substrate or material constituting the contact connector, etc.

[0051] The on-chip address decoder 114 provides an address interface between the addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. It may include drivers for word lines, SGS transistors, SGD transistors, and source lines. In one approach, the sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0052] In some implementations, some components may be combined. In various designs, one or more components (individually or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2...SBp, read / write circuit 128, controller 122, etc.

[0053] The control circuitry may include programming circuitry configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of the plurality of data states; the programming and verification operations include a plurality of programming and verification iterations; and in each programming and verification iteration, the programming circuitry performs programming on a selected word line, after which the programming circuitry applies a verification signal to the selected word line. The control circuitry may also include a counting circuit configured to obtain a count of memory cells that pass a verification test for one data state. The control circuitry may also include a determining circuit configured to determine a specific programming and verification iteration among the plurality of programming and verification iterations based on an amount by which the count exceeds a threshold, in which a verification test for another data state is performed on the memory cells assigned to represent another data state.

[0054] For example, Figure 1B This is a block diagram of an example control circuit 150, including a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0055] The off-chip controller 122 may include a processor 122c, storage devices (memory) (such as ROM 122a and RAM 122b), and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques presented herein reduce the likelihood of uncorrectable errors.

[0056] Storage devices 122a and 122b include code such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c may access the code from storage device 126a of memory structure 126 (such as a reserved area of ​​memory cells in one or more word lines). For example, the code may be used by controller 122 to access memory structure 126, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes controller 122 during a boot or startup process and enables controller 122 to access memory structure 126. This code may be used by controller 122 to control one or more memory structures 126. Upon power-up, processor 122c retrieves boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM 122b, it can be executed by processor 122c. The control code includes drivers for performing basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0057] Typically, control code may include instructions to perform the functions described herein (including the steps in the flowcharts discussed further below) and to provide those voltage waveforms, including those discussed further below.

[0058] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory communicating with the one or more processors, one or more input / output interfaces, and / or one or more input / output devices.

[0059] Other types of non-volatile memory besides NAND flash memory can also be used.

[0060] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) devices or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0061] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements (such as antifuse or phase-change materials) and optionally manipulation elements (such as diodes or transistors). Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0062] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND string is an example of a group of transistors connected in series, including memory cells and SG transistors.

[0063] NAND memory arrays can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0064] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single planar level or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory element (e.g., in an xy-direction plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory element after the memory element has been formed. As a non-limiting example, the substrate may include a semiconductor (such as silicon).

[0065] Memory elements can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines (such as bit lines and word lines).

[0066] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y and z directions, where the z direction is generally perpendicular to the main surface of the substrate, and the x and y directions are generally parallel to the main surface of the substrate).

[0067] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., along the y-direction), each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xy-plane) to produce a three-dimensional arrangement of memory elements with multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0068] As a non-limiting example, in a three-dimensional NAND string array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR and ReRAM configurations.

[0069] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers located at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor (such as silicon). In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the underlying memory device class of the array. However, layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or intermediate layers may be present between memory device classes.

[0070] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on individual substrates and then stacking the memory stages on top of each other. The substrate can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on individual chips and then packaged together to form a stacked chip memory device.

[0071] Figure 2 Schematic diagrams illustrating three types of memory architectures utilizing interleaved memory strings are shown. For example, reference numeral 201 shows a schematic diagram of a first example memory architecture, reference numeral 203 shows a schematic diagram of a second example memory architecture, and reference numeral 205 shows a schematic diagram of a third example memory architecture. In some embodiments, as shown, the memory architecture may include an interleaved NAND string array.

[0072] Figure 2 Examples Figure 1A The memory array 126 includes blocks 200 and 210 of memory cells in an example two-dimensional configuration. The memory array 126 may include a plurality of such blocks 200 and 210. Each example block 200, 210 includes multiple NAND strings and corresponding bit lines, such as BL0, BL1, etc., which are shared between blocks. Each NAND string is connected at one end to a drain-side selected gate (SGD), and the control gate of the drain-side selected gate is connected via a common SGD line. The NAND string is connected at its other end to a source-side selected gate (SGS), which is in turn connected to a common source line 220. Sixteen word lines (e.g., WL0 to WL15) extend between the SGS and the SGD. In some cases, dummy word lines that do not contain user data may also be used in the memory array adjacent to the selected gate transistor. Such dummy word lines can shield edge data word lines to protect them from certain edge effects.

[0073] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory, such as... Figure 3A and Figure 3B The type shown. However, other types of non-volatile memory can also be used. As discussed in further detail below, in Figure 4A and Figure 4B In another example shown, the charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a limited area. The stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0074] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across a channel between the source and drain. The charge of one data bit is located in the dielectric layer adjacent to the drain, and the charge of the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0075] Figure 3A A cross-sectional view of example floating-gate memory cells 300, 310, and 320 in a NAND string is illustrated. In this figure, the bit lines or NAND string direction extends perpendicularly into the page, and the word line direction is from left to right. As an example, word line 324 extends across the NAND string including corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is located in a different corresponding NAND string. An inter-silicon dielectric (IPD) layer 328 is also illustrated. Control gates 302, 312, and 322 are portions of the word lines. exist Figure 3B A cross-sectional view along the contact line connector 329 is provided.

[0076] Control gates 302, 312, and 322 surround floating gates 304, 314, and 321, thereby increasing the surface contact area between control gates 302, 312, and 322 and floating gates 304, 314, and 321. This results in higher IPD capacitance, leading to a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices scale down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, resulting in almost no space between two adjacent floating gates 302, 312, and 322 for control gates 302, 312, and 322 and the IPD layer 328.

[0077] As an alternative, such as Figure 4A and Figure 4B As shown, planar or flat memory cells 400, 410, and 420 have been developed, wherein control gates 402, 412, and 422 are planar or flat; that is, the control gate does not surround the floating gate and only contacts the charge storage layer 428 from above. In this case, having a high floating gate offers no advantage. Instead, the floating gate is fabricated to be thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0078] Figure 4A A cross-sectional view of example charge-trapping memory cells 400, 410, and 420 in a NAND string is depicted. This view is taken in the word line direction of memory cells 400, 410, and 420, including the flat control gate and charge-trapping region. Figure 1A A two-dimensional example of memory cells 400, 410, and 420 in the memory cell array 126. Charge-trapped memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, in contrast to floating-gate MOSFET technology which uses a conductor such as doped polysilicon to store electrons. As an example, word line 424 extends across a NAND string including corresponding channel regions 406, 416, and 426. Various portions of the word line provide control gates 402, 412, and 422. Below the word line are an IPD layer 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge-trapping layer 404, 414, and 421 extends continuously within its corresponding NAND string. The flat configuration of the control gate can be thinner than that of a floating gate. Additionally, the memory cells can be placed more closely together.

[0079] Figure 4B Examples Figure 4AThe structure is shown in a cross-sectional view along the contact connector 429. The NAND string 430 includes an SGS transistor 431, example memory cells 400, 433…435, and an SGD transistor 436. Channels in the IPD layer 428 of the SGS transistor 431 and SGD transistor 436 allow communication between the control gate layer 402 and the floating gate layer. For example, the control gate 402 and the floating gate layer may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0080] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. The channel voltage Vch can be directly applied to the channel region of the substrate.

[0081] Figure 5 Examples Figure 1A An example block diagram of a sensing block SB1 is provided. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with this group of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible approach, the voltage is provided to each sensing circuit independently, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include the precharge circuit 561, a memory 562, and a processor 563. Memory 562 may store code that can be executed by a processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, 553b associated with sensing circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing voltage to set precharge levels in the sensing nodes of sensing circuits 550a, 551a, 552a, 553a. Further example details of the sensing circuit controller 560 and sensing circuits 550a, 551a, 552a, 553a are provided below.

[0082] In some implementations, a memory cell may include a flag register comprising a set of latches storing flag bits. In some implementations, the number of flag registers may correspond to the number of data states. In some implementations, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some implementations, the output of the flag bits may modify relevant logic of the device (e.g., address decoding circuitry) such that a specified cell block is selected. Batch operations (e.g., erase operations, etc.) may be performed using flags set in the flag registers or a combination of flag registers and address registers (as in implicit addressing) or alternatively by direct addressing using only address registers.

[0083] Figure 6A yes Figure 1A This is a perspective view of a set of blocks 600 in an example three-dimensional configuration of a memory array 126. On the substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, this circuitry may include a voltage driver 605, which may be connected to the control gate layer of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layers at a common height in blocks BLK0, BLK1, BLK2, and BLK3 are commonly driven. The substrate 601 may also carry circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, as well as one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a central region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block BLK0, BLK1, BLK2, BLK3 includes a stacked region of memory cells, where alternating stacked levels represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides from which vertical contacts extend upwards to the upper metal layer to form connections to the conductive paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are shown as an example, two or more blocks extending in the x and / or y directions can be used.

[0084] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0085] Figure 6B Examples Figure 6A An example cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, regions of stack 610 including NAND strings NS1 and NS2 are illustrated. Each NAND string includes memory holes 618 and 619 filled with material forming memory cells adjacent to the word lines. Region 622 of stack 610 is... Figure 6D This is shown in more detail below and discussed further in detail.

[0086] Stack 610 includes a portion of source line SL, substrate 611, and insulating film 612 on substrate 611. NS1 has a source end 613 located at the bottom 614 of the stack and a drain end 615 located at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be periodically provided across stack 610 as interconnects extending through stack 610, such as to connect source lines to specific contact lines above stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently metal-filled. A portion of bit line BL0 is also shown. Conductive via 621 connects drain end 615 to BL0.

[0087] Figure 6C Examples Figure 6B A graph showing the diameter of the storage holes in the stack. The vertical axis is... Figure 6B The stack alignment is shown, and the width (wMH) of storage holes 618 and 619 is illustrated, for example, the diameter. Figure 6A Word line layers WLL0 to WLL10 are repeated as an example and are located at corresponding heights z0 to z10 in the stack. In this memory device, the memory vias etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of about 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory via can vary along the length of the via. Typically, the diameter gradually decreases from the top to the bottom of the memory via. That is, the memory via is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the via near the select gate, causing the diameter to widen slightly before gradually decreasing from the top to the bottom of the memory via.

[0088] Due to the non-uniformity of via width, the programming speed (including programming slope and erase speed) of a memory cell can vary based on its location along the via (e.g., based on its height in the stack). For smaller diameter vias, the electric field across the tunnel oxide is relatively strong, resulting in relatively high programming and erase speeds. One approach is to define groups of adjacent word lines with similar via diameters (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line in the group. Different groups can have different optimized verification schemes.

[0089] Figure 6D Examples Figure 6B A close-up view of region 622 of stack 610. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680, 681 are disposed above dummy memory cells 682, 683 and data memory cell MC. Multiple layers may be deposited along the sidewalls (SW) of memory via 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory via 630) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. Word line layers may include a blocking oxide / bulk high-k material 660, a metal blocking layer 661, and a conductive metal 662 (such as tungsten) serving as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are disposed within memory via 630. In other methods, some layers can be formed within the control gate layer. Similarly, additional pillars are formed in different memory vias. These pillars can form pillared active regions (AA) of the NAND string.

[0090] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0091] Each memory via 630 may be filled with a plurality of annular layers, including a barrier oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. The core region of each memory via 630 is filled with a host material, and the plurality of annular layers are located between the core region and the word line in each memory via 630.

[0092] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0093] Figure 7A Examples Figure 6B A top view of an example word line layer WLL0 of stack 610. As described above, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the word line layer. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0094] In a three-dimensional memory device, a block BLK can be divided into sub-blocks, each sub-block comprising a group of NAND strings with a common SGD control line. See, for example, the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. Furthermore, the word line layer within the block can be divided into multiple regions. Each region is within a corresponding sub-block and can extend between contact line connectors (e.g., slots) periodically formed in a stack to process the word line layer during the manufacturing process of the memory device. This processing may include replacing the sacrificial material of the word line layer with metal. Generally, the distance between the contact line connectors should be relatively small to account for the distance limitations on the etchant's ability to travel laterally to remove the sacrificial material, and the distance limitations on the metal's ability to travel to fill the voids created by the removal of the sacrificial material. For example, the distance between the contact line connectors may allow for several rows of memory vias between adjacent contact line connectors. The layout of the memory vias and contact line connectors should also consider limitations on the number of bit lines that can extend across the region, while each bit line is connected to a different memory cell. After processing the word line layer, the contact line connectors may optionally be filled with metal to provide interconnects across the stack.

[0095] In this example, there are four rows of memory holes between adjacent contact line connectors. Here, a row is a set of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the density of the memory holes. The word line layer or word line is divided into regions WLL0a, WLL0b, WLL0c, and WLL0d, each connected by contact line 713. In one method, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 713 is in turn connected to a voltage driver for the word line layer. Region WLL0a has example memory holes 710, 711 along contact line 712. Region WLL0b has example memory holes 714, 715. Region WLL0c has example memory holes 716, 717. Region WLL0d has example memory holes 718, 719. The memory holes are also... Figure 7BAs shown in the diagram. Each storage hole can be part of the corresponding NAND string. For example, storage holes 710, 714, 716, and 718 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0096] Each circle represents a cross-section of a memory via at a word line layer or SG layer. Example circles shown in dashed lines represent memory cells provided by the material in the memory via and adjacent word line layers. For example, memory cells 820 and 821 are in WLL0a, memory cells 824 and 825 are in WLL0b, memory cells 826 and 827 are in WLL0c, and memory cells 828 and 829 are in WLL0d. These memory cells are at a common height in the stack.

[0097] Contact line connectors (e.g., slots, such as metal-filled slots) 801, 802, 803, 804 may be located between and adjacent to the edges of regions WLL0a to WLL0d. Contact line connectors 801, 802, 803, 804 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where this conductive line is connected to a voltage driver in a peripheral region of the memory device.

[0098] Figure 8B Examples Figure 7B The image shows a top view of the top dielectric layer DL19 of the stack. The dielectric layer is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in a region of the word line layer to be programmed simultaneously, with each memory cell located in a corresponding NAND string connected to the corresponding bit line. A voltage can be set on each bit line to enable or disable programming during each programming voltage.

[0099] Region DL19a has example memory holes 710, 711 along contact lines 712 coinciding with bit line BL0. Multiple bit lines extend above and are connected to the memory holes, as indicated by the "X" symbol. BL0 is connected to a set of memory holes including memory holes 711, 715, 717, and 719. Another example bit line BL1 is connected to a set of memory holes including memory holes 710, 714, 716, and 718. Figure 7A Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 are also shown, extending vertically through the stack. Bit lines may cross the DL19 layers in the x-direction, numbered sequentially from BL0 to BL23.

[0100] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in the adjacent row of cells adjacent to the first row at the left edge.

[0101] The memory unit can be programmed to be 2 n Each data state is stored in multiple bits, where n is a positive integer. For example, such as Figure 9 As shown, in each two-bit memory device (MLC), there are four data states, including an erase state and three programming data states (S1, S2, and S3). Figure 10 As shown, in each three-cell memory device (TLC), there are eight data states, including an erase state and seven programming data states (S1, S2, S3, S4, S5, S6, and S7). Figure 11 As shown, there are sixteen data states in each cell of a four-bit memory device (QLC), including erase state and fifteen programming data states (S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15).

[0102] Generally, programming operations may involve applying a pulse train to selected word lines, where the pulse train comprises multiple programming loops or programming-verification iterations. The programming portion of a programming-verification iteration includes Vpgm pulses, and the verification portion includes one or more verification pulses. The programming operation of an exemplary embodiment is configured to operate in two modes: a first mode (STPFINE enabled) for good strings, where verification pulses are skipped in the final programming-verification iteration; and a second mode (STPFINE disabled) for suspected bad strings, in which verification pulses are not skipped and programming continues until a failure is determined or until programming is complete. For bad memory blocks that may have leaky memory holes, the controller automatically adopts the second mode (STPFINE disabled).

[0103] Figure 13The diagram depicts a waveform or pulse train 1300 used to program three-bit data (TLC) into each memory cell of a selected word line according to a first mode (STPFINE enabled). The horizontal axis depicts time, and the vertical axis depicts the control gate or word line voltage. For simplicity, a square wave waveform is depicted for each pulse; however, other shapes are possible, such as multi-stage or ramp shapes. Furthermore, incremental step pulse programming (ISPP) is used in this example, where the Vpgm pulse amplitude gradually increases in each successive programming cycle. This example uses ISPP in a single programming pass in which programming is completed. ISPP can also be used in any one or two programming passes of multi-pass operation.

[0104] The pulse train comprises Vpgm pulses whose amplitude increases progressively with each program-verify iteration in fixed step sizes (dVpgm). A new pulse train begins at an initial Vpgm pulse level and ends at a final Vpgm pulse level not exceeding the maximum permissible level. In this example, pulse train 1300 comprises a total of twelve program-verify iterations, and therefore includes a series of twelve Vpgm pulses 1302, 1304, 1306, 1308, 1310, 1312, 1314, 1316, 1318, 1320, and 1322, which are applied to a selected word line comprising a set of non-volatile memory cells. For example, in each program-verify iteration, based on the target memory state being verified, one, two, three, or more verification voltage pulses are provided after each Vpgm pulse. A 0V voltage can be applied to the selected word line between the Vpgm pulses and the verification voltage pulses.

[0105] exist Figure 13 In the first two programming-verification iterations following each of the first Vpgm pulse 1302 and the second Vpgm pulse 1304, a verification voltage Vv1 is applied (see [link to program / verification]). Figure 10 The programmable state (S1) is used to verify the memory cell being programmed into data state S1. A verification voltage Vv2 is applied in each of the first three programming-verification iterations following the first three Vpgm pulses 1302, 1304, and 1306. A verification voltage Vv3 is applied in the second, third, and fourth programming-verification iterations following Vpgm pulses 1304, 1306, and 1308. This process continues until the tenth programming-verification iteration, where the programming of data states S1 through S6 is complete, and only the last data state (S7) remains. Therefore, the preceding data states (S1 through S6) are programmed through programming-verification iterations, each iteration consisting of a programming pulse and one or more verification pulses.

[0106] In the tenth and eleventh programming cycles, a verification voltage Vv7 is applied after Vpgm pulses 1320 and 1322. However, in the twelfth programming-verification iteration, no verification voltage is applied after Vpgm pulse 1324. In other words, verification is skipped in the twelfth programming-verification iteration to shorten tProg. In this embodiment, the controller is configured to automatically verify the S7 data state for no more than three programming-verification iterations after programming the S6 data state is complete, and then skip verification in the third programming-verification iteration. In some embodiments, the number of programming-verification iterations used to verify the S7 data state after programming S6 is complete may be more or less than two, and verification will still be skipped in whichever programming-verification iteration is the last programming-verification iteration.

[0107] Figure 14 Depicting something similar to Figure 13 The pulse train is pulse train 1400, but the controller in it is in the second mode (STPFINE disabled). In this pulse train, the twelfth programming-verification iteration does indeed include a verification pulse, and may include an additional programming loop after the twelfth programming loop to complete the programming of the last data state (S7). Programming can continue by continuing to verify the S7 data state to prevent errors. Figure 12 The threshold voltage distribution of the S7 data state shown exhibits a long lower tail, or continues until programming fails. Preventing this from happening reduces the risk of programming errors and corresponding data loss. These benefits can be achieved without any time-consuming EPWR operations.

[0108] exist Figure 13 and Figure 14 In the embodiments described, the programming operation involves programming the memory cells as a TLC. However, these techniques are also applicable to MLCs, QLCs, or PLCs (five bits per memory cell).

[0109] See now Figure 15The figure depicts a flowchart illustrating the steps of an exemplary method for programming a selected word line of a memory device. At step 1500, all preceding data states (i.e., all data states except the last data state with the highest threshold voltage) are programmed using an ISPP programming operation, where each program-verify iteration includes one or more verification pulses. In this embodiment, the memory cell is programmed as a TLC, and data states S1 through S6 are programmed at step 1500. Also at step 1500, a total loop counter (Total_Loop) is maintained and the total number of program-verify iterations in the programming operation is counted, and an extra loop counter (Extra_Loop) is set to zero. Total_Loop starts at the beginning of the programming operation and increments with each program-verify iteration throughout the entire programming operation (including programming the last data state, discussed below).

[0110] At step 1502, a programming pulse (Vpgm) is applied to the control gate of the selected word line to program the S7 data state. Also at step 1502, the Total_Loop and Extra_Loop counters are incremented (Total_Loop = Total_Loop + 1 and Extra_Loop = Extra_Loop + 1).

[0111] At decision step 1504, it is determined whether the first programming mode is even enabled, in which verification can be skipped in the last programming-verification iteration if the memory block is a good memory block.

[0112] If the answer at decision step 1504 is no (i.e., only the second mode is enabled, in which each programming-verification iteration includes verification), the method proceeds to step 1506. At step 1506, the S7 data state is verified. Specifically, a verification pulse is applied to the control gate of the selected word line to determine whether the memory cell of the selected word line being programmed into the S7 data state has a threshold voltage greater than the verification pulse. The method then proceeds to decision step 1508.

[0113] At decision step 1508, it is determined whether the S7 data state has passed verification. This is achieved by comparing the number of memory cells that failed the verification operation with a predetermined failure bit count (FBC).

[0114] If the answer at decision step 1508 is yes, then at step 1510, the programming passes and the programming operation is completed. If the answer at decision step 1508 is no (verification of the S7 data state fails), then the method proceeds to decision step 1512.

[0115] At decision step 1512, determine whether Total_Loop is less than the predetermined maximum number of programming-verification iterations (Max_Loop).

[0116] If the answer at decision step 1512 is no, then at step 1514, programming fails and the programming operation completes. If the answer at decision step 1512 is yes, then the method returns to step 1502 to begin the next programming-verification iteration.

[0117] If the answer at decision step 1504 is yes, the method proceeds to decision step 1516. At decision step 1516, it is determined whether Total_Loop is less than a first predetermined threshold number (NLP_Smart) of loops available in the first mode. NLP_Smart can be set to any suitable level capable of distinguishing between good and bad strings. For example, if a good string should complete the programming of the S7 data state within no more than twelve (12) programming-verification iterations, then NLP_Smart can be set to twelve (12) such that if programming continues after the twelfth programming-verification iteration, the memory block must be a bad block and verification should not be skipped. Thus, decision step 1516 effectively determines whether the memory block being programmed is a good or bad string.

[0118] If the answer at decision step 1516 is no, the memory block is determined to be a suspected bad string, and the method proceeds to step 1506 to verify the S7 data status, thereby ensuring that programming will only pass if the verification passes.

[0119] If the answer at decision step 1516 is yes, the method proceeds to decision step 1518. At decision step 1518, it is determined whether Extra_Loop is less than the second predetermined threshold number (PROCOMP_F+n) of programming-verification iterations to be performed after programming the S6 data state is complete. Figure 13 In the exemplary programming operation described, PROCOMP_F+n is three (3), such that programming of the S6 data state is completed after the ninth programming-verification iteration, and the twelfth programming-verification iteration is the final programming-verification iteration. In other embodiments, PROCOMP_F+n may be greater than or less than three (3).

[0120] If the answer at decision step 1518 is (Extra_Loop≤PROCOMP_F+n), then the method proceeds to step 1506 to verify the S7 data status.

[0121] If the answer at decision step 1518 is no (Extra_Loop≥PROCOMP_F+n), then at step 1510, it is determined that the programming operation has passed and been completed.

[0122] Figure 15 The described programming operations shorten tProg by skipping the last verification operation on good memory blocks, while reducing programming errors by allowing verification of bad strings to continue until programming passes or fails. A similar process can be followed for MLC, QLC, or PLC programming. This type of verification skipping is called "Stop Fine-tuning" (STPFINE).

[0123] As discussed earlier, during a full-sequence programming operation of a three-level cell (TLC), a verification operation is performed after each programming pulse to determine whether the cell should be subjected to full-intensity programming, QPW programming, or programming-inhibited. Since programming verification constitutes a significant portion of the programming time tProg, the number of programming verification operations needs to be kept as low as possible to achieve high programming performance. However, as mentioned above, typically only the last data state or the highest data state is skipped. Figure 10 and Figure 12 The verification operation for the S7 data state (also known as the G data state) is performed. Specifically, the timing for stopping the verification of a specific data state (state_n) is determined by a bit scan of the verification result. Once the number of remaining cells below the verification level for that data state is sufficiently low, state_n programming is considered complete, and therefore not verified in the next programming cycle. For the G data state of TLC, there is a special case where, after the F state is completed, the maximum number of programming cycles defined by the parameter F_STPFINE is allowed to complete the G data state programming. For example, when F_STPFINE = enabled, after the F data state has been programmed and verified, no more than two additional programming pulses are allowed to complete the G data state programming. Figure 16A and Figure 16B The diagram shows where skipping (disabling STPFINE) is shown. Figure 16B ) and not skipped ( Figure 16AThe sequence of parts of the programming operation for the highest data state verification. When STPFINE is disabled, it can be assumed that two additional programming pulses are required to complete the G data state programming after the F data state is completed. Since the bit scan occurs during the period known as the P clock in the programming operation, the G data state memory cell receives a third programming pulse. The third programming pulse will program memory cells below the verification level, although the actual number is less than the BSPF (bit scan pass / fail) threshold. With F_STPFINE = enabled, no more than two additional programming pulses are allowed to complete the G data state after the F data state is completed, and no verification is performed after programming pulse N+2. In this example, one verification and one programming cycle are saved (see...). Figure 16A and Figure 16B If there are still some G data state memory cells below the verification level VH after the second programming pulse is enabled, there may be some F data state to G data state (F2G) margin penalty when F_STPFINE is enabled. If there are no G data state memory cells below the verification level VH after the second programming pulse is enabled, there is no penalty when F_STPFINE is enabled. In some memory devices, the incremental programming voltage DVPGM or step size is larger than the incremental control gate voltage VCGRV or threshold voltage between two adjacent states, so it is highly certain that state n+1 can be completed within two additional programming pulses after state n is programmed and verified.

[0124] Therefore, this paper describes a memory device (e.g., Figure 1A The memory device 100 includes memory cells (e.g., memory storage devices). Figure 6D The data memory unit MC and virtual memory units 682, 683), each memory unit is connected to multiple word lines (e.g., Figure 6B One of the word lines in the word line layers WLL0 to WLL10) and configured to maintain a threshold voltage (e.g., ) corresponding to one of the multiple data states. Figures 9 to 12 Multiple data states include the highest data state (e.g., Figure 10 and Figure 12 The S7 data state (also known as the G data state) is the highest data state in which the threshold voltage of the memory cell associated with this highest data state is higher than that of other data states (e.g., ...). Figure 10 and Figure 12 The threshold voltage for the S1 to S6 data states in the memory. The memory device also includes control components (e.g., control circuitry 110, decoder 124 / 132, sensing blocks SBb, SB2…SBp, read / write circuitry 128, etc.). Figure 1AController 122 Figure 1B Control circuit 150 and / or Figure 5 The control unit is configured to apply, during each programming cycle of a plurality of programming cycles, a series of programming pulses of programming voltage to a selected word line of a plurality of word lines, followed by verification pulses of a plurality of programming verification voltages, each associated with a data state of a plurality of data states, to program and verify memory cells connected to the selected word line. The control unit is also configured to skip verification of memory cells targeting at least one of the other data states of the plurality of data states in at least one programming cycle of the plurality of programming cycles. In other words, STPFINE can be extended to lower data states (i.e., not just the highest data state), and each data state can therefore have a parameter similar to F_STPFINE described above, which determines whether verification of that data state should be skipped. By avoiding unnecessary bit scan operations, power consumption can be reduced and performance improved.

[0125] Figure 17A and Figure 17B The example shows where skipping (B_STPFINE = enabled) is shown. Figure 17B ) and not skipped (disabling STPFINE for B, Figure 17A The sequence of programming operations for data status verification (B). Figure 17A As shown, when the scan is complete and the remaining B cells are found to be below the BSPF threshold, another programming pulse is applied (as indicated by the circled number 3). Similar to using STPFINE for the highest data state discussed above, STPFINE avoids applying unnecessary scan operations for lower states (such as the B data state shown). In the example shown, scanning can be skipped or avoided in... Figure 17A and Figure 17B Unnecessary B-verification occurs after the circled number 2. Alternatively, the BSPF can be increased. However, this may be impractical if the number or count of memory cells needs to be very large. (The BSPF can be set so that the bit scan passes one programming pulse ahead of the actually desired standard.) Furthermore, bit scans that would otherwise consume power or potentially degrade gate performance can be avoided.

[0126] According to another aspect of this disclosure, other data states among the plurality of data states include at least one skip verification data state, in which verification of the memory cell targeted by the at least one skip verification data state is skipped in at least one programming loop among the plurality of programming loops (e.g., Figure 17A and Figure 17BThe B data state in the data states). Other data states in the multiple data states also include at least one previous data state (e.g., when at least one skipped verification data state is). Figure 17A and Figure 17B When the data is in the B data state (i.e., the B data state), in the at least one previous data state, the threshold voltage of the memory cell associated with the at least one previous data state is lower than the threshold voltage of the memory cell associated with the at least one skip verification data state. The control unit is also configured to apply a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the at least one skip verification data state after programming and verification of the memory cell targeted by the at least one previous data state is completed.

[0127] Figure 18 The following three modes are shown: the prior art that skips only the verification of the highest data state (i.e., only the verification of data state G), the first mode (mode 1) that skips the verification of the two lower data states, and the second mode (mode 2) that skips the verification of the four lower data states. As discussed above and referenced again... Figure 10 and Figure 12 For example, each memory cell in a memory unit can be configured to store three bits. Therefore, multiple data states, in order of increasing threshold voltage values, include erase data states (…). Figure 10 and Figure 12 Er state) and first data state ( Figure 10 and Figure 12 The S1 data state (also known as the A data state) and the second data state ( Figure 10 and Figure 12 The S2 data state (also known as the B data state) and the third data state ( Figure 10 and Figure 12 The S3 data state (also known as the C data state) and the fourth data state ( Figure 10 and Figure 12 The S4 data state (also known as the D data state) and the fifth data state ( Figure 10 and Figure 12 The S5 data state (also known as the E data state) and the sixth data state ( Figure 10 and Figure 12 The S6 data state (also known as the F data state) and the seventh data state ( Figure 10 and Figure 12 The S7 data state in the data is also known as the G data state. Therefore, the highest data state is the seventh data state. (See reference...) Figure 18(Mode 1) and, according to other aspects, at least one skipped verification data state includes the third data state, the fifth data state, and the seventh data state. Therefore, the control unit is also configured to apply a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the third data state after programming and verification are completed for the memory cell targeted by the second data state. Furthermore, after programming and verification are completed for the memory cell targeted by the fourth data state, the control unit applies a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the fifth data state. The control unit is also configured to apply a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the seventh data state after programming and verification are completed for the memory cell targeted by the sixth data state. Using Mode 1, STPFINE is enabled every other data state, and the risk of underprogramming is minimized when some memory cells are programmed very slowly. In this example, by setting STPFINE to these two lower data states (C data state and E data state) in the lower data states, up to four or more verification cycles can be saved, equivalent to a reduction of approximately 6% in programming time tProg.

[0128] According to another aspect, at least one prior data state includes at least one fully verified data state in which programming and verification of the memory cell targeted by the at least one fully verified data state have been completed. The control unit is also configured to select a predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeted by the at least one skipped verification data state based on the proximity of the threshold voltage of the memory cell targeted by the at least one skipped verification data state and the threshold voltage of the memory cell targeted by the at least one fully verified data state associated with the at least one skipped verification data state. The predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeted by the at least one skipped verification data state decreases as the proximity decreases.

[0129] More specifically, and according to an additional aspect, the predetermined number of programming pulses of the programming voltage applied to the memory cell targeting the at least one skipped verification data state increases in magnitude order, including a first predetermined number, a second predetermined number, and a third predetermined number of programming pulses of the programming voltage. Therefore, the control unit is further configured to apply no more than a first predetermined number of programming pulses of the programming voltage to the memory cell targeting the at least one skipped verification data state after programming and verification have been completed for the memory cell targeting the at least one skipped verification data state, in response to at least one skipped verification data state being immediately adjacent to at least one fully verified data state associated with the at least one skipped verification data state. The control unit is additionally configured to apply no more than a second predetermined number of programming pulses of the programming voltage to the memory cell targeting the at least one skipped verification data state after programming and verification have been completed for the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state, in response to at least one skipped verification data state and at least one fully verified data state being separated by a plurality of data states, in response to at least one skipped verification data state and at least one fully verified data state being associated with the at least one skipped verification data state being completely separated by a data state, in response to at least one skipped verification data state being completely separated from the at least one fully verified data state associated with the at least one skipped verification data state. The control unit is also configured to, in response to two data states separated by a plurality of data states, after programming and verification are completed in a memory cell targeted by at least one fully verified data state associated with at least one skipped verification data state, apply a programming voltage of no more than a third predetermined number of programming pulses to the memory cell targeted by the at least one skipped verification data state.

[0130] refer to Figure 18(Mode 2) And according to other aspects, at least one skipped verification data state includes a second data state, a third data state, a fifth data state, a sixth data state, and a seventh data state. The control unit is also configured to apply a programming voltage of no more than a first predetermined number of programming pulses to the memory cell targeted by the second data state after programming and verification are completed in the memory cell targeted by the second data state. Furthermore, the control unit is configured to apply a programming voltage of no more than a second predetermined number of programming pulses to the memory cell targeted by the third data state after programming and verification are completed in the memory cell targeted by the fourth data state. After programming and verification are completed in the memory cell targeted by the fourth data state, the control unit applies a programming voltage of no more than a first predetermined number of programming pulses to the memory cell targeted by the fifth data state. Furthermore, the control unit is configured to apply a programming voltage of no more than a second predetermined number of programming pulses to the memory cell targeted by the sixth data state after programming and verification are completed in the memory cell targeted by the fourth data state. The control unit is also configured to apply a programming voltage of no more than a third predetermined number of programming pulses to the memory cell targeting the seventh data state after programming and verification are completed in the memory cell targeting the fourth data state. For mode 2, the programming time tProg can be further shortened. By including regular pvfy in the D state, the risk of underprogramming of higher states (E / F / G) is reduced. This method is also compatible with Independent Bit Scan (IBS), which relies on comparing the completion of states such as A and D to check for defects.

[0131] More aggressively, a predetermined number of STPFINEs can be set to one for some WL / string / state, with a controlled tradeoff for threshold voltage margin. This can be applied to memory devices using very large step sizes (i.e., DVPGM), such as for achieving very high performance or performing multi-pass programming (e.g., fuzzy stages in QLC). As discussed earlier, memory cells can be set in memory apertures (e.g., Figure 6D Storage hole 630, Figure 7A and Figure 7B In storage holes 710, 714, 716, and 718). These storage holes are arranged in rows comprising each of the multiple strings. (For example, Figure 7A and Figure 7B Storage holes 710, 714, 716, and 718 are Figure 8A(A portion of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe.) The control unit is also configured to select, in different ways, a predetermined number of programming pulses applied to the programming voltage of the memory cell targeting at least one skip-verification data state for at least one of multiple word lines, multiple strings, or multiple data states.

[0132] Figure 19 This is a graph showing the relationship between the number of programming loops required to complete programming of the initial data state N (e.g., data state E), the second-level data state N+1 (e.g., data state F), and the third-level data state N+2 (e.g., data state G) and the bit scan through the failure bit (BSPF_FV). Figure 20 This is a graph showing the threshold voltage distribution of a three-layer cell (TLC) for different BSPF values. As shown, increasing BSPF_FV does not decrease the threshold voltage Vt-margin. In this example, VH detection is enabled, BSPF_FV is scanned, and STPFINE_G is set to no more than two cycles. As BSPF_FV increases, the E data state completion cycle remains unchanged, while the F data state completion cycle decreases, and the ΔE2F margin becomes 1. However, the tail remains unchanged in the F data state. This data indicates that the STPFINE cycle count (i.e., the predetermined number of STPFINEs) for the F data state after E data state completion programming and verification can be set to two. Simultaneously, since the G data state STPFINE cycle count is equal to two, the G data state completion cycle also decreases. Therefore, the tail is improved in the Er state, while the tail remains unchanged in the G data state. Furthermore, ΔVCGRV_F2G = 1V, and ΔF2G_CompleteLoop does not exceed two. Similarly, the predetermined number of STPFINEs should be set to two for other states while giving minimal consideration to the threshold voltage margin.

[0133] Figure 21 This is a comparison performed between a relaxed bit scan through the failure bit (BSPF_FV) and using STPFINE with the predetermined number set to two. (Followed by...) Figure 19 and Figure 20 The previous example shown can advance the completion of the F data state by relaxing the bit scan through the failure bit (BSPF_FV) or by setting the predetermined number of STPFINEs to two. However, according to Figure 21The BSCAN_Time formula shown indicates that relaxing the BSPF may result in a bit scan time penalty. Specifically, the scan time depends on the number of failed bits. If this number is large (because the allowed BSPF is high), the scan time may also be long. In contrast, using STPFINE may complete the F data state earlier without a bit scan penalty and save one F data state scan, which is beneficial for both programming time tProg and current consumption ICC. Further reductions in tProg can be achieved by setting a predetermined number of STPFINEs to one. Simply relaxing the BSPF cannot do this because the scan operation occurs during the P clock cycle of the next cycle, so the scan result is always only available after one programming pulse.

[0134] Figure 22 The steps of a method for operating a memory device are illustrated. As discussed above, a memory device (e.g., Figure 1A The memory device 100 includes memory cells (e.g., Figure 6D The data memory unit MC and virtual memory units 682, 683), each memory unit is connected to multiple word lines (e.g., Figure 6B One of the word lines in the word line layers WLL0 to WLL10) and configured to maintain a threshold voltage (e.g., ) corresponding to one of the multiple data states. Figures 9 to 12 Multiple data states include the highest data state (e.g., Figure 10 and Figure 12 The S7 data state (also known as the G data state) is the highest data state in which the threshold voltage of the memory cell associated with this highest data state is higher than that of other data states (e.g., ...). Figure 10 and Figure 12 The method includes step 2200: applying each of a series of programming pulses of a programming voltage to a selected word line of a plurality of word lines during each programming cycle of a plurality of programming cycles, followed by verification pulses of a plurality of programming verification voltages each associated with a data state of a plurality of data states, to program and verify memory cells connected to the selected word line. The method also includes step 2202: skipping verification of memory cells targeting at least one of the other data states of the plurality of data states in at least one programming cycle of the plurality of programming cycles.

[0135] Similarly, according to another aspect of this disclosure, other data states among the plurality of data states include at least one skip verification data state, in which verification of the memory cell targeted by the at least one skip verification data state is skipped in at least one programming loop among the plurality of programming loops (e.g., Figure 17A and Figure 17B The B data state in the data states). Other data states in the multiple data states also include at least one previous data state (e.g., when at least one skipped verification data state is). Figure 17A and Figure 17B When the data is in the B data state (i.e., the B data state), in the at least one previous data state, the threshold voltage of the memory cell associated with the at least one previous data state is lower than the threshold voltage of the memory cell associated with the at least one skip verification data state. Therefore, the method further includes the step of: after programming and verification are completed for the memory cell targeted by the at least one previous data state, applying a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the at least one skip verification data state.

[0136] Similarly, refer to again Figure 10 and Figure 12 For example, each memory cell in a memory unit can be configured to store three bits. Therefore, multiple data states, in order of increasing threshold voltage values, include erase data states (…). Figure 10 and Figure 12 Er state) and first data state ( Figure 10 and Figure 12 The S1 data state (also known as the A data state) and the second data state ( Figure 10 and Figure 12 The S2 data state (also known as the B data state) and the third data state ( Figure 10 and Figure 12 The S3 data state (also known as the C data state) and the fourth data state ( Figure 10 and Figure 12 The S4 data state (also known as the D data state) and the fifth data state ( Figure 10 and Figure 12 The S5 data state (also known as the E data state) and the sixth data state ( Figure 10 and Figure 12 The S6 data state (also known as the F data state) and the seventh data state ( Figure 10 and Figure 12 The S7 data state in the data is also known as the G data state. Therefore, the highest data state is the seventh data state. (Refer to previous text) Figure 18(Mode 1) And according to other aspects, at least one skipped verification data state includes a third data state, a fifth data state, and a seventh data state. Therefore, the method further includes the step of: after programming and verification are completed in the memory cell targeted by the second data state, applying a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the third data state. Furthermore, the method further includes the step of: after programming and verification are completed in the memory cell targeted by the fourth data state, applying a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the fifth data state. The method further includes the step of: after programming and verification are completed in the memory cell targeted by the sixth data state, applying a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the seventh data state.

[0137] Similarly, according to another aspect, at least one prior data state includes at least one fully verified data state in which programming and verification of a memory cell targeted by the at least one fully verified data state have been completed. The method further includes the step of selecting a predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeted by the at least one skipped verification data state, based on the proximity of a threshold voltage of a memory cell targeted by at least one skipped verification data state and a threshold voltage of a memory cell targeted by at least one fully verified data state associated with the at least one skipped verification data state. The predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeted by the at least one skipped verification data state decreases as the proximity decreases.

[0138] As discussed above and according to the additional aspect, the predetermined number of programming pulses of the programming voltage applied to the memory cell targeting the at least one skipped verification data state increases in magnitude order including a first predetermined number, a second predetermined number, and a third predetermined number of programming pulses of the programming voltage. Therefore, the method further includes the step of: in response to at least one skipped verification data state being immediately adjacent to at least one fully verified data state associated with the at least one skipped verification data state, after programming and verification are completed in the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state, applying no more than a first predetermined number of programming pulses of the programming voltage to the memory cell targeting the at least one skipped verification data state. The method further includes the step of: in response to at least one skipped verification data state and at least one fully verified data state associated with the at least one skipped verification data state being separated by one of a plurality of data states, after programming and verification are completed in the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state, applying no more than a second predetermined number of programming pulses of the programming voltage to the memory cell targeting the at least one skipped verification data state. The method further includes the following steps: in response to two data states separated by a plurality of data states, namely at least one skip verification data state and at least one full verification data state associated with the at least one skip verification data state, after programming and verification are completed in the memory cell targeted by the at least one full verification data state associated with the at least one skip verification data state, applying a programming voltage of no more than a third predetermined number of programming pulses to the memory cell targeted by the at least one skip verification data state.

[0139] Re-reference Figure 18(Mode 2) And according to other aspects, at least one skipped verification data state includes a second data state, a third data state, a fifth data state, a sixth data state, and a seventh data state. The method further includes the step of: after programming and verification are completed in a memory cell targeted by the second data state, applying a programming voltage of no more than a first predetermined number of programming pulses to the memory cell targeted by the second data state. Furthermore, the method further includes the step of: after programming and verification are completed in a memory cell targeted by the second data state, applying a programming voltage of no more than a second predetermined number of programming pulses to the memory cell targeted by the third data state. The method additionally includes the step of: after programming and verification are completed in a memory cell targeted by the fourth data state, applying a programming voltage of no more than a first predetermined number of programming pulses to the memory cell targeted by the fifth data state. Furthermore, the method includes the step of: after programming and verification are completed in a memory cell targeted by the fourth data state, applying a programming voltage of no more than a second predetermined number of programming pulses to the memory cell targeted by the sixth data state. The method further includes the following steps: after programming and verification are completed in the memory cell targeting the fourth data state, a programming voltage of no more than a third predetermined number of programming pulses is applied to the memory cell targeting the seventh data state.

[0140] As discussed above, a predetermined number of STPFINEs can be set to one for some WL / string / state, with a controlled trade-off for threshold voltage margin. Similarly, memory cells can be located in memory holes (e.g., Figure 6D Storage hole 630, Figure 7A and Figure 7B In storage holes 710, 714, 716, and 718). These storage holes are arranged in rows comprising each of the multiple strings. (For example, Figure 7A and Figure 7B Storage holes 710, 714, 716, and 718 are Figure 8A (A portion of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe.) The method also includes the step of: selecting, in different ways, a predetermined number of programming pulses applied to a memory cell targeting at least one skip verification data state, for at least one of a plurality of word lines, a plurality of strings, or a plurality of data states.

[0141] Several aspects of this disclosure may be embodied in the form of an apparatus, system, method, or computer program process. Therefore, aspects of this disclosure may be entirely in the form of a hardware implementation or a software implementation (including, but not limited to, firmware, resident software, microcode, etc.), or a combination of both hardware and software components, which are generally referred to collectively as a “circuit,” “module,” “apparatus,” or “system.” Furthermore, aspects of this disclosure may be in the form of a computer program process, for example embodied in one or more non-transitory computer-readable storage media storing computer-readable and / or executable program code.

[0142] Additionally, various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this description is not intended to distinguish components with different names but the same function. With regard to the various functional units described in the following disclosure being referred to as “modules,” this characterization is intended not to unduly limit the scope of potential implementation mechanisms. For example, a “module” can be implemented as hardware circuitry comprising custom-designed very large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In another example, a module can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, or programmable logic devices. Furthermore, modules can also be implemented, at least in part, by software executed by various types of processors. For example, a module may include fragments of executable code constituting one or more physical or logical blocks of computer instructions that translate into objects, procedures, or functions. Furthermore, it is not required that the executable portions of such a module be physically located together, but rather that they may include different instructions stored in different locations and, when executed together, constitute the identified module and achieve the module’s stated purpose. Executable code may consist of a single instruction or a set of instructions, and may be distributed across different code segments, different programs, or multiple memory devices. In specific implementations of software or software modules, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatuses, or devices, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing programs used by or in connection with an instruction execution system, apparatus, processor, or device.

[0143] Similarly, for the purposes of this disclosure, the term "component" can include any tangible, physical, and non-transitory device. For example, a component can be in the form of hardware logic circuitry, including custom VLSI circuitry, gate arrays, or other integrated circuits, or off-the-shelf semiconductors containing logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic equipment. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, a component can include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices configured to communicate electrically with one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied in or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0144] When the term "circuit" is used herein, it includes one or more electrical and / or electronic components that form one or more conductive paths allowing current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components provide a return path for the current. In contrast, in an open-loop configuration, the circuit components are still considered to form a circuit, although a return path for the current is not included. For example, an integrated circuit is referred to as a circuit regardless of whether it is coupled to ground (as a return path for the current). In some exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, configured to communicate electrically with one or more other components via electrical conductors, such as a printed circuit board (PCB). A circuit may also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, modules as defined above may be embodied in or implemented as circuits in some embodiments.

[0145] It should be understood that the example embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions that control one or more microprocessors in combination with certain non-processor circuitry and other elements to implement some, most, or all of the functions disclosed herein.

[0146] Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combination of functions is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the term "controller" as used below should be defined as including individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0147] Furthermore, the terms “program,” “software,” “software application,” etc., as may be used herein, refer to a sequence of instructions designed to be executed on a computer-implemented system. Therefore, “program,” “software,” “application,” “computer program,” or “software application” can include subroutines, functions, procedures, object methods, object implementations, executable applications, applets, service applets, source code, object code, shared libraries / dynamically loaded libraries, and / or other specific sequences of instructions designed to be executed on a computer system.

[0148] Additionally, the terms “coupled,” “being coupled,” or “coupled” as used herein are intended to indicate a direct or indirect connection. Thus, if a first device is coupled or is coupled to a second device, the connection can be a direct connection or an indirect connection via other devices (or components) and connectors.

[0149] Regarding terms such as “implementation,” “an implementation,” “exemplary implementation,” “specific implementation,” or other similar terms as used herein, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with that implementation is found in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one implementation,” “in an implementation,” “in an exemplary implementation,” etc., may, but not necessarily, refer to the same implementation, but rather means “one or more, but not all, implementations,” unless expressly stated otherwise. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…,” unless expressly stated otherwise. Moreover, without further constraints, an element prefixed with “comprising…” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element.

[0150] The terms “a,” “an,” and “the / said” also mean “one or more” unless otherwise expressly stated. Furthermore, the phrase “at least one of A and B” (where A and B are variables indicating a particular object or attribute) that may be used herein and / or in the following claims indicates a choice of A or B, or both A and B, similar to the phrase “and / or.” When more than two variables are present in such a phrase, the phrase is thus defined to include only one variable, any one variable, any combination (or sub-combination) of any variables, and all variables.

[0151] Furthermore, when used herein, the terms “approximately” or “about” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated value (e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0152] Furthermore, any list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless otherwise expressly stated. Additionally, the term "set" as used herein should be interpreted as "one or more," and in the case of "set," it should be interpreted as "one or more," "one or more," and / or "one or more" according to set theory, unless otherwise expressly stated.

[0153] For purposes of illustration and description, the foregoing detailed description has been provided. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible based on the above description. The described embodiments have been chosen to best explain the principles of the technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and to make various modifications suitable for the intended particular use. The scope of this technology is defined by the appended claims.

Claims

1. A memory device, the memory device comprising: A memory cell, each memory cell being connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the plurality of data states including a highest data state, in which the threshold voltage of the memory cell associated with the highest data state is higher than the threshold voltage for the other data states among the plurality of data states; and Control unit, the control unit being configured to: During each programming cycle of a plurality of programming operations, each of a series of programming pulses applying a programming voltage to a selected word line among the plurality of word lines, followed by verification pulses of a plurality of programming verification voltages each associated with a data state among the plurality of data states, to program and verify the memory cell connected to the selected word line. In at least one of the plurality of programming loops, the verification of the memory cell targeting at least one of the other data states of the plurality of data states is skipped.

2. The memory device of claim 1, wherein the other data states among the plurality of data states include: At least one skip verification data state, in which the verification of the memory cell targeted by the at least one skip verification data state is skipped in at least one programming loop among the plurality of programming loops; and at least one previous data state, wherein the threshold voltage of the memory cell associated with the at least one previous data state is lower than the threshold voltage of the memory cell associated with the at least one skip verification data state; and the control unit is further configured to apply a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the at least one skip verification data state after programming and verification of the memory cell targeted by the at least one previous data state is completed.

3. The memory device of claim 2, wherein each memory cell in the memory cell is configured to store three bits, and the plurality of data states, in ascending order of the threshold voltage, include an erase data state and a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, wherein the highest data state is the seventh data state, the at least one skip verification data state includes the third data state, the fifth data state, and the seventh data state, and the control unit is further configured to: After the programming and verification are completed in the memory cell targeting the second data state, programming pulses of no more than the predetermined number of programming voltages are applied to the memory cell targeting the third data state. After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the predetermined number are applied to the memory cell targeting the fifth data state; and After the programming and verification are completed in the memory cell targeting the sixth data state, programming pulses of no more than the predetermined number of programming voltages are applied to the memory cell targeting the seventh data state.

4. The memory device of claim 2, wherein the at least one prior data state includes at least one fully verified data state, in which the programming and verification of the memory cell targeted by the at least one fully verified data state have been completed; and the control unit is further configured to select, based on the proximity of the threshold voltage of the memory cell targeted by the at least one skipped verification data state and the threshold voltage of the memory cell targeted by the at least one fully verified data state associated with the at least one skipped verification data state, a predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeted by the at least one skipped verification data state; the predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeted by the at least one skipped verification data state decreases as the proximity decreases.

5. The memory device of claim 4, wherein the predetermined number of programming pulses of the programming voltage applied to the memory cell targeting the at least one skip verification data state increases in magnitude order including a first predetermined number, a second predetermined number, and a third predetermined number of programming pulses of the programming voltage, and the control unit is further configured to: In response to the at least one skipped verification data state being adjacent to the at least one fully verified data state associated with the at least one skipped verification data state, after the programming and verification are completed in the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state, a programming pulse of no more than the first predetermined number of programming voltages is applied to the memory cell targeting the at least one skipped verification data state. In response to a data state that is separated from one of the plurality of data states by the at least one skipped verification data state and the at least one fully verified data state associated with the at least one skipped verification data state, after the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state has completed the programming and the verification, a programming voltage of no more than the second predetermined number of programming pulses is applied to the memory cell targeting the at least one skipped verification data state. as well as In response to the at least one skip verification data state and the at least one full verification data state associated with the at least one skip verification data state being separated from two of the plurality of data states, after the memory cell targeting the at least one full verification data state associated with the at least one skip verification data state has completed the programming and the verification, a programming voltage of no more than the third predetermined number of programming pulses is applied to the memory cell targeting the at least one skip verification data state.

6. The memory device of claim 5, wherein each memory cell in the memory cell is configured to store three bits, and the plurality of data states, in ascending order of the threshold voltage, include an erase data state and a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, the at least one skip verification data state including the second data state, the third data state, the fifth data state, the sixth data state, and the seventh data state, and the control unit is further configured to: After the programming and verification are completed in the memory cell targeting the second data state, programming pulses of no more than the first predetermined number of programming voltages are applied to the memory cell targeting the second data state. After the programming and verification are completed in the memory cell targeting the second data state, programming pulses of no more than the second predetermined number of programming voltages are applied to the memory cell targeting the third data state. After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the first predetermined number of programming voltages are applied to the memory cell targeting the fifth data state. After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the second predetermined number are applied to the memory cell targeting the sixth data state; and After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the third predetermined number are applied to the memory cell targeting the seventh data state.

7. The memory device of claim 2, wherein the memory cell is disposed in a memory hole arranged to include a row of each of a plurality of strings, and the control element is further configured to select, in different ways, the predetermined number of programming pulses applied to the programming voltage of the memory cell targeting the at least one skip verification data state for different of at least one of the plurality of word lines, the plurality of strings, or the plurality of data states.

8. A controller for communicating with a memory device, the memory device including memory cells, each memory cell being connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the plurality of data states including a highest data state, wherein in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than the threshold voltage for the other data states of the plurality of data states, the controller being configured to: Each programming pulse in a series of programming pulses instructing the memory device to apply a programming voltage to a selected word line among a plurality of word lines during each programming cycle of a plurality of programming cycles of a programming operation, followed by verification pulses of a plurality of programming verification voltages each associated with a data state among a plurality of data states, to program and verify the memory cell connected to the selected word line; and The memory device is instructed to skip verification of the memory cell targeting at least one of the other data states in at least one of the plurality of programming cycles.

9. The controller of claim 8, wherein the other data states among the plurality of data states include: At least one skip verification data state, in which the verification of the memory cell targeted by the at least one skip verification data state is skipped in at least one programming loop among the plurality of programming loops; and at least one previous data state, wherein the threshold voltage of the memory cell associated with the at least one previous data state is lower than the threshold voltage of the memory cell associated with the at least one skip verification data state; and the controller is further configured to apply a programming voltage of no more than a predetermined number of programming pulses to the memory cell targeted by the at least one skip verification data state after programming and verification of the memory cell targeted by the at least one previous data state is completed.

10. The controller of claim 9, wherein each memory cell in the memory cells is configured to store three bits, and the plurality of data states, in ascending order of the threshold voltage, include an erase data state and a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, the at least one skip verification data state including the third data state, the fifth data state, and the seventh data state, and the controller is further configured to: After the memory device has completed the programming and verification of the memory cell targeting the second data state, it applies programming pulses of no more than the predetermined number to the memory cell targeting the third data state. The memory device is instructed to apply programming pulses of no more than the predetermined number to the memory cell targeting the fifth data state after the programming and verification are completed in the memory cell targeting the fourth data state; and The memory device is instructed to apply programming pulses of no more than the predetermined number to the memory cell targeting the seventh data state after the programming and verification are completed in the memory cell targeting the sixth data state.

11. The controller of claim 9, wherein the at least one previous data state includes at least one fully verified data state in which the programming and verification of the memory cell targeted by the at least one fully verified data state have been completed; and the controller is further configured to select, based on the proximity of the threshold voltage of the memory cell targeted by the at least one skipped verification data state and the threshold voltage of the memory cell targeted by the at least one fully verified data state associated with the at least one skipped verification data state, a predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeted by the at least one skipped verification data state decreases as the proximity decreases.

12. The controller of claim 11, wherein the predetermined number of programming pulses of the programming voltage applied to the memory cell targeting the at least one skip verification data state comprises, in ascending order of magnitude, a first predetermined number, a second predetermined number, and a third predetermined number of programming pulses of the programming voltage, and the controller is further configured to: The memory device is instructed to apply programming pulses of no more than the first predetermined number to the memory cell targeting the at least one skip verification data state after the programming and verification are completed in the memory cell targeting the at least one skip verification data state, in response to the at least one skip verification data state immediately adjacent to the at least one full verification data state associated with the at least one skip verification data state. The memory device is instructed to respond to one of the plurality of data states, which is separated from the at least one skipped verification data state and the at least one fully verified data state associated with the at least one skipped verification data state, after the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state has completed the programming and the verification, to apply a programming voltage of no more than the second predetermined number of programming pulses to the memory cell targeting the at least one skipped verification data state; and The memory device is instructed to respond to two of the plurality of data states, namely the at least one skip verification data state and the at least one full verification data state associated with the at least one skip verification data state, after the memory cell targeting the at least one full verification data state associated with the at least one skip verification data state has completed the programming and the verification, to apply a programming voltage of no more than the third predetermined number of programming pulses to the memory cell targeting the at least one skip verification data state.

13. The controller of claim 12, wherein each memory cell in the memory cells is configured to store three bits, and the plurality of data states, in ascending order of the threshold voltage, include an erase data state and a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, the at least one skip verification data state including the second data state, the third data state, the fifth data state, the sixth data state, and the seventh data state, and the controller is further configured to: After the memory device has completed the programming and verification of the memory cell targeting the second data state, it instructs the memory device to apply programming pulses of no more than the first predetermined number of programming voltages to the memory cell targeting the second data state. After the memory device has completed the programming and verification of the memory cell targeting the second data state, it instructs the memory device to apply programming pulses of no more than the second predetermined number of programming voltages to the memory cell targeting the third data state. After the memory device has completed the programming and verification of the memory cell targeting the fourth data state, it instructs the memory device to apply programming pulses of no more than the first predetermined number of programming voltages to the memory cell targeting the fifth data state. After the memory device has completed the programming and verification of the memory cell targeting the fourth data state, it is instructed to apply programming pulses of no more than the second predetermined number of programming voltages to the memory cell targeting the sixth data state. as well as The memory device is instructed to apply programming pulses of no more than the third predetermined number to the memory cell targeting the seventh data state after the programming and verification are completed in the memory cell targeting the fourth data state.

14. A method of operating a memory device, the memory device including memory cells, each memory cell being connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the plurality of data states including a highest data state, wherein in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than the threshold voltage for the other data states of the plurality of data states, the method comprising the steps of: During each programming cycle of a plurality of programming operations, each of a series of programming pulses in which a programming voltage is applied to a selected word line among the plurality of word lines, followed by verification pulses of a plurality of programming verification voltages each associated with a data state among the plurality of data states, to program and verify the memory cell connected to the selected word line. as well as In at least one of the plurality of programming loops, the verification of the memory cell targeting at least one of the other data states of the plurality of data states is skipped.

15. The method of claim 14, wherein the other data states among the plurality of data states include: At least one skip verification data state, in which the verification of the memory cell targeted by the at least one skip verification data state is skipped in at least one programming loop among the plurality of programming loops; The method further includes the following steps: after programming and verification are completed for the memory cell targeted by the at least one previous data state, the threshold voltage of the memory cell associated with the at least one previous data state is lower than the threshold voltage of the memory cell associated with the at least one skip verification data state; and the method further includes the following steps: after programming and verification are completed for the memory cell targeted by the at least one previous data state, applying no more than a predetermined number of programming pulses of the programming voltage to the memory cell targeted by the at least one skip verification data state.

16. The method of claim 15, wherein each memory cell in the memory cell is configured to store three bits, and the plurality of data states, in ascending order of the magnitude of the threshold voltage, include an erase data state and a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, wherein the highest data state is the seventh data state, the at least one skip verification data state includes the third data state, the fifth data state, and the seventh data state, and the method further comprises the following steps: After the programming and verification are completed in the memory cell targeting the second data state, programming pulses of no more than the predetermined number of programming voltages are applied to the memory cell targeting the third data state. After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the predetermined number of programming voltages are applied to the memory cell targeting the fifth data state. as well as After the programming and verification are completed in the memory cell targeting the sixth data state, programming pulses of no more than the predetermined number of programming voltages are applied to the memory cell targeting the seventh data state.

17. The method of claim 15, wherein the at least one prior data state includes at least one fully verified data state, in which the programming and verification of the memory cell targeted by the at least one fully verified data state have been completed; and the method further includes the step of: The predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeting the at least one skipped verification data state is selected based on the proximity of the threshold voltage of the memory cell targeting the at least one full verification data state associated with the at least one skipped verification data state; the predetermined number of programming pulses to be applied to the programming voltage of the memory cell targeting the at least one skipped verification data state decreases as the proximity decreases.

18. The method of claim 17, wherein the predetermined number of programming pulses of the programming voltage applied to the memory cell targeting the at least one skip verification data state increases in magnitude order including a first predetermined number, a second predetermined number, and a third predetermined number of programming pulses of the programming voltage, and the method further comprises the step of: In response to the at least one skipped verification data state being adjacent to the at least one fully verified data state associated with the at least one skipped verification data state, after the programming and verification are completed in the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state, a programming pulse of no more than the first predetermined number of programming voltages is applied to the memory cell targeting the at least one skipped verification data state. In response to a data state that is separated from one of the plurality of data states by the at least one skipped verification data state and the at least one fully verified data state associated with the at least one skipped verification data state, after the memory cell targeting the at least one fully verified data state associated with the at least one skipped verification data state has completed the programming and the verification, a programming voltage of no more than the second predetermined number of programming pulses is applied to the memory cell targeting the at least one skipped verification data state. as well as In response to the at least one skip verification data state and the at least one full verification data state associated with the at least one skip verification data state being separated from two of the plurality of data states, after the memory cell targeting the at least one full verification data state associated with the at least one skip verification data state has completed the programming and the verification, a programming voltage of no more than the third predetermined number of programming pulses is applied to the memory cell targeting the at least one skip verification data state.

19. The method of claim 18, wherein each memory cell in the memory cell is configured to store three bits, and the plurality of data states, in ascending order of the threshold voltage, include an erase data state and a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, the at least one skip verification data state including the second data state, the third data state, the fifth data state, the sixth data state, and the seventh data state, and the method further comprising the following steps: After the programming and verification are completed in the memory cell targeting the second data state, programming pulses of no more than the first predetermined number of programming voltages are applied to the memory cell targeting the second data state. After the programming and verification are completed in the memory cell targeting the second data state, programming pulses of no more than the second predetermined number of programming voltages are applied to the memory cell targeting the third data state. After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the first predetermined number of programming voltages are applied to the memory cell targeting the fifth data state. After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the second predetermined number of programming voltages are applied to the memory cell targeting the sixth data state. as well as After the programming and verification are completed in the memory cell targeting the fourth data state, programming pulses of no more than the third predetermined number are applied to the memory cell targeting the seventh data state.

20. The method of claim 15, wherein the memory cell is disposed in a memory hole arranged to include a row comprising each of a plurality of strings, and the method further comprises the step of: For at least one of the plurality of word lines, the plurality of strings, or the plurality of data states, the predetermined number of programming pulses applied to the programming voltage of the memory cell targeting the at least one skip verification data state are selected in different ways.

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