Flexible clock distribution for program-verify operations

Abstract

The present disclosure provides for performing a program-verify operation of a memory device. The memory device includes a memory block including a plurality of memory cells connected to a plurality of data word lines. The memory device also includes circuitry configured to conduct a first operation of the program-verify operation to verify that a threshold voltage of one or more memory cells connected to a selected data word line of the plurality of data word lines is above a verify low voltage. The circuitry is also configured to apply a program voltage to the selected data word line during the first operation. In some examples, the first operation can be a lock low bit scan.

Description

Background Technology 1. Technical Field

[0001] This disclosure relates in general to the operation of NAND memory devices, and more specifically to techniques for verifying the flexible allocation of sub-clocks for memory cell programming.

[0002] 2. Related Technologies

[0003] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0004] NAND memory devices include a chip having multiple memory blocks, each of which includes an array of memory cells arranged in multiple word lines. Programming the memory cells of the word lines to retain data typically occurs in multiple programming cycles. Each programming cycle includes the application of a programming pulse to a control gate of the word line and, optionally, a verification operation sensing a threshold voltage of the memory cell being programmed. Each programming cycle may also include a pre-charge operation prior to the programming pulse to pre-charge the multiple channels containing the memory cell to be programmed. Summary of the Invention

[0005] One aspect of this disclosure relates to a method for performing a programming-verification operation on a memory device. The method includes the step of preparing a memory block comprising a plurality of memory cells connected to a plurality of data word lines. The method further includes performing a first operation of the programming-verification operation to verify that a threshold voltage of one or more memory cells connected to a selected data word line of the plurality of data word lines is higher than a verification low voltage. The method further includes applying a programming voltage to the selected data word line during the first operation.

[0006] According to another aspect of this disclosure, the first operation may be locking the low-order scan.

[0007] According to another aspect of this disclosure, performing the first operation may further include the steps of: applying a verification low voltage to the selected data word line, and verifying the programming of the one or more memory cells connected to the selected data word line based on the verification low voltage.

[0008] According to another aspect of this disclosure, the method may include the steps of: performing the first operation after ramping down the voltage on the gate of a bit line clamp (BLC) transistor connected to a bit line coupled to the one or more memory cells; and applying VBLC_QPW to the gate of the BLC transistor after the first operation is completed.

[0009] According to another aspect of this disclosure, the time window allocated to the first operation can be defined based on the time at which the VBLC_QPW is applied to the gate of the BLC transistor.

[0010] According to another aspect of this disclosure, the first operation may be initiated based on setting the time at which the VBLC_QPW is applied to the gate of the BLC transistor.

[0011] According to another aspect of this disclosure, performing the first operation may include determining that the threshold voltage of the one or more memory cells is higher than the verification low voltage, and based on the determination, applying a fast write voltage to a bit line coupled to the one or more memory cells.

[0012] According to another aspect of this disclosure, after the programming voltage is applied to the selected data word line, the fast pass-through voltage can be applied to the bit line coupled to the one or more memory cells.

[0013] According to another aspect of this disclosure, the method may further include the steps of: applying a boost voltage to one or more of the unselected data word lines and the selected data word line; and initiating the first operation after applying the boost voltage.

[0014] According to another aspect of this disclosure, the method may include the steps of: performing a second operation prior to performing the first operation to verify that a threshold voltage of at least one memory cell connected to a selected data word line among the plurality of data word lines is higher than a verification high voltage; and applying a programming disable voltage to a bit line coupled to the at least one memory cell.

[0015] Another aspect of this disclosure relates to a memory device. The memory device includes a memory block comprising a plurality of memory cells arranged in a plurality of data word lines. The memory device also includes circuitry configured to perform a first operation of a programming-verification operation to verify that a threshold voltage of one or more memory cells connected to a selected data word line among the plurality of data word lines is higher than a verification low voltage, and during the first operation, to apply a programming voltage to the selected data word line.

[0016] According to another aspect of this disclosure, performing the first operation may further include the steps of: applying a verification comparison voltage to a first set of data word lines; and verifying the programming of one or more memory cells connected to selected data word lines based on the verification comparison voltage.

[0017] According to another aspect of this disclosure, the circuit may also be configured to perform the first operation after causing a voltage ramp on the gate of a bit line clamp (BLC) transistor connected to a bit line coupled to the one or more memory cells to decrease, and to apply VBLC_QPW to the gate of the BLC transistor after the first operation is completed.

[0018] According to another aspect of this disclosure, the time window allocated to the first operation can be defined based on the time at which the VBLC_QPW is applied to the gate of the BLC transistor.

[0019] According to another aspect of this disclosure, the first operation may be initiated based on setting the time at which the VBLC_QPW is applied to the gate of the BLC transistor.

[0020] According to another aspect of this disclosure, performing the first operation may include determining that the threshold voltage of the one or more memory cells is higher than the verification low voltage, and based on the determination, applying a fast write voltage to the bit line coupled to the one or more memory cells.

[0021] According to another aspect of this disclosure, after the programming voltage is applied to the selected data word line, the fast pass-through voltage can be applied to the bit line coupled to the one or more memory cells.

[0022] According to another aspect of this disclosure, the circuit may be further configured to perform a second operation before performing the first operation to verify that the threshold voltage of at least one memory cell connected to the selected data word line among the plurality of data word lines is higher than the verification high voltage, and to apply a programming disable voltage to the bit line coupled to the at least one memory cell.

[0023] Another aspect of this disclosure relates to an apparatus. The apparatus includes a memory block comprising a plurality of memory cells arranged in a plurality of word lines and a plurality of bit lines. These bit lines include bit line clamping (BLC) transistors. The apparatus also includes a controller configured to program one or more memory cells connected to selected word lines in a programming operation, and to allocate a portion of the programming operation to a first operation based on settings defining when a voltage is applied to the BLC transistor. The programming operation includes, during the program-verify operation, verifying that a threshold voltage of one or more memory cells connected to selected data word lines among the plurality of data word lines is higher than a verification low voltage, and applying a programming voltage to the selected data word line.

[0024] According to another aspect of this disclosure, the programming operation may further include performing the first operation after causing the voltage ramp on the BLC transistor to drop, and applying VBLC_QPW to the BLC transistor after the first operation is completed. Attached Figure Description

[0025] A more detailed description is given below with reference to exemplary embodiments depicted in the accompanying drawings. It should be understood that these drawings depict only exemplary embodiments of this disclosure and are therefore not intended to limit its scope. This disclosure is described and explained more specifically and in detail using the accompanying drawings, wherein:

[0026] Figure 1A This is a block diagram of an example memory device;

[0027] Figure 1B This is a block diagram of an example control circuit;

[0028] Figure 1C This is an example of what is done according to this disclosure. Figure 1A A block diagram showing the memory device configured to operate according to a precharge technique;

[0029] Figure 2 Depicting Figure 1A A block of memory cells in an example two-dimensional configuration of a memory array;

[0030] Figure 3A and Figure 3B A cross-sectional view of an example floating gate memory cell in a NAND string is depicted;

[0031] Figure 4A and Figure 4B A cross-sectional view of an example charge-trapping memory cell in a NAND string is depicted;

[0032] Figure 5 An example block diagram of the sensing block SB1 in Figure 1 is depicted;

[0033] Figure 6A This is a perspective view of a set of blocks in an example three-dimensional configuration of the memory array in Figure 1;

[0034] Figure 6B Depicting Figure 6A An example cross-sectional view of a portion of one of the blocks;

[0035] Figure 6C Depicting Figure 6B A graph showing the diameter of memory holes in a stack;

[0036] Figure 6D Depicting Figure 6B A close-up view of the stacked area 622;

[0037] Figure 7A Depicting Figure 6B A top view of an example stacked wordline layer WL0;

[0038] Figure 7B Depicting Figure 6B A top view of the stacked example top dielectric layer DLl16;

[0039] Figure 8 Example specific implementations of a sensing circuit according to an embodiment of the present disclosure are illustrated;

[0040] Figure 9 The threshold voltage distribution of a page of memory cells programmed as one bit per memory cell (SLC) is depicted;

[0041] Figure 10 The threshold voltage distribution of a page of memory cells programmed as three bits per memory cell (TLC) is depicted;

[0042] Figure 11 The threshold voltage distribution of a page of memory cells programmed as four bits per memory cell (QLC) is depicted;

[0043] Figure 12 The waveform of the voltage applied to the control gate of the selected word line during an exemplary programming operation is depicted;

[0044] Figure 13 It is a flowchart describing the process for programming the example memory block;

[0045] Figure 14 The threshold voltage distribution of memory cells on the data state line before and after programming using the Quick By Write (QPW) programming technique is depicted.

[0046] Figure 15 An example is given of a method for programming using the QPW programming technique, which includes multiple programming-verification operations;

[0047] Figure 16A This is a signal diagram describing the behavior of various signals during the example programming-verification operation;

[0048] Figure 16B yes Figure 16A Schematic block timing diagrams of various signals;

[0049] Figure 17A This is a signal diagram describing the behavior of various signals during an example of early programming-verification operations;

[0050] Figure 17B yes Figure 17A Schematic block timing diagrams of various signal examples;

[0051] Figure 18 It is a graphical representation of the drain-side selected gate voltage (VSGD) window loss;

[0052] Figure 19 It is a graphical representation of the distortion of the erased state distribution;

[0053] Figure 20 The voltage waveforms applied to various components of the memory block during the programming cycle, which includes programming-verification operations, pre-charge operations, and programming, are illustrated.

[0054] Figure 21 This is a flowchart depicting the steps of programming a memory cell for a selected data word line according to an example embodiment of the present disclosure;

[0055] Figure 22 A schematic block diagram depicts the timing assigned to at least one programming-verification operation;

[0056] Figure 23 The voltages applied to various components of a memory block during an exemplary implementation of a programming loop with delayed programming-verification operations are illustrated.

[0057] Figure 24 A schematic block diagram depicts the timing allocation for delayed programming-verification operations; and

[0058] Figure 25 This is a flowchart depicting the steps of programming a memory cell for a selected data word line according to an example embodiment of the present disclosure. Detailed Implementation

[0059] This disclosure relates to a pre-charging technique for flexibly allocating portions of a programming cycle for performing a program-verify operation based on portions allocated for slow programming of memory cells. According to the technique disclosed herein, during the application of a programming pulse (VPGM) to a selected word line, a fast pass-write (QPW) voltage (VQPW) can be applied to a bit line coupled to one or more memory cells determined for slow programming. The bit line can be charged by turning on a BLC transistor connected to the bit line via applying a BLC QPW voltage (VBLC_QPW) to the gate of the BLC transistor. The timing of turning on the BLC transistor and charging the bit line can be set to certain time windows of the programming cycle (also referred to herein as sub-clocks). Based on the assigned time windows, an earlier time window can be allocated to at least one bit scan of the program-verify operation, which can be performed to determine which memory cells will be programmed via slow programming. For example, after VPGM is applied to the selected word line, more time can be allocated for performing at least one bit scan depending on whether the BLC transistor is turned on. Compared to the conventional approach of activating the BLC transistor before applying the VPGM, the examples in this paper activate the BLC transistor later, allowing for flexible sub-clock allocation. These techniques offer improved performance with reduced programming latency compared to other program-verify techniques, and will be discussed in further detail below.

[0060] Figure 1A This is a block diagram of an example memory device 100 configured to operate according to the precharge technique of this disclosure. Memory die 108 includes a memory structure 126 of memory cells (such as an array of memory cells), control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable by word lines via row decoder 124 and by bit lines via column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks SB1, SB2, ..., SBp (sensing circuitry) and allows parallel reading or programming of a page of memory cells. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0061] Memory structure 126 can be two-dimensional or three-dimensional. Memory structure 126 may include one or more memory cell arrays comprising a three-dimensional array. Memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory stages are formed on (rather than in) a single substrate (such as a wafer), without intermediate substrates. Memory structure 126 may include any type of non-volatile memory monolithically formed in one or more physical stages of a memory cell array having active regions disposed above a silicon substrate. Memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is above or within the substrate.

[0062] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0063] Storage region 113 may be provided, for example, for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, and / or verification voltage, etc. Location parameters may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, and / or the location of the memory cell on a specific plane, etc. Contact connector thickness parameters may indicate the thickness of the contact connector and / or the substrate or material constituting the contact connector, etc.

[0064] The on-chip address decoder 114 provides an address interface between addresses used by the host or memory controller and hardware addresses used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. It may include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, the sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0065] In some implementations, some components may be combined. In various designs, one or more components (individually or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0066] The control circuitry may include programming circuitry configured to perform programming and program-verification operations on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of the plurality of data states; the programming and program-verification operations include multiple programming and program-verification iterations; and in each programming and program-verification iteration, the programming circuitry performs programming on a selected word line, after which the programming circuitry applies a programming pulse. The control circuitry may also include a counting circuit configured to obtain a count of memory cells that have passed a verification test for a data state. The control circuitry may further include a determining circuit configured to determine whether the programming operation is complete based on an amount by which the count exceeds a threshold.

[0067] For example, Figure 1B This is a block diagram of an example control circuit 150, including a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0068] The off-chip controller 122 may include a processor 122c, storage devices (memory) (such as ROM 122a and RAM 122b), and an error correction code (ECC) engine 245. The ECC engine can correct many read errors that occur when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques presented herein reduce the likelihood of uncorrectable errors.

[0069] Storage devices 122a and 122b include code such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c may access the code from storage device 126a of memory structure 126 (such as a reserved area of ​​memory cells in one or more word lines). For example, the code may be used by controller 122 to access memory structure 126, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes controller 122 during a boot or startup process and enables controller 122 to access memory structure 126. The code may be used by controller 122 to control one or more memory structures 126. Upon power-up, processor 122c retrieves boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. Control code includes drivers that perform basic tasks, such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0070] Typically, control code may include instructions to perform the functions described herein (including the steps in the flowcharts discussed further below) and to provide those voltage waveforms, including those discussed further below.

[0071] Figure 1C Example: Control circuitry 110, controller 122, and / or control circuitry 150 are configured to operate according to the programming-verification techniques disclosed in this subject matter. Specifically, these components are configured to apply a programming voltage (VPGM) to selected data word lines during programming-verification operation.

[0072] At step 160, a programming disable voltage is applied to the bit line of at least one memory cell to be disabled for programming, coupled to the memory block. The memory block comprises multiple memory cells connected to multiple word lines. At step 162, a first voltage (e.g., VTH_BLDR) slopes down on the gate of the bit line clamp (BLC) transistor connected to the bit line of the memory block. At step 164, a bit scan is performed to verify that the threshold voltage of one or more memory cells connected to selected data word lines is higher than the verification low voltage. The bit scan determines which memory cells (if any) will be slowly programmed, as the threshold voltage may be between the verification low voltage and the verification high voltage of the expected data state. At step 166, during the bit scan, a programming voltage (VPGM) is applied to the selected data word line. At step 168, after the bit scan is complete, a second voltage (e.g., VBLC_QPW) is applied to the gate of the BLC transistor, which slowly charges the bit line coupled to the memory cell to be programmed to the QPW voltage (VQPW). The memory cell to be programmed (e.g., those on the selected word line with a threshold voltage below the verification low voltage) is maintained at a quiescent voltage (e.g., ground, 0 volts, or another suitable quiescent voltage). Due to the difference between the quiescent voltage and the drain-side selected gate voltage (VSGD), sufficient conduction exists on the drain-side selected gate of the memory cell to be programmed, which allows programming. Applying the VQPW voltage to the bit line of the memory cell to be programmed slowly increases the voltage in the channel, thereby reducing the voltage difference between the programming pulse VPGM and the channel and slowing the flow of electrons into the charge-trapping material of the memory cell being programmed. In this example, the timing of the first voltage ramp down on the gate of the BLC transistor and the initiation of the bit scan depends on the timing at which the voltage will be applied to the gate of the BLC transistor.

[0073] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory in communication with the one or more processors, one or more input / output interfaces, and / or one or more input / output devices.

[0074] Other types of non-volatile memory besides NAND flash memory can also be used.

[0075] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) devices or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0076] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements (such as antifuse or phase-change materials) and optionally manipulation elements (such as diodes or transistors). Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0077] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND string is an example of a group of transistors connected in series, including memory cells and SG transistors.

[0078] NAND memory arrays can be configured such that the array consists of multiple memory strings, wherein a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0079] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single planar level or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory element (e.g., in the xy-direction plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory element after the memory element has been formed. As a non-limiting example, the substrate may include a semiconductor (such as silicon).

[0080] Memory elements can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines (such as bit lines and word lines).

[0081] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y and z directions, where the z direction is generally perpendicular to the main surface of the substrate, and the x and y directions are generally parallel to the main surface of the substrate).

[0082] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., along the y-direction), each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xy-plane) to produce a three-dimensional arrangement of memory elements having multiple vertically stacked elements on the memory plane. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0083] As a non-limiting example, in a three-dimensional NAND string array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0084] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers that are at least partially located within the single substrate. As a non-limiting example, the substrate may include a semiconductor (such as silicon). In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the lower memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or there may be intermediate layers between memory device classes.

[0085] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on individual substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on individual chips and then packaged together to form a stacked chip memory device.

[0086] Figure 2Blocks 200 and 210 of memory cells in an example two-dimensional configuration of the memory array 126 of FIG1 are illustrated. The memory array 126 may comprise a plurality of such blocks 200 and 210. Each example block 200, 210 includes multiple NAND strings and respective bit lines, such as BL0, BL1, ..., which are shared between blocks. Each NAND string is connected to a drain-side selected gate (SGD) at one end, and the control gate of the drain-side selected gate is connected via a common SGD line. The NAND string is connected to a source-side selected gate (SGS) at its other end, which is then connected to a common source line 220. One hundred and twelve data word lines (e.g., WL0 to WL111) extend between the SGS and the SGD. In some embodiments, a memory block may include more or fewer than one hundred and twelve data word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four data word lines. In some cases, virtual word lines that do not contain user data may also be used in the memory array adjacent to the selected gate transistor. This virtual word line can shield edge data word lines from certain edge effects. As used herein, the term "word line" can refer to the collection of virtual word lines and data word lines, and the term "word line" can refer to either a virtual word line or a data word line, unless it is explicitly stated which type of word line is being referred to.

[0087] One type of non-volatile memory that can be provided in a memory array is a floating-gate memory, such as... Figure 3A and Figure 3B The type shown is correct. However, other types of non-volatile memory can also be used. As discussed in further detail below, in Figure 4A and Figure 4B In another example shown, the charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a limited area. The stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0088] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across a channel between the source and drain. The charge of one data bit is located in the dielectric layer adjacent to the drain, and the charge of the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0089] Figure 3A A cross-sectional view of example floating-gate memory cells 300, 310, and 320 in a NAND string is illustrated. In this figure, the bit line or NAND string direction enters the page, and the word line direction is from left to right. As an example, word line 324 extends across the NAND string including corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is located in a different corresponding NAND string. An inter-silicon dielectric (IPD) layer 328 is also illustrated. Control gates 302, 312, and 322 are portions of the word lines. Figure 3B A cross-sectional view along the contact line connector 329 is provided.

[0090] Control gates 302, 312, and 322 surround floating gates 304, 314, and 321, thereby increasing the surface contact area between control gates 302, 312, and 322 and floating gates 304, 314, and 321. This results in higher IPD capacitance, leading to a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices scale down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, resulting in almost no space between two adjacent floating gates 302, 312, and 322 for control gates 302, 312, and 322 and the IPD layer 328.

[0091] As an alternative, such as Figure 4A and Figure 4BAs shown, planar or flat memory cells 400, 410, and 420 have been developed, in which the control gates 402, 412, and 422 are planar or flat; that is, they do not surround the floating gate and only contact the charge storage layer 428 from above. In this case, having a high floating gate offers no advantage. Instead, the floating gate is fabricated to be thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0092] Figure 4A A cross-sectional view of example charge-trapping memory cells 400, 410, and 420 in a NAND string is depicted. This view is a two-dimensional example of memory cells 400, 410, and 420 in the memory cell array 126 of FIG1, in the word line direction including the flat control gate and charge-trapping region. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, in contrast to floating-gate MOSFET technology which uses a conductor such as doped polysilicon to store electrons. As an example, word line 424 extends across the NAND string including corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are IPD layer 428, charge trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge trapping layer 404, 414, and 421 extends continuously within its respective NAND string. The flat configuration of the control gate can be made thinner than that of a floating gate. Additionally, memory cells can be placed more closely together.

[0093] Figure 4B Examples Figure 4A The structure is shown in a cross-sectional view along the contact wire connector 429. The NAND string 430 includes an SGS transistor 431, example memory cells 400, 433, ... 435, and an SGD transistor 436. Channels in the IPD layer 428 of the SGS transistor 431 and SGD transistor 436 allow communication between the control gate layer 402 and the floating gate layer. For example, the control gate 402 and the floating gate layer may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0094] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. The channel voltage VCH can be directly applied to the channel region of the substrate.

[0095] Figure 5 An example block diagram of the sensing block SB1 in Figure 1 is illustrated. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with this group of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible approach, the voltage is provided to each sensing circuit independently, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include the precharge circuit 561, a memory 562, and a processor 563. Memory 562 may store code that can be executed by a processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, 553b associated with sensing circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing voltages for setting precharge levels in the sensing nodes of sensing circuits 550a, 551a, 552a, 553a. Further example details of the sensing circuit controller 560 and sensing circuits 550a, 551a, 552a, 553a are provided below.

[0096] In some implementations, a memory cell may include a flag register comprising a set of latches storing flag bits. In some implementations, the number of flag registers may correspond to the number of data states. In some implementations, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some implementations, the output of the flag bits may modify relevant logic of the device (e.g., address decoding circuitry) such that a specified cell block is selected. Batch operations (e.g., erase operations, etc.) may be performed using flags set in the flag registers or a combination of flag registers and address registers (as in implicit addressing) or alternatively by direct addressing using only address registers.

[0097] Figure 6A This is a perspective view of a group of blocks 600 in an example three-dimensional configuration of the memory array 126 of Figure 1. On the substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, this circuitry may include a voltage driver 605, which may be connected to the control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, the control gate layers at a common height in blocks BLK0, BLK1, BLK2, and BLK3 are commonly driven. The substrate 601 may also carry circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, as well as one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a central region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block BLK0, BLK1, BLK2, BLK3 includes a stacked region of memory cells, wherein alternating stacked levels represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides from which vertical contacts extend upwards to the upper metal layer to form connections to the conductive paths. Although four blocks BLK0, BLK1, BLK2, and BLK3 are illustrated as an example, two or more blocks extending in the x and / or u directions can be used.

[0098] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0099] Figure 6B Examples Figure 6AAn example cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers WL0 to WL111, the conductive layers include two SGD layers, two SGS layers, and four virtual word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL116. Furthermore, a region of stack 610 including NAND strings NS1 and NS2 is illustrated. Each NAND string contains memory holes 618 and 619 filled with material forming memory cells adjacent to the word lines. Region 622 of stack 610 is... Figure 6D This is shown in more detail below and discussed further in detail.

[0100] Stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source end 613 at the bottom 614 of the stack and a drain end 615 at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be periodically provided across stack 610 as interconnects extending through stack 610, for example, to connect source lines to specific contact lines above stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently metal-filled. A portion of a bit line BL0 is also illustrated. A conductive via 621 connects the drain end 615 to BL0.

[0101] Figure 6C Examples Figure 6B A graph showing the diameter of memory holes in a stack. The vertical axis is parallel to... Figure 6B The stacking alignment is shown, and the width (wMH), such as the diameter, of memory holes 618 and 619 is illustrated. Figure 6A Word line layers WL0 to WL111 are repeated as an example and are located at their respective heights z0 to z111 in the stack. In this memory device, the memory holes etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of about 24 to 30 is common. The memory holes may have a circular cross-section. Due to the etching process, the width of the memory hole can vary along the length of the hole. Typically, the diameter gradually decreases from the top to the bottom of the memory hole. That is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, causing the diameter to become slightly wider before gradually narrowing from the top to the bottom of the memory hole.

[0102] Due to the non-uniformity of memory via width, the programming speed (including programming slope and erase speed) of a memory cell can vary based on its position along the memory via (e.g., based on its height in the stack). For smaller diameter memory vias, the electric field across the tunnel oxide is relatively strong, resulting in relatively high programming and erase speeds. One approach is to define groups of adjacent word lines with similar memory via diameters (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line in the group. Different groups can have different optimized verification schemes.

[0103] Figure 6D Examples Figure 6B A close-up view of region 622 of stack 610. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680, 681 are disposed above virtual memory cells 682, 683 and data memory cells MC. Multiple layers may be deposited along the sidewalls (SW) of memory via 630 and / or within each word line layer, for example using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory via 630) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. Word line layers may include a barrier oxide / bulk high-k material 660, a metal barrier 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are disposed within memory via 630. In other methods, some layers can be formed within the control gate layer. Similarly, additional pillars are formed in different memory vias. These pillars can form the pillared active regions (AA) of a NAND string.

[0104] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0105] Each memory via 630 may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. The core region of each memory via 630 is filled with a host material, and the multiple annular layers are located between the core region and the word line in each memory via 630.

[0106] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked one on top of the other and separated from each other by dielectric layers.

[0107] Figure 7A Examples Figure 6B A top view of an example data word line layer WL0 of stack 610. As described above, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the data word line layer. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0108] In a three-dimensional memory device, a block BLK can be divided into sub-blocks, each sub-block comprising a group of NAND strings with a common SGD control line. See, for example, the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. Furthermore, the word line layer within the block can be divided into multiple regions. Each region is within a corresponding sub-block and can extend between contact line connectors (e.g., slots) periodically formed in a stack to process the word line layer during the manufacturing process of the memory device. This processing may include replacing the sacrificial material of the word line layer with metal. Generally, the distance between the contact line connectors should be relatively small to account for limitations on the distance that etchant can travel laterally to remove the sacrificial material, and the distance that metal can travel to fill the voids created by the removal of the sacrificial material. For example, the distance between the contact line connectors may allow for several rows of memory vias between adjacent contact line connectors. The layout of the memory vias and contact line connectors should also consider limitations on the number of bit lines that can extend across the region, while each bit line is connected to a different memory cell. After processing the data word line layer, the contact line connectors may optionally be filled with metal to provide interconnects across the stack.

[0109] In this example, four rows of memory holes exist between adjacent contact line connectors. Here, a row is a set of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the density of the memory holes. The data word line layer, or data word line, is divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by contact line 713. In one method, the last region of the data word line layer in a block can be connected to the first region of the data word line layer in the next block. Contact line 713 is then connected to a voltage driver for the data word line layer. Region WL0a has example memory holes 710, 711 along contact line 712. Region WL0b has example memory holes 714, 715. Region WL0c has example memory holes 716, 717. Region WL0d has example memory holes 718, 719. Memory holes are also... Figure 7B As shown in the diagram. Each memory hole can be part of a corresponding NAND string. For example, memory holes 710, 714, 716, and 718 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0110] Each circle represents a cross-section of a memory aperture at a data word line layer or SG layer. Example circles shown in dashed lines represent the material within the memory aperture and the memory cell provided by the adjacent data word line layer. For example, memory cells 720 and 721 are in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells are at a common height in the stack.

[0111] Contact wire connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 may be located between and adjacent to the edges of regions WL0a to WL0d. Contact wire connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where this conductive line is connected to a voltage driver in a peripheral region of the memory device.

[0112] Figure 7B Examples Figure 6BThe image shows a top view of the top dielectric layer DL116, an example of a stacked array. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in a region of the data word line layer to be programmed simultaneously, with each memory cell located in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to enable or disable programming during each programming voltage.

[0113] Region DL116a has example memory holes 710, 711 along contact lines 712 coinciding with bit line BL0. Multiple bit lines extend above and are connected to the memory holes, as indicated by the "X" symbol. BL0 is connected to a set of memory holes including memory holes 711, 715, 717, and 719. Another example bit line BL1 is connected to a set of memory holes including memory holes 710, 714, 716, and 718. Also illustrated... Figure 7A The contact wire connectors (e.g., slots, such as metal-filled slots) are 701, 702, 703, and 704, because they extend vertically through the stack. Bit lines can cross the DL116 layers in the x-direction, numbered sequentially from BL0 to BL23.

[0114] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in the adjacent row of cells adjacent to the first row at the left edge.

[0115] Figure 8 A specific embodiment of the sensing circuit 800 according to an embodiment of the present disclosure is generally illustrated. The sensing circuit 800 may be an example embodiment of one of the sensing circuits 550a, 551, 552a, and 553a. Therefore, the sensing circuit 800 may be associated with a corresponding data latch, as described above in conjunction with... Figure 5 As described. The sensing circuit 800 includes NAND strings connected to corresponding bit lines (BLs). BLs may be bit lines included in the memory array 126 (e.g., as...). Figure 2The example implementation (BL0, BL1, etc.) is shown. The NAND string is connected to the SGD at one end, and the control gate of the drain-select gate is connected via the common SGD line. The NAND string is connected to the SGS at the other end.

[0116] In addition, such as Figure 8 As shown, the sensing circuit 800 includes a transistor BLS, a bit line clamp (BLC), BLX, XXL, and NLO. BL communicates with the BLS and BLC transistors. The BLS transistor is a high-voltage transistor that isolates the sensing circuit, which has low-voltage transistors, from the high voltage of the memory array. During sensing, the BLS is conductive. The BLC transistor clamps the voltage on the bit line by controlling its gate voltage and supplying a sufficiently high voltage at the drain of the BLC transistor. Furthermore, in Figure 8 In this circuit, sensing circuit 800 includes a bit line discharge (BLD) transistor configured to discharge HV from BL. In some embodiments, the BLD signal may be generated by a data latch in the local bus (LBUS) (e.g., in conjunction with the above). Figure 5 The described sensing circuit is controlled by an associated data latch. Using the output of the data latch, the BLD transistor can be individually turned on or off. Therefore, bit-by-bit control can be achieved.

[0117] The memory cells of the memory block discussed above can be erased, programmed, and read. At the end of a successful programming operation, the threshold voltage of the memory cell should appropriately fall within one or more distributions of the threshold voltages of the programmed memory cell or within the distribution of the threshold voltages of the erased memory cell. For example, Figure 9 The threshold voltage Vth distribution of a set of memory cells programmed according to a single-cell-per-memory-bit (SLC) memory scheme is depicted. In the SLC memory scheme, there are two data states, including an erase state (Er) and a single-programmed data state (S1). Figure 9 Two threshold voltage distributions are shown, one for the erase state (Er) and one for a single programmed data state (S1). Memory cells with threshold voltages in threshold voltage distribution Er are therefore in the erased data state (e.g., they are erased). Memory cells with threshold voltages in threshold voltage distribution S1 are therefore in the programmed data state (e.g., they are programmed). By testing (e.g., performing one or more sensing operations) whether the threshold voltage of a given memory cell is higher or lower than the read comparison voltage Vr, the memory device can determine whether the memory cell is in the erase state (Er) or the programmed data state (S1). Furthermore, Figure 9 A verification reference voltage Vv is described. In some implementations, when memory cells are programmed to the programming data state S1, the memory device can test whether those memory cells have a threshold voltage greater than or equal to Vv.

[0118] Figure 10 and Figure 11 An example threshold voltage distribution of a memory array is illustrated when each memory cell stores multiple bits of data. A memory cell that stores multiple bits of data per memory cell is called a multilevel cell (“MLC”). Figure 10 The threshold voltage Vth distribution for a three-cell per-cell (TLC) memory scheme is illustrated, which includes a total of eight data states: an erase state (Er) and seven programming data states (S1, S2, S3, S4, S5, S6, and S7). Figure 11 The threshold voltage Vth distribution for a four-bit per cell (QLC) memory scheme is depicted, which includes a total of sixteen data states: an erase state (Er) and fifteen programming data states (S1 to S15). Other memory schemes are also available, such as two-bit per cell with four data states or five-bit per cell (PLC) with thirty-two data states.

[0119] refer to Figure 10 As an illustrative example, each programmed data state (S1 to S7) is associated with a corresponding read comparison voltage (Vr1 to Vr7), which can be used to read data from the memory cell. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is higher or lower than the read comparison voltage, the memory device can determine what data state the memory cell is in (i.e., S1 to S7). It should be noted that, although not explicitly stated for readability purposes... Figure 10 It is explicitly shown in the document, but each programmed data state (S1 to S15) can be associated with a corresponding read comparison voltage (Vr1 to Vr15).

[0120] Each programming data state (S1 to S7) is also associated with a corresponding verification voltage (Vv1 to Vv7), which is used during the programming verification portion of the programming operation. In some embodiments, when a memory cell is programmed to data state S1, the memory device tests whether those memory cells have a threshold voltage greater than or equal to Vv1. When a memory cell is programmed to data state S2, the memory device tests whether the memory cell has a threshold voltage greater than or equal to Vv2. Thus, for example, when a memory cell is programmed to a data state, the memory device determines whether the memory cell has a threshold voltage greater than or equal to the corresponding verification voltage. Figure 10 The verification voltage Vev is also shown, which is the voltage level used to test whether a memory cell has been properly erased.

[0121] In implementations utilizing full sequence programming, the following can be used: Figure 13 and / or Figure 15The process (discussed below) directly programs the memory cell from the erased data state Er to the programmed data state (e.g., Figure 10 In the example, any programming data state in S1 to S7). For example, first, the group of memory cells to be programmed is erased, such that all memory cells in the group are in the erased state Er. Then, the memory cells are directly programmed into programming data states (e.g., ...) using a programming process. Figure 10 In the examples S1 to S7). For example, while some memory cells are being programmed from erase state Er to programming data state S1, other memory cells may be programmed from erase state Er to programming data state S2 and / or from erase state Er to programming data state S3, and so on. In some embodiments, programming data states may overlap, wherein control circuitry 110, controller 122, and / or control circuitry 150 rely on error correction to identify the correct data being stored. Note that in some embodiments, the system may use a multi-pass programming process known in the art, rather than using full-sequence programming.

[0122] Generally, during programming-verification and reading operations, the selected data word line is connected to a voltage (an example of a reference signal), the level of which is specified for each read operation (e.g., ...). Figure 10 In the example, reading the comparison voltages Vr1 to Vr7) or a program-verification operation (e.g., Figure 10 The example uses verification voltages Vv1 to Vv7 to determine if the threshold voltage of the relevant memory cell has reached such a level. After applying the data word line voltage, the conduction current of the memory cell is measured to determine if the memory cell is turned on (conducting current) in response to the voltage applied to the data word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the data word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell is not turned on and the voltage applied to the data word line is not greater than the threshold voltage of the memory cell. During a read or program-verify operation, unselected memory cells are provided with one or more read-through voltages (also known as bypass voltages) at their control gate, causing these memory cells to operate as pass-through voltages (e.g., conducting current, regardless of whether they are being programmed or erased).

[0123] There are many ways to measure the conduction current of a memory cell during a read or program-verify operation. In one example, the conduction current of the memory cell is measured by the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or disallows) the discharge of the NAND string of the memory cell to the corresponding bit line. The voltage on the bit line is measured after a period of time to see if it has been discharged. Note that the techniques described herein can be used in conjunction with various methods known in the art for verification / read. Other read and verification techniques known in the art can also be used.

[0124] Figure 12 The waveform 1200, or pulse train, of the example programming operation is depicted. The horizontal axis depicts time, and the vertical axis depicts the control gate or word line voltage through multiple program-verify iterations. For simplicity, a square waveform is depicted for each programming pulse and each verification pulse; however, other shapes are possible, such as multi-level shapes or diagonal variation shapes. Furthermore, incremental step pulse programming (ISPP) is used in this example, where the amplitude of the programming (VPGM) pulses 1202 to 1218 gradually increases in a fixed increment (e.g., dVpgm) in each successive programming cycle.

[0125] The pulse train begins at an initial VPGM pulse level and ends at a final VPGM pulse level, which does not exceed the maximum allowed level. The pulse train 1200 includes a series of VPGM pulses 1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216, 1218… which are applied to the control gate of the selected word line. As an example, based on the target memory state being verified in each program-verify iteration, one, two, three, or more verification voltage pulses 1220 to 1236 are provided after each VPGM pulse 1202 to 1218. A 0V voltage can be applied to the control gate of the selected word line between the VPGM pulses and the verification voltage pulses.

[0126] Figure 13This is a flowchart describing one embodiment of a process 1300 for programming memory cells. For the purposes of this document, the terms program and programming are synonymous with write and writing. In an example embodiment, one or more control circuits discussed above (e.g., control circuit 110, controller 122, and / or controller 150) may be used to perform process 1300 against memory array 126. Process 1300 may include multiple loops (referred to as programming loops), each of which includes a programming operation and a program-verification operation. Process 1300 can be executed to implement full-sequence programming as well as other programming schemes that include multi-pass programming, which involves a programming process that uses multiple passes to complete the programming. When implementing multi-pass programming, process 1300 can be used to implement any pass / per pass of the multi-pass programming process.

[0127] The programming cycle of a programming operation comprises the following phases: P_CLK (a preparation clock as a precursor to actual programming), PD_CLK (a programming duration clock during which actual programming occurs), PR_CLK (a programming recovery clock), and RR_CLK (a read recovery clock as the final phase of the programming verification operation, which may follow P_CLK). P_CLK includes bit line and word line voltage ramp changes and pre-charge. During P_CLK, the selected word line ramp rises (e.g., pre-charges) to VPGM, and the unselected word line ramp changes to VPASS. During PD_CLK, the signals level off, and the memory cell is programmed. In RR_CLK, the word line voltage is brought back to ground to prepare for the next programming cycle. RR_CLK is also where some bit scan operations may occur as part of a programming-verification operation, verifying that the memory cell has reached a target state and can be locked in the next programming cycle without further programming. Each phase can be divided into multiple sub-clocks (or time windows) during which certain actions of the programming operation can be performed. For example, P_CLK can be divided into 15 sub-blocks (P1 to P15). PD_CLK can also be divided into multiple sub-clocks, such as, but not limited to, 10 sub-blocks (e.g., PD1, PD2, PD3, ..., PD10).

[0128] During the programming operation, a programming voltage is applied as a series of programming pulses (e.g., voltage pulses) to the control gate (via a selected data word line). Between the programming pulses is a set of verification pulses (e.g., voltage pulses) used to perform verification. In many implementations, the magnitude of the programming pulses increases by a predetermined step with each successive pulse. In step 1302, the programming voltage signal (VPGM) is initialized to a starting value (e.g., between approximately 12V and -16V or another suitable level), and the programming counter PC maintained by state machine 112 is initialized to 1. In one example, a set of memory cells selected for programming (referred to herein as selected memory cells) are programmed concurrently and all connected to the same data word line (referred to herein as selected data word line). There may be other memory cells not selected for programming (referred to herein as unselected memory cells), which are also connected to the selected data word line. That is, the selected data word line may also be connected to memory cells that should be prevented from being programmed. Furthermore, when a memory cell reaches its expected target data state, further programming of these memory cells is prohibited. The NAND strings (e.g., unselected NAND strings) that include memory cells connected to selected data word lines to be disabled for programming are boosted in their channels to disable programming. When the channel has a boost voltage, the voltage difference between the channel and the data word line is not large enough to induce programming. To assist the boost, in step 1304, the control die precharges the channels of the NAND strings that include memory cells connected to selected data word lines to be disabled for programming. In some embodiments, precharging the channels of unselected NAND strings clears the electrons from the channels and raises the channels to a low positive voltage (e.g., approximately 1V to 1.3V). In step 1306, the NAND strings that include memory cells connected to selected data word lines to be disabled for programming are boosted in their channels to disable programming. Such NAND strings are referred to herein as "unselected NAND strings". In some examples, the unselected data word line receives one or more boost voltages (e.g., approximately 7V to 11V), also known as the through voltage (VPASS), to perform the boost scheme. Before boosting the channel via VPASS, a programming inhibit voltage (VHSA) is applied to the bit line coupled to the unselected NAND string. In one example, the channel is pre-charged to 2 volts in step 1304 and then floated. In step 1306, the channel is boosted from 2 volts to a boost voltage of approximately 8 to 10 volts.

[0129] In step 1308, a programming voltage pulse of the programming voltage signal VPGM is applied to the selected data word line (the data word line selected for programming). In some embodiments, the magnitude and / or pulse width of the programming voltage pulse may be modified from standard magnitude and / or pulse width by one or more offsets, as described below. If a memory cell on the NAND string is to be programmed, the corresponding bit line is biased to the programming enable voltage. In step 1308, the programming pulse is concurrently applied to all memory cells connected to the selected data word line, such that all memory cells connected to the selected data word line are programmed concurrently (unless programming is disabled). That is, they are programmed at the same time or during the overlap time (both are considered concurrent). In this way, all memory cells connected to the selected data word line will concurrently change their threshold voltage unless programming is disabled. Step 1308 may be performed at the end of P_CLK and tends to stabilize during PD_CLK.

[0130] In step 1310, a programming-verification operation is performed, and memory cells that have reached their target state may be locked to prevent further programming by one or more control circuits (e.g., system control circuit 110, controller 122, controller 150, and / or sensing circuit controller 550). The programming-verification operation may include one or more sensing operations and one or more bit scans. For example, step 1310 includes performing verification of the programming by sensing a threshold voltage of the memory cell selected for programming (e.g., one or more sensing operations) and verifying that the sensed voltage is at one or more verification comparison levels (e.g., one or more bit scans). The results of the sensing operations may be collected in a data latch and used for one or more bit scans. In some examples, the programming-verification operation is performed by testing whether the threshold voltage of the memory cell selected for programming has reached an appropriate verification voltage to prepare for the next programming pulse. Figure 10In one example, process 1300 can be executed concurrently for memory cells being programmed into data states S1, S2, S3, S4, S5, S6, and S7. In this example, step 1310 may include testing for each of data states S1, S2, S3, S4, S5, S6, and S7 (e.g., testing to see if the memory cell has a threshold voltage greater than Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7). In another example, during a process called the smart verification process, the system may test a subset of data states S1, S2, S3, S4, S5, S6, and S7 based on the current threshold voltage of the memory cell during each loop of steps 1304 to 1326. In step 1310, the memory cell may be locked after it has been verified (by the test of Vth) that it has reached its target state. The programming-verification operation (or a portion thereof) may be performed during RR_CLK.

[0131] If it is determined in step 1312 that all memory cells have reached their target threshold voltage (pass), the programming process is complete and successful because all selected memory cells have been programmed and verified to their target state. The status "pass" is reported in step 1314. Otherwise, if it is determined in step 1312 that not all memory cells have reached their target threshold voltage (failure), the programming process continues to step 1316.

[0132] In step 1316, the number of memory cells that have not yet reached their corresponding target threshold voltage distribution is counted. That is, the number of memory cells that have failed to reach their target state so far is counted. This counting can be performed by state machine 112, circuit 110, controller 122, control circuit 150, and / or another circuit. In one example, there may be a total count that reflects the total number of currently programmed memory cells that have failed the previous verification step. In another example, a separate count is maintained for each data state.

[0133] In step 1318, it is determined whether the count from step 1316 is less than or equal to a predetermined limit. In some examples, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during a page read operation targeting a memory cell. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and the status "passed" is reported in step 1314. In this case, enough memory cells have been correctly programmed so that ECC can be used during the read operation to correct the few remaining memory cells that have not yet been fully programmed. In some examples, the predetermined limit used in step 1318 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read operation to allow for future / additional errors. When programming fewer than all memory cells for a page, or when comparing counts for only one data state (or fewer than all states), the predetermined limit may be a portion (proportional or non-proportional) of the number of bits that can be corrected by ECC during a page read operation targeting a memory cell. In some embodiments, the limit is not predetermined. Instead, the limit varies based on the number of errors counted against the page, the number of program-erase cycles performed, or other criteria.

[0134] If the number of failed memory cells is not less than a predetermined limit, the programming process continues at step 1320 and the programming counter (PC) is checked against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​may be used. If the programming counter (PC) is not less than the programming limit value (PL), the programming process is considered to have failed, and a "failure" status is reported in step 1324. If the programming counter (PC) is less than the programming limit value (PL), the process continues at step 1326, during which time the programming counter (PC) increments by 1 and the programming voltage signal VPGM gradually increases to the next magnitude. For example, the next pulse will have a magnitude of dVpgm that is larger than the previous pulse (e.g., a step size of 0.1 volts to 1.0 volts). After step 1326, the process loops back to step 1304, and another programming pulse is applied to the selected data word line (by controlling the die), causing another loop of the programming process 1300 (steps 1304 to 1326) to be executed. The loop of programming process 1300 (steps 1304 to 1326) can be referred to as the programming loop.

[0135] In some implementations, memory cells are programmed in order from the source side to the drain side. For example, process 1300 is first executed to program the memory cells connected to WL0, then process 1300 is used to program the memory cells connected to WL1, then process 1300 is used to program the memory cells connected to WL2, then process 1300 is used to program the memory cells connected to WL3, ..., and then process 1300 is used to program the memory cells connected to the final WL (e.g., ...). Figure 2 , Figure 6B and Figure 6C In the example, the memory cell WL111 is programmed. This programming sequence can be called Normal Sequential Programming (NOP).

[0136] In another implementation, the memory cells are programmed in order from the drain side to the source side. For example, process 1300 is first executed to program the memory cell connected to the final WL111, then process 1300 is used to program the memory cell connected to WL110, ..., and so on. Figure 13 The process involves programming the memory cells connected to WL1, and then using process 1300 to program the memory cells connected to WL0. This programming sequence can be called reverse sequential programming (ROP).

[0137] In one implementation, memory cells are erased before programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programming data state to an erase data state. For example, changing the threshold voltage of one or more memory cells from... Figure 9 The state changes from S1 to Er. Figure 9 The state changes from S1 to S7 to state Er, or from... Figure 10 The state changes from S1 to S15 to state Er.

[0138] There is an ongoing need to develop programming techniques that tighten the threshold voltage distribution of programming data states to improve programming reliability, but without sacrificing performance (i.e., programming time). One such technique is called Quick Through Write (QPW), which slows down the programming of memory cells that have passed the verification low VL voltage but not yet the verification high VH voltage for a given data state. To slow down programming, a QPW voltage (VQPW) is applied to the bit line coupled to the memory cell that has passed the verification low (VL) voltage associated with the programming data state (e.g., data state S1) during the application of a VPGM pulse to the control gate of the selected word line. The QPW voltage increases the voltage in the channel containing the memory cell that is to be programmed slowly, thereby reducing the voltage difference between the programming pulse VPGM and the channel and slowing the flow of electrons into the charge trapping material of the memory cell being programmed. Then, any memory cell that is verified to be high (VH) is locked or disabled to prevent further programming (e.g., programming is disabled by the next programming pulse) by applying a disable voltage VHSA to the bit line coupled to those memory cells during the subsequent VPGM pulse.

[0139] Now go to Figure 14 The diagram illustrates the Vt distribution of memory cells programmed to a given programming data state (e.g., data state S1) at different points during a programming operation. Curve 1400 identifies the Vt distribution of memory cells after a given programming pulse, and curve 1402 identifies the Vt distribution of the same memory cells after a subsequent programming pulse. As shown, in curve 1400, some memory cells fall between the verification low VL and verification high VH, while some memory cells fall above the verification high VH. During subsequent programming pulses, programming is disabled for memory cells falling above the verification high VH, and programming is slowed down via QPW for memory cells falling between the verification low VL and verification high VH. After subsequent programming pulses, curve 1402 illustrates that the Vt distribution has been tightened, and all memory cells now fall above VH.

[0140] Figure 15 An example of a process 1500 for applying QPW to program a memory cell is illustrated. Process 1500 includes receiving a programming command (e.g., specifying data to be read at a location such as a word line) at step 1502 and delivering a programming pulse (e.g., ...) at step 1504. Figure 13 Step 1308). Process 1500 includes performing a programming-verification operation at steps 1504 to 1516 to verify that the memory cell has reached its target state and can be locked without further programming (e.g., Figure 13 Step 1310).

[0141] Process 1500 may include a program-verification operation that verifies whether a threshold voltage of the memory cell selected for programming has reached a verification high (VH) voltage associated with the programming data state. At step 1506, the program-verification operation can be performed by applying appropriate signals to the data word line, bit line, source line, and selected line to verify whether the threshold voltage of the memory cell selected for programming has reached a verification high (VH) voltage associated with the programming data state. Figure 9 Sensing (e.g., a second sensing operation) is performed under one or more of the verification high voltages (S1 to S7). Step 1506 may include testing for each of the data states S1, S2, S3, S4, S5, S6, and S7. In another example, in a process called a smart verification process, the system may test a subset of the data states S1, S2, S3, S4, S5, S6, and S7 during each cycle based on the current threshold voltage of the memory cell. The results of the second sensing process may be collected in one or more data latches. At step 1508, the operation of the programming-verification operation determines whether the selected memory cell being tested and programmed has a threshold voltage greater than the verification high voltage (e.g., the threshold voltage passes through or reaches the VH voltage) (sometimes referred to herein as a second bit scan, also known as a lockout high or lockout H bit scan). At step 1510, any memory cell passing through the VH voltage can be locked or disabled without further programming by applying a programming inhibit voltage (VHSA) to the bit lines coupled to those memory cells during a subsequent VPGM pulse. In the example, step 1508 (e.g., the second bit scan) can be performed during RR_CLK, while step 1506 (e.g., the second sensing operation) can be performed before RR_CLK.

[0142] Process 1500 may include another operation of the programming-verification operation that verifies whether the threshold voltage (not yet reached VH voltage) of the memory cell selected for programming has reached the verification low (VL) voltage associated with the programming data state. At step 1512, the programming-verification operation can be performed by applying appropriate signals to the data word line, bit line, source line, and selected line to verify whether the threshold voltage (not yet reached VH voltage) of the memory cell selected for programming has reached the verification low (VL) voltage associated with the programming data state. Figure 9Sensing (e.g., a first sensing operation) is performed at one or more of the verification low voltages (S1 to S7). The results of the first sensing process can be collected in one or more data latches. At step 1514, the operation of the programming-verification operation determines whether the selected memory cell being programmed under test has a threshold voltage greater than the verification low voltage (e.g., the threshold voltage passes or reaches the VL voltage) (sometimes referred to herein as the first scan, also known as the lockout low-bit scan or lockout L-bit scan). During this time, memory cells determined at step 1506 to have passed the VH voltage are locked and not sensed at step 1512. At step 1516, a QPW voltage (VQPW) is applied to the bit lines coupled to those memory cells that have passed the verification low (VL) voltage associated with the programming data state. As noted above, the QPW voltage increases the voltage in the channel containing the memory cell that is desired to be slowly programmed, thereby reducing the voltage difference between the programming pulse VPGM and the channel and slowing the flow of electrons into the charge trapping material of the memory cell being programmed. In the example, step 1514 (e.g., the first scan) can be initiated during P_CLK or PD_CLK and can be completed during P_CLK or PD_CLK, while step 1512 (e.g., the first sensing operation) can be performed before RR_CLK. By applying VTH_BLDR, the BLC transistor can operate in the linear region (opposite to the saturation region), which allows the entire BLC transistor channel to be inverted. At time ta, SGD rises to VSGD (which is high enough to turn on the voltage of the transistor used for selecting the gate, which can be approximately 3.5V to 6V). The lockout L-bit scan waits for the BLC transistor (e.g., ...) before initialization. Figure 15 The voltage ramp on the BLC (Band LC) drops, which waits for the SGD ramp to drop to VSS. Therefore, at time tb (e.g., the end of P7), the SGD ramp drops to VSS, and at time tc (e.g., the end of P9), the BLC ramp drops to VSS. This allows the channel to float (e.g., Figure 13Step 1304) can be performed, and a lockoutL bit scan can be performed during P10 to P13. Once the lockoutL bit scan is complete and it is determined that the memory cell has a threshold voltage between the VH and VL voltages, the BLC signal ramp can be raised to the BLC QPW voltage (VBLC_QPW), which is high enough to turn on the BLC transistor and precharge the selected bit line. VBLC_QPW can be lower than VTH_BLDR, for example, VBLC_QPW can be significantly lower than VTH_BLDR (e.g., VBLC_QPW can be approximately 0.3V to 1.05V). Turning on the BLC transistor precharges the selected bit line, specifically allowing the voltage on the bit line coupled to the memory cell (referred to as the QPW bit line or BL(QPW) to VQPW) determined during the lockoutL bit scan.

[0143] In the example, the operation of verifying whether the threshold voltage of the selected memory cell for programming has reached the verification high (VH) voltage associated with the programming data state in a programming-verification operation can be referred to as the second operation of the programming-verification operation. In one example, the second operation of the programming-verification operation may include a second sensing operation (e.g., applying an appropriate signal to perform sensing at one or more verification high voltages) and a second bit scan operation (e.g., determining whether the selected memory cell being programmed has a threshold voltage greater than the verification high voltage). In this case, the operation of verifying whether the threshold voltage of the selected memory cell is between the VH voltage and the verification low (VL) voltage in a programming-verification operation can be referred to as the first operation of the programming-verification operation. In one example, the first operation of the programming-verification operation may include a first sensing operation (e.g., applying an appropriate signal to perform sensing at one or more verification low voltages) and a first bit scan operation (e.g., determining whether the selected memory cell being programmed has a threshold voltage between the verification low voltage and the verification high voltage).

[0144] In the case of NOP (e.g., memory cells are precharged in order from drain to source), the voltage on the gate of the BLC transistor must wait for the voltage on SGD to decrease before the voltage on the BLC signal can decrease. Figure 16A As shown. This is because NOP relies on pre-charging the memory cells from the drain side. The BLC transistor ramp-down clamps the voltage on the bit lines and allows the lockoutL bit scan to be performed. Therefore, the lockoutL bit scan can begin only after the ramp-down of the BLC signal at P10 of P_CLK. However, the lockoutL bit scan logic may take time to execute, which may be longer than the time allocated for P10 to P13. Therefore, as... Figure 16B As shown, a lockoutL bit scan can cause gating of the bit line at P14 that applies VQPW to the memory cell coupled to the lockoutL bit scan, thereby delaying the programming operation.

[0145] In the case of ROP (e.g., memory cells are precharged in order from source to drain), BLC operation is separated from memory precharge. Therefore, BLC does not need to wait for SGS descent before its own descent, as... Figure 17A As shown. Therefore, to address programming latency, an early lockout L-bit scan mode can be used, shifting the start of the lockout L-bit scan from P10 to P7. This is possible because the voltage on the gate of the BLC transistor can slope down earlier (e.g., at P7), as... Figure 17A As shown. This is possible in ROP because the channel precharge primarily comes from the source side (e.g., SGS). Therefore, the BLC transistor can be turned off earlier without degrading the channel precharge. By shifting the start of the lockoutL bit scan to P7, the lockoutL bit scan can be performed in the background of precharge during P_CLK. This allows for a shorter time window from P10 to P13, after which VQPW can be applied to the appropriate bit line (e.g., as shown) at P14. Figure 17B (As shown). Early LockoutL mode can reduce programming time by 1.3µs for TLC storage solutions, 10µs for MLC storage solutions, and 40µs for more sophisticated storage solutions.

[0146] However, when using the early lockoutL bit scan mode, issues may arise regarding VSGD window degradation. Insufficient charging of prohibited bit lines and long channel float times lead to VSGD window degradation (see, for example, [link to relevant documentation]). Figure 18 This illustrates the VSGD window loss during DAC shift as a function of the upper tail of the erase state voltage distribution. Each NAND parameter has a digital-to-analog mapping table, and the DAC can be referenced to its position in this table to represent the corresponding analog value applied to that parameter. The VSGD window loss causes distortion of the upper tail of the erase state distribution (see, for example, [reference needed]). Figure 19 This illustrates the increased upper tail distortion as a function of the VSGD DAC offset. Upper tail distortion can cause programming interference or unintentional programming of some memory cells within the memory cell.

[0147] Figure 20 The voltages applied to various components of the memory block during the programming cycle, in which programming-verification operations are performed during precharge, are illustrated. Figure 20An example is given in preparation for a lockoutL bit scan to be performed using an early lockoutL mode (e.g., a lockoutL bit scan starting at P7 in the time period P_CLK, as described above). Figure 17A The example voltage signal applied during the process is described.

[0148] Figure 20 The following signals are described: SGS, SGD(sel), SGD(unsel), WL(sel), WL(unse1), BLC, BL(QPW), BL(Prog), BL(Inhibit). BL(Prog) is the voltage applied to a bit line connected to a NAND string with memory cells selected for programming. BL(Inhibit) is the voltage applied to a bit line connected to a NAND string without any memory cells selected for programming. BL(QPW) is the voltage applied to a bit line connected to a NAND string with memory cells selected for slow programming. SGD(sel) is the voltage applied to the region selected for programming (e.g., combined with the above). Figure 7A The voltages on the drain-side select (SGD) lines for the regions WL0a, WL0b, WL0c, and WL0d are described. SGD(unsel) is the voltage applied to the SGD lines for regions not selected for programming. SGS is the voltage applied to the source-side select (SGS) lines. WL(sel) is the voltage on the data word lines selected for programming, meaning WL(sel) is connected to the memory cell selected for programming. WL(unsel) is the voltage on the unselected data word lines. BLC is the voltage applied to the gate of the BLC transistor connected to the bit line.

[0149] Figure 20 The sub-clocks P1 through P15 correspond to P_CLK, during which the selected word line ramp rises (e.g., channel precharge) to VPGM, and the unselected word line ramp changes to VPASS (e.g., ...). Figure 13 Steps 1304 to 1308). PD_CLK corresponds to the programming of the selected memory cell during programming cycle M in the programming loop of steps 1304 to 1326 (e.g., Figure 13 Step 1308). The sub-clocks P10 to P13 also correspond to a part of the programming-verification operation (e.g., Figure 13Step 1310), where the memory cell selected for programming is verified by a VL voltage associated with the programming data state (e.g., lockoutL bit scan). For example, sub-clocks P10 to P13 may correspond to bit scans (e.g., lockoutL bit scans). In the example, a previous bit scan (e.g., lockoutH bit scan) may be performed before P_CLK (e.g., during RR_CLK). Sub-clocks P13 to P15 correspond to boosting the channel of the unselected NAND string during loop M in the programming loop of steps 1304 to 1326 (see step 1310). Figure 13 Step 1306), and a programming voltage pulse is applied to the selected data word line and the selected memory cell (see step 1306). Figure 13 Step 1308).

[0150] Before P1, the BLC signal can be in VTH_BLDR, and Figure 20 All other signals depicted are at a quiescent voltage of VSS (e.g., ground, 0 volts, or another suitable quiescent voltage). At time P4, signal SGS may rise to VSGDPCH. Between P1 and P6, the BL (Inhibit) signal may rise to the programming inhibit voltage VHSA (e.g., approximately 3.5 volts). That is, the signal applied to the bit line coupled to the memory cell verified during the previous lockoutH bit scan may be precharged to VHSA. Setting the BLC signal to VTH_BLDR activates the BLC transistor and allows precharging of the bit line coupled to the memory cell to be inhibited from programming. With Economic Verified Programming (ECOV2P) disabled, the BL (Inhibit) signal may slope down to VHSA starting at P5, as shown by signal 2002. With ECOV2P enabled, the BL (Inhibit) signal may slope down to VHSA before initializing P_CLK, as shown by signal 2004. In either case, the BL (Inhibit) signal can ramp up after a previous lockout H bit scan that determines which memory cells have been successfully programmed (e.g., the threshold voltage has reached VH voltage). At P7, the BLC signal can ramp down to VSS, and the SGS signal can ramp down to VSS at P8. This ramp down of the BLC signal clamps the voltage on the bit lines and allows a lockout L bit scan to begin at P7. By starting the lockout L bit scan at P7, the scan can be completed before P13, and P14 will not be gated. The lockout L bit scan determines which memory cells, which are not inhibited from programming, have a threshold voltage higher than VL voltage (e.g., ...). Figure 5 Steps 1512 to 1514).

[0151] At time P13, the SGD(sel) signal can be boosted to VSGD (which is a voltage high enough to turn on the selected gate transistor, which can be approximately 3.5V to 6V), and WL(sel) and WL(unsel) can be boosted to VPASS (e.g., Figure 13 (Step 1306). At time P15, a programming voltage pulse (VPGM) is applied to WL(sel), which programs the memory cells connected to BL(Prog) that are selected for programming and have a threshold voltage below VL. At time P14, the BLC signal is raised to VBLC_QPW, a voltage level high enough to turn on the BLC transistor to precharge the bit line. Therefore, at P14, BL(QPW) is precharged to VQPW. Raising the BL(QPW) signal to VQPW increases the voltage in the channel containing the memory cells to be slowly programmed, thereby reducing the voltage difference between VPGM and the channel and slowing the flow of electrons into the charge trapping material of the memory cells being programmed when VPGM is applied to the selected WL. As noted above, starting the lockoutL-bit scan at P7 avoids gating the application of VBLC_QPW at P14, which also does not delay the pre-charge of the BL(QPW) signal. Therefore, programming of memory cells can be performed without the delay caused by the lockoutL-bit scan.

[0152] Ideally, when the VQPW signal is applied to the selected BL, the BL (Inhibit) signal changes from the VHSA ramp to VSHA+VQPW, as shown by signal 2006. Therefore, while memory cells connected to the BL (Prog) can be programmed in response to the application of a certain dose of VPGM, memory cells connected to the BL (Inhibit) will be inprogrammable due to the boost in their channel. However, because the BLC signal ramps down earlier (e.g., at P7 in this example), the channel will float (e.g., all bit lines will float) for a longer period than in the case without an early lockout L-bit scan mode, and the BL (Inhibit) signal may not be adequately charged to VHSA, as shown by signal 2008. That is, for example, in the case where the BLC signal ramps down at P10 (e.g.) Figure 16A As shown), BL(Prog), BL(Inhibit), and BL(QPW) each float between sub-clocks P10 and P14, at which time the BLC signal rises to VBLC_QPW. However, in Figure 20In this case, BL(Prog), BL(Inhibit), and BL(QPW) each begin to float at P7, resulting in an increased float time. This increased float time can lead to insufficient VHSA charging on the BL(inhibit) signal, causing programming interference, which can contribute to VSGD window degradation.

[0153] One aspect of this disclosure relates to flexibly assigning a sub-clock to a programming operation based on a sub-clock configured for slow programming of one or more memory cells. In an example, during the application of a programming pulse to a selected word line, a QPW voltage (VQPW) can be applied to a bit line coupled to one or more memory cells determined for slow programming. The bit line can be pre-charged by VQPW by turning on the BLC transistor via applying VBLC_QPW to the gate of the BLC transistor. The timing of turning on the BLC transistor and pre-charging the bit line can be set in control circuitry (e.g., control circuitry 110, controller 122, and / or controller 150) by assigning the voltage to the sub-clock. Based on the assigned sub-clock, the control circuitry can assign one or more earlier sub-clocks to at least one programming-verification operation, which can be performed to determine which memory cells will be programmed via slow programming (e.g., having a threshold voltage between VL and VH voltages). For example, in response to assigning BLC activation to a later sub-clock, a larger number of sub-blocks (e.g., more time) can be allocated to at least one program-verify operation. Compared to the conventional approach of activating the BLC transistor before applying the programming pulse, the example in this paper activates the BLC transistor after applying the programming pulse, which allows for flexible allocation of sub-clocks when the programming pulse is applied to at least one program-verify operation (e.g., lockout L-bit scan).

[0154] Figure 21 The voltages applied to various components of a memory block during an exemplary implementation having a programming cycle with a flexible time window allocated for at least one programming-verification operation are illustrated. Figure 21 Examples are illustrated of voltage signals applied during the preparation for and during the lockout L-bit scan, under multiple sub-clocks allocated according to sub-clocks configured for slow programming (e.g., applying VQPW to the bit line).

[0155] Figure 21The following signals are described: SGS, SGD(sel), SGD(unsel), WL(sel), WL(unsel), BLC, BL(QPW), BL(Prog), BL(Inhibit). BL(Prog) is the voltage applied to a bit line connected to a NAND string with memory cells selected for programming. BL(Inhibit) is the voltage applied to a bit line connected to a NAND string without any memory cells selected for programming. BL(QPW) is the voltage applied to a bit line connected to a NAND string with memory cells selected for slow programming. SGD(sel) is the voltage applied to the region selected for programming (e.g., combined with the above). Figure 7A The voltages on the drain-side select (SGD) lines for the regions WL0a, WL0b, WL0c, and WL0d are described. SGD(unsel) is the voltage applied to the SGD lines for regions not selected for programming. SGS is the voltage applied to the source-side select (SGS) lines. WL(sel) is the voltage on the data word lines selected for programming, meaning WL(sel) is connected to the memory cell selected for programming. WL(unsel) is the voltage on the unselected data word lines. BLC is the voltage applied to the gate of the BLC transistor connected to the bit line.

[0156] Figure 21 P_CLK is divided into sub-clocks P1 to P15, during which the selective word line ramp rises (e.g., channel precharge) to VPGM, and the unselected word line ramp rises to VPASS (e.g., ...). Figure 13 Steps 1304 to 1308). The PD_CLK, divided into PD1 to PDN, corresponds to the programming of the selected memory cell during programming cycle M in the programming loops of steps 1304 to 1326 (e.g., Figure 13 Step 1308). In the example, a programming-verification operation (e.g., a lockoutH bit scan) may be performed before P_CLK (e.g., during RR_CLK) to identify one or more memory cells that will be disabled for programming (e.g., the threshold voltage has passed the VH voltage). The sub-clocks of P13 through P15 correspond to the boosting of the channels of the unselected NAND strings during loop M in the programming loops of steps 1304 through 1326 (see step 1308). Figure 13 Step 1306), and a programming voltage pulse is applied to the selected data word line and the selected memory cell (see step 1306). Figure 13 Step 1308).

[0157] exist Figure 21In the example described above, the sub-clock PD2 can be set for slow programming according to QPW technology. Therefore, in this example, the BLC signal rises to VBLC_QPW at PD2, which turns on the BLC transistor and applies VQPW to BL(QPW). In this case, the sub-clocks P10 to PD1 can be allocated to the programming-verification operation (e.g., Figure 13 Step 1310), wherein the memory cell selected for programming is verified by the VL voltage associated with the programming data state (e.g., lockout L-bit scan), such as Figure 22 As shown. Figure 22 A schematic block timing diagram is depicted for a sub-clock assigned to a programming-verification operation (e.g., lockout L-bit scan) that does not gate the start of slow programming to sub-clock PD2. (Combined with...) Figures 16A to 20 Compared to the described method, this allocation provides additional time for completing the programming-verification operation (e.g., an additional sub-clock), such as Figure 22 As shown. For example, in addition to P10 to P13, this example may also provide three sub-clocks (e.g., P14 to PD1) to complete the programming-verification operation.

[0158] However, depending on the desired application, slow programming can be set to other sub-clocks. For example, in BiCS8 generation flash memory, the VBLC_QPW slash variation can be set to P14, PD1, PD2, or PD3. Table 1 below shows the sub-clock allocations for the programming-verification operation and the additional time allocated under various example VBLC_QPW slash settings.

[0159]

[0160] Table 1

[0161] Return to reference Figure 21 Before P1, the BLC signal can be in VTH_BLDR, and Figure 21All other signals depicted are at the quiescent voltage of VSS. At P4, the signal SGS may rise to VSGDPCH. Between P1 and P6, the BL (Inhibit) signal may rise to the programming inhibit voltage VHSA (e.g., approximately 3.5 volts). That is, the signal applied to the bit line coupled to the memory cell verified during the previous lockoutH bit scan may be precharged to VHSA to inhibit programming. With ECOV2P disabled, the BL (Inhibit) signal may begin to slope to VHSA at P5, as shown by signal 2102. With ECOV2P enabled, the BL (Inhibit) signal may slope to VHSA before the initialization of P_CLK, as shown by signal 2104. In either case, the BL (Inhibit) signal may slope up after the previous lockoutH bit scan of those memory cells that have been successfully programmed (e.g., the threshold voltage has reached VH voltage). At P8, the SGS signal can slope down to VSS, and the BLC signal can slope down to VSS at P9, allowing bit line float, such as... Figure 21 The dashed lines 2106 to 2110 in the diagram indicate that the BLC signal ramp is lowered to clamp the voltage on the bit lines. A lockoutL bit scan can then be initiated at P10 to determine which memory cells that are not disabled for programming have a threshold voltage higher than the VL voltage (e.g., ...). Figure 5 Steps 1512 to 1514).

[0162] At P13, the SGD(sel) signal can be boosted to VSGD, and WL(sel) and WL(unsel) can be boosted to VPASS (e.g., Figure 13 (Step 1306). At P15, a programming voltage pulse (VPGM) can be applied to WL(sel), which programs the memory cells connected to BL(Prog), those memory cells selected for programming with a threshold voltage lower than VL. As discussed above, the BLC signal rises to VBLC_QPW at PD2 to turn on the BLC transistor to precharge the bit line. Therefore, at PD2, the BL(QPW) signal ramps up to VQPW. As noted above, since the bit line starts to float from P10, the BL(Inhibit) signal has sufficient time to charge to VHSA, thus avoiding the aforementioned programming interference and VSGD window degradation. In addition, by allocating an additional sub-clock to the lockoutL bit scan via ramping up the BLC signal at PD2, the lockoutL bit scan does not delay the precharging of the BL(QPW) signal. Therefore, programming of the memory cells can be performed without the delay caused by the lockoutL bit scan.

[0163] Applying VPQW to BL(QPW) at a delayed sub-clock (e.g., PD2 in this example) helps ensure proper programming of memory cells. For example, when the BL(Inhibit) signal is higher than the SGD(sel) signal, the BL(Inhibit) signal cuts off the SGD signal and disables programming of the coupled memory cells. When the SGD(sel) signal is cut off and the word lines (WL(sel) and WL(unsel)) ramp up, the channel is floating and programming is disabled. However, programming is required for memory cells connected to BL(Prog) and BL(QPW). For the bit lines that need to be programmed, SGD needs to be conductive. The bit line coupled to the memory cell to be programmed (e.g., BL(Prog)) can be successfully turned on because BL(Prog) is at VSS, and therefore sufficient conductivity on SGD is easily achieved due to the difference between VSS and VSGD. However, because VQPW is higher than VSS, insufficient conductivity may occur on BL(QPW). In some cases, there may not be sufficient conductivity, and the SGD may be cut off or slightly cut off on the BL(QPW) as the word line is sloping up to VPASS. In this case, because the SGD is cut off (or slightly cut off), programming of the memory cells coupled to the BL(QPW) may be disabled. Therefore, to avoid such complexity, the BL(QPW) can be held at VSS as the word line slops up to VPASS, and sloping up to VQPW after the word line slops up, which avoids accidental disabling of programming.

[0164] Another aspect of this disclosure relates to a flexible delay of at least one program-verify operation based on a sub-clock configured for slow programming of one or more memory cells. In an example, a VQPW can be applied to a bit line coupled to one or more memory cells determined for slow programming during the application of a programming pulse to a selected word line. The bit line can be pre-charged by the VQPW by turning on the BLC transistor via applying the VBLC_QPW to the gate of the BLC transistor. The timing of turning on the BLC transistor and pre-charging the bit line can be set in control circuitry (e.g., control circuitry 110, controller 122, and / or controller 150) by assigning a voltage to the sub-clock. Based on the assigned sub-clock, the control circuitry can delay the start of the program-verify operation, which allows the BLC transistor to remain active for charging the programming inhibit voltage coupled to the bit line of the memory cell to be inhibited from programming. This feature reduces bit line float time to improve the VSGD window. (As described above...) Figures 22 to 24As described, the use of delayed programming-verification operations, coupled with the flexible allocation of sub-clocks for executing and completing the operations, allows the example in this paper to avoid VSGD window degradation while permitting sufficient time to complete the operation.

[0165] Figure 23 The voltages applied to various components of a memory block during an exemplary implementation of a programming loop with delayed programming-verification operations are illustrated. Figure 23 Examples are illustrated of voltage signals applied during the preparation for and during the lockout L-bit scan, under multiple sub-clocks allocated according to sub-clocks configured for slow programming (e.g., applying VQPW to the bit line).

[0166] Figure 23 The following signals are described: SGS, SGD(sel), SGD(unsel), WL(sel), WL(unsel), BLC, BL(QPW), BL(Prog), BL(Inhibit). BL(Prog) is the voltage applied to a bit line connected to a NAND string with memory cells selected for programming. BL(Inhibit) is the voltage applied to a bit line connected to a NAND string without any memory cells selected for programming. BL(QPW) is the voltage applied to a bit line connected to a NAND string with memory cells selected for slow programming. SGD(sel) is the voltage applied to the region selected for programming (e.g., combined with the above). Figure 7A The voltages on the drain-side select (SGD) lines for the regions WL0a, WL0b, WL0c, and WL0d are described. SGD(unsel) is the voltage applied to the SGD lines for regions not selected for programming. SGS is the voltage applied to the source-side select (SGS) lines. WL(sel) is the voltage on the data word lines selected for programming, meaning WL(sel) is connected to the memory cell selected for programming. WL(unsel) is the voltage on the unselected data word lines. BLC is the voltage applied to the gate of the BLC transistor connected to the bit line.

[0167] Figure 23 P_CLK is divided into sub-clocks P1 to P15, during which the selective word line ramp rises (e.g., channel precharge) to VPGM, and the unselected word line ramp rises to VPASS (e.g., ...). Figure 13 Steps 1304 to 1308). The PD_CLK, divided into PD1 to PDN, corresponds to the programming of the selected memory cell during programming cycle M in the programming loops of steps 1304 to 1326 (e.g., Figure 13Step 1308). In the example, a programming-verification operation (e.g., a lockoutH bit scan) may be performed before P_CLK (e.g., during RR_CLK) to identify one or more memory cells that will be disabled for programming (e.g., the threshold voltage has passed the VH voltage). The sub-clocks of P13 through P15 correspond to the boosting of the channels of the unselected NAND strings during loop M in the programming loops of steps 1304 through 1326 (see step 1308). Figure 13 Step 1306), and a programming voltage pulse is applied to the selected data word line and the selected memory cell (see step 1306). Figure 13 Step 1308).

[0168] Before P1, the BLC signal can be in VTH_BLDR, and Figure 21 All other signals depicted are at the quiescent voltage of VSS. At P4, the SGS signal may rise to VSGDPCH. Between P1 and P6, the BL (Inhibit) signal may rise to the programming inhibit voltage VHSA. That is, the signal applied to the bit line coupled to the memory cell verified during the previous lockoutH bit scan may be precharged to VHSA to inhibit programming. With ECOV2P disabled, the BL (Inhibit) signal may begin to slope to VHSA at P5, as shown by signal 2302. With ECOV2P enabled, the BL (Inhibit) signal may slope to VHSA before the initialization of P_CLK, as shown by signal 2304. In either case, the BL (Inhibit) signal may slope up after the previous lockoutH bit scan of those memory cells that have been successfully programmed (e.g., the threshold voltage has reached VH voltage). At P8, the SGS may slope down to VSS.

[0169] The BLC signal can descend from the VTH_BLDR ramp by setting the sub-clock that causes the BLC signal ramp to rise to VBLC_QPW. Figure 23 In the example, sub-clock PD2 can be set to ramp up to VBLC_QPW, which turns on the BLC transistor and applies VQPW to BL(QPW) at PD2. Because the BLC signal ramps up at PD2, an additional sub-clock can be assigned to the programming-verification operation (e.g., Figure 13 Step 1310), as described above in conjunction with Figure 21 As described. That is, for example, an additional sub-clock can be assigned to the lockoutL bit scan (e.g., Figure 15(Step 1514). Because there is an additional sub-clock allocated for the lockout L-bit scan, the start of the lockout L-bit scan can be delayed, especially if the lockout L-bit scan does not require the entire allocated time. Because the lockout L-bit scan can be delayed, the descent of the BLC signal from VTH_BLDR can also be delayed to a later sub-clock.

[0170] exist Figure 23 In the example, because the BLC signal is set to ramp up to VBLC_QPW at PD2, sub-clocks P15 through PD1 can be allocated for the lockout L bit scan, and the BLC signal can ramp down to VSS at P15. This clamps the voltage on the bit lines and allows the bit lines to float, as... Figure 23 The dashed lines 2306 to 2310 are shown in the diagram. A lockoutL bit scan can then be initiated at P15 to determine which memory cells that are not disabled for programming have a threshold voltage higher than the VL voltage (e.g., ...). Figure 5 (Steps 1512 to 1514). Since the bit line starts floating from P15, the BL (Inhibit) signal has sufficient time to charge to VHSA, thus avoiding the aforementioned programming interference and VSGD window degradation. Furthermore, by allocating an additional sub-clock to the lockoutL bit scan via a ramp-up of the BLC signal at PD2, the lockoutL bit scan does not delay the pre-charging of the BL (QPW) signal. Therefore, programming of memory cells can be performed without the delay caused by the lockoutL bit scan.

[0171] At P13, the SGD(sel) signal can be boosted to VSGD, and WL(sel) and WL(unsel) can be boosted to VPASS (e.g., Figure 13 Step 1306). At P15, a programming voltage pulse (VPGM) can be applied to WL(sel), which programs the memory cells connected to BL(Prog) that are selected for programming and have a threshold voltage lower than VL. Figure 23 In the example, the BLC signal rises to VBLC_QPW at PD2 to turn on the BLC transistor to precharge the bit line. Therefore, at PD2, the BL(QPW) signal rises slopingly to VQPW.

[0172] Figure 24 A schematic block timing diagram depicts a sub-clock assigned to a program-verification operation with a delayed start. In various examples, Figure 24 The sub-clocks assigned to bit scans (such as lockoutL bit scans) for programming-verification operations are shown. Figure 24 As shown, the lockoutL bit scan can be delayed within the allocated sub-block without gating the start of the slow programming to sub-clock PD2.

[0173] In the examples above, PD2 is set as the sub-clock where the BLC signal ramps up to VBLC_QPW. However, depending on the desired application, slow programming can be set to other sub-clocks. Table 2 below shows the sub-clock allocation for BLC descent (e.g., ramping down from VTH_BLDR), the sub-clock allocation for lockout L-bit scans, and the additional time allocated under various example VBLC_QPW ramp settings.

[0174]

[0175]

[0176] Table 2

[0177] Figure 25 This is flowchart 2500, which depicts example steps of programming memory cells of selected word lines into multiple bits per memory cell in multiple programming loops. These steps may be performed by a controller, processor, or processing device, or any other circuitry that executes instructions stored in memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps. For example, control circuitry 110, controller 122, and / or control circuitry 150 may be used to perform the steps of flowchart 2500.

[0178] At step 2502, a VPGM pulse is applied to the selected data word line to program one or more non-prohibited memory cells connected to the selected word line. At step 2504, a second bit scan is performed. The second bit scan may include verifying the result of the sensing operation (e.g., verifying one or more pulses) to check whether the threshold voltage Vth of the memory cells connected to the selected data word line exceeds the verification high (VH) voltage associated with the expected data state of those memory cells. The second bit scan can determine which memory cells will be prohibited from further programming because their threshold voltage has passed the VH voltage associated with the expected data state. The second bit scan may be an example lockoutH scan.

[0179] At decision step 2506, it is determined whether the programming of the selected data word line is complete, that is, whether programming to all data states has been completed. If the answer at decision step 2506 is "yes", the programming operation is completed. If the answer at decision step 2506 is "no", the process continues through multiple programming loops until programming is completed or fails.

[0180] At step 2508, a portion of the programming cycle can be allocated to the first scan based on a portion of the programming cycle allocated to initiate slow programming. For example, at step 2508, a setting for causing the voltage ramp applied to the gate of the BLC transistor to rise to VBLC_QPW can be checked, and a portion of the programming cycle (e.g., a sub-clock) can be allocated to the first scan based on this setting. In this example, the allocated portion may include allocating an additional portion (e.g., a sub-clock) to the operation. As an illustrative example, sub-clocks P14 to PD1 can be allocated to the first scan, where slow programming is initiated at sub-clock PD2, as described above. Figure 21 As described. In the example, step 2508 may also include a portion of setting up the programming loop, where the first scan may begin based on settings used to initiate slow programming (e.g., as described above in conjunction with...). Figure 23 (The aforementioned delay begins).

[0181] At step 2510, a programming disable voltage (VHSA) is applied to the bit lines coupled to those memory cells to be disabled from further programming, as determined by the second bit scan (step 2504), while a first voltage (e.g., VTH_BLDR) is applied to the gate of the BLC transistor connected to the bit line. At step 2512, the first voltage slopes down to VSS (or ground). The first voltage may slope down according to a portion of the programming cycle set for the start of the first bit scan. In one example, step 2512 may be performed at sub-clock P10, as in conjunction with... Figure 21 As described. In another example, step 2512 can be performed at any sub-clock between P10 and the sub-clock set to begin slow programming, as in combination. Figure 23 As described.

[0182] At step 2514, a first-bit scan is performed during the allocation portion of the programming loop. The first-bit scan may include verifying the result of a sensing operation to check whether the threshold voltage Vth of the memory cells connected to the selected data word lines exceeds the verification low (VL) voltage associated with the expected data state of those memory cells. The first-bit scan determines which memory cells will be programmed slowly because their threshold voltage has passed the VL voltage associated with the expected data state but is below the VH voltage. The first-bit scan may be an example of a lockout L-bit scan.

[0183] At step 2516, the channel of the data word line is boosted by applying a pass voltage (VPASS). VPASS can be applied to both selected and unselected data word lines. In some examples, such as... Figure 21 As shown, the channel of the data word line can be boosted after the first voltage is ramped down. In other examples, such as... Figure 23 As shown, the channel of the data word line can be boosted before the first voltage is ramped down (e.g., step 2516 can be performed before steps 2512 and 2514). At step 2518, a VPGM pulse for the next programming cycle is applied to the selected data word line to program any non-prohibited memory cells connected to the selected data word line (including memory cells to be slowly programmed).

[0184] At step 2520, a second voltage is applied to the gate of the BLC transistor (e.g., VBLC_QPW), which turns on the BLC transistor and applies VQPW to the bit lines coupled to those memory cells determined for slow programming (e.g., step 2514). VQPW increases the voltage in the channel containing the memory cells to be slow programmed, thereby reducing the voltage difference between the programming pulse VPGM and the channel and slowing the flow of electrons into the charge trapping material of the memory cells being programmed.

[0185] Each of the processes, methods, and flowcharts described in the preceding sections may be embodied in code components executed by one or more controllers or memory devices and may be fully or partially automated by these code components. The methods, processes, and flowcharts described herein are not limited to any particular sequence, and the boxes or steps associated with them may be performed in a suitable other order, or in parallel, or in some other manner. Boxes or steps may be added to or removed from the disclosed examples. For example, the various features and processes described in the various embodiments disclosed above may be used independently of each other or may be combined in various ways. Because of the combination of the various examples disclosed above, the disclosed processes, methods, and flowcharts may have steps or boxes added to or removed from them.

[0186] Various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this description is not intended to distinguish components with different names but the same function. With regard to the various functional units described in the following disclosure being referred to as “modules,” this characterization is intended not to unduly limit the scope of potential implementation mechanisms. For example, a “module” can be implemented as hardware circuitry comprising custom-designed very large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components. In another example, a module can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, or programmable logic devices. Furthermore, modules can also be implemented, at least in part, by software executed by various types of processors. For example, a module may include fragments of executable code constituting one or more physical or logical blocks of computer instructions that translate into objects, procedures, or functions. Furthermore, it is not required that the executable portions of such a module be physically located together, but rather that they may include different instructions stored in different locations and, when executed together, constitute the identified module and achieve the module’s stated purpose. Executable code may consist of a single instruction or a set of instructions, and may be distributed across different code segments, different programs, or multiple memory devices. In software or partial software module implementations, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, apparatuses, or devices, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing programs used by or in connection with an instruction execution system, apparatus, processor, or device.

[0187] Similarly, for the purposes of this disclosure, the term "component" can include any tangible, physical, and non-transitory device. For example, a component can be in the form of hardware logic circuitry, including custom VLSI circuitry, gate arrays, or other integrated circuits, or off-the-shelf semiconductors containing logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic equipment. Furthermore, components can also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, a component can include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices configured to communicate electrically with one or more other components via electrical conductors such as printed circuit boards (PCBs). Therefore, modules as defined above can be embodied in or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0188] When the term "circuit" is used herein, it includes one or more electrical and / or electronic components that form one or more conductive paths allowing current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components provide a return path for the current. In contrast, in an open-loop configuration, the circuit components are still considered to form a circuit, although a return path for the current is not included. For example, an integrated circuit is referred to as a circuit regardless of whether it is coupled to ground (as a return path for the current). In some exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, configured to communicate electrically with one or more other components via electrical conductors, such as a printed circuit board (PCB). A circuit may also be implemented as a composite circuit relative to programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, modules as defined above may be embodied in or implemented as circuits in some embodiments.

[0189] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions that control one or more microprocessors in combination with certain non-processor circuitry and other elements to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without the stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combinations of certain functions is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the term "controller" as used below should be defined to include individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0190] Alternatively, the terms “coupled,” “coupled,” or “couples” as used herein are intended to indicate a direct or indirect connection. Thus, if a first device is coupled or coupled to a second device, the connection can be a direct connection or an indirect connection via other devices (or components) and connectors.

[0191] Regarding terms such as “implementation,” “an implementation,” “exemplary implementation,” “specific implementation,” or other similar terms as used herein, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with that implementation is found in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as “in one implementation,” “in an implementation,” “in an exemplary implementation,” etc., may, but not necessarily, refer to the same implementation, but rather means “one or more, but not all, implementations,” unless expressly stated otherwise. Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…,” unless expressly stated otherwise. Moreover, without further constraints, an element prefixed with “comprising…a” does not exclude the presence of additional identical elements in the subject matter process, method, system, article, or apparatus that includes that element.

[0192] The terms “a,” “an,” and “the” also mean “one or more” unless otherwise expressly stated. For example, a “processor” programmed to perform various functions means one processor programmed to perform each function, or more than one processor collectively programmed to perform each of the various functions. Furthermore, the phrase “at least one of A and B” (where A and B are variables indicating a particular object or attribute) that may be used herein and / or in the following claims indicates either A or B, or a choice of both A and B, similar to the phrase “and / or.” When more than two variables are present in such a phrase, the phrase is thus defined to include only one variable, any one variable, any combination (or subcombination) of any variables, and all variables.

[0193] Furthermore, when used herein, the terms “approximately” or “about” apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated value (e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0194] Furthermore, any list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless otherwise expressly stated. Additionally, the term "set" as used herein should be interpreted as "one or more," and in the case of "set," it should be interpreted as "one or more," "ones or more," and / or "ones or mores" according to set theory, unless otherwise expressly stated.

[0195] For purposes of illustration and description, the foregoing detailed description has been provided. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible based on the above description. The described embodiments have been chosen to best explain the principles of the technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and to make various modifications suitable for the intended particular use. The scope of this technology is defined by the appended claims.

Claims

1. A method for performing a programming-verification operation on a memory device, the method comprising the following steps: Prepare a memory block, the memory block comprising a plurality of memory cells connected to a plurality of data word lines; The first operation of the programming-verification operation is to verify that the threshold voltage of one or more memory cells connected to selected data word lines among the plurality of data word lines is higher than the verification low voltage; as well as During the first operation, a programming voltage is applied to the selected data word line.

2. The method according to claim 1, wherein the first operation is locking the low-order scan.

3. The method of claim 1, wherein performing the first operation further comprises the following steps: A low voltage will be applied to the selected data word line for verification. as well as The low voltage is used to verify the programming of one or more memory cells connected to the selected data word line.

4. The method according to claim 1, further comprising: The first operation is performed after the voltage ramp on the gate of the bit line clamp (BLC) transistor connected to the bit line coupled to the one or more memory cells is reduced. as well as After the first operation is completed, VBLC_QPW is applied to the gate of the BLC transistor.

5. The method of claim 4, wherein the time window allocated to the first operation is defined based on the time for setting the VBLC_QPW to be applied to the gate of the BLC transistor.

6. The method of claim 4, wherein the first operation is initiated based on setting the time for applying the VBLC_QPW to the gate of the BLC transistor.

7. The method of claim 1, wherein performing the first operation comprises: Determine that the threshold voltage of the one or more memory cells is higher than the verification low voltage; as well as Based on the determination, a write voltage is rapidly applied to the bit lines coupled to the one or more memory cells.

8. The method of claim 6, wherein after the programming voltage is applied to the selected data word line, the fast pass-through voltage is applied to the bit line coupled to the one or more memory cells.

9. The method according to claim 1, further comprising: Apply a boost voltage to one or more of the unselected data word lines and the selected data word lines; as well as The first operation begins after the boost voltage is applied.

10. The method according to claim 1, further comprising: Before performing the first operation, A second operation is performed to verify that the threshold voltage of at least one memory cell connected to a selected data word line among the plurality of data word lines is higher than the verification high voltage. as well as A programming disable voltage is applied to a bit line coupled to the at least one memory cell.

11. A memory device, the memory device comprising: A memory block, the memory block comprising a plurality of memory cells arranged in a plurality of data word lines; and The circuit is configured to perform a first operation of a programming-verification operation to verify that a threshold voltage of one or more memory cells connected to a selected data word line among the plurality of data word lines is higher than a verification low voltage, and during the first operation, to apply a programming voltage to the selected data word line.

12. The memory device of claim 11, wherein performing the first operation further comprises the following steps: Apply the verification comparison voltage to the first set of data word lines; as well as The programming of one or more memory cells connected to a selected data word line is verified based on the verification comparison voltage.

13. The memory device of claim 11, wherein the circuitry is further configured to: The first operation is performed after the voltage ramp on the gate of the bit line clamp (BLC) transistor connected to the bit line coupled to the one or more memory cells is reduced; and After the first operation is completed, VBLC_QPW is applied to the gate of the BLC transistor.

14. The memory device of claim 13, wherein the time window allocated to the first operation is defined based on the time for setting the VBLC_QPW to be applied to the gate of the BLC transistor.

15. The memory device of claim 13, wherein the first operation is initiated based on setting the time for applying the VBLC_QPW to the gate of the BLC transistor.

16. The memory device of claim 11, wherein performing the first operation comprises: Determine that the threshold voltage of the one or more memory cells is higher than the verification low voltage; as well as Based on the determination, a write voltage is rapidly applied to the bit lines coupled to the one or more memory cells.

17. The memory device of claim 14, wherein after the programming voltage is applied to the selected data word line, the fast pass-through voltage is applied to the bit line coupled to the one or more memory cells.

18. The memory device of claim 11, wherein the circuitry is further configured to: Before performing the first operation, Perform a second operation to verify that the threshold voltage of at least one memory cell connected to a selected data word line among the plurality of data word lines is higher than the verification high voltage; and A programming disable voltage is applied to a bit line coupled to the at least one memory cell.

19. An apparatus comprising: A memory block comprising a plurality of memory cells arranged in a plurality of word lines and a plurality of bit lines, wherein the bit lines include bit line clamp (BLC) transistors; A controller configured to program one or more memory cells connected to selected word lines in a programming operation, and to allocate a portion of the programming operation to a first operation based on settings defining when to apply voltage to the BLC transistors, the programming operation including: During the programming-verification operation: Verify that the threshold voltage of one or more memory cells connected to selected data word lines of the plurality of data word lines is higher than the verification low voltage, and The programming voltage is applied to the selected data word line.

20. The apparatus of claim 19, wherein the programming operation further comprises: The first operation is performed after the voltage ramp on the BLC transistor is reduced; as well as After the first operation is completed, VBLC_QPW is applied to the BLC transistor.

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