Data storage device and method for improved read threshold calibration of request clustering

Abstract

In some data storage devices, the read threshold for reading a memory page is not fixed and can vary significantly depending on various conditions. The data storage device can perform a read threshold calibration operation for each read request to ensure that the data storage device is reading the memory at the accurate read threshold. However, performing an operation for each read request can reduce power consumption and require expensive hardware. To overcome this problem, one example data storage device described herein applies a clustering method to reduce the read threshold calibration operations performed. In another example, recently computed read thresholds are cached so that if conditions are similar, the read thresholds can be provided without recomputing.

Description

Background Technology

[0001] Data storage devices typically need to support a wide range of operating conditions (such as different programming / erasing cycles, retention times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variations, the read threshold used to read memory pages is not fixed and can vary significantly depending on physical location and operating conditions, especially for newer, less mature memory nodes. Reading with inaccurate read thresholds can result in higher bit error rates, which can degrade performance and quality of service due to decoding failures. Attached Figure Description

[0002] Figure 1A This is a block diagram of the data storage device in the implementation plan.

[0003] Figure 1B This is a block diagram illustrating the storage module of an example implementation.

[0004] Figure 1C This is a block diagram illustrating a hierarchical storage system for an example implementation.

[0005] Figure 2A This is an example based on the implementation plan. Figure 1A The diagram illustrates the components of the controller for a data storage device.

[0006] Figure 2B This is an example based on the implementation plan. Figure 1A The diagram illustrates the components of a data storage device.

[0007] Figure 3 This is a block diagram of the host and data storage devices in the implementation plan.

[0008] Figure 4 This is an example of an implementation scheme architecture.

[0009] Figure 5 This is an example of an implementation scheme architecture.

[0010] Figure 6 This is a flowchart of a method for an implementation of request clustering for improved read threshold calibration.

[0011] Figure 7 This is a flowchart of a method for an implementation of request clustering for improved read threshold calibration. Detailed Implementation

[0012] The following embodiments generally relate to a data storage device and method for request clustering for improved read threshold calibration. In one embodiment, a data storage device is provided, comprising a memory and one or more processors. The one or more processors are configured individually or in combination to: receive a plurality of read requests from a host; determine a cluster of read requests among the plurality of read requests that point to locations in the memory having similar memory conditions; and perform a read threshold calibration operation only on a subset of the read requests in that cluster, and apply the result of the read threshold calibration operation to all read requests in that cluster, rather than performing a read threshold calibration operation on each read request in the cluster.

[0013] In another embodiment, a method is provided to be performed in a data storage device including memory. The method includes: caching read thresholds of a plurality of computations; receiving a read request from a host, wherein the read request points to a location in the memory; determining whether a condition of the location in the memory is similar to a condition associated with a read threshold of one of the plurality of computations in the cache; and in response to determining that the condition of the location in the memory is similar to the condition associated with the read threshold of that one of the plurality of computations in the cache, using the read threshold of that one of the plurality of computations in the cache for the read request, instead of calculating a new read threshold for the read request.

[0014] In another embodiment, a data storage device is provided, the data storage device comprising: a memory; and components for performing the following operations: receiving a plurality of read requests from a host; identifying clusters of read requests among the plurality of read requests that point to locations in the memory with similar conditions; and performing a read threshold calibration operation only on a subset of read requests in the cluster, and applying the result of the read threshold calibration operation to all read requests in the cluster, rather than performing a read threshold calibration operation on each read request in the cluster.

[0015] Other embodiments are possible, and each embodiment can be used alone or in combination. Therefore, various embodiments will now be described with reference to the accompanying drawings.

[0016] Implementation Plan

[0017] The implementation schemes described below relate to data storage devices (DSDs). As used herein, a "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Detailed information about example DSDs is provided below.

[0018] Figures 1A to 1C Examples of data storage devices suitable for implementing various aspects of these implementation schemes are shown below. It should be noted that these are merely examples and other specific implementations may be used. Figure 1A This is a block diagram illustrating a data storage device 100 according to an implementation scheme. (See reference) Figure 1A In this example, the data storage device 100 includes a controller 102 coupled to non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term "die" refers to a non-volatile memory cell formed on a single semiconductor substrate and the associated circuitry for managing the physical operation of those non-volatile memory cells. The controller 102 interfaces with a host system and sends a sequence of commands for read, program, and erase operations to the non-volatile memory die 104. Furthermore, as used herein, the phrase "communicating with" or "coupled with" can mean directly communicating / coupling with or indirectly communicating / coupling with through one or more components, which may or may not be shown or described herein. The communication / coupling can be wired or wireless.

[0019] Controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller) may include one or more components configured individually or in combination to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, such as Figure 2A As shown, controller 102 may include one or more processors 138, which are individually or in combination configured to perform these functions, such as, but not limited to, those described herein and illustrated in the flowcharts, by executing computer-readable program code stored within and / or outside controller 102 (e.g., stored in random access memory (RAM) 116 or read-only memory (ROM) 118). Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0020] In one example implementation, a nonvolatile memory controller 102 is a device that manages data stored on nonvolatile memory and communicates with a host (such as a computer or electronic device) having any suitable operating system. The nonvolatile memory controller 102 may have various functionalities beyond those specifically described herein. For example, the nonvolatile memory controller may format the nonvolatile memory to ensure proper operation, map out faulty nonvolatile memory cells, and allocate spare cells to replace future failed cells. A portion of the spare cells may be used to maintain firmware (and / or other metadata for housekeeping and tracking) to operate the nonvolatile memory controller and implement other features. In operation, the host may communicate with the nonvolatile memory controller when it needs to read data from or write data to the nonvolatile memory. If the host provides a logical address where data will be read / written, the nonvolatile memory controller may translate the logical address received from the host into a physical address in the nonvolatile memory. The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wear on specific blocks of memory that would otherwise be repeatedly written) and garbage collection (moving only valid data pages to a new block after a block is full, so that the full block can be erased and reused).

[0021] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash memory) memory cells and may be programmable once, less-programmable, or more-programmable. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., two-level cells, three-level cells (TLC), four-level cells (QLC), etc.) or may use other memory cell-level technologies now known or developed hereafter. Furthermore, the memory cells may be fabricated in two or three dimensions.

[0022] The interface between controller 102 and non-volatile memory die 104 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, data storage device 100 can be a card-based system, such as a Secure Digital (SD) card or a micro-Secure Digital (micro-SD) card. In another embodiment, data storage device 100 can be part of an embedded data storage device.

[0023] Despite Figure 1AIn the illustrated example, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as...) Figure 1B and Figure 1C In the architecture shown, depending on the controller's capabilities, there may be two, four, eight, or more memory channels between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the figures, there may be more than one single channel between the controller and the memory die.

[0024] Figure 1B An example is illustrated of a storage module 200 comprising multiple non-volatile data storage devices 100. Thus, the storage module 200 may include a storage controller 202 that interfaces with a host and with data storage devices 204, which include multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Rapid Interconnect (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Connected Small Scale Compute Interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptops and tablets.

[0025] Figure 1C This is a block diagram illustrating a tiered storage system. The tiered storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding data storage device 204. A host system 252 can access the memory within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) interface or an Ethernet Fibre Channel (FCoE) interface. In one embodiment, Figure 1C The illustrated system may be a rack-mounted mass storage system that can be accessed by multiple host computers, such as those found in data centers or other locations where mass storage is required.

[0026] Refer again Figure 2AThe controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls the internal bus arbitration of controller 102. Modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. Although in Figure 2A The RAM 116 is illustrated as being located separately from the controller 102, but in other embodiments, one or both of the RAM 116 and ROM 118 may be located within the controller 102. In yet another embodiment, portions of the RAM 116 and ROM 118 may be located both within and outside the controller 102.

[0027] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide electrical interfacing with a host or next-level storage controller. The type of host interface 120 may be chosen depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial ATA Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0028] Backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. Command sequencer 126 generates command sequences (such as programming and erasing command sequences) to be sent to the non-volatile memory die 104. RAID (Redundant Array of Independent Disks) module 128 manages the generation of RAID parity and the recovery of faulty data. RAID parity can be used as an additional level of integrity protection for data being written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132, which controls the overall operation of the back-end module 110.

[0029] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not necessary in the controller 102.

[0030] Figure 2B This is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes a data cache 156 and address decoders 148, 150 for caching data. In this example, the peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102. The peripheral circuitry 141 may also include one or more components that are individually or in combination configured to perform certain functions, including but not limited to those described herein and illustrated in the flowchart. For example, as... Figure 2B As shown, the memory die 104 may include one or more processors 168, which are individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, in the memory array 142, or external to the memory die 104. Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0031] As a complement or alternative to one or more processors 138 (or more generally, components) in controller 102 and one or more processors 168 (or more generally, components) in memory die 104, data storage device 100 may include another set of one or more processors (or more generally, components). Generally, regardless of the location and number of the one or more processors (or more generally, components) in data storage device 100, these processors may be configured individually or in combination to perform various functions, including but not limited to those described herein and illustrated in the flowcharts. For example, the one or more processors (or components) may be located in controller 102, memory device 104, and / or other locations within data storage device 100. Furthermore, different processors (or components) or combinations of processors (or components) may be used to perform different functions. Additionally, components for performing functions may be implemented using a controller that includes one or more components (e.g., processors or other components described above).

[0032] Return again Figure 2A The flash control layer 132 (which will be referred to herein as the flash translation layer (FTL)) handles flash errors and interfaces with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internal operations of memory management and translates writes from the host into writes destined for memory 104. An FTL may be necessary because memory 104 may have limited endurance, may only be written in multi-page format, and / or may not be written to at all (unless it is erased as a block). The FTL understands these potential limitations of memory 104, which may be invisible to the host. Therefore, the FTL attempts to translate writes from the host into writes destined for memory 104.

[0033] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table structure or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses (“LBA”) from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (enabling the recovery of the FTL’s data structure in the event of a sudden power outage) and wear leveling (ensuring uniform wear across memory blocks to prevent some blocks from becoming excessively worn, which would lead to a greater likelihood of failure).

[0034] Turn to the attached image again. Figure 3This is a block diagram of a host 300 and a data storage device 100 according to an embodiment. The host 300 may take any suitable form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 (hereinafter referred to as a computing device) in this embodiment includes one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform actions described herein as being performed by the host 300. Therefore, actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to transfer data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0035] One of the main challenges brought about by NAND process shrinkage and 3D stacking is maintaining process uniformity. Additionally, products may need to support a wide range of operating conditions, such as different program / erase (P / E) cycles, retention times, and temperatures, which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variations, the read threshold (RT) used to read memory pages is not fixed and can vary significantly depending on physical location and operating conditions, especially for newer, less mature memory nodes.

[0036] Reading with an inaccurate read threshold may result in a higher bit error rate (BER), which can degrade performance and quality of service (QoS) due to decoding failures. This may require invoking a high-latency recovery stream, which can lead to latency and performance failures.

[0037] Maintaining optimal read thresholds is particularly challenging for enterprise memory systems (where quality of service requirements can be very stringent) and for mobile, Internet of Things (IoT) and automotive memory systems (where a wider range of operating conditions are required and the frequency of condition changes (e.g., temperature variations) can be relatively high). The problem becomes even more difficult during the transition to newer, less mature memory nodes.

[0038] Current solutions for read threshold calibration (such as BER estimation scan (BES) and valley search (VS)) are likely to be relatively high-latency operations designed to optimize read thresholds for specific word lines. This is beneficial for rare read recovery processes in the event of data decoding failures, but may not be suitable for frequent operations with frequent read threshold changes. To address this issue, data storage devices can implement read threshold management schemes that attempt to track read threshold changes in the background via maintenance processes to ensure that an appropriate read threshold is used when the host issues a read command.

[0039] A common approach used in many data storage devices is to track read thresholds for each group of blocks that share the same conditions. More specifically, blocks written at approximately the same time and temperature are grouped into time-temperature (TT) groups. Read thresholds are tracked for each TT group, typically taken from a representative word line of a block within the group. When the host performs a read operation, the read threshold associated with the TT group corresponding to the read block is used, where additional adjustments to the read threshold are made based on a pre-calibrated word line partition table according to the specific read word line.

[0040] Unfortunately, existing read threshold management schemes may not be optimal and cannot perfectly track read thresholds under frequently changing conditions and high variations between memory pages. U.S. Patent Application No. 17 / 838,481 describes an implementation for performing read threshold calibration by applying a machine learning predictive model, which is incorporated herein by reference. One implementation presented therein can be used to infer the optimal read threshold from all available information, including TT group information, temperature information, BER information, program-erase count (PEC) information, and physical page location.

[0041] Figure 4 An example architecture is shown below. Figure 4As shown, this example architecture includes multiple physical storage (PS) modules 400 (e.g., high-level processors running hardware that manages physical storage), multiple low-level flash memory sequence (LLFS) modules 410 (e.g., low-level processors running low-level flash memory sequences), a queue 420, and an artificial intelligence read threshold (“ART”) calibration module 430, which can be implemented in controller 102 (e.g., using the specific implementation described in the aforementioned '481 patent application). In this example, the ART module 430 serves several clients, and the PS modules 400 that activate the ART module 420 are each attached to several channels and ultimately to multiple dies. At any given time, there may be several read threshold calibration requests in the queue 420 of the ART module 430. After the ART module 430 completes the calibration of the read threshold, it returns the read threshold directly to the LLFS modules 410, which are responsible for reading from memory with the calibrated read threshold.

[0042] In one example implementation, the ART module 430 is configured to infer an optimized read threshold level for each read. However, to support high-throughput reads with reduced hardware cost (and reduced power consumption), it may be desirable to bypass the ART module 430 when reading several read commands with similar conditions. The following implementation addresses this issue by applying a clustering method to the read requests. More specifically, in one implementation, compared to previous read threshold hardware that performs read threshold calculations for each read command, the controller 102 clusters the read requests to provide read threshold calculations faster and with less power, since the hardware calculator does not need to be activated for each read. Therefore, this implementation reduces the number of times the ART module 430 is activated, achieving higher throughput and reduced power consumption, and providing a reduced ASIC footprint for the ART module 430. In another implementation, recently calculated read thresholds are cached so that these read thresholds can be provided without recalculation if conditions are similar.

[0043] In one example implementation, the conditions requested by ART module 430 are clustered from different clients (e.g., by examining the conditions of the memory location targeted by the read request). ART module 420 can then operate on the cluster representatives, reducing the total number of block operations without materially affecting the read calibration results. This allows representative commands to be selected from queue 420 as targets, thereby reducing the number of activations of ART module 430 at a given time. In another implementation, several sets of read thresholds are maintained for each set of typical condition groups. Controller 102 can associate each incoming read command with an existing group. In the case of a match, controller 102 can employ a pre-calculated updated read threshold (pre-computed by ART module 430) and skip the actual operation of ART module 430.

[0044] Figure 5 This is an example architecture that enables these implementation schemes. Figure 4 Compared to the architecture shown, this architecture includes an ART queue analysis module 500, which is configured to operate on the current ART queue 420 to cluster requests and provide read threshold calibration results to the LLFS module 410, without requiring actual operation of the ART module 430.

[0045] In one implementation, the ART queue analysis module 500 receives a read threshold calibration request from the PS module 400, analyzes the request along with other requests currently in queue 420, makes decisions regarding the order of operations, and may reduce the number of ART activations. Within this analysis block, different requests can be clustered to find a representative for each request cluster, which reflects the read threshold for the entire cluster. The representative can be one or more sets.

[0046] All read thresholds for a corresponding logical page can be calibrated. This concept may require clustering all read thresholds. Thus, if even one of these read thresholds is far from the cluster representative, it will not be considered a good representative. Clustering can be performed by applying a simple difference function to each read threshold less than a certain threshold.

[0047] The example is specifically implemented in Figure 6 As shown in flowchart 600. Figure 6As shown, in this example, upon a new read threshold calibration request, the controller 102 of the data storage device 100 performs an analysis of queue 420 to determine if the new request is sufficiently close to existing queue requests (610, 620). If the new queue request is not close enough, the new request is inserted into queue 420 (630). However, if the new queue request is close enough, a representation (which may be a single request or a combination of all cluster members) is inserted into queue 420 (640). After activating the ART module 430, the ART results are used for all cluster members to read memory 104 (650).

[0048] In another implementation, the final ART activation condition and the resulting read threshold can be maintained for a short period after activation to provide results should a similar request occur shortly thereafter. This may require small amounts of additional memory, or it may utilize memory space reserved for general use in the controller or even in the host member buffer (HMB). Figure 7 This is flowchart 700 illustrating the implementation scheme. For example... Figure 7 As shown, in this example, upon receiving a new read threshold calibration request, the controller 102 of the data storage device 100 performs analysis of queue 420 to determine if the new request conditions are sufficiently close to the stored read request conditions (710, 720). If not sufficiently close, the new request is inserted into queue 420 (730). However, if sufficiently close, the controller 102 returns the ART result of the stored close condition request, which can be used to read memory 104 (740). In this example, the ART queue analysis block 500 receives the read threshold calibration request from the PS module 400, analyzes the read threshold calibration request, and compares it with the conditions of the currently stored read requests. If a suitable match is found, the result corresponding to the read threshold is returned as the result of the request.

[0049] When clustering groups of read request conditions, the goal of clustering can be to find different read requests that have similar basic conditions and therefore similar read thresholds. It should be understood that a clustering solution that groups similar read requests may not be a viable alternative to the fine-tuning solution of the ART module 430. In fact, there may be situations where the BER difference between implicit ART inference and the read threshold calculated for similar read requests may not justify the reduced throughput (in the case of limited ART hardware) and additional power consumption.

[0050] Clustering of similar read commands can be based on any suitable memory conditions, such as, but not limited to, time pools and read temperatures. A time pool represents a combined measure of the cumulative stress applied to the data, including the time elapsed at different device temperatures. Data with similar time pool indices and read temperatures may have close read thresholds. Other example conditions include, but are not limited to, block age, memory die number, programming temperature, read temperature, differences between programming temperatures of representative word lines, cycle level, data retention level, word line number, and / or bit error rate (BER) estimates measured at the default read temperature.

[0051] In another example, when multiple read commands target the same physical memory entity (e.g., the same memory die, memory block, etc.), and in the case of sequential read operations where operating conditions are fairly stable between these read commands (e.g., temperature does not change), a single ART inference operation can serve multiple read commands because most attributes (such as block age, block time pool, memory die number, temperature, etc.) are the same across different commands. In addition to the ART read threshold (inferred based on shared attributes), additional specific fine-tuning can be applied to each command based on specific attributes for each command (e.g., word line (WL) number or WL area). When the number of specific attributes for each command is relatively small (e.g., the specific attribute for each command is the number of WLs, or WL areas, or planes, or strings), fine-tuning for each command can be done based on a simple lookup table (LUT). Fine-tuning using LUTs is much simpler than applying a full ART inference operation for each command, thus reducing power consumption and enabling the use of a lower-complexity ART inference engine (e.g., operating once per batch of commands instead of once per command).

[0052] In addition, various clustering algorithms can be used, such as, but not limited to, K-means (including many variations such as K-means++, K-median, K-centroid, etc.), GMM, or newer algorithms such as HDBSCAN. However, clustering algorithms can be based on a simple calculation of similarity scores, which can be computed between the current representative parameter values ​​(such as time pool and read temperature) and representative values ​​of these parameters for each cluster of the read command group.

[0053] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) devices or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0054] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as antifuses, phase-change materials, and optionally manipulation elements such as diodes. As yet another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0055] Multiple memory elements can be configured such that they are connected in series or such that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple memory strings, wherein a string consists of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0056] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0057] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single planar level or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory element (e.g., in the xz plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory element after the memory element is formed. As a non-limiting example, the substrate may include a semiconductor (such as silicon).

[0058] Memory elements can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0059] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y and z directions, where the y direction is generally perpendicular to the main surface of the substrate, and the x and z directions are generally parallel to the main surface of the substrate).

[0060] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., along the y-direction), each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xz plane) to produce a three-dimensional arrangement of memory elements having multiple vertically stacked elements on the memory plane. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0061] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0062] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers located at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor (such as silicon). In a monolithic three-dimensional array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, layers of adjacent memory device levels in a monolithic three-dimensional memory array may be shared or intermediate layers may be present between memory device levels.

[0063] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on individual substrates and then stacking the memory stages on top of each other. The substrate can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on individual chips and then packaged together to form a stacked chip memory device.

[0064] The operation and communication with memory elements typically require associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0065] Those skilled in the art will recognize that the present invention is not limited to the described two-dimensional and three-dimensional structures, but covers all relevant memory structures as described herein and as understood by those skilled in the art.

[0066] The above detailed description is intended to be understood as an illustration of selected forms of the invention, and not a definition of the invention. Only the following claims (including all equivalents) are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A data storage device, the data storage device comprising: Memory; and One or more processors, wherein the one or more processors are configured individually or in combination to: Receive multiple read requests from the host; Determine the clustering of read requests among the plurality of read requests that point to locations in the memory with similar memory conditions; as well as The read threshold calibration operation is performed only on a subset of read requests in the cluster, and the result of the read threshold calibration operation is used for all read requests in the cluster, instead of performing the read threshold calibration operation on every read request in the cluster.

2. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to determine that the memory conditions are similar by using a difference function to determine that a similarity score associated with the memory conditions is less than a threshold.

3. The data storage device of claim 1, wherein the memory conditions include block age, time pool index, memory die number, programming temperature, read temperature, difference between programming temperatures of representative word lines, cycle level, data retention level, word line number, and / or bit error rate (BER) estimate measured at the default read temperature.

4. The data storage device according to claim 1, wherein the read threshold calibration operation is performed using an Artificial Intelligence Read Threshold ("ART") calibration hardware module.

5. The data storage device of claim 4, wherein the one or more processors are further configured individually or in combination to: Only the subset of read requests in the cluster are added to the queue for processing by the ART calibration hardware module; and Read requests from the plurality of read requests that are not in the cluster are added to the queue for processing by the ART calibration hardware module.

6. The data storage device of claim 4, wherein the ART calibration hardware module is configured to perform a fine-tuning operation on the result of the read threshold calibration operation.

7. The data storage device of claim 6, wherein the fine-tuning operation is performed using a lookup table.

8. The data storage device of claim 1, wherein the subset of read requests comprises a single read request.

9. The data storage device of claim 1, wherein the subset of read requests includes more than one read request.

10. The data storage device of claim 1, wherein at least some of the read requests in the cluster originate from different clients in the host.

11. The data storage device of claim 1, wherein the read request in the cluster targets the same physical entity of the memory.

12. The data storage device according to claim 1, wherein the memory includes a three-dimensional memory.

13. In a data storage device including a memory, a method includes: The read threshold for multiple computations in the cache; Receive a read request from the host, wherein the read request points to a location in the memory; Whether the conditions for determining the location in the memory are similar to the conditions associated with a read threshold calculated from one of a plurality of calculated read thresholds cached; as well as In response to the condition for determining the location in the memory being similar to the condition associated with one of the cached computed read thresholds, the cached computed read threshold is used for the read request, instead of calculating a new read threshold for the read request.

14. The method of claim 13, wherein the plurality of calculated read thresholds are cached in the memory.

15. The method of claim 13, wherein the plurality of calculated read thresholds are cached in the memory of the host.

16. The method of claim 15, wherein the memory in the host includes a host memory buffer.

17. The method of claim 13, further comprising using a difference function to determine whether the similarity score of the condition of the location in the memory and the condition associated with the one of a plurality of computed read thresholds of the cached memory is less than a threshold.

18. The method of claim 13, wherein the conditions of the location in the memory and the conditions associated with the one of a plurality of computed read thresholds cached include block age, time pool index, memory die number, programming temperature, read temperature, difference between programming temperatures of representative word lines, cycle level, data retention level, word line number, and / or a measured bit error rate (BER) estimate at the default read temperature.

19. The method of claim 13, wherein the plurality of calculated read thresholds are calculated using an Artificial Intelligence Read Threshold ("ART") calibration hardware module.

20. A data storage device, the data storage device comprising: Memory; and Components used to perform the following operations: Receive multiple read requests from the host; Clustering of read requests that point to locations in the memory with similar conditions among the multiple read requests; as well as The read threshold calibration operation is performed only on a subset of read requests in the cluster, and the result of the read threshold calibration operation is used for all read requests in the cluster, instead of performing the read threshold calibration operation on every read request in the cluster.

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