Semiconductor laser pulse shaping device and method

Abstract

The application provides a semiconductor laser pulse shaping device and a shaping method, which realize laser pulse shaping and suppress the front peak of the semiconductor laser output pulse. The device comprises an FPGA module, N digital-analog conversion modules, N high-speed pulse driving modules, a semiconductor laser and an optical isolator. The FPGA module outputs a time-controllable LVDS signal to control the multiple high-speed pulse driving modules, control the size and width of the pulse current output by the multiple high-speed pulse driving modules, and further control the output laser pulse shape. The application realizes the shaping of the laser pulse through multi-stage adjustment, does not need complex external optical devices and feedback adjustment modules, has a simple structure, is convenient to implement, is suitable for various semiconductor lasers, and has wide practicability.

Description

Technical Field

[0001] This invention belongs to the field of laser technology, specifically relating to a method and apparatus for suppressing laser pulse spikes in semiconductor lasers. Background Technology

[0002] Semiconductor lasers, with their advantages of small size, high energy conversion efficiency, rapid modulation response, and high reliability, have become the core light source in fields such as optical communication, lidar, precision measurement, and quantum information processing. The direct-drive generation of laser pulses using semiconductor lasers is a simple and convenient adjustment method, and is a commonly used adjustment scheme for pulsed lasers.

[0003] While direct-drive methods for generating laser pulses using semiconductor lasers can produce pulses, their adjustment capabilities are typically limited, usually only producing square wave pulses. Furthermore, in pulsed operation mode, the laser pulses output by semiconductor lasers are prone to exhibiting extremely narrow peaks at the leading edge. These peaks have high power, which is rapidly amplified by subsequent laser amplification stages, leading to accelerated device aging, pulse energy fluctuations, and decreased temporal resolution, severely limiting the application of semiconductor lasers in high-precision scenarios.

[0004] To achieve laser pulse shaping, external modulation is typically used to obtain fine laser pulse shaping. However, external modulation systems are complex, involving high-speed signal generation, amplification, and expensive high-speed electro-optic modulation devices. Regarding laser pulse spike suppression, a method for suppressing laser pulse spikes in fiber laser systems has been proposed (patent number: 202311504138.0). Its core is designed for the quasi-continuous operation mode of fiber lasers. It requires multiple samplings and gradual compensation of the pump signal amplitude to address the spike problem caused by the delay accumulation of excited-state particles. The operation is relatively complex, and its technical principles and applicable devices are not suitable for semiconductor lasers. Summary of the Invention

[0005] To address the shortcomings of existing semiconductor laser pulse generation technologies, this invention constructs a multi-channel laser pulse driving scheme and provides a semiconductor laser pulse shaping method to achieve laser pulse shaping and suppress spike pulses. The semiconductor laser pulse shaping device and method proposed in this invention have the advantages of flexible laser pulse shaping and the absence of spike pulses.

[0006] The first objective of this invention is to provide a semiconductor laser pulse shaping device, comprising an FPGA module, N digital-to-analog converters, N high-speed pulse drive modules, a semiconductor laser, and an optical isolator. The FPGA module is electrically connected to each of the digital-to-analog converters, and also electrically connected to the EP and EN interfaces of each of the high-speed pulse drive modules. Each digital-to-analog converter is configured in a one-to-one correspondence with a high-speed pulse drive module, and the digital-to-analog converter is electrically connected to the CS interface of the corresponding high-speed pulse drive module to control the current amplitude output by that high-speed pulse drive module. The outputs of all the high-speed pulse drive modules are combined and electrically connected to the input terminal of the semiconductor laser, thereby driving the semiconductor laser to emit light. The output terminal of the semiconductor laser is electrically connected to the optical isolator and outputs laser light through the optical isolator.

[0007] It adopts an FPGA multi-channel timing + DAC multi-channel current hierarchical control architecture, with multiple driving currents combined to drive the laser. The back end is equipped with an optical isolator, which relies on the multi-channel step current to smooth carrier accumulation. It does not require complex optical modulation devices, has a simple structure, can shape pulses in multiple stages, suppress the leading edge spikes from the source, and the optical isolator avoids waveform distortion caused by reflected light. It is compatible with various pulsed semiconductor lasers.

[0008] In some possible implementations, the FPGA module can output a timing-controllable LVDS signal for controlling the switching of the high-speed pulse drive module, and the timing control accuracy of the LVDS signal is less than 10 ns.

[0009] The FPGA outputs a <10ns precision LVDS differential signal, with timing and current independently and digitally controlled by hardware. The low noise and low latency characteristics of LVDS can accurately match the carrier recombination time, ensuring no timing deviation in multi-channel drive.

[0010] In some possible implementations, the high-speed pulse drive module receives the LVDS signal through the EP and EN interfaces, thereby enabling the switching of the high-speed pulse drive module.

[0011] In some possible implementations, the high-speed pulse drive module outputs the pulse drive current magnitude via the CS interface.

[0012] The driver module has an EP / EN timing interface and a CS current interface, with decoupled and adjustable timing and current.

[0013] In some possible implementations, the switching time of the high-speed pulse drive module is less than 10 ns.

[0014] In some possible implementations, the current control accuracy of the high-speed pulse drive module is less than the threshold current of the semiconductor laser.

[0015] The high-speed pulse drive module has a switching speed of <10ns and a current accuracy below the threshold current, enabling precise matching of nanosecond-level carrier dynamics, fine-tuning of pre-injected carrier concentration, stable elimination of spikes, and support for high-frequency pulse operation.

[0016] In some possible implementations, the FPGA module can control the magnitude of the output current of the corresponding high-speed pulse drive module through the digital-to-analog converter module.

[0017] The pulse profile can be adjusted arbitrarily, and the waveform can be switched by simply changing the parameters in the software. It is easy to debug and has a high degree of freedom in shaping.

[0018] In some possible implementations, the number N of the high-speed pulse drive modules is greater than or equal to 2.

[0019] Setting up N≥2 drive channels differs from the single-channel one-time large current that causes a sudden increase in charge carriers and spikes. Multiple channels can inject current in a staggered and step-by-step manner, which is the basis for smoothing the charge carrier concentration and suppressing spikes. Custom non-square wave pulses can be defined to distribute the current load across multiple channels and extend the life of the drive circuit.

[0020] The second objective of this invention is to provide a method for shaping laser pulses in a semiconductor laser, which is implemented using the aforementioned semiconductor laser pulse shaping device and includes the following steps:

[0021] Step 1: Query and obtain the threshold current of the semiconductor laser. and carrier effective recombination lifetime ;

[0022] Step 2, Configure the operating timing and current of the high-speed pulse drive module: Configure the drive current of the first high-speed pulse drive module as follows: The delay after opening is no less than Turn on the second high-speed pulse drive module, in which Preferably, k takes a value of 0.8 to 2. It is less than the maximum drive current that a semiconductor laser can withstand. α is not less than 0.3. Not greater than half the pulse drive period; the second high-speed pulse drive module is configured with a drive current of , The current is greater than the minimum drive current of the high-speed pulse drive source, and the sum of the drive currents of the first two high-speed pulses is less than the maximum drive current that the semiconductor laser can withstand; there is a delay after the second high-speed pulse drive module is turned on. Turn on the third high-speed pulse drive module. The third high-speed pulse drive module is configured with a drive current of [value missing]. , The current is greater than the minimum drive current of the high-speed pulse drive source, and the sum of the drive currents of the first three high-speed pulses is less than the maximum drive current that the semiconductor laser can withstand. The timing control accuracy of the FPGA module should be greater than that of the pulse drive cycle, but not greater than half of the pulse drive cycle. The target waveform can be used as a reference for configuration. Subsequent high-speed pulse drive modules should be turned on sequentially. The current configured for each subsequent high-speed pulse drive module should be greater than the minimum drive current of the high-speed pulse drive source. The sum of the high-speed pulse drive currents should be less than the maximum drive current of the semiconductor laser. The delay time should be greater than the timing control accuracy of the FPGA module, but not greater than half of the pulse drive cycle. The target waveform can be used as a reference for configuration. After turning on the Nth high-speed pulse drive module, a certain delay time should be set, which can be configured with reference to the target waveform. Subsequently, the high-speed pulse drive modules should be gradually turned off, or all high-speed pulse drive modules should be turned off directly, referring to the design waveform.

[0023] Step 3: Configure the high-speed pulse drive module's operating timing and current magnitude to the FPGA module;

[0024] Step 4: Power on and run the high-speed pulse drive module to drive the semiconductor laser and achieve the output of shaping laser pulses.

[0025] The entire method is based on the core theory of laser carrier dynamics. Through the complete process of parameter calibration, formula quantization configuration, real-time execution of FPGA hardware, and overall output, it achieves high-precision pulse shaping and peak suppression by relying solely on electrical control. It avoids the shortcomings of traditional external modulation schemes, such as expensive devices, complex systems, and cumbersome debugging. The waveform has a wide adjustable range and strong versatility.

[0026] The beneficial effects of this invention are:

[0027] 1. This invention uses FPGA configuration to realize the driving timing and driving current control of multiple high-speed pulse driving modules, overcoming the insufficient adjustment capability of a single high-speed pulse driving module, and obtaining a wider and finer driving current fast control capability, ultimately realizing pulsed laser shaping based on semiconductor laser.

[0028] 2. This invention provides a laser pulse shaping method. By calculating and configuring a high-speed pulse driving module, and then having it executed rapidly by an FPGA in a time sequence, the method can suppress the spike pulse of the laser pulse gain switch, resulting in an output laser pulse without obvious spike pulses. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the semiconductor laser pulsed laser shaping device of the present invention;

[0030] Figure 2This is a simulation diagram of the output laser pulses corresponding to multiple high-speed pulse drives. The horizontal axis represents time in ns, and the vertical axis represents the normalized output laser amplitude. S1, S2, S3, S4, S5, and S6 are the laser output amplitudes driven by driving pulse 1, driving pulse 2, driving pulse 3, driving pulse 4, driving pulse 5, and driving pulse 6, respectively.

[0031] Figure 3 This is a simulation diagram of the driving current of a single high-speed pulse. The horizontal axis represents time in ns, and the vertical axis represents the pulse amplitude in A. Among them, A1 is the driving pulse amplitude generated by a single high-speed pulse driving module.

[0032] Figure 4 The simulation diagram of the output laser pulse corresponding to a single high-speed pulse drive is shown. The horizontal axis represents time in ns, and the vertical axis represents the normalized output laser amplitude. S1 is the amplitude of the output laser pulse peak, and S2 is the laser output amplitude driven by a single driving pulse.

[0033] The attached diagram lists the components represented by each number as follows:

[0034] 101. FPGA module; 102. Digital-to-analog converter module; 103. High-speed pulse drive module; 104. Semiconductor laser; 105. Optical isolator. Detailed Implementation

[0035] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0036] Example 1

[0037] like Figure 1 As shown, a semiconductor laser pulse shaping device includes an FPGA module (101), six digital-to-analog conversion modules, namely digital-to-analog conversion module 1 (102-1), digital-to-analog conversion module 2 (102-2), digital-to-analog conversion module 3 (102-3), digital-to-analog conversion module 4 (102-4), digital-to-analog conversion module 5 (102-5), and digital-to-analog conversion module 6 (102-6), six high-speed pulse driving modules, namely high-speed pulse driving module 1, high-speed pulse driving module 2, up to high-speed pulse driving module 6, and also includes a semiconductor laser and an optical isolator.

[0038] The FPGA module is connected to each high-speed pulse drive module via the EP and EN interfaces of the corresponding high-speed pulse drive module. The FPGA module is also connected to each digital-to-analog converter module, and each digital-to-analog converter module is connected to the corresponding high-speed pulse drive module to control the output current amplitude of the high-speed pulse drive module. The outputs of the high-speed pulse drive modules are combined and connected to a semiconductor laser to drive the semiconductor laser to emit light. The output of the semiconductor laser is connected to an optical isolator, and the laser light is emitted after passing through the optical isolator.

[0039] The FPGA module can be selected from the Xilinx K7 series and can output timing-controllable LVDS signals to control the switching of the high-speed pulse drive module. The timing control accuracy of the LVDS signal is less than 1ns. The FPGA module can control the output current of the high-speed pulse drive module through a digital-to-analog converter. LVDS signal transmission features low power consumption, low voltage, low latency, and low interference, making it suitable for high-speed pulse driving.

[0040] The high-speed pulse drive module includes EP, EN interfaces and a CS interface. The EP and EN interfaces are used to switch the high-speed pulse drive module on and off, while the CS interface is used to control the output current of the constant current input source. The switching time of the high-speed pulse drive module is less than 1 ns, and the current control accuracy of the high-speed pulse drive module is less than 5 mA.

[0041] The semiconductor laser is a DFB laser with a center wavelength of 1064nm, which supports pulsed operation mode.

[0042] Example 2

[0043] This embodiment develops a laser pulse shaping method based on the semiconductor laser pulse shaping device of Embodiment 1. The FPGA module controls the output current of six high-speed pulse drive modules through six digital-to-analog converters, and the FPGA module controls the switching of the six high-speed pulse drive modules by outputting a timing-controllable LVDS signal, thus controlling the width of the output pulses from the six high-speed pulse drive modules. The threshold current of the DFB semiconductor laser is approximately 11 mA and the effective carrier recombination lifetime is approximately 3 ns, resulting in a calculated lasing delay time of approximately 8 ns. The operating parameters of the drive modules are configured as follows: The first high-speed pulse drive module is selected with a drive current of 15mA. After 4ns, the second high-speed pulse drive module is then turned on, with a current of 15mA. After the third high-speed pulse drive module is turned on, the fourth high-speed pulse drive module is turned on after a 1ns delay, with a current of 30mA. After the fourth high-speed pulse drive module is turned on, the fifth high-speed pulse drive module is turned on after a 1ns delay, with a current of 30mA. After the fifth high-speed pulse drive module is turned on, the sixth high-speed pulse drive module is turned on after a 1ns delay, with a current of 30mA. After the sixth high-speed pulse drive module is turned on, a command is issued to turn off the output of all high-speed pulse drive modules after 4ns. The simulation diagram of the output laser pulses corresponding to multiple pulse drives using the above timing parameters is shown below. Figure 2 The output laser shaping pulse has an adjustable pulse shape and no obvious spike at the leading edge. S1, S2, S3, S4, S5, and S6 are the normalized amplitude values ​​of the output laser shaping pulses corresponding to the six driving pulses, and the width of each stage of the output laser shaping pulse is determined by the pulse width of the corresponding driving pulse.

[0044] like Figure 3 The image shows a simulation example of a single-drive pulse current, where A1 is the pulse amplitude, the current is 150mA, and the pulse width is 2ns.

[0045] like Figure 4 As shown Figure 3 The simulation example of the output laser pulse corresponding to a single driving pulse shows that the output laser pulse has a distinct pulse spike. Here, S1 is the normalized amplitude of the pulse spike, and S2 is the amplitude of the output laser pulse.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A semiconductor laser pulse shaping device, characterized in that, The system includes an FPGA module, N digital-to-analog converters, N high-speed pulse drive modules, a semiconductor laser, and an optical isolator. The FPGA module is electrically connected to each of the digital-to-analog converters, and also electrically connected to the EP and EN interfaces of each of the high-speed pulse drive modules. Each digital-to-analog converter corresponds to one of the high-speed pulse drive modules, and each digital-to-analog converter is electrically connected to the CS interface of its corresponding high-speed pulse drive module to control the current amplitude output by that high-speed pulse drive module. The outputs of all the high-speed pulse drive modules are combined and then electrically connected to the input terminal of the semiconductor laser, thereby driving the semiconductor laser to emit light; the output terminal of the semiconductor laser is electrically connected to the optical isolator and then outputs laser light through the optical isolator.

2. The semiconductor laser pulse shaping device according to claim 1, characterized in that, The FPGA module can output a timing-controllable LVDS signal for controlling the switching of the high-speed pulse drive module, and the timing control accuracy of the LVDS signal is less than 10ns.

3. The semiconductor laser pulse shaping device according to claim 2, characterized in that, The high-speed pulse drive module receives the LVDS signal through the EP and EN interfaces, thereby enabling the switching of the high-speed pulse drive module.

4. The semiconductor laser pulse shaping device according to claim 1, characterized in that, The high-speed pulse drive module outputs the pulse drive current through the CS interface.

5. The semiconductor laser pulse shaping device according to claim 1, characterized in that, The switching time of the high-speed pulse drive module is less than 10 ns.

6. The semiconductor laser pulse shaping device according to claim 1, characterized in that, The current control accuracy of the high-speed pulse drive module is less than the threshold current of the semiconductor laser.

7. The semiconductor laser pulse shaping device according to claim 1, characterized in that, The FPGA module can control the magnitude of the output current of the corresponding high-speed pulse drive module through the digital-to-analog converter module.

8. The semiconductor laser pulse shaping device according to claim 1, characterized in that, The number N of the high-speed pulse drive modules is greater than or equal to 2.

9. A method for shaping laser pulses in a semiconductor laser, implemented using the semiconductor laser pulse shaping apparatus according to any one of claims 1 to 8, characterized in that, Includes the following steps: Step 1: Query and obtain the threshold current of the semiconductor laser. and carrier effective recombination lifetime ; Step 2: Configure the operating timing and operating current of the high-speed pulse drive module; Step 3: Configure the high-speed pulse drive module's operating timing and current magnitude to the FPGA module; Step 4: Power on and run the high-speed pulse drive module to drive the semiconductor laser and achieve the output of shaping laser pulses.

10. The semiconductor laser pulse shaping method according to claim 9, characterized in that, Step 2 is as follows: Step 2.1, Configure the first high-speed pulse drive module: ① Set the drive current of the first high-speed pulse drive module The formula is: Where k takes values ​​from 0.8 to 2, and Less than the maximum driving current that a semiconductor laser can withstand; ② After the first high-speed pulse drive module is turned on, the delay... When the second high-speed pulse drive module is activated, the delay calculation formula is as follows: Where α is not less than 0.3, Not greater than half the pulse drive period; Step 2.2, Configure the second high-speed pulse drive module: ① Set the drive current of the second high-speed pulse drive module to be... , Greater than the minimum drive current of the high-speed pulse drive source; ②The sum of the driving currents of the first two high-speed pulses is less than the maximum driving current that the semiconductor laser can withstand; Step 2.3, Configure the third high-speed pulse drive module: ① Delay after the second path is opened Enable the third high-speed pulse drive module and constrain it. The timing control precision is greater than that of the FPGA module but not greater than half the pulse drive period. Adjust according to the target output waveform; ② Set the drive current of the third high-speed pulse drive module to be [value missing]. , Greater than the minimum drive current of the high-speed pulse drive source; ③ The sum of the driving currents of the first three high-speed pulse drives is less than the maximum driving current that the semiconductor laser can withstand; Step 2.4, iteratively configure the 4th to Nth high-speed pulse drive modules: ① The corresponding delay after the previous driver is enabled To enable the next channel, all delays must meet the following conditions: greater than the FPGA timing accuracy and no greater than half the pulse period. The delay value can be customized with reference to the target waveform. ②Drive current for each path All are greater than the minimum output current of the drive module; ③ The total driving current of the N channels is always less than the maximum driving current that the laser can withstand; Step 2.5, Configure pulse shutdown timing: After all N high-speed pulse drive modules are turned on in sequence, maintain the preset conduction time, and then select to turn off the multi-channel drive step by step or turn off all high-speed pulse drive modules at once according to the target shaping waveform; Step 2.6: Summarize the current amplitude, turn-on delay, conduction duration, and turn-off sequence of all N high-speed pulse drive modules to form a complete set of drive parameters.

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