An adaptive over-current protection circuit, method, voltage regulator and electronic product

Abstract

The application discloses a kind of self-adapting overcurrent protection circuit, method, voltage stabilizer and electronic product, it is related to integrated circuit technical field.The circuit includes: LDO main loop, for generating gate control signal according to the feedback of reference voltage and output voltage, drive power tube to provide current to output end;Bias voltage generation module, for generating bias voltage with power voltage same direction variation;Overcurrent detection and clamping module is connected bias voltage generation module and LDO main loop respectively, for detecting output current according to the difference of gate control signal and bias voltage, and when output current exceeds threshold value, the gate control signal is clamped, realizes constant current overcurrent protection;Short circuit protection control module, enable end is connected to overcurrent detection and clamping module, only when overcurrent detection and clamping module act, be waken up.The circuit of the application has the function of preventing starting deadlock, and adaptive turn-back type overcurrent and short circuit protection can be realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an adaptive overcurrent protection circuit, method, voltage regulator, and electronic product. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Currently, the core drawback of traditional folded-back current-limiting low-dropout linear regulators (LDOs) is that the zero output voltage during power-on can be mistaken for a short circuit, leading to startup latch-up and preventing the system from establishing a proper output voltage. Existing solutions typically employ soft-start circuits, increase the short-circuit current threshold, or introduce independent comparators and startup blanking timers. However, these methods all have significant shortcomings: soft-start requires large on-chip capacitors or external components, significantly increasing chip area and cost; increasing the short-circuit current threshold undermines the initial goal of folded-back protection to reduce power consumption, and the thermal stress on the power transistor remains high even under extreme short circuits; while independent comparators and blanking time circuits not only continuously consume static power but also pose timing mismatch risks—setting the time too short may fail to resolve latch-up, while setting it too long may result in delayed protection during actual short circuits. Therefore, existing technologies struggle to balance low cost, low static power consumption, and high reliability protection performance when avoiding startup latch-up. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an adaptive overcurrent protection circuit, method, regulator, and electronic product. Based on the principle of current limiting protection, an adaptive foldback overcurrent and short-circuit protection circuit with anti-latch-up function is designed for wide input range LDOs (linear regulators). This circuit not only effectively achieves adaptive current limiting protection but also significantly reduces the power consumption of the chip under heavy load conditions.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: The first aspect of the present invention provides an adaptive overcurrent protection circuit, comprising: The LDO main loop is used to generate a gate control signal based on the feedback of the reference voltage and the output voltage, which drives the power transistor to provide current to the output terminal. Bias voltage generation module, used to generate a bias voltage that changes in the same direction as the power supply voltage; The overcurrent detection and clamping module is connected to the bias voltage generation module and the LDO main loop, respectively. It is used to detect the output current based on the difference between the gate control signal and the bias voltage, and clamp the gate control signal when the output current exceeds the threshold to achieve constant current overcurrent protection. The short-circuit protection control module has its enable terminal connected to the overcurrent detection and clamping module, and is only awakened when the overcurrent detection and clamping module is activated; its input terminal is connected to the LDO output voltage, and its output terminal is connected to the gate of the power transistor in the main loop of the LDO; when awakened, when the LDO output voltage drops below the short-circuit threshold, the short-circuit protection control module forcibly pulls the gate control signal to the power supply voltage, limiting the output current to the short-circuit protection current value.

[0006] Furthermore, the bias voltage generation module includes a fifth PMOS transistor and a sixth PMOS transistor, with the source of the fifth PMOS transistor M5 connected to the power supply voltage V. M The gate and drain of M5 are connected, forming a diode-connected load. The drain is connected to the sixth PMOS transistor. The source pole, The gate and drain are connected to form a diode connection, and are connected to the bias voltage. .

[0007] Furthermore, the overcurrent detection and clamping module includes a zero-order NMOS transistor M0 and a zero-order resistor R0, one end of which is connected to the power supply voltage V. M The other end is connected to the drain of the zeroth NMOS transistor M0; the gate of the zeroth NMOS transistor M0 is connected to the output of the bias voltage generation module to receive the bias voltage. The source of the zeroth NMOS transistor M0 is connected to the gate of the source follower M1 in the main loop of the LDO. When the gate potential of the LDO power transistor M2 decreases below a preset threshold as the output current increases, the zeroth NMOS transistor M0 is turned on and clamps the gate potential to achieve constant current overcurrent protection.

[0008] Furthermore, the short-circuit protection control module includes the seventh PMOS transistor M7, the eighth NMOS transistor M8, the ninth NMOS transistor M9, and the tenth PMOS transistor M10. 10 The source of the seventh PMOS transistor M7 is connected to the power supply voltage V. M The gate of the seventh PMOS transistor M7 is connected to the drain of the zeroth NMOS transistor M0, and the drain of the seventh PMOS transistor M7 is connected to the drain of the eighth NMOS transistor M8; the source of the eighth NMOS transistor M8 is grounded, and its gate and drain are connected to form a current mirror; the drain of the ninth NMOS transistor M9 is connected to the first resistor R1, and its source is connected to the LDO output voltage V. out The gate of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8; the tenth PMOS transistor M... 10 The drain of the tenth PMOS transistor M is connected to the gate of the LDO power transistor M2. 10 The source is connected to the power supply voltage V. MThe tenth PMOS transistor M 10 The gate of the transistor is connected to the drain of the ninth NMOS transistor M9.

[0009] Furthermore, the short-circuit protection control module only receives operating current and is woken up when the zeroth NMOS transistor M0 in the overcurrent detection and clamping module is turned on, thereby pulling down the gate potential of the seventh PMOS transistor M7 and turning on the seventh PMOS transistor M7; in the woken-up state, when the LDO output voltage V out When the voltage drops below the short-circuit detection threshold, the ninth NMOS transistor M9 turns on and pulls down the tenth PMOS transistor M1. 10 The gate potential of the tenth PMOS transistor M 10 Turning on the transistor forces the gate potential of the LDO power transistor M2 to the power supply voltage V. M This shuts off the LDO power transistor M2 to limit the output current to a very small short-circuit protection current value.

[0010] Furthermore, the main loop of the LDO includes an operational amplifier, a source follower M1, an LDO power transistor M2, a first resistor R3, and a second resistor R2. The non-inverting input of the operational amplifier is connected to a reference voltage V. ref The inverting input is connected to the voltage divider point V of the LDO output voltage through R2 and R3. fb The drain of source follower M1 is grounded, and its gate is connected to the output of the operational amplifier and simultaneously to the source of the sensing power transistor M0. The source of the LDO power transistor M2 is connected to the power supply voltage V. M The drain of M2 is used as the output voltage V. out .

[0011] Furthermore, the circuit's operation includes a system startup and normal operation phase for preventing deadlock hibernation, an overcurrent protection phase for adaptive constant current clamping, and a short-circuit protection phase for achieving deep foldback.

[0012] A second aspect of the present invention provides a protection method for the adaptive overcurrent protection circuit described in the first aspect, comprising the following steps: A gate control signal is generated based on the feedback of the reference voltage and the output voltage, which drives the power transistor to provide current to the output terminal. Generate a bias voltage that changes in the same direction as the power supply voltage; The output current is detected based on the difference between the gate control signal and the bias voltage, and the gate control signal is clamped when the output current exceeds the threshold to achieve constant current overcurrent protection. The short-circuit protection control module is awakened when the overcurrent detection and clamping module operates. In the awakened state, when the LDO output voltage drops below the short-circuit threshold, the short-circuit protection control module forcibly pulls the gate control signal to the power supply voltage, limiting the output current to the short-circuit protection current value.

[0013] A third aspect of the present invention provides a voltage regulator including the adaptive overcurrent protection circuit described in the first aspect.

[0014] A fourth aspect of the present invention provides an electronic product including the voltage regulator described in the third aspect.

[0015] The above one or more technical solutions have the following beneficial effects: Existing technologies, when addressing the startup deadlock problem in foldback current limiting, often suffer from costly trade-offs such as sacrificing chip area, increasing static power consumption, or weakening short-circuit protection. This invention discloses an adaptive overcurrent protection circuit, method, voltage regulator, and electronic product. It divides the protection mechanism into two levels: constant current overcurrent protection and short-circuit foldback protection. The status signal of the first-level protection is used as the enable switch for the second-level protection. This eliminates the need for large-area capacitors or high-power comparators. The physical conduction state of the overcurrent clamping transistor is used as the enable gating for the short-circuit foldback protection module. With a minimalist architecture featuring zero external components and extremely low static power consumption, it fundamentally solves the startup deadlock problem.

[0016] This circuit uses an NMOS transistor as the switching power transistor, and provides a bias voltage to the gate of the switching power transistor that varies with the power supply voltage, enabling overcurrent protection under different power supply voltages. The switching power transistor can then act as a comparator to determine whether an overcurrent has occurred, thus eliminating the need for a comparator and bias voltage. Furthermore, the overcurrent protection module does not require a high-voltage transistor. This invention enables overcurrent protection in an LDO overcurrent protection circuit without additional detection circuitry, adapting to changes in power supply voltage. The overcurrent protection circuit simplifies the design by eliminating the need for a comparator and additional bias voltage, significantly reducing layout area and power consumption. Compared to traditional structures, this invention is simpler, omitting the comparator and additional bias voltage, adapting to changes in power supply voltage, providing faster response, and reducing the number of high-voltage transistors, thus greatly saving layout area.

[0017] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a schematic diagram of the conventional LDO overcurrent protection circuit of the present invention; Figure 2 This is a structural diagram of the adaptive overcurrent protection circuit in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the simulation results in Embodiment 1 of the present invention. Detailed Implementation

[0020] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0021] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] like Figure 1 As shown, the traditional LDO overcurrent protection circuit consists of a detection switching power transistor, a comparator, a reference voltage, and another switching power transistor. Its working principle is to detect the current in the switching power transistor, convert it into a voltage, and compare it with the reference voltage. When this voltage exceeds the reference voltage, an overcurrent signal is output, causing the switching power transistor to conduct and clamping its gate, preventing further increase in its drain-source current.

[0023] Working process: Testing the switching power transistor The current of the switching power transistor is replicated, and this current flows through the resistor. , generate voltage When the output current of the switching power transistor exceeds the preset value, the voltage... Reference voltage This causes the comparator output to go low, thus enabling the switching power transistor to... When the transistor is turned on, it clamps the gate of the switching power transistor, preventing its drain-source current from increasing.

[0024] For LDOs with wide input voltage ranges, the supply voltage varies greatly. If a traditional LDO overcurrent protection circuit is used, a high-voltage transistor needs to be added to each branch of the overcurrent protection circuit, thus increasing the layout area. Furthermore, the comparator generates significant power consumption and requires an additional reference voltage.

[0025] Currently, in the design of low dropout linear regulators (LDOs), a foldback current limiting mechanism is typically introduced to reduce the extremely high power consumption during output short circuits. However, traditional foldback current limiting circuits are prone to startup lock-up because the output capacitor has not yet charged, resulting in a zero output voltage. Several solutions are commonly used to avoid this startup lock-up, but all have significant drawbacks: 1. Introducing soft-start circuitry leads to a significant increase in area and cost. Traditional solutions often employ soft-start strategies to suppress startup inrush current and prevent deadlock. Traditional soft-start implementations typically require numerous external components or a loop coupling between two on-chip capacitors and a clock generator. However, these methods are unattractive in practical applications due to the overhead of external components and the significant chip area overhead caused by using large on-chip capacitors. This greatly increases the manufacturing cost of power management chips and fails to meet the high integration requirements of modern portable electronic products.

[0026] 2. Compromising the short-circuit current threshold leads to increased heat dissipation and negates the purpose of foldback. Another common design approach to avoid lockout is to directly increase the short-circuit current threshold in the low-voltage region. Some solutions can indeed avoid the intersection of the overcurrent protection curve and the load demand curve (i.e., avoid lockout) by increasing the short-circuit current value, but this often increases the system's short-circuit power consumption, thus completely negating the purpose of the foldback protection mechanism itself, which is to reduce power consumption. Under extreme short-circuit conditions, a large short-circuit current still exposes the power transistor to extremely high thermal stress risks.

[0027] 3. Introducing an independent low-voltage comparator or boot blanking introduces power consumption and timing risks. Existing technologies often integrate an independent low-voltage comparator internally to monitor the output voltage in real time and forcibly disable the foldback function during the initial startup phase (i.e., boot blanking time). This approach not only requires the introduction of an additional reference voltage network, but its high-speed comparator also generates a non-negligible continuous static bias current, severely deteriorating the ultra-low power consumption characteristics of the LDO in standby mode. Furthermore, the setting of the blanking time carries a significant timing mismatch risk: a setting time that is too short can lead to system deadlock recurrence, while a setting time that is too long may cause the chip to burn out due to untimely protection during a physical short circuit fault at the moment of actual power-on.

[0028] To overcome the above-mentioned defects, the present invention discloses an adaptive overcurrent protection circuit, method, voltage regulator and electronic product, as detailed in the embodiments.

[0029] Example 1: Embodiment 1 of the present invention provides an adaptive overcurrent protection circuit, specifically as follows: Figure 2 As shown, the system includes a bias voltage generation module, an overcurrent detection and clamping module, a short-circuit protection control module, and an LDO main loop. The LDO main loop generates a gate control signal based on feedback from the reference voltage and output voltage, driving the power transistor to provide current to the output terminal. The bias voltage generation module generates a bias voltage that changes in the same direction as the power supply voltage. The overcurrent detection and clamping module, connected to both the bias voltage generation module and the LDO main loop, detects the output current based on the difference between the gate control signal and the bias voltage, and clamps the gate control signal when the output current exceeds a threshold, achieving constant current overcurrent protection. The short-circuit protection control module has its enable terminal connected to the overcurrent detection and clamping module and is only activated when the overcurrent detection and clamping module operates. Its output terminal is connected to the gate of the power transistor in the LDO main loop. In the activated state, when the LDO output voltage drops below the short-circuit threshold, the short-circuit protection control module forcibly pulls the gate control signal back to the power supply voltage V. M This limits the output current to the short-circuit protection current value.

[0030] In one specific implementation, the bias voltage generation module is connected to the power supply voltage V. M Between and ground, used to generate voltage V that varies with the power supply voltage. M Bias voltage changing in the same direction .

[0031] The bias voltage generation module includes a fifth PMOS transistor and a sixth PMOS transistor. The source of the fifth PMOS transistor M5 is connected to the power supply voltage V. M The gate and drain of M5 are connected, forming a diode-connected load. The drain is connected to the sixth PMOS transistor. The source pole, The gate and drain are connected to form a diode connection, and are connected to the bias voltage. .

[0032] In one specific implementation, the overcurrent detection and clamping module includes a zero-order NMOS transistor M0 and a zero-order resistor R0, one end of which is connected to the power supply voltage V. M The other end is connected to the drain of the zeroth NMOS transistor M0; the gate of the zeroth NMOS transistor M0 is connected to the output of the bias voltage generation module to receive the bias voltage. The source of the zeroth NMOS transistor M0 is connected to the gate of the source follower M1 in the main loop of the LDO. When the gate potential of the LDO power transistor M2 decreases below a preset threshold as the output current increases, the zeroth NMOS transistor M0 is turned on and clamps the gate potential to achieve constant current overcurrent protection.

[0033] In one specific implementation, the short-circuit protection control module includes a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, and a tenth PMOS transistor M10. 10 The source of the seventh PMOS transistor M7 is connected to the power supply voltage V. M The gate of the seventh PMOS transistor M7 is connected to the drain of the zeroth NMOS transistor M0, and the drain of the seventh PMOS transistor M7 is connected to the drain of the eighth NMOS transistor M8; the source of the eighth NMOS transistor M8 is grounded, and its gate and drain are connected to form a current mirror; the drain of the ninth NMOS transistor M9 is connected to the first resistor R1, and its source is connected to the LDO output voltage V. out The gate of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8; the tenth PMOS transistor M... 10 The drain of the tenth PMOS transistor M is connected to the gate of the LDO power transistor M2. 10 The source is connected to the power supply voltage V. M The tenth PMOS transistor M 10 The gate of the transistor is connected to the drain of the ninth NMOS transistor M9.

[0034] The short-circuit protection control module only receives operating current and is woken up when the zeroth NMOS transistor M0 in the overcurrent detection and clamping module is turned on, thereby pulling down the gate potential of the seventh PMOS transistor M7 and turning it on; in the woken-up state, when the LDO output voltage V out When the voltage drops below the short-circuit detection threshold, the ninth NMOS transistor M9 turns on and pulls down the tenth PMOS transistor M1. 10 The gate potential of the tenth PMOS transistor M 10 Turning on the transistor forces the gate potential of the LDO power transistor M2 to the power supply voltage V. M This shuts off the LDO power transistor M2 to limit the output current to a very small short-circuit protection current value.

[0035] In one specific implementation, the LDO main loop includes an operational amplifier, a source follower M1, an LDO power transistor M2, a first resistor R3, and a second resistor R2. The non-inverting input of the operational amplifier is connected to a reference voltage V. ref The inverting input is connected to the voltage divider point V of the LDO output voltage through R2 and R3. fbThe drain of source follower M1 is grounded, and its gate is connected to the output of the operational amplifier and simultaneously to the source of the sensing power transistor M0. The source of the LDO power transistor M2 is connected to the power supply voltage V. M The drain of M2 is used as the output voltage V. out .

[0036] The circuit's operation can be divided into three stages: system startup and normal operation, overcurrent protection, and short-circuit back-off protection, each corresponding to different load conditions.

[0037] State 1: System startup and normal operation phase used to prevent deadlock hibernation.

[0038] Triggering condition: The chip powers on and starts up (at this time V out =0V) or within the normal load range.

[0039] Operating principle: During this stage, the error amplifier outputs a normal control level, and the main power transistor M2 provides current normally. The gate-source voltage of the clamping transistor M0 has not reached the turn-on threshold and is in the off state.

[0040] Anti-deadlock mechanism: Since M0 is turned off, the gate of M7 is pulled high to near the power supply potential V through its source by a resistor. M This keeps control transistor M7 off. The shutdown of M7 directly cuts off the subsequent short-circuit detection branches (M8, M9, M...). 10 The operating current of the circuit is such that even if the detection tube M9 detects Vout=0V at startup, the short-circuit protection module is in a "forced sleep" state and will not clamp the main loop incorrectly. This ensures that the output capacitor can be charged smoothly with full load current, completely solving the startup deadlock problem of traditional foldback circuits.

[0041] State 2: Overcurrent protection stage for adaptive constant current clamping.

[0042] Triggering conditions: The load becomes suddenly heavier, and the output current exceeds the set maximum threshold, but no deep short circuit occurs at the output terminal.

[0043] Operating principle: To provide a large current, the output potential of the operational amplifier (i.e., the gate potentials of M1 and M2) is forced to drop. When this potential drops to a level that makes the source potential of M0 sufficiently low, satisfying VGS0 > VTH0, M0 turns on. After M0 turns on, it clamps the gate potential of the main power transistor M2 to a fixed value, limiting further increases in output current, and the system enters "constant current protection" mode.

[0044] Short-circuit module wake-up: At this time, current is generated in the M0 branch, causing the gate potential of M7 to be pulled low, and the control transistor M7 turns on. After M7 turns on, the eighth NMOS transistor M8 receives bias current, and the short-circuit protection module is officially "wake up (enabled)" and enters the short-circuit monitoring standby state. State 3: Short-circuit protection stage used to achieve deep turnaround.

[0045] Triggering condition: Under overcurrent conditions, an extreme short circuit occurs at the load end, causing the output voltage V to surge. out Severe drop (close to 0V).

[0046] Operating principle: At this time, the short-circuit protection module has been activated. With V... out The drop, the source is connected to V out As the source voltage of the detection transistor M9 decreases, its conduction capability increases, and it begins to draw current mirrored from M8. This current generates a voltage drop across resistor R1, thereby pulling down and fully turning on the strong pull-down transistor M8. 10 .

[0047] Return clamp: M 10 After being turned on, its strong current-pull capability directly overrides the control of the error amplifier, forcibly pushing the gate of the main power transistor M2 towards the power supply voltage V. M Directional pull-up. This forces M2 to be deeply turned off, and the output current drops sharply from the "constant current maximum value" to a very small safe short-circuit current, achieving perfect foldback characteristics and greatly reducing chip power consumption under extreme short circuit conditions.

[0048] To better illustrate the circuit operation principle of the above embodiments, circuit simulation was performed, such as... Figure 3 As shown, the horizontal axis is the load resistance res (unit: ohms), and the vertical axis is the output load current I (unit: milliamperes).

[0049] The load resistance decreases from right to left, representing an increasingly heavy load, until it eventually becomes 0 (complete short circuit).

[0050] By gradually reducing the load resistance through DC analysis (simulating the process of increasing load until a complete short circuit), the circuit of this invention exhibits a clear "three-stage" response curve, perfectly verifying the effectiveness of the two-stage cascaded protection mechanism: First section: Normal operating range (right side of the chart, resistance approximately...) (Interval).

[0051] Curve characteristics: As the load resistance decreases, the output current exhibits a smooth, inversely proportional upward trend.

[0052] Principle Explanation: Within this range, the LDO operates in a normal voltage regulation state (e.g., a stable output of 3.3V or 5V). According to Ohm's Law: .

[0053] because Keep constant when the load resistance When reduced, the output current The corresponding increase. At this time, the overcurrent clamping tube... and short circuit protection control tube Both are in the off state, and the protection circuit does not interfere with the operation of the main loop at all.

[0054] Second section: Adaptive constant current protection zone (flat area at the top of the chart, resistance approximately...) (interval) Curve characteristics: When the resistance decreases to a specific value, the current reaches its maximum point (as shown in the diagram). After that, a distinct horizontal straight line appeared. Within this range, no matter how much the load resistance continued to decrease, the output current was stuck at a certain level. No more will be added.

[0055] Principle Explanation: This signifies that the first-level protection (constant current overcurrent protection) has been successfully triggered. When the current attempts to exceed the current limiting threshold, the gate potential of the main power transistor drops, causing the clamping transistor to... Conduction. main power transistor The gate potential clamping limits further current rise. At this time... Although it was activated (the short-circuit protection module was awakened and ready), due to... The detection tube has not yet fallen to the short-circuit threshold. Without strong intervention, the system maintained a constant current output.

[0056] Third section: Foldback protection zone (left side of the diagram, resistance approximately...) (interval) Curve characteristics: As the load resistance continues to decrease, it crosses the critical point (approximately...). After that, the curve experienced an extremely steep, precipitous drop (reversal). Ultimately, it short-circuited completely (…). When this occurs, the current is limited to a very low safe value (as shown in the diagram). ).

[0057] Principle Analysis: This signifies the strong intervention of the second-level protection (short-circuit foldback protection). Under constant current conditions, due to the extreme reduction in load resistance, the output voltage... Significant collapse and drop: .

[0058] when Falling below the critical point, detection tube Deep conduction, pull-down transistor It was opened completely in an instant, forcibly towards A high level is injected into the gate of the main power transistor, forcing it to... Deep shutdown. Output current from Compressed to "turnback" .

[0059] The simulation results above demonstrate the accuracy of the protection logic: between the flat constant current region and the steep turnaround region in the figure, there exists an extremely sharp and clean transition point. This indicates that... The cascaded design of the state-enabled short-circuit module did not produce any state ambiguity or oscillation, and the mechanism switching was very decisive.

[0060] This demonstrates extremely low power consumption under extreme operating conditions (thermal safety): if only constant current protection is available (only the flat region is available), then in Even during a short circuit, the main power transistor must still output power. The current is so high that it can withstand the entire power supply voltage drop, which can easily burn out the chip. This invention successfully reduces the short-circuit current to approximately 1 / 8 of the original current limit (approximately...). This greatly reduces the thermal stress on the chip and achieves truly high-reliability deep short-circuit protection.

[0061] This invention implements an innovative cascaded enable architecture that eliminates startup deadlock at zero cost. Traditional foldback current limiting circuits, in order to avoid deadlock during power-on startup, typically require the introduction of complex RC soft-start timers, additional blanking time circuits, or independent low-voltage comparators. This not only increases the chip area and static power consumption but also poses a timing mismatch risk.

[0062] This invention abandons the conventional approach of adding extra timing / comparison modules and creatively extracts the overcurrent clamping transistor. The conduction state serves as the enable signal (control) for the short-circuit protection module. By utilizing the inherent physical timing of the circuit to create a time difference, the problem is perfectly solved without adding any complex sequential logic. Startup and The system avoids misjudgment issues caused by short circuits, and its architecture is extremely simple and highly robust.

[0063] The circuit of this invention can improve adaptive clamping accuracy over a wide input voltage range. The current limiting threshold of traditional circuits is often easily affected by fluctuations in the input power supply voltage. The bias voltage network in this invention generates… It can synchronize with the input power supply voltage. This allows the clamping transistor to... and control tube The trigger point can adapt to changes in input voltage, ensuring consistency and high accuracy of overcurrent and short-circuit protection thresholds over a wide input voltage range.

[0064] The circuit of this invention also features extremely high area efficiency and ultra-low static power consumption. Compared to traditional PMIC protection schemes that employ multiple high-voltage operational amplifiers and precision current sampling resistors, the topology of this invention uses only a mirror structure composed of conventional MOS transistors, a simple voltage divider resistor network, and a state switch transistor. ).

[0065] Under normal operating conditions, the entire short-circuit reversal branch (due to...) (When turned off) it consumes almost no zero quiescent current penalty. At the same time, it eliminates the need for precision comparators and large sampling resistors, greatly saving silicon area, making it ideal for use in low dropout linear regulator (LDO) designs for portable electronic devices that are extremely sensitive to power consumption and cost.

[0066] This invention's circuit achieves smooth, seamless switching between two stages of "constant current-foldback". This invention provides clearly defined two-stage protection: under slight overload, only... Intervention maintains "constant current output" to ensure that the power supply to the downstream system is not unexpectedly cut off to the greatest extent possible; only in the event of a physical dead short circuit, Only when it completely collapses, by A powerful intervention is implemented for "deep back-off". The trigger boundaries of the two-level protection mechanism are clear and the transition is smooth, avoiding system oscillations that are easily caused by single back-off protection, and significantly improving the survivability of the power chip under complex and harsh operating conditions.

[0067] Example 2: Embodiment 2 of the present invention provides a protection method for the adaptive overcurrent protection circuit described in Embodiment 1, comprising the following steps: Based on the feedback of the reference voltage and the output voltage, a gate control signal is generated to drive the power transistor to provide current to the output terminal.

[0068] Generate a bias voltage that changes in the same direction as the power supply voltage.

[0069] The output current is detected based on the difference between the gate control signal and the bias voltage, and the gate control signal is clamped when the output current exceeds the threshold to achieve constant current overcurrent protection.

[0070] The short-circuit protection control module is awakened when the overcurrent detection and clamping module operates. In the awakened state, when the LDO output voltage drops below the short-circuit threshold, the short-circuit protection control module forcibly pulls the gate control signal to the power supply voltage, limiting the output current to the short-circuit protection current value.

[0071] The above steps rely on the adaptive overcurrent protection circuit described in Embodiment 1, including a bias voltage generation module, an overcurrent detection and clamping module, a short-circuit protection control module, and an LDO main loop. The LDO main loop generates a gate control signal based on feedback from the reference voltage and the output voltage, driving the power transistor to provide current to the output terminal. The bias voltage generation module generates a bias voltage that changes in the same direction as the power supply voltage. The overcurrent detection and clamping module is connected to the bias voltage generation module and the LDO main loop, respectively. It is used to detect the output current based on the difference between the gate control signal and the bias voltage, and clamp the gate control signal when the output current exceeds the threshold to achieve constant current overcurrent protection. The short-circuit protection control module has its enable terminal connected to the overcurrent detection and clamping module and is only awakened when the overcurrent detection and clamping module is activated. Its input terminal is connected to the LDO output voltage, and its output terminal is connected to the gate of the power transistor in the LDO main loop. In the awakened state, when the LDO output voltage drops below the short-circuit threshold, the short-circuit protection control module forcibly pulls the gate control signal to the power supply voltage, limiting the output current to the short-circuit protection current value.

[0072] In one specific implementation, the bias voltage generation module is connected to the power supply voltage V. M Between and ground, used to generate voltage V that varies with the power supply voltage. M Bias voltage changing in the same direction .

[0073] The bias voltage generation module includes a fifth PMOS transistor and a sixth PMOS transistor. The source of the fifth PMOS transistor M5 is connected to the power supply voltage V. M The gate and drain of M5 are connected, forming a diode-connected load. The drain is connected to the sixth PMOS transistor. The source pole, The gate and drain are connected to form a diode connection, and are connected to the bias voltage. .

[0074] In one specific implementation, the overcurrent detection and clamping module includes a zero-order NMOS transistor M0 and a zero-order resistor R0, one end of which is connected to the power supply voltage V. M The other end is connected to the drain of the zeroth NMOS transistor M0; the gate of the zeroth NMOS transistor M0 is connected to the output of the bias voltage generation module to receive the bias voltage. The source of the zeroth NMOS transistor M0 is connected to the gate of the source follower M1 in the main loop of the LDO. When the gate potential of the LDO power transistor M2 decreases below a preset threshold as the output current increases, the zeroth NMOS transistor M0 is turned on and clamps the gate potential to achieve constant current overcurrent protection.

[0075] In one specific implementation, the short-circuit protection control module includes a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, and a tenth PMOS transistor M10. 10 The source of the seventh PMOS transistor M7 is connected to the power supply voltage V. M The gate of the seventh PMOS transistor M7 is connected to the drain of the zeroth NMOS transistor M0, and the drain of the seventh PMOS transistor M7 is connected to the drain of the eighth NMOS transistor M8; the source of the eighth NMOS transistor M8 is grounded, and its gate and drain are connected to form a current mirror; the drain of the ninth NMOS transistor M9 is connected to the first resistor R1, and its source is connected to the LDO output voltage V. out The gate of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8; the tenth PMOS transistor M... 10 The drain of the tenth PMOS transistor M is connected to the gate of the LDO power transistor M2. 10 The source is connected to the power supply voltage V. M The tenth PMOS transistor M 10 The gate of the transistor is connected to the drain of the ninth NMOS transistor M9.

[0076] The short-circuit protection control module only receives operating current and is woken up when the zeroth NMOS transistor M0 in the overcurrent detection and clamping module is turned on, thereby pulling down the gate potential of the seventh PMOS transistor M7 and turning it on; in the woken-up state, when the LDO output voltage V out When the voltage drops below the short-circuit detection threshold, the ninth NMOS transistor M9 turns on and pulls down the tenth PMOS transistor M1. 10 The gate potential of the tenth PMOS transistor M 10 Turning on the transistor forces the gate potential of the LDO power transistor M2 to the power supply voltage V. M This shuts off the LDO power transistor M2 to limit the output current to a very small short-circuit protection current value.

[0077] In one specific implementation, the LDO main loop includes an operational amplifier, a source follower M1, an LDO power transistor M2, a first resistor R3, and a second resistor R2. The non-inverting input of the operational amplifier is connected to a reference voltage V. ref The inverting input is connected to the voltage divider point V of the LDO output voltage through R2 and R3. fbThe drain of source follower M1 is grounded, and its gate is connected to the output of the operational amplifier and simultaneously to the source of the sensing power transistor M0. The source of the LDO power transistor M2 is connected to the power supply voltage V. M The drain of M2 is used as the output voltage V. out .

[0078] The circuit's operation can be divided into three stages: system startup and normal operation, overcurrent protection, and short-circuit back-off protection, each corresponding to different load conditions.

[0079] State 1: System startup and normal operation phase used to prevent deadlock hibernation.

[0080] Triggering condition: The chip powers on and starts up (at this time V out =0V) or within the normal load range.

[0081] Operating principle: During this stage, the error amplifier outputs a normal control level, and the main power transistor M2 provides current normally. The gate-source voltage of the clamping transistor M0 has not reached the turn-on threshold and is in the off state.

[0082] Anti-deadlock mechanism: Since M0 is turned off, the gate of M7 is pulled high to near the power supply potential V through its source by a resistor. M This keeps control transistor M7 off. The shutdown of M7 directly cuts off the subsequent short-circuit detection branches (M8, M9, M...). 10 The operating current of the circuit is such that even if the detection tube M9 detects Vout=0V at startup, the short-circuit protection module is in a "forced sleep" state and will not clamp the main loop incorrectly. This ensures that the output capacitor can be charged smoothly with full load current, completely solving the startup deadlock problem of traditional foldback circuits.

[0083] State 2: Overcurrent protection stage for adaptive constant current clamping.

[0084] Triggering conditions: The load becomes suddenly heavier, and the output current exceeds the set maximum threshold, but no deep short circuit occurs at the output terminal.

[0085] Operating principle: To provide a large current, the output potential of the operational amplifier (i.e., the gate potentials of M1 and M2) is forced to drop. When this potential drops to a level that makes the source potential of M0 sufficiently low, satisfying VGS0 > VTH0, M0 turns on. After M0 turns on, it clamps the gate potential of the main power transistor M2 to a fixed value, limiting further increases in output current, and the system enters "constant current protection" mode.

[0086] Short-circuit module wake-up: At this time, current is generated in the M0 branch, causing the gate potential of M7 to be pulled low, and the control transistor M7 turns on. After M7 turns on, the eighth NMOS transistor M8 receives bias current, and the short-circuit protection module is officially "wake up (enabled)" and enters the short-circuit monitoring standby state. State 3: Short-circuit protection stage used to achieve deep turnaround.

[0087] Triggering condition: Under overcurrent conditions, an extreme short circuit occurs at the load end, causing the output voltage V to surge. out Severe drop (close to 0V).

[0088] Operating principle: At this time, the short-circuit protection module has been activated. With V... out The drop, the source is connected to V out As the gate voltage of the detection transistor M9 decreases, its conduction capability increases, and it begins to draw current mirrored from M8. This current creates a voltage drop at the node between the source of M9 and the drain of M8, thereby pulling down and fully turning on the strong pull-down transistor M8. 10 .

[0089] Return clamp: M 10 Once turned on, its powerful current-pull capability directly overrides the control of the error amplifier, forcibly pulling the gate of the main power transistor M2 towards ground potential. This forces M2 to be deeply turned off, and the output current drops sharply from the "constant current maximum value" to a very small safe short-circuit current, achieving perfect foldback characteristics and greatly reducing chip power consumption under extreme short-circuit conditions.

[0090] Example 3: Embodiment 3 of the present invention provides a voltage regulator, including the adaptive overcurrent protection circuit described in Embodiment 1.

[0091] Example 4: Embodiment 4 of the present invention provides an electronic product, including the voltage regulator described in Embodiment 3.

[0092] The steps and methods involved in Examples 2, 3 and 4 above correspond to those in Example 1. For specific implementation details, please refer to the relevant description section of Example 1.

[0093] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data processing device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, an optical medium, or a semiconductor medium, etc.

[0095] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An adaptive overcurrent protection circuit, characterized in that, include: The LDO main loop is used to generate a gate control signal based on the feedback of the reference voltage and the output voltage, which drives the power transistor to provide current to the output terminal. Bias voltage generation module, used to generate a bias voltage that changes in the same direction as the power supply voltage; The overcurrent detection and clamping module is connected to the bias voltage generation module and the LDO main loop, respectively. It is used to detect the output current based on the difference between the gate control signal and the bias voltage, and clamp the gate control signal when the output current exceeds the threshold to achieve constant current overcurrent protection. The short-circuit protection control module has its enable terminal connected to the overcurrent detection and clamping module, and is only awakened when the overcurrent detection and clamping module is activated; its input terminal is connected to the LDO output voltage, and its output terminal is connected to the gate of the power transistor in the main loop of the LDO; when awakened, when the LDO output voltage drops below the short-circuit threshold, the short-circuit protection control module forcibly pulls the gate control signal to the power supply voltage, limiting the output current to the short-circuit protection current value.

2. The adaptive overcurrent protection circuit as described in claim 1, characterized in that, The bias voltage generation module includes a fifth PMOS transistor and a sixth PMOS transistor. The source of the fifth PMOS transistor M5 is connected to the power supply voltage V. M The gate and drain of M5 are connected, forming a diode-type load. The drain is connected to the sixth PMOS transistor. The source pole, The gate and drain are connected to form a diode connection, and are connected to the bias voltage. .

3. The adaptive overcurrent protection circuit as described in claim 1, characterized in that, The overcurrent detection and clamping module includes a zero-order NMOS transistor M0 and a zero-order resistor R0, one end of which is connected to the power supply voltage V. M The other end is connected to the drain of the zeroth NMOS transistor M0; the gate of the zeroth NMOS transistor M0 is connected to the output of the bias voltage generation module to receive the bias voltage. The source of the zeroth NMOS transistor M0 is connected to the gate of the source follower M1 in the main loop of the LDO. When the gate potential of the LDO power transistor M2 decreases below a preset threshold as the output current increases, the zeroth NMOS transistor M0 is turned on and clamps the gate potential to achieve constant current overcurrent protection.

4. The adaptive overcurrent protection circuit as described in claim 1, characterized in that, The short-circuit protection control module includes the seventh PMOS transistor M7, the eighth NMOS transistor M8, the ninth NMOS transistor M9, and the tenth PMOS transistor M10. 10 The source of the seventh PMOS transistor M7 is connected to the power supply voltage V. M The gate of the seventh PMOS transistor M7 is connected to the drain of the zeroth NMOS transistor M0, and the drain of the seventh PMOS transistor M7 is connected to the drain of the eighth NMOS transistor M8; the source of the eighth NMOS transistor M8 is grounded, and its gate and drain are connected to form a current mirror; the drain of the ninth NMOS transistor M9 is connected to the first resistor R1, and its source is connected to the LDO output voltage V. out The gate of the ninth NMOS transistor M9 is connected to the drain of the eighth NMOS transistor M8; the tenth PMOS transistor M... 10 The drain of the tenth PMOS transistor M is connected to the gate of the LDO power transistor M2. 10 The source is connected to the power supply voltage V. M The tenth PMOS transistor M 10 The gate of the transistor is connected to the drain of the ninth NMOS transistor M9.

5. The adaptive overcurrent protection circuit as described in claim 1, characterized in that, The short-circuit protection control module only obtains operating current and is woken up when the zeroth NMOS transistor M0 in the overcurrent detection and clamping module is turned on, thereby pulling down the gate potential of the seventh PMOS transistor M7 and turning on the seventh PMOS transistor M7. In wake-up state, when the LDO output voltage V out When the voltage drops below the short-circuit detection threshold, the ninth NMOS transistor M9 turns on and pulls down the tenth PMOS transistor M1. 10 The gate potential of the tenth PMOS transistor M 10 Turning on the transistor forces the gate potential of the LDO power transistor M2 to the power supply voltage V. M This shuts off the LDO power transistor M2 to limit the output current to a very small short-circuit protection current value.

6. The adaptive overcurrent protection circuit as described in claim 1, characterized in that, The main loop of the LDO includes an operational amplifier, a source follower M1, an LDO power transistor M2, a first resistor R3, a second resistor R2, and a reference voltage V connected to the non-inverting input of the operational amplifier. ref The inverting input is connected to the voltage divider point V of the LDO output voltage through R2 and R3. fb The drain of source follower M1 is grounded, and its gate is connected to the output of the operational amplifier and simultaneously to the source of the sensing power transistor M0. The source of the LDO power transistor M2 is connected to the power supply voltage V. M The drain of M2 is used as the output voltage V. out .

7. The adaptive overcurrent protection circuit as described in claim 1, characterized in that, The circuit's operation includes a system startup and normal operation phase for preventing deadlock hibernation, an overcurrent protection phase for adaptive constant current clamping, and a short-circuit protection phase for achieving deep foldback.

8. A protection method for an adaptive overcurrent protection circuit as described in any one of claims 1-7, characterized in that, Includes the following steps: A gate control signal is generated based on the feedback of the reference voltage and the output voltage, which drives the power transistor to provide current to the output terminal. Generate a bias voltage that changes in the same direction as the power supply voltage; The output current is detected based on the difference between the gate control signal and the bias voltage, and the gate control signal is clamped when the output current exceeds the threshold to achieve constant current overcurrent protection. The short-circuit protection control module is awakened when the overcurrent detection and clamping module operates. In the awakened state, when the LDO output voltage drops below the short-circuit threshold, the short-circuit protection control module forcibly pulls the gate control signal to the power supply voltage, limiting the output current to the short-circuit protection current value.

9. A voltage regulator, characterized in that, Includes the adaptive overcurrent protection circuit as described in any one of claims 1-7.

10. An electronic product, characterized in that, Includes the voltage regulator as described in claim 9.

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