An over-temperature protection circuit, a power management chip and a vehicle

Abstract

The present application belongs to the field of vehicle power management chip design, and provides an over-temperature protection circuit, a power management chip and a vehicle, which solves the problems of hiccup phenomenon, latch risk and poor batch consistency of the existing over-temperature protection circuit. The over-temperature protection circuit comprises: a bias current mirror unit that receives a bias current and copies and distributes the bias current to each functional branch; a temperature sensing unit that converts chip temperature changes into a sensing voltage that decreases with temperature rise under the drive of the bias current; a reference voltage generation unit that receives a temperature positively related current and generates a reference voltage that increases with temperature rise; a differential comparison unit that differentially compares the sensing voltage and the reference voltage and outputs a comparison result; a common source amplification unit that amplifies the comparison result; an output shaping unit that outputs a full-amplitude digital over-temperature protection signal; and a hysteresis feedback unit that actively lowers or releases the reference voltage according to the over-temperature protection signal level, so as to form a hysteresis temperature difference between the over-temperature trigger threshold and the recovery threshold.

Description

Technical Field

[0001] This invention belongs to the field of vehicle power management chip design technology, specifically relating to an over-temperature protection circuit, a power management chip, and a vehicle. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] The core function of the over-temperature protection circuit is to monitor the chip junction temperature in real time. When the junction temperature exceeds the set threshold, the power output is quickly shut off to prevent the chip from being damaged due to continuous overheating. The circuit will automatically re-enable power supply after the temperature returns to a safe range.

[0004] Existing technologies typically employ an NTC thermistor voltage divider scheme combined with an external comparator and an independent hysteresis positive feedback module to achieve over-temperature protection. The protection threshold relies on batch calibration through a trimming process. However, the hysteresis mechanism, which depends on an independent positive feedback module or a passive compensation network, cannot actively suppress oscillations at the source of the sensing node, making it prone to hiccups. Furthermore, the sensing node exhibits a large dv / dt at the moment of switching, lacking effective on-chip voltage swing limiting measures, thus posing a latch-up risk. Additionally, the large resistance tolerance of NTC thermistors necessitates threshold calibration through a trimming process, resulting in poor batch consistency and high manufacturing costs. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes an over-temperature protection circuit, a power management chip, and a vehicle. This invention provides a highly reliable over-temperature protection circuit that requires no adjustment, features an active hysteresis mechanism, and prevents latch-up. Through the coordinated operation of various functional units, the negative temperature coefficient sensing voltage output by the temperature sensing unit and the positive temperature coefficient reference voltage output by the reference voltage generation unit form a dual temperature coefficient structure that changes in opposite directions. The over-temperature trigger threshold is naturally determined by the inherent temperature characteristics of the device, requiring no adjustment process calibration. After over-temperature triggering, the hysteresis feedback unit actively adjusts the reference voltage, forming a stable hysteresis temperature difference from the source, completely eliminating the hiccuping phenomenon.

[0006] According to some embodiments, the first solution of the present invention provides an over-temperature protection circuit, which adopts the following technical solution: An over-temperature protection circuit, having a bias current input terminal and a temperature-dependent current input terminal, includes: The bias current mirror unit is used to receive the bias current input from the bias current input terminal and copy and distribute the bias current to each functional branch. A temperature sensing unit is used to convert the chip temperature change into a sensing voltage that decreases as the temperature rises, driven by the bias current provided by the bias current mirror unit. A reference voltage generation unit is used to receive the current input from the temperature-correlated current input terminal and generate a reference voltage that increases with increasing temperature. A differential comparison unit is used to perform a differential comparison between the sensed voltage and the reference voltage, and output a differential comparison result signal; A common-source amplifier unit is used to amplify the differential comparison result signal and output an amplified output signal; The output shaping unit is used to shape the amplified output signal and output a full-scale digital over-temperature protection signal. The hysteresis feedback unit is used to actively lower or release the output reference voltage of the reference voltage generation unit according to the level state of the over-temperature protection signal, so as to form a hysteresis temperature difference between the over-temperature trigger threshold and the recovery threshold.

[0007] In some embodiments, the bias current mirror unit includes an NMOS current mirror composed of a first NMOS transistor (N4) and a second NMOS transistor (N5), and a PMOS current mirror composed of a first PMOS transistor (P5), a second PMOS transistor (P0), a third PMOS transistor (P1), and a fourth PMOS transistor (P2). The gate-drain shorting node of the first NMOS transistor (N4) is connected to the bias current input terminal, the gate of the second NMOS transistor (N5) is connected to the gate of the first NMOS transistor (N4), and the drain of the second NMOS transistor (N5) is connected to the gate-drain shorting node of the first PMOS transistor (P5). The gate-drain short-circuit node of the first PMOS transistor (P5) is simultaneously connected to the gates of the second PMOS transistor (P0), the third PMOS transistor (P1), and the fourth PMOS transistor (P2); the drains of the second PMOS transistor (P0), the third PMOS transistor (P1), and the fourth PMOS transistor (P2) respectively provide bias current to the temperature sensing unit, the differential comparator unit, and the common-source amplifier unit.

[0008] The above-mentioned two-stage cascaded NMOS and PMOS current mirror structures improve the current mirroring accuracy, enabling the bias current of each functional branch to effectively suppress fluctuations in the power supply voltage AVDD, ensuring that the accuracy of the over-temperature protection threshold is not affected by power supply fluctuations, and achieving high-precision current distribution.

[0009] In some embodiments, the temperature sensing unit includes a PNP transistor (Q0), with the collector and base of the PNP transistor (Q0) shorted and connected to analog ground (AGND), and the emitter of the PNP transistor (Q0) connected to the drain of a second PMOS transistor (P0). Utilizing the inherent negative temperature coefficient of the PNP transistor (Q0), the chip junction temperature change is converted into a sensing voltage that decreases monotonically with increasing temperature. This characteristic is determined by the band structure of the semiconductor material and is unaffected by batch variations in the manufacturing process, ensuring batch-to-batch threshold consistency without external adjustment.

[0010] In some embodiments, the reference voltage generation unit includes a voltage divider network consisting of a first resistor (R1) and a second resistor (R2) connected in series; The upper end of the first resistor (R1) is connected to the temperature-dependent current input terminal, the lower end of the first resistor (R1) is connected to the upper end of the second resistor (R2), and the lower end of the second resistor (R2) is connected to the analog ground terminal (AGND).

[0011] The voltage divider network described above utilizes the positive temperature coefficient characteristic of the PTAT current to generate a reference voltage at the IPTAT node that monotonically increases with temperature. This forms a dual temperature coefficient structure with the negative temperature coefficient sensing voltage output by the temperature sensing unit. The over-temperature trigger threshold is naturally determined by the inherent temperature characteristics of the device, eliminating the need for process calibration and ensuring good batch consistency.

[0012] In some embodiments, the differential comparator unit includes a differential input pair consisting of a fifth PMOS transistor (P3) and a sixth PMOS transistor (P4); the sources of the fifth PMOS transistor (P3) and the sixth PMOS transistor (P4) are connected to the drain of a third PMOS transistor (P1); the gate of the fifth PMOS transistor (P3) is connected to the drain of the second PMOS transistor (P0), and the gate of the sixth PMOS transistor (P4) is connected to the temperature-dependent current input terminal (IPTAT) and the upper end of the first resistor (R1).

[0013] In some embodiments, the differential comparison unit further includes an active current mirror load composed of a third NMOS transistor (N0) and a fourth NMOS transistor (N1); The drain of the fifth PMOS transistor (P3) is connected to the gate-drain short-circuit node of the third NMOS transistor (N0), and the gate of the third NMOS transistor (N0) is also connected to the gate of the fourth NMOS transistor (N1). The drain of the sixth PMOS transistor (P4) is connected to the drain of the fourth NMOS transistor (N1), and this common node serves as the differential comparator output node. The sources of the third NMOS transistor (N0) and the fourth NMOS transistor (N1) are both connected to analog ground (AGND).

[0014] The aforementioned differential comparator structure utilizes the N0 / N1 active current mirror load to increase the equivalent output impedance of the differential pair, thereby increasing the differential comparator gain. This makes the over-temperature triggering switching process cleaner and faster, effectively reducing oscillations and glitches during the switching process and improving the accuracy and reliability of over-temperature judgment.

[0015] In some embodiments, the common-source amplifier unit includes a fifth NMOS transistor (N2) and a fourth PMOS transistor (P2); the gate of the fifth NMOS transistor (N2) is connected to the differential comparator output node, the drain is connected to the drain of the fourth PMOS transistor (P2), and the source is connected to analog ground (AGND); the drain node of the fourth PMOS transistor (P2) also serves as the common-source amplifier output node (DOTP node) connected to the input terminal of the Schmitt trigger (SMITT) in the output shaping unit; the common-source amplifier output node (DOTP node) is also connected to one end of a first filter capacitor (C1), and the other end of the first filter capacitor (C1) is connected to analog ground (AGND).

[0016] The aforementioned common-source amplifier structure converts the differential comparison result signal into a single-ended amplified output signal. The first filter capacitor (C1) performs integral filtering on the common-source amplifier output node, smoothing the voltage change rate (dv / dt) at the moment of switching, limiting dv / dt to less than 50V / μs, effectively suppressing the triggering conditions of on-chip parasitic thyristors, and reducing the risk of on-chip latch-up.

[0017] In some embodiments, the output shaping unit includes a Schmitt trigger (SMITT), a first inverter (I0), and a second inverter (I1). The input of the Schmitt trigger (SMITT) is connected to the output of the common-source amplifier unit, and the output of the Schmitt trigger (SMITT) is connected to the input of the first inverter (I0). The output terminal of the first inverter (I0) is connected to the input terminal of the second inverter (I1); the output terminal of the second inverter (I1) serves as the over-temperature protection signal output terminal (OTP), outputting a full-amplitude (0 to AVDD) digital signal.

[0018] The above-mentioned output shaping structure effectively eliminates glitches and oscillations during the switching process by utilizing the dual threshold characteristics of the Schmitt trigger. After being shaped and driven by two stages of inverters, it outputs a full-amplitude digital over-temperature protection signal with a clear and unambiguous logic state. It can directly drive the gate of subsequent logic circuits or power devices without the need for additional level conversion circuits, thus meeting the requirements of automotive-grade functional safety for the integrity of protection signals.

[0019] In some embodiments, the hysteresis feedback unit includes a sixth NMOS transistor (N3); the gate of the sixth NMOS transistor (N3) is connected to the over-temperature protection signal output terminal (OTP), the drain of the sixth NMOS transistor (N3) is connected to the node between the lower end of the first resistor (R1) and the upper end of the second resistor (R2) in the reference voltage generation unit, and the source of the sixth NMOS transistor (N3) is connected to the analog ground terminal (AGND).

[0020] When the over-temperature protection signal output terminal (OTP) outputs a high level, the sixth NMOS transistor (N3) is turned on, pulling down the voltage divider node and reducing the reference voltage, thus forming active hysteresis feedback. When the over-temperature protection signal output terminal (OTP) outputs a low level, the sixth NMOS transistor (N3) is turned off, the voltage divider node voltage increases, and the reference voltage increases accordingly, preventing hiccups. The above-mentioned active hysteresis feedback mechanism, in conjunction with the dual threshold characteristics of the Schmitt trigger (SMITT), forms a stable hysteresis temperature difference between the over-temperature trigger threshold and the temperature recovery threshold, actively suppressing oscillations during comparator switching from the source of the sensing node, and completely eliminating the frequent switching (hiccups) phenomenon near the protection point.

[0021] In some embodiments, the over-temperature protection circuit further includes a second filter capacitor (C0); one end of the second filter capacitor (C0) is connected to the temperature-dependent current input terminal (IPTAT), and the other end is connected to the analog ground terminal (AGND), used to filter out high-frequency noise from the IPTAT node and prevent the differential comparator unit from being falsely triggered. The second filter capacitor (C0) works in conjunction with the first filter capacitor (C1) to suppress high-frequency noise at key nodes from the input and output sides respectively, thereby improving the overall anti-interference capability and operational reliability of the over-temperature protection circuit in complex electromagnetic environments.

[0022] According to some embodiments, a second aspect of the present invention provides a power management chip, employing the following technical solution: A power management chip includes an over-temperature protection circuit as described in the first embodiment, and also includes a bandgap reference source; The first output terminal of the bandgap reference source is connected to the bias current input terminal (IB) to provide a reference current to the bias current mirror unit; the second output terminal of the bandgap reference source is connected to the temperature-dependent current input terminal (IPTAT) to provide a current proportional to the absolute temperature to the reference voltage generation unit.

[0023] The bandgap reference source utilizes the bandgap voltage characteristics of the semiconductor PN junction to generate a high-precision reference output that is highly independent of process deviations, power supply voltage variations, and temperature changes. Both outputs originate from the same reference core and have good correlation, effectively suppressing the impact of process deviations and temperature changes on the over-temperature protection threshold, thus meeting the high reliability requirements of automotive-grade (AEC-Q100) applications.

[0024] According to some embodiments, a third aspect of the present invention provides a vehicle.

[0025] A vehicle, including a power management chip as described in the second embodiment; The power management chip is integrated into the vehicle's electronic control unit; the over-temperature protection signal output terminal (OTP) is signal-connected to the power control terminal of the electronic control unit, and is used to shut down the power output when the junction temperature of the power management chip exceeds the over-temperature trigger threshold, and automatically restore power supply when the junction temperature drops below the recovery threshold.

[0026] The approximately 18°C ​​hysteresis temperature difference ensures that the chip junction temperature has sufficient margin to drop before power supply can be restored after power output is turned off, preventing stress accumulation in power devices and unstable load power supply caused by frequent switching, and ensuring the safe and reliable operation of the vehicle power system.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention uses a temperature sensing unit to convert chip temperature changes into a sensing voltage that decreases as the temperature rises, and a reference voltage generation unit to generate a reference voltage that increases as the temperature rises. These two units form a dual-temperature coefficient structure that changes in opposite directions. The over-temperature trigger threshold is naturally determined by the inherent temperature characteristics of the device, eliminating the need for batch calibration using trimming processes, thus reducing manufacturing costs and improving batch consistency. A differential comparison unit performs a differential comparison between the sensing voltage and the reference voltage, exhibiting a high common-mode rejection ratio, effectively suppressing the influence of power supply noise and substrate noise on the comparison result. A common-source amplification unit amplifies the differential comparison result signal, and an output shaping unit shapes the amplified output signal to output a full-amplitude digital over-temperature protection signal with strong driving capability, effectively preventing malfunctions in subsequent logic circuits. A hysteresis feedback unit actively lowers or releases the output reference voltage of the reference voltage generation unit based on the level of the over-temperature protection signal, actively forming a stable hysteresis temperature difference from the source of the sensing node. This completely eliminates the hiccuping phenomenon that easily occurs in existing passive hysteresis schemes, improving the reliability of the protected load. Attached Figure Description

[0028] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0029] Figure 1 The circuit diagram is shown for the over-temperature protection circuit provided in Embodiment 1 of the present invention.

[0030] Figure 2 The graph shows the hysteresis characteristic of the over-temperature protection signal as a function of temperature, provided in Embodiment 1 of the present invention. The horizontal axis represents temperature (°C) and the vertical axis represents output voltage (V). It shows the over-temperature trigger threshold of 171.4°C and the temperature recovery threshold of 153.4°C, with a hysteresis temperature difference of approximately 18°C. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0032] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0033] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0034] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0035] Before describing the embodiments of the present invention, the core technical terms involved in this application are first uniformly defined to ensure the clarity and consistency of the subsequent description.

[0036] PTAT current (Proportional to Absolute Temperature): refers to a current signal generated by a bandgap reference source whose value increases linearly with increasing absolute temperature. The temperature coefficient of PTAT current is positive, and it is often used in integrated circuit design to generate reference voltages with positive temperature coefficients, or in conjunction with negative temperature coefficient signals to achieve temperature detection. In this application, the PTAT current is provided by the second output terminal of the bandgap reference source and input to the over-temperature protection circuit through the temperature-positive current input terminal IPTAT, serving as the drive current source for the reference voltage generation unit.

[0037] A bandgap reference, utilizing the bandgap voltage characteristics of a semiconductor PN junction, generates a high-precision reference voltage or current that is highly independent of process variations, power supply voltage changes, and temperature variations by compensating for the base-emitter voltage VBE (which has a negative temperature coefficient) and the PTAT voltage (which has a positive temperature coefficient). Bandgap references are among the most important reference sources in analog integrated circuits and are widely used in ADCs, DACs, LDOs, and power management chips. In this application, the bandgap reference simultaneously outputs a high-precision bias reference current IB and a PTAT current IPTAT, both originating from the same reference core.

[0038] Hysteresis temperature difference: The temperature difference between the over-temperature trigger threshold (the temperature at which the circuit switches from normal operation to protection mode) and the temperature recovery threshold (the temperature at which the circuit automatically recovers from protection mode to normal operation). The existence of the hysteresis temperature difference means that after the over-temperature protection circuit is triggered, it must wait for the temperature to drop sufficiently before automatically restoring power supply. This effectively prevents the circuit from frequently switching on and off near the threshold due to small temperature fluctuations, protecting the driven load from repeated start-stop shocks. In this application, the hysteresis temperature difference is formed by the active pull-down effect of the sixth NMOS transistor N3 in the hysteresis feedback unit after it is turned on, which is approximately 18°C ​​according to simulation results.

[0039] A Schmitt trigger is a shaping circuit with dual threshold comparison characteristics. The threshold required to trigger the output to flip during the rising phase of the input signal (upper threshold VT+) is higher than the threshold required to trigger the output to flip during the falling phase (lower threshold VT-). The difference between the two thresholds constitutes the hysteresis window of the Schmitt trigger. Schmitt triggers effectively eliminate noise, glitches, and slowly changing signals in the input signal, shaping the analog signal into a clean digital signal. They are commonly used shaping devices in digital-to-analog interface circuits. In this application, the input of the Schmitt trigger (SMITT) is connected to the common-source amplifier output node (DOTP), shaping the analog signal output from the common-source amplifier unit before sending it to the subsequent inverter chain.

[0040] Common-Source Amplification: A single-transistor amplifier topology using an NMOS transistor with its source grounded (or connected to a fixed potential), gate as input, and drain as output. Common-source amplifiers are characterized by high voltage gain (approximately -gm×Rd) and high input impedance, making them one of the most basic amplification units in analog integrated circuits. They are commonly used to amplify small-amplitude differential comparator output signals into signals capable of driving subsequent shaping circuits. In this application, the common-source amplifier unit consists of a fifth NMOS transistor N2 and a fourth PMOS transistor P2. The gate of N2 receives the signal from the differential comparator output node VOUT, and the drain outputs the amplified signal to node DOTP.

[0041] Diode-connected MOS: This method directly connects the gate and drain of a MOS transistor, causing it to operate in diode mode (always in saturation). A MOS transistor with a gate-drain connection has a defined gate-source voltage VGS, and its drain current is uniquely determined by VGS. It is commonly used in the reference branch of a current mirror to provide a stable bias gate voltage for the mirror branch. In this application, both the first NMOS transistor N4 and the first PMOS transistor P5 are connected with a gate-drain connection, serving as the reference transistors for the NMOS and PMOS current mirrors, respectively.

[0042] As described in the background section, in existing technologies, over-temperature protection circuits typically use an NTC thermistor and a fixed resistor to form a voltage divider network, converting temperature changes into a voltage signal. This signal is then compared with an internal reference voltage by a comparator. When the voltage at the divider point is lower than the reference, the over-temperature protection is triggered, shutting off the PMOS transistor connected in series in the main power circuit, thus de-energizing the load and stopping heating. When the temperature drops and the voltage at the divider point rises above the reference again, the comparator flips again, restoring power supply, thereby achieving the over-temperature protection function. To introduce hysteresis, some solutions add an independent positive feedback resistor network around the comparator or use a dedicated hysteresis comparator module to establish a certain temperature difference between the trigger threshold and the recovery threshold, preventing frequent switching.

[0043] However, the existing technical solutions mentioned above have the following three core defects: First, the existing hysteresis solutions rely on independent positive feedback modules or passive compensation networks, which cannot actively suppress the oscillation during the comparator switching process from the source of the sensing node. When the temperature is close to the threshold, frequent switching "hiccups" are still likely to occur, affecting the reliability of the protected load. Second, the sensing node has a large dv / dt at the moment of comparator switching. If there is a lack of effective on-chip voltage swing limiting measures, it may trigger parasitic thyristors, resulting in latch-up risk and threatening chip safety. Third, the voltage divider solution based on NTC thermistors has a large resistance tolerance. The over-temperature trigger threshold varies significantly between different batches. It usually requires a trimming process to calibrate the threshold, which increases manufacturing costs and cannot fundamentally eliminate the consistency deviation between batches.

[0044] Based on the above problems, this invention provides a high-reliability over-temperature protection circuit solution based on a differential comparator structure, active hysteresis feedback, utilizing the natural threshold setting of the negative temperature coefficient of PNP transistors, and requiring no process adjustment, specifically addressing the three core defects mentioned above. This solution is centered on the collaborative operation of seven functional units: the bias current mirror unit consists of four PMOS transistors (P5, P0, P1, P2) and two NMOS transistors (N4, N5), receiving a high-precision reference current IB provided by an external bandgap reference source, and accurately replicating and distributing the bias current to each functional branch through two-stage current mirrors; the temperature sensing unit utilizes the inherent negative temperature coefficient of PNP transistor Q0 to convert the chip junction temperature change into a sensing voltage (VS node, i.e., the P0 drain / Q0 emitter node) that monotonically decreases with increasing temperature; the reference voltage generation unit receives the PTAT current provided by the bandgap reference source, flows through a series voltage divider network of first resistor R1 and second resistor R2, and generates a reference voltage that monotonically increases with increasing temperature at the intermediate node of R1 / R2; the differential comparator unit consists of… The P3 / P4 differential input pair and N0 / N1 active current mirror loads are used to perform differential comparison between the sensed voltage and the reference voltage, and the differential comparison result is output at the drain node of P4 / N1. The common-source amplifier unit consists of N2 (common-source amplifier) ​​and P2 (active load), which amplifies the differential comparison result into a single-ended signal and sends it to the output shaping unit via the DOTP node. The output shaping unit consists of a Schmitt trigger (SMITT), an inverter I0, and an inverter I1 connected in series, which shapes the DOTP node signal into a full-scale digital over-temperature protection signal OTP. In the hysteresis feedback unit, the gate of N3 is connected to the OTP terminal, and the drain is connected to the R1 / R2 voltage divider node. When OTP is high, N3 conducts and pulls down the voltage divider node to form active hysteresis feedback, which works with SMITT to form a stable hysteresis temperature difference of about 18°C.

[0045] like Figure 1As shown, the over-temperature protection circuit in this embodiment is a functional sub-module (OVERTEMPERATURE PROTECTION, OTP module) inside the power management chip. It has four input ports and one output port: the input ports include the power supply terminal AVDD, the bias current input terminal IB, the temperature-dependent current input terminal IPTAT, and the analog ground terminal AGND; the output port is the over-temperature protection signal output terminal OTP, which outputs a full-amplitude (0 to AVDD) digital signal that can directly drive the gate of the subsequent logic circuit or power device.

[0046] Figure 1 The components are labeled as follows: P5 is the first PMOS transistor (current mirror reference transistor, gate and drain shorted), P0 is the second PMOS transistor, P1 is the third PMOS transistor, and P2 is the fourth PMOS transistor. These four PMOS transistors together constitute the PMOS portion of the bias current mirror unit; N4 is the first NMOS transistor (current mirror reference transistor, gate and drain shorted), and N5 is the second NMOS transistor. These two NMOS transistors constitute the NMOS portion of the bias current mirror unit; Q0 is a PNP transistor (collector and base shorted to AGND, emitter connected to P0 drain), forming the temperature sensing unit; R1 and R2 are series junction transistors. The voltage regulator forms the reference voltage generation unit; P3 is the fifth PMOS transistor, P4 is the sixth PMOS transistor, N0 is the third NMOS transistor, and N1 is the fourth NMOS transistor, which together form the differential comparator unit; N2 is the fifth NMOS transistor (common source amplifier), which together with P2 forms the common source amplifier unit; N3 is the sixth NMOS transistor, which forms the hysteresis feedback unit; C0 is the second filter capacitor (connected to the IPTAT node and AGND), and C1 is the first filter capacitor (connected to the DOTP node and AGND); SMITT is a Schmitt trigger, and I0 and I1 are inverters, which together form the output shaping unit.

[0047] It should be understood that the embodiments described in this application are for illustrative purposes only and do not imply any limitation on the scope of protection of this application. The over-temperature protection circuit of this application can also be applied to other integrated circuit applications that require over-temperature protection, such as industrial power management and consumer electronics power management.

[0048] The following combination Figure 1 This application provides a detailed description of the specific structure, connection relationship, and working principle of each functional unit of the over-temperature protection circuit provided in the embodiments.

[0049] Example 1 like Figure 1 As shown, this embodiment provides an over-temperature protection circuit, which has a bias current input terminal and a temperature-dependent current input terminal, including: The bias current mirror unit is used to receive the bias current input from the bias current input terminal and copy and distribute the bias current to each functional branch. A temperature sensing unit is used to convert the chip temperature change into a sensing voltage that decreases as the temperature rises, driven by the bias current provided by the bias current mirror unit. A reference voltage generation unit is used to receive the current input from the temperature-correlated current input terminal and generate a reference voltage that increases with increasing temperature. A differential comparison unit is used to perform a differential comparison between the sensed voltage and the reference voltage, and output a differential comparison result signal; A common-source amplifier unit is used to amplify the differential comparison result signal and output an amplified output signal; The output shaping unit is used to shape the amplified output signal and output a full-scale digital over-temperature protection signal. The hysteresis feedback unit is used to actively lower or release the output reference voltage of the reference voltage generation unit according to the level state of the over-temperature protection signal, so as to form a hysteresis temperature difference between the over-temperature trigger threshold and the recovery threshold.

[0050] like Figure 1 As shown, the bias current mirror unit consists of two cascaded stages: an NMOS current mirror composed of a first NMOS transistor N4 and a second NMOS transistor N5, and a PMOS current mirror composed of a first PMOS transistor P5, a second PMOS transistor P0, a third PMOS transistor P1, and a fourth PMOS transistor P2. The NMOS current mirror uses the first NMOS transistor N4 as the reference transistor, and the PMOS current mirror uses the first PMOS transistor P5 as the reference transistor. The two-stage cascaded structure accurately replicates and distributes the high-precision reference current from the bias current input terminal IB to the three functional branches.

[0051] In terms of specific connections, the gate and drain of the first NMOS transistor N4 are shorted together and connected to the bias current input terminal IB, forming a gate-drain shorted diode connection, serving as the reference transistor for the NMOS current mirror. The gate of the second NMOS transistor N5 is connected to the gate of the first NMOS transistor N4, sharing the same bias gate voltage. The sources of both the first NMOS transistor N4 and the second NMOS transistor N5 are connected to the analog ground terminal AGND. The drain of the second NMOS transistor N5 is connected to the drain of the first PMOS transistor P5, and the gate and drain of the first PMOS transistor P5 are shorted together, forming a gate-drain shorted diode connection, serving as the reference transistor for the PMOS current mirror. The source of the first PMOS transistor P5 is connected to the power supply terminal AVDD. The gate-drain shorted node of the first PMOS transistor P5 is also connected to the gates of the second PMOS transistor P0, the third PMOS transistor P1, and the fourth PMOS transistor P2, providing a unified bias gate voltage for the three mirror transistors. The sources of the second PMOS transistor P0, the third PMOS transistor P1, and the fourth PMOS transistor P2 are all connected to the power supply terminal AVDD. The drain of the second PMOS transistor P0 provides bias current to the temperature sensing unit, the drain of the third PMOS transistor P1 provides tail current to the differential comparator unit, and the drain of the fourth PMOS transistor P2 provides active load current to the common-source amplifier unit.

[0052] In terms of working principle, a high-precision bias current IB provided by an external bandgap reference source flows into the bias current input terminal. This current, after passing through the first NMOS transistor N4, establishes a stable gate-source voltage. Then, it is mirrored by the second NMOS transistor N5 and drives the first PMOS transistor P5, establishing a stable bias potential at the drain node of P5. This provides a unified bias gate voltage for the three PMOS mirror transistors P0, P1, and P2. The three PMOS mirror transistors precisely replicate and distribute the current to their respective functional branches according to their width-to-length ratios, achieving stable bias current distribution. The two-stage cascaded current mirror structure (NMOS mirror + PMOS mirror) improves the mirroring accuracy. The bias current of each branch has good suppression capability against fluctuations in the power supply voltage AVDD, ensuring the stability of the operating point of each functional unit, thereby ensuring that the accuracy of the over-temperature protection threshold is not affected by power supply fluctuations.

[0053] The two-stage cascaded current mirror structure, through the coordinated operation of the NMOS mirror reference transistor N4 and the PMOS mirror reference transistor P5, achieves high-precision current replication and distribution from the bias current input terminal IB to each functional branch. The bias current of each branch is stable and unaffected by fluctuations in the power supply voltage AVDD, providing a reliable operating foundation for the subsequent temperature sensing unit, differential comparator unit, and common-source amplifier unit, and is the fundamental guarantee for the stable operation of the entire over-temperature protection circuit.

[0054] Reference Figure 1 The temperature sensing unit is composed of a PNP transistor Q0, which is connected in a diode configuration.

[0055] In terms of specific connections, the collector and base of the PNP transistor Q0 are shorted together and connected to the analog ground AGND. The emitter of Q0 is connected to the drain of the second PMOS transistor P0. This node also serves as the sensing voltage node (VS node) and is connected to the gate of the fifth PMOS transistor P3 in the differential comparator unit. The drain current of P0 (approximately 30μA) flows from AVDD through P0 to the emitter of Q0, and then through the emitter of Q0 to AGND.

[0056] In terms of operating principle, when the PNP transistor Q0 is connected in diode configuration, its emitter-junction voltage VEB decreases with increasing temperature. The equivalent impedance of Q0 (emitter to collector / base) exhibits a negative temperature coefficient, approximately -0.25% / ℃ (about 6kΩ at room temperature, decreasing to about 1.2kΩ at the over-temperature trigger point of 171.4℃). Therefore, as the chip junction temperature rises, the voltage drop across the Q0 emitter junction caused by the P0 drain current (approximately 30μA) (i.e., the sensing voltage VS, at the P0 drain node) decreases monotonically: approximately 1.1V at cold state (room temperature), decreasing to approximately 0.04V at the over-temperature trigger point (171.4℃). This sensing voltage is fed to the gate of P3 in the differential comparator unit via the VS node as the sensing-side signal for over-temperature detection.

[0057] The negative temperature coefficient of the PNP transistor Q0 is a physical characteristic determined by the band structure of the semiconductor material and is not affected by batch deviations in the manufacturing process. Therefore, by utilizing the negative temperature coefficient of the equivalent impedance of Q0 to achieve temperature-voltage conversion, the consistency of threshold values ​​between batches can be guaranteed without external adjustment, fundamentally solving the problem of large batch differences caused by relying on NTC thermistors in the existing technology.

[0058] like Figure 1 As shown, the reference voltage generation unit consists of a voltage divider network formed by the first resistor R1 and the second resistor R2 connected in series.

[0059] In terms of specific connections, the upper end of the first resistor R1 is connected to the temperature-dependent current input terminal IPTAT. This node is also connected to the gate of the sixth PMOS transistor P4 in the differential comparator unit and one end of the second filter capacitor C0 (the other end of C0 is connected to AGND). The lower end of the first resistor R1 is connected in parallel with the upper end of the second resistor R2 to form a voltage divider node. This voltage divider node is also connected to the drain of the sixth NMOS transistor N3 in the hysteresis feedback unit. The lower end of the second resistor R2 is connected to the analog ground terminal AGND.

[0060] In its working principle, the PTAT current (proportional to absolute temperature) from the bandgap reference source flows into the IPTAT terminal, sequentially through the first resistor R1 and the second resistor R2, generating a voltage at the IPTAT node (upper end of R1) that monotonically increases with temperature. This voltage serves as the gate bias for the right-side input transistor P4 of the differential comparator unit. A reference voltage VREF is generated at the voltage divider node, which is regulated by the hysteresis feedback unit N3. Since IPTAT increases linearly with temperature (temperature coefficient approximately +100nA / ℃), the gate node voltage of P4 also monotonically increases with temperature, forming a reference-side signal with a positive temperature coefficient: approximately 0.3V at cold state (room temperature), rising to approximately 0.65V at the over-temperature trigger point (171.4℃). This positive temperature coefficient reference signal and the negative temperature coefficient sensing voltage (VS node) output by the temperature sensing unit form a dual temperature coefficient structure that changes in opposite directions, jointly determining the over-temperature trigger threshold.

[0061] In terms of technical effectiveness, the reference voltage generation unit utilizes the PTAT current flowing through the R1+R2 voltage divider network to generate a positive temperature coefficient reference voltage. This, together with the negative temperature coefficient sensing voltage of the temperature sensing unit, forms a dual temperature coefficient structure that changes in opposite directions. This allows the over-temperature trigger threshold to be naturally determined by the circuit parameters, eliminating the need for process calibration and fundamentally eliminating the problems of high manufacturing costs and poor batch consistency caused by reliance on calibration processes in existing technologies. The intermediate node of the voltage divider between the first resistor R1 and the second resistor R2 also serves as the point of application for the hysteresis feedback unit, providing a structural foundation for the subsequent implementation of the active hysteresis mechanism.

[0062] like Figure 1 As shown, the differential comparator unit consists of a differential input pair formed by the fifth PMOS transistor P3 and the sixth PMOS transistor P4, and an active current mirror load formed by the third NMOS transistor N0 and the fourth NMOS transistor N1. The fifth PMOS transistor P3 is the sensing-side input transistor, and the sixth PMOS transistor P4 is the reference-side input transistor; the third NMOS transistor N0 is the active load reference transistor, and the fourth NMOS transistor N1 is the active load mirror transistor.

[0063] In terms of specific connections, the sources of the fifth PMOS transistor P3 and the sixth PMOS transistor P4 are connected to the drain of the third PMOS transistor P1 (tail current source node); the gate of P3 is connected to the sensing voltage node (VS node, i.e., Q0 emitter / P0 drain), and the drain of P3 is connected to the drain of the third NMOS transistor N0; the gate of P4 is connected to the temperature-dependent current input terminal IPTAT (i.e., the upper node of R1), and the drain of P4 is connected to the drain of the fourth NMOS transistor N1. The common node of the drains of P4 and N1 also serves as the differential comparator output node, connected to the gate of the fifth NMOS transistor N2 in the common-source amplifier unit. The gate and drain of the third NMOS transistor N0 are shorted and connected to the gate of the fourth NMOS transistor N1; the sources of both N0 and N1 are connected to the analog ground AGND.

[0064] In terms of operation, the tail current provided by P1 is distributed between P3 and P4. Under normal operating conditions (temperature below the trigger threshold), the voltage of the VS node (P3 gate) is higher than the voltage of the IPTAT node (P4 gate). The conduction capability of P3 is weaker than that of P4, the drain current of P4 is greater than the drain current of P3, the drain voltage of N1 (differential comparator output node) is low, the gate voltage of N2 is low, N2 is cut off or weakly conducted, and the DOTP node remains at a high level. When the temperature rises to the trigger threshold (171.4℃), the VS node drops sharply to about 0.04V, the IPTAT node rises to about 0.65V, and the differential pair flips: the conduction capability of P3 increases, the conduction capability of P4 decreases, the drain voltage of N1 increases, the gate voltage of N2 increases, N2 conducts, the DOTP node is pulled down to a low level, triggering the subsequent output shaping unit to flip, the OTP output is low, and the over-temperature protection trigger is completed. The active current mirror load consisting of N0 / N1 increases the equivalent output impedance of the differential pair, increases the differential comparison gain, makes the switching process cleaner and faster, and reduces oscillations and glitches during the switching process.

[0065] like Figure 1 As shown, in some embodiments, the over-temperature protection circuit further includes a second filter capacitor (C0); one end of the second filter capacitor C0 is connected to the temperature-dependent current input terminal IPTAT, and the other end is connected to the analog ground terminal AGND.

[0066] In terms of specific connections, the second filter capacitor C0 is connected in parallel between the IPTAT input node and the analog ground AGND, and is connected to the same node along with the upper end of the first resistor R1 and the gate of the sixth PMOS transistor P4. The first filter capacitor C1 is connected in parallel between the common-source amplifier output node (DOTP node) and the analog ground AGND, and is connected to the DOTP node along with the input of the Schmitt trigger SMITT. The second filter capacitor C0 and the first filter capacitor C1 are independent of each other in the circuit, providing filtering protection for critical nodes on the input side and the output side, respectively. The typical capacitance of both is approximately 2pF.

[0067] In terms of operating principle, the IPTAT node serves as the gate bias source for the right-side input transistor P4 of the differential comparator unit. If high-frequency noise or glitches exist at this node, they will directly affect the gate voltage of P4, causing the differential comparator unit to malfunction and triggering a false over-temperature protection action. The second filter capacitor C0 is connected in parallel between the IPTAT node and AGND, forming a low-pass filter network together with the output impedance of the IPTAT current source. This effectively filters out high-frequency noise components on the IPTAT node, ensuring a pure and stable gate input signal for P4 and preventing the differential comparator unit from malfunctioning due to noise interference. Simultaneously, the first filter capacitor C1 is connected in parallel between the DOTP node and AGND, performing integral filtering on the common-source amplifier output node. This smooths the voltage change rate (dv / dt) at the moment of switching, limiting dv / dt to less than 50V / μs, suppressing the triggering conditions of on-chip parasitic thyristors, and reducing the risk of on-chip latch-up. The second filter capacitor C0 works in conjunction with the first filter capacitor C1 to implement dual high-frequency noise suppression at key nodes from the differential comparator input side and the common-source amplifier output side, respectively, thereby improving the anti-interference capability and operational reliability of the over-temperature protection circuit in complex electromagnetic environments.

[0068] The sensed voltage and reference voltage are differentially compared using a differential comparator unit (P3 / P4 differential pair and N0 / N1 active load). Utilizing the inherent negative temperature coefficient characteristic of the PNP transistor (Q0) (collector and base shorted to AGND, emitter connected to P0 drain, temperature coefficient approximately -0.25% / ℃, room temperature approximately 6kΩ, over-temperature point approximately 1.2kΩ), the junction temperature is converted into a sensed voltage. A positive temperature coefficient reference signal is generated by the PTAT current flowing through a series voltage divider network of the first resistor (R1) and the second resistor (R2). The difference in temperature coefficients between the two naturally determines the over-temperature trigger threshold, eliminating the need for process calibration and ensuring good batch consistency. This fundamentally eliminates the defects of existing technologies that rely on large resistance tolerances and batch variations of NTC thermistors, reducing manufacturing costs.

[0069] like Figure 1As shown, the common-source amplifier unit consists of a fourth PMOS transistor P2 (active load transistor) and a fifth NMOS transistor N2 (common-source amplifier transistor). The source of the fourth PMOS transistor P2 is connected to the power supply terminal AVDD, and its gate is connected to the gate-drain short-circuit node (bias current mirror reference node) of the first PMOS transistor P5. Its drain is connected to the drain of the fifth NMOS transistor N2, forming the common-source amplifier output node DOTP. The common-source amplifier output node (DOTP node) is connected to the input terminal of the Schmitt trigger SMITT in the output shaping unit, and one end of the first filter capacitor C1 (the other end of C1 is connected to AGND). The gate of the fifth NMOS transistor N2 is connected to the differential comparator output node VOUT, and its source is connected to the analog ground terminal AGND. The fifth NMOS transistor N2 operates in a common-source topology, and its voltage gain is approximately -gm×Rd (where gm is the transconductance of N2 and Rd is the output impedance of P2), which can amplify the small amplitude signal of the differential comparator output node VOUT to a signal amplitude sufficient to reliably drive the subsequent Schmitt trigger SMITT. The fourth PMOS transistor P2 is uniformly controlled by the bias current mirror, and its gate bias voltage shares the same reference with P0 and P1, ensuring that the active load current is stable and is not affected by power supply voltage AVDD fluctuations.

[0070] In terms of working principle, the differential comparison result (drain voltage of N1) output by the differential comparator unit is input through the gate of N2. N2 and P2 (active load) form a common-source amplifier stage, converting the differential comparison result into a single-ended output signal (DOTP node). Under normal operating conditions, the drain voltage of N1 is low, N2 is cut off or weakly conducting, and P2, as an active load, pulls the DOTP node up to a high level. During over-temperature triggering, the drain voltage of N1 increases, N2 is deeply conducting, and the DOTP node is strongly pulled down to a low level by N2, achieving inverting amplification. The first filter capacitor C1 (typical capacitance of about 2pF) is connected between the DOTP node and AGND, performing integral filtering on the DOTP node to smooth the voltage change rate (dv / dt) at the moment of switching, limiting dv / dt to less than 50V / μs, effectively preventing false triggering caused by high-frequency noise, and suppressing the triggering conditions of on-chip parasitic thyristors, reducing the risk of on-chip latch-up.

[0071] In terms of technical effectiveness, the first filter capacitor (C1, typically 2pF) in the common-source amplifier unit is connected between the common-source amplifier output node (DOTP node) and the analog ground terminal, which smooths the dv / dt at the moment of switching and limits dv / dt to less than 50V / μs, effectively preventing the on-chip parasitic thyristor triggering and reducing the risk of latch-up; the second filter capacitor (C0, typically 2pF) is connected between the IPTAT node and the analog ground terminal, which filters out high-frequency noise of the IPTAT node and prevents the differential comparator unit from being falsely triggered, thus overcoming the deficiency of the lack of on-chip effective voltage swing limiting measures in the prior art.

[0072] like Figure 1 As shown, the hysteresis feedback unit is composed of the sixth NMOS transistor N3.

[0073] In terms of specific connections, the gate of the sixth NMOS transistor N3 is connected to the over-temperature protection signal output terminal OTP, the drain is connected to the voltage divider node between the lower end of the first resistor R1 and the upper end of the second resistor R2, and the source is connected to the analog ground terminal AGND. The gate of the sixth NMOS transistor N3 is directly driven by the signal at the OTP terminal, forming an active feedback closed loop from the output terminal to the reference voltage generation unit.

[0074] In terms of working principle, the hysteresis feedback unit actively adjusts the voltage divider node of the reference voltage generation unit using the output signal of the OTP terminal, forming a positive feedback hysteresis mechanism. The working process of the hysteresis feedback unit is divided into the following two stages.

[0075] Under normal operating conditions (temperature below the trigger threshold), the OTP terminal outputs a low level, the gate of the sixth NMOS transistor N3 is low, N3 is cut off, and there is no effect on the R1 / R2 voltage divider network. The reference voltage VREF = IPTAT × (R1 + R2) maintains the normal reference voltage value, and the over-temperature trigger threshold is thus determined. During the N3 cutoff period, the series voltage divider network of the first resistor R1 and the second resistor R2 operates normally. The PTAT current IPTAT establishes a positive temperature coefficient reference voltage VREF at the upper node of R1, which, together with the sensing voltage VS, acts on the differential comparator unit to realize the temperature monitoring function.

[0076] When the temperature rises to the over-temperature trigger threshold (171.4℃), the differential comparator flips. After common-source amplification and output shaping, the OTP terminal outputs a high level, and the gate of the sixth NMOS transistor N3 becomes high, turning on N3 and pulling the intermediate node of the voltage divider between the lower end of R1 and the upper end of R2 to the analog ground AGND. At this time, R2 is partially short-circuited by the on-resistance of N3, reducing the equivalent voltage drop across R2. The reference voltage VREF actively decreases to VREF' (depending on the ratio of the on-resistance of N3 to R2). The active decrease in the reference voltage changes the flip threshold of the differential comparator: the sensing voltage VS needs to drop to a lower value (i.e., the temperature needs to drop to a lower value) for VS to be higher than VREF' again, thus causing the differential comparator to flip in reverse, the OTP terminal returns to a low level, N3 is turned off, VREF returns to its original value, and the circuit exits the protection state.

[0077] As the temperature begins to drop from the over-temperature trigger threshold (171.4℃), the IPTAT current decreases with the decrease in temperature, and VREF' also decreases accordingly; at the same time, the sensing voltage VS increases with the decrease in temperature. When the temperature drops to the temperature recovery threshold (153.4℃), VS rises again to a level higher than the current VREF', the differential comparator flips in reverse, the OTP terminal outputs a low level, N3 is cut off, VREF returns to its original value, the circuit completely exits the protection state, and power is automatically restored.

[0078] The aforementioned active hysteresis feedback mechanism creates a hysteresis temperature difference of approximately 18°C ​​between the over-temperature trigger threshold (171.4°C) and the temperature recovery threshold (153.4°C), such as... Figure 2 As shown. Figure 2 The hysteresis characteristic curve clearly shows the dual threshold characteristics of the over-temperature protection signal OTP as temperature increases (triggered flip-over) and as temperature decreases (recovery flip-over). The two vertical dashed lines mark the trigger threshold of 171.4℃ and the recovery threshold of 153.4℃, respectively, and the horizontal dashed line represents the flip-over threshold determination benchmark. The hysteresis temperature difference range of approximately 18℃ is clearly visible. This active hysteresis mechanism actively adjusts the threshold from the source of the reference voltage generation. Compared with the passive hysteresis scheme in the prior art that relies on an external positive feedback resistor network, it has the following advantages: First, the hysteresis temperature difference is accurately determined by the circuit parameters (the resistance ratio of R1 and R2 and the on-resistance of N3), resulting in good stability; second, active feedback can effectively suppress oscillations near the threshold and completely eliminate the hiccup phenomenon; third, no additional hysteresis comparator module is required, resulting in a small circuit area and low power consumption.

[0079] By connecting the gate of the sixth NMOS transistor (N3) in the hysteresis feedback unit to the OTP terminal, N3 is turned on and pulls down the voltage divider node when the OTP output is high, and N3 is turned off when the OTP output is low, and the voltage of the voltage divider node increases, forming active hysteresis feedback. In conjunction with the dual threshold characteristics of the Schmitt trigger (SMITT), a stable hysteresis temperature difference of about 18°C ​​is formed between the over-temperature trigger threshold (171.4°C) and the temperature recovery threshold (153.4°C), which effectively prevents the frequent switching (hiccups) phenomenon near the protection point and completely overcomes the defects of the passive hysteresis scheme in the prior art that relies on an independent positive feedback module and cannot actively suppress oscillation from the source of the sensing node.

[0080] like Figure 1As shown, the output shaping unit consists of a Schmitt trigger (SMITT), a first inverter (I0), and a second inverter (I1) connected in series. The input of the Schmitt trigger (SMITT) is connected to the common-source amplifier output node (DOTP), and its output is connected to the input of the first inverter (I0). The output of the first inverter (I0) is connected to the input of the second inverter (I1). The output of the second inverter (I1) serves as the over-temperature protection signal output terminal (OTP), outputting a full-scale digital over-temperature protection signal to the outside. The power supply terminals of the Schmitt trigger (SMITT), the first inverter (I0), and the second inverter (I1) are all connected to the power supply terminal (AVDD), and their ground terminals are all connected to the analog ground terminal (AGND).

[0081] In terms of working principle, although the signal at the common-source amplifier output node DOTP is amplified, it may still contain interference signals introduced by thermal noise, substrate noise, or power supply glitches during the switching process. If it directly drives the subsequent digital logic circuit, it may cause malfunctions. The Schmitt trigger (SMITT) utilizes its dual-threshold characteristic (hysteresis window between the upper threshold VT+ and the lower threshold VT-) to shape the analog signal at the DOTP node, effectively eliminating glitches and oscillations during the switching process and outputting a clean digital signal. After the first inverter I0 performs the first stage of inversion buffering, and then the second inverter I1 performs the second stage of inversion buffering, the final digital over-temperature protection signal with the same polarity as the protection state and full amplitude (0 to AVDD) is output at the OTP terminal. The cascaded buffer structure of the two-stage inverters improves the driving capability of the OTP terminal, enabling it to directly drive the gates of subsequent logic circuits or power devices without the need for an additional drive buffer stage.

[0082] When over-temperature protection is triggered (chip junction temperature exceeds the trigger threshold), the DOTP node is low, and after being shaped by SMITT, it outputs a high level. After being inverted by I0, it outputs a low level, and after being inverted by I1, the OTP terminal outputs a high level, indicating the over-temperature protection status. Under normal operating conditions (chip junction temperature is below the recovery threshold), the DOTP node is high, and after processing by the above signal link, the OTP terminal outputs a low level, indicating the normal operating state. It should be understood that the polarity definition of the OTP signal can be configured by adjusting the number of inverter stages according to specific application requirements. This embodiment uses a two-stage inverter as an example for illustration and does not constitute a limitation on the scope of protection of this application.

[0083] In one embodiment of this application, the hysteresis temperature difference formed by the hysteresis feedback unit is in the range of 10°C to 20°C. The specific value of the hysteresis temperature difference is determined by the resistance ratio of the first resistor R1 and the second resistor R2, as well as the on-resistance of the sixth NMOS transistor N3. It can be flexibly designed within the range of 10°C to 20°C by adjusting the above parameters.

[0084] When the hysteresis temperature difference is designed to be 10℃, the pull-down of the intermediate node of the R1 / R2 voltage divider after the sixth NMOS transistor N3 is turned on is relatively small, the active reduction of the reference voltage VREF is small, and the temperature interval between the recovery threshold and the trigger threshold is approximately 10℃. This parameter is suitable for applications that require high recovery speed and allow for rapid power restoration after trigger protection, such as consumer electronics power management chips that need to recover quickly after a short period of overheating.

[0085] When the hysteresis temperature difference is designed to be approximately 18°C ​​(a typical simulation value in this application embodiment, with an over-temperature trigger threshold of 171.4°C and a temperature recovery threshold of 153.4°C), after the sixth NMOS transistor N3 is turned on, it pulls down the intermediate node of the R1 / R2 voltage divider to a moderate level. The reference voltage VREF is actively reduced by a moderate amount, forming a temperature gap of approximately 18°C ​​between the recovery threshold and the trigger threshold. Figure 2 As shown in the figure. This parameter strikes a good balance between preventing hiccups and recovery speed, making it suitable for high-reliability applications such as automotive power management chips.

[0086] When the hysteresis temperature difference is designed to be 20℃, the pull-down of the intermediate node of the R1 / R2 voltage divider is maximized after the sixth NMOS transistor N3 is turned on, resulting in the largest active reduction of the reference voltage VREF. The temperature interval between the recovery threshold and the trigger threshold is approximately 20℃. This parameter is suitable for applications with large temperature fluctuations in the operating environment that require a larger hysteresis margin to completely prevent hiccups, such as industrial power modules or automotive DC-DC converter chips with extremely high power density.

[0087] In summary, the hysteresis temperature range of 10℃ to 20℃ covers the over-temperature protection hysteresis characteristics required by various applications from consumer electronics to automotive and industrial applications. This range can be flexibly configured by adjusting the resistance ratio of R1 and R2 and the parameters of the N3 device without modifying the circuit topology, providing good design flexibility.

[0088] like Figure 2 The figure shows the temperature-voltage scan simulation waveform of the over-temperature protection circuit provided in this embodiment. The simulation performs hysteresis scan on a temperature range of 130°C to 190°C. The horizontal axis is the temperature (°C), and the vertical axis is the output voltage (V) of the over-temperature protection signal OTP (0 to AVDD at full scale, 0 to 5V). Figure 2 A closed curve with dual threshold hysteresis can be seen: in the direction of temperature increase (scanning from 130℃ to 190℃), the OTP output signal flips at 171.4℃, rapidly dropping from high level (5V, normal operating state) to low level (0V, over-temperature protection state), corresponding to the over-temperature trigger threshold; in the direction of temperature decrease (scanning from 190℃ to 130℃), the OTP output signal flips in the opposite direction at 153.4℃, rapidly rising from low level (0V) to high level (5V), corresponding to the temperature recovery threshold. Figure 2 The two vertical dashed lines mark the trigger threshold of 171.4℃ and the recovery threshold of 153.4℃, respectively. The approximately 18℃ hysteresis temperature difference between the two vertical dashed lines is clearly visible, explicitly verifying the technical effect of the synergistic effect of the hysteresis feedback mechanism and Schmitt trigger in this application. The simulation results show that the over-temperature protection circuit of this application has stable and clear dual-threshold hysteresis characteristics between 171.4℃ and 153.4℃, with a clean and oscillating switching process and a hysteresis temperature difference of approximately 18℃, completely eliminating the hiccuping phenomenon.

[0089] Combination Figure 1 This embodiment describes in detail the complete working process of the over-temperature protection circuit under typical working scenarios, including the cold power-on stage, the normal working stage, the over-temperature triggering stage, and the temperature recovery stage.

[0090] (a) Cold power-on stage At the moment of cold power-on, P5's gate-drain shorting establishes a stable PMOS bias gate voltage. P0, P1, and P2, biased by the gate voltage provided by P5, all conduct, sending AVDD to their respective branches. The bias reference current IB (typically approximately 30μA) flows into the drain of N4. N4's gate-drain shorting establishes a stable gate-source voltage (approximately 0.9V), which simultaneously biases N5. The drain of N5 is connected to the drain of P5, forming an NMOS current mirror. The drain current of P5 is determined by the mirror image of N5. The drain current of P0 drives the PNP transistor Q0: Q0's collector and base are shorted to AGND, and its emitter is connected to the drain of P0 (VS node). The drain current of P0 (approximately 30μA) flows through the emitter junction of Q0, establishing a sensing voltage of approximately 1.1V at the VS node. The drain of P1 is connected to the common terminal of the P3 / P4 differential pair source, providing tail current for the differential comparator unit. The PTAT current IPTAT (approximately 30μA at room temperature) flows into the upper end of R1 (also connected to the gate of P4), and through R1 to R2, establishing a reference voltage at the voltage divider node; at room temperature, the voltage drop across R2 is approximately 0.3V, and the voltage divider node (i.e., the gate node of P4) is approximately 0.3V. In the differential comparator unit, the gate of P3 is connected to the VS node (approximately 1.1V), and the gate of P4 is connected to the IPTAT / R1 upper node (approximately 0.3V + R1 voltage drop). The differential pair output forms a differential comparator output at the drain of N1 through the active loads N0 / N1; the gate of the N2 common-source amplifier is connected to the drain of N1, and the drain of N2 is shared with the drain of P2 (DOTP node). After being filtered by C1, it is sent to SMITT. SMITT→I0→I1 are shaped in series, and the output OTP of I1 is high (AVDD), and the system is in normal operation (non-protection) state. C0 (connected to the IPTAT node and AGND, typically 2pF) filters out high-frequency noise from the IPTAT node, ensuring a clean P4 gate input; C1 (connected to the DOTP node and AGND, typically 2pF) smooths the dv / dt during the DOTP node flip, reducing the risk of latch-up.

[0091] (ii) Normal operating phase (temperature rises but does not reach the trigger threshold) As the chip's operating temperature increases, the emitter junction characteristics of Q0 change with temperature, and the VS node sensing voltage decreases monotonically with increasing temperature. Simultaneously, the PTAT current IPTAT increases linearly with increasing temperature (temperature coefficient approximately +100nA / ℃), and the voltage at the P4 gate node (IPTAT flows through the upper end of R1) increases accordingly. In the differential comparator unit, the voltage at the P3 gate (connected to the VS node) decreases, and the voltage at the P4 gate (connected to the IPTAT node) increases, causing a change in the differential pair output. However, as long as the temperature has not reached the over-temperature trigger threshold, the differential comparator output remains in a cutoff or weakly conducting state for N2, the DOTP node remains high, and after shaping by SMITT→I0→I1, OTP continuously outputs a high level, maintaining the system's normal operating state. With the gate of N3 connected to OTP (high level), N3 conducts, pulling down the voltage divider node. This is the operating state of the hysteresis feedback unit under normal operating conditions, ensuring the reference voltage is slightly lower than the voltage divider value without N3, providing a parameter basis for precise setting of the trigger threshold.

[0092] (iii) Over-temperature triggering stage (temperature rises to the trigger threshold of 171.4℃) When the chip junction temperature continues to rise to the over-temperature trigger threshold (171.4℃), the VS node sensing voltage drops sharply to about 0.04V, IPTAT rises to about 45μA, and the P4 gate node voltage rises accordingly. In the differential comparator unit, the differential signal between P3 (gate about 0.04V) and P4 (gate about 0.65V) exceeds the differential pair switching threshold, the N1 drain (differential comparator output node) voltage flips, the N2 gate voltage rises, the N2 conduction capability is enhanced, and the DOTP node voltage is pulled down to a low level by N2; C1 (2pF) performs integral filtering on the DOTP node, limiting the dv / dt at the moment of switching to less than 50V / μs, effectively preventing on-chip parasitic thyristor triggering and reducing the risk of latch-up. The low-level signal at the DOTP node is shaped by a series connection of SMITT→I0→I1: SMITT utilizes its double threshold characteristic to eliminate glitches and oscillations during the switching process, outputting a clean digital signal; I0 and I1 are inverted sequentially, and the I1 output OTP flips to a low level (AGND), completing the over-temperature protection trigger action and issuing an over-temperature shutdown command to the gate of the subsequent logic circuit or power device. After OTP flips to a low level, the gate of N3 (connected to OTP) also becomes low, N3 is cut off, the voltage divider node is no longer pulled down by N3, the voltage of the voltage divider node increases, causing the reference voltage to increase, forming an active hysteresis feedback, ensuring that OTP remains in a low-level protection state until the temperature drops sufficiently, preventing hiccups.

[0093] (iv) Temperature recovery phase (temperature drops from 171.4℃ to the recovery threshold of 153.4℃) After the over-temperature protection is triggered, the power output is shut off, the chip stops heating, and the junction temperature begins to drop. As the temperature decreases, the VS node sensing voltage slowly rises, the IPTAT current decreases synchronously, and the P4 gate node voltage decreases accordingly. Since OTP is at a low level, N3 is off, and the voltage divider node maintains a high reference voltage (without N3 pull-down). The differential comparator unit needs to wait for a greater temperature drop, a higher VS node rise, and a greater P4 gate node drop before the differential comparator output can flip in reverse. This is the source of the approximately 18°C ​​hysteresis temperature difference. When the temperature drops to the temperature recovery threshold (153.4°C), the differential comparator output flips in reverse, N2 is off, the DOTP node rises to a high level, and after being shaped by SMITT→I0→I1, the I1 output OTP flips back to a high level (AVDD), the system exits the protection state, and automatically restores power supply. After OTP flips back to a high level, N3 turns on again, the voltage divider node is pulled down again, restoring the reference voltage setting under normal operating conditions, preparing for the next over-temperature trigger. The entire cooling process requires no human intervention. C1 absorbs and flips the instantaneous charge, ensuring a smooth dv / dt ratio and naturally forming a hysteresis temperature difference of about 18°C, thus eliminating thermal oscillation.

[0094] The complete working process described above—cold power-on → normal operation → over-temperature triggering → temperature recovery—creates a stable hysteresis temperature difference of approximately 18°C ​​between the over-temperature triggering threshold (171.4°C) and the temperature recovery threshold (153.4°C). Figure 2 As shown. Throughout the entire operation, the functional units work together: the bias current mirror unit provides a stable bias base, the temperature sensing unit and the reference voltage generation unit form a dual temperature coefficient sensing structure, the differential comparison unit accurately compares the two signals, the common-source amplifier unit converts the differential result into a single-ended signal, the hysteresis feedback unit actively forms a stable hysteresis temperature difference, and the output shaping unit ensures the quality of the output signal, together achieving a highly reliable over-temperature protection function.

[0095] This embodiment integrates the over-temperature protection circuit into the power management chip and provides high-precision, temperature- and power-voltage- and temperature-independent dual-path reference currents (bias reference current IB and PTAT current IPTAT) through a bandgap reference source. The two outputs come from the same reference core and have good correlation, further improving the accuracy and stability of the over-temperature protection threshold and meeting the high reliability requirements of automotive-grade applications. The vehicle integrates this chip into the electronic control unit. When the junction temperature exceeds the trigger threshold, the power output is shut down, and when it drops below the recovery threshold, the power supply is automatically restored, ensuring the safe and reliable operation of the vehicle power system.

[0096] Example 2 This embodiment provides a power management chip that integrates the over-temperature protection circuit described in Embodiment 1, and also includes a bandgap reference source. The bandgap reference source is the core analog reference module in the power management chip. Utilizing the bandgap voltage characteristics of a semiconductor PN junction, it generates a high-precision reference voltage or reference current output that is highly independent of process variation (PVT), power supply voltage variations, and temperature variations by compensating for the base-emitter voltage VBE (which has a negative temperature coefficient) with the PTAT voltage (which has a positive temperature coefficient).

[0097] In this embodiment, the bandgap reference source simultaneously outputs two reference signals: the first is a high-precision bias reference current IB, which has an extremely low temperature coefficient and remains stable across the entire temperature range; the second is a PTAT current IPTAT, whose current value is strictly proportional to the absolute temperature, has a positive temperature coefficient, and is precisely determined by the PTAT current generation circuit inside the bandgap reference source. Both outputs originate from the same bandgap reference core and have a high correlation, effectively suppressing the influence of process angle deviations (Fast-Fast, Slow-Slow, etc.) on the ratio between the two outputs, thereby ensuring the consistency of the over-temperature trigger threshold across different process batches.

[0098] In terms of specific connections, the bandgap reference source has a first output terminal and a second output terminal: the first output terminal of the bandgap reference source is connected to the bias current input terminal IB, providing a high-precision reference current to the first NMOS transistor N4 in the bias current mirror unit. This reference current has an extremely low temperature coefficient, ensuring that the bias current of each functional branch is stable and does not drift with changes in chip temperature, thereby ensuring the stability of the operating point of the differential comparator unit; the second output terminal of the bandgap reference source is connected to the temperature-dependent current input terminal IPTAT, providing a PTAT current to the upper end of the first resistor R1 in the reference voltage generation unit. This PTAT current is strictly proportional to the absolute temperature, and its temperature coefficient is precisely determined by the internal circuit parameters of the bandgap reference source, ensuring that the reference voltage VREF has an accurate positive temperature coefficient, thereby ensuring the accuracy of the over-temperature trigger threshold. In some embodiments, the bandgap reference source can also integrate an enable control terminal, which can control the power-on / power-off of the entire over-temperature protection circuit through an external enable signal. When the chip is in standby or low-power mode, the bandgap reference source is turned off to reduce static power consumption, and it is re-enabled when over-temperature protection is required, realizing flexible configuration of power consumption and protection function.

[0099] The bandgap reference source simultaneously provides high-precision bias reference current IB and PTAT current IPTAT. Both outputs originate from the same reference core, exhibiting excellent correlation and effectively suppressing the impact of process deviations and temperature variations on the over-temperature protection threshold. Compared to solutions using external resistor voltage dividers or independent reference voltage sources, the bandgap reference source solution offers higher accuracy and better temperature stability, meeting the stringent over-temperature protection accuracy requirements of automotive-grade (AEC-Q100) power management chips. The characteristic that both reference outputs originate from the same reference core also ensures a high correlation between IB and IPTAT, further suppressing the impact of process corner deviations on the over-temperature trigger threshold and improving batch consistency. In one embodiment of this application, the typical output reference voltage of the bandgap reference source is approximately 1.2V (corresponding to the bandgap voltage of silicon), the typical IB value is approximately 30μA, the typical IPTAT value is approximately 30μA at room temperature (27°C) and approximately 45μA at high temperature (171.4°C over-temperature trigger point), and the PTAT temperature coefficient of IPTAT is approximately +100nA / °C. These parameters, together with the resistance ratio of R1 and R2, determine the over-temperature trigger threshold of 171.4°C and the temperature recovery threshold of 153.4°C, with a hysteresis temperature difference of approximately 18°C. It should be understood that the above typical parameter values ​​are merely illustrative; in practical applications, the resistance ratio of R1 and R2 can be adjusted according to the design requirements of the target over-temperature trigger threshold, and this does not constitute a limitation on the scope of protection of this application.

[0100] The power management chip provided in this application can be applied to, but is not limited to, the following applications: battery protection ICs in vehicle battery management systems (BMS), vehicle DC-DC converter control chips, on-board charger (OBC) power management chips, electric power steering (EPS) motor drive chips, and other applications requiring high-reliability over-temperature protection, as well as general power management applications such as industrial power modules and consumer electronics chargers.

[0101] Example 3 This embodiment provides a vehicle that includes the power management chip described in Embodiment 2. The power management chip is integrated into the vehicle's electronic control unit (ECU). The over-temperature protection signal output terminal OTP is connected to the power control terminal of the ECU. It is used to shut down the power output when the junction temperature of the power management chip exceeds the over-temperature trigger threshold (171.4°C) and automatically restore power supply when the junction temperature drops below the temperature recovery threshold (153.4°C).

[0102] In vehicle applications, the power control terminal of the electronic control unit receives the OTP signal and executes corresponding power control actions based on the OTP signal's level: when the OTP terminal outputs a high level (over-temperature protection state), the electronic control unit shuts down the power output stage (e.g., shuts down the drive signal of the main power MOSFET), cutting off power supply to the load and preventing chip damage due to continuous overheating; when the OTP terminal outputs a low level (normal operating state), the electronic control unit allows the power output stage to operate normally, supplying power to the load normally. An approximately 18°C ​​hysteresis temperature difference ensures that after power output is shut down, the chip junction temperature has sufficient margin to decrease before power supply can be restored, preventing stress accumulation in power devices and load power instability caused by frequent switching.

[0103] In specific application scenarios of various vehicle subsystems, the hysteresis temperature difference characteristics of the over-temperature protection circuit are of great significance to the safe and reliable operation of each subsystem, which will be explained in detail below.

[0104] In battery management system (BMS) applications, the over-temperature protection signal output terminal (OTP) is connected to the power control terminal of the battery protection IC. When the junction temperature of the power management chip exceeds the over-temperature trigger threshold (171.4℃), the electronic control unit immediately shuts down the power MOSFET in the main charging and discharging circuit, cutting off the current path and preventing thermal runaway of the power battery due to sustained high temperatures. When the junction temperature drops below the temperature recovery threshold (153.4℃), the OTP terminal returns to a low level, and the electronic control unit re-enables the power MOSFET, restoring the charging and discharging function. The approximately 18℃ hysteresis temperature difference ensures that the battery management system has sufficient heat dissipation time after the over-temperature shutdown, avoiding the heat accumulation effect caused by restoring power supply after only a slight drop in junction temperature, thus ensuring the long-term cycle life and safety of the power battery.

[0105] In automotive DC-DC converter applications, the OTP signal directly acts on the enable terminal of the power stage drive circuit, enabling safe shutdown and automatic recovery in case of over-temperature. Automotive DC-DC converters typically operate at high switching frequencies (hundreds of kHz to several MHz), and power devices generate switching losses in each switching cycle, easily leading to heat accumulation under high load or poor heat dissipation conditions. The over-temperature protection circuit rapidly shuts off the drive enable and stops switching when the junction temperature exceeds the trigger threshold, allowing the power devices to enter a heat dissipation state. Once the junction temperature drops below the recovery threshold, it automatically restores the drive enable and restarts the DC-DC converter, requiring no manual intervention throughout the process and ensuring the continuity of the vehicle's power supply system. The hysteresis temperature difference range of 10℃ to 20℃ can be flexibly configured according to the thermal time constant of the DC-DC converter. High-power converters with larger thermal time constants are better suited to a larger hysteresis temperature difference to fully utilize the heat capacity for natural cooling.

[0106] In on-board charger (OBC) applications, the OTP signal acts on the protection logic enable pin of the OBC power stage. During charging, the power devices in the OBC withstand high current for extended periods, placing stringent demands on thermal management. The over-temperature protection circuit immediately interrupts the charging process when the junction temperature exceeds the trigger threshold, protecting the power stage devices from thermal damage. Charging automatically resumes once the junction temperature drops below the recovery threshold. The interruption and resumption of the charging process are transparent to the user, enhancing the user experience. The full-amplitude digital OTP signal, shaped by a Schmitt trigger, can directly drive the protection input of the OBC controller without requiring additional level conversion circuitry, simplifying system design.

[0107] In electric power steering (EPS) systems, the over-temperature protection signal is connected to the protection logic of the motor drive module. EPS systems have extremely high functional safety (ISO26262) requirements, and the reliability of the over-temperature protection signal directly affects the safety of the steering system. In this application, the full-amplitude digital OTP signal shaped by the Schmitt trigger eliminates glitches and oscillations during the over-temperature process, ensuring that the logic state of the protection signal is clear and unambiguous, meeting the functional safety requirements for the integrity of the protection signal. The active hysteresis feedback mechanism completely eliminates the hiccuping phenomenon, avoiding steering jitter that may be caused by frequent start-stop cycles of the EPS motor drive near the threshold, ensuring that the steering system maintains a stable protection state after performing a safety shutdown under thermal anomaly conditions, without generating dangerous random actions.

[0108] The vehicles in this application embodiment can be, but are not limited to, the following types: new energy vehicles such as pure electric vehicles (BEV), plug-in hybrid electric vehicles (PHEV), and fuel cell electric vehicles (FCEV), as well as traditional fuel vehicles equipped with high-power-density electronic control units. The power management chip can be integrated into, but is not limited to, the following on-board modules: the main control board of the battery management system (BMS), the on-board DC-DC converter module, the on-board charger (OBC) module, the electric power steering (EPS) controller, the body control module (BCM), and other on-board electronic systems requiring high-reliability power management.

[0109] It should be understood that the above vehicle embodiments are described for illustrative purposes only and do not constitute a limitation on the scope of protection of this application. The over-temperature protection circuit and power management chip of this application are not limited to vehicle applications, but can also be widely used in fields such as industrial automation, rail transportation, and aerospace where there are strict requirements for power management reliability.

[0110] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. An over-temperature protection circuit, characterized in that, It has a bias current input terminal and a temperature-dependent current input terminal, including: The bias current mirror unit is used to receive the bias current input from the bias current input terminal and copy and distribute the bias current to each functional branch. A temperature sensing unit is used to convert the chip temperature change into a sensing voltage that decreases as the temperature rises, driven by the bias current provided by the bias current mirror unit. A reference voltage generation unit is used to receive the current input from the temperature-correlated current input terminal and generate a reference voltage that increases with increasing temperature. A differential comparison unit is used to perform a differential comparison between the sensed voltage and the reference voltage, and output a differential comparison result signal; A common-source amplifier unit is used to amplify the differential comparison result signal and output an amplified output signal; The output shaping unit is used to shape the amplified output signal and output a full-scale digital over-temperature protection signal. The hysteresis feedback unit is used to actively lower or release the output reference voltage of the reference voltage generation unit according to the level state of the over-temperature protection signal, so as to form a hysteresis temperature difference between the over-temperature trigger threshold and the recovery threshold.

2. The over-temperature protection circuit as described in claim 1, characterized in that, The bias current mirror unit includes an NMOS current mirror composed of a first NMOS transistor and a second NMOS transistor, and a PMOS current mirror composed of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The gate-drain shorting node of the first NMOS transistor is connected to the bias current input terminal, the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the second NMOS transistor is connected to the gate-drain shorting node of the first PMOS transistor. The gate-drain shorting node of the first PMOS transistor is simultaneously connected to the gates of the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor; the drains of the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor respectively provide bias current to the temperature sensing unit, the differential comparator unit, and the common-source amplifier unit.

3. The over-temperature protection circuit as described in claim 2, characterized in that, The temperature sensing unit includes a PNP transistor, the collector and base of which are shorted and connected to analog ground, and the emitter of which is connected to the drain of a second PMOS transistor.

4. The over-temperature protection circuit as described in claim 2, characterized in that, The reference voltage generation unit includes a voltage divider network consisting of a first resistor and a second resistor connected in series. The upper end of the first resistor is connected to the temperature-dependent current input terminal, the lower end of the first resistor is connected to the upper end of the second resistor, and the lower end of the second resistor is connected to the analog ground terminal.

5. The over-temperature protection circuit as described in claim 4, characterized in that, The differential comparator unit includes a differential input pair consisting of a fifth PMOS transistor and a sixth PMOS transistor; the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to the drain of the third PMOS transistor; the gate of the fifth PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the sixth PMOS transistor is connected to the temperature-dependent current input terminal and the upper end of the first resistor.

6. The over-temperature protection circuit as described in claim 5, characterized in that, The differential comparator unit also includes an active current mirror load composed of a third NMOS transistor and a fourth NMOS transistor. The drain of the fifth PMOS transistor is connected to the gate-drain shorting node of the third NMOS transistor, the gate of the third NMOS transistor is also connected to the gate of the fourth NMOS transistor, and the drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are both connected to the analog ground.

7. The over-temperature protection circuit as described in claim 4, characterized in that, The output shaping unit includes a Schmitt trigger, a first inverter, and a second inverter; The input terminal of the Schmitt trigger is connected to the output terminal of the common-source amplifier unit, and the output terminal of the Schmitt trigger is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter; the output terminal of the second inverter serves as the over-temperature protection signal output terminal.

8. The over-temperature protection circuit as described in claim 7, characterized in that, The hysteresis feedback unit includes a sixth NMOS transistor; The gate of the sixth NMOS transistor is connected to the over-temperature protection signal output terminal, the drain of the sixth NMOS transistor is connected to the node between the lower end of the first resistor and the upper end of the second resistor in the reference voltage generation unit, and the source of the sixth NMOS transistor is connected to the analog ground terminal.

9. A power management chip, characterized in that, The circuit includes an over-temperature protection circuit as described in any one of claims 1-8, and also includes a bandgap reference source; The first output terminal of the bandgap reference source is connected to the bias current input terminal to provide a reference current to the bias current mirror unit; the second output terminal of the bandgap reference source is connected to the temperature-dependent current input terminal to provide a current proportional to the absolute temperature to the reference voltage generation unit.

10. A vehicle, characterized in that, Includes the power management chip as described in claim 9; The power management chip is integrated into the vehicle's electronic control unit; the over-temperature protection signal output terminal is connected to the power control terminal of the electronic control unit, and is used to shut down the power output when the junction temperature of the power management chip exceeds the over-temperature trigger threshold, and automatically restore power supply when the junction temperature drops below the recovery threshold.

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