On-chip surge protection circuit

Abstract

An on-chip surge protection circuit includes a first voltage rail, a second voltage rail, a third voltage rail, a coupling circuit, and a protection circuit. The first voltage rail is configured to provide a first voltage to at least one protected device. The second voltage rail is configured to provide a second voltage to the at least one protected device, wherein the second voltage is lower than the first voltage. The coupling circuit is coupled between the first voltage rail and the third voltage rail. The protection circuit is coupled between the third voltage rail and the second voltage rail. The on-chip surge protection circuit and the at least one protected device are integrated in the same chip.

Description

Technical Field

[0001] This invention relates to surge protection technology, and more particularly to an on-chip surge protection circuit employing a first technical feature of reducing or eliminating disturbances caused by surges on the supply voltage through an additional voltage rail and a coupling circuit, and / or a second technical feature of sharing the same protection circuit between surge protection and electrostatic discharge (ESD) protection. Background Technology

[0002] A surge event refers to a transient overcurrent or overvoltage event in an electronic circuit, which can potentially damage the circuitry. Traditional surge protection solutions use on-board surge protectors, which are mounted on the printed circuit board (PCB) and located outside the chip requiring surge protection. Because on-board surge protectors are located externally, they require additional components and occupy extra PCB space. Therefore, an innovative on-chip surge protection circuit is needed, which can be integrated inside the chip requiring surge protection. Summary of the Invention

[0003] One of the objectives of this invention is to provide an on-chip surge protection circuit that employs a first technical feature of reducing or eliminating disturbances caused by surges on the supply voltage through an additional voltage rail and coupling circuit, and / or a second technical feature of sharing the same protection circuit between surge protection and electrostatic protection.

[0004] In one embodiment of the present invention, an on-chip surge protection circuit is disclosed. The on-chip surge protection circuit includes a first voltage rail, a second voltage rail, a third voltage rail, a coupling circuit, and a protection circuit. The first voltage rail provides a first voltage to at least one protected device. The second voltage rail provides a second voltage to the at least one protected device, wherein the second voltage is lower than the first voltage. The coupling circuit is coupled between the first voltage rail and the third voltage rail. The protection circuit is coupled between the third voltage rail and the second voltage rail. The on-chip surge protection circuit and the at least one protected device are integrated into the same chip.

[0005] In one embodiment of the present invention, an on-chip surge protection circuit is disclosed. The on-chip surge protection circuit includes a surge detection circuit, an electrostatic discharge (ESD) detection circuit, and a protection circuit. The surge detection circuit detects a surge event on a first voltage rail and generates a first control signal. The ESD detection circuit detects an ESD event on the first voltage rail and generates a second control signal. The protection circuit is coupled between the first voltage rail and a second voltage rail and is jointly controlled by the first control signal and the second control signal. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a first type of on-chip surge protection circuit according to an embodiment of the present invention.

[0007] Figure 2 This is a schematic diagram of a front-end integrated circuit containing an on-chip surge protection circuit in one embodiment of the present invention.

[0008] Figure 3 yes Figure 1 The diagram shown illustrates the working principle of the surge protection circuit on the chip.

[0009] Figure 4 This is a schematic diagram of a surge current path according to an embodiment of the present invention.

[0010] Figure 5 This is a schematic diagram of a second type of on-chip surge protection circuit according to an embodiment of the present invention.

[0011] Figure 6 This is a schematic diagram of a third type of on-chip surge protection circuit according to an embodiment of the present invention.

[0012] [Symbol Explanation]

[0013] 100, 500, 600: On-chip surge protection circuit

[0014] 101: Protected device

[0015] 102, 104, 106: Voltage rails

[0016] 108: Coupling circuit

[0017] 110: Protection Circuit

[0018] 112: Surge Detection Circuit

[0019] 114: V REF Generator circuit

[0020] 116: ESD detection circuit

[0021] 118, 518: Logic circuits

[0022] 120, 620: Pull-up circuits

[0023] 122, 622: Pull-down circuits

[0024] 202: Primary-side transformer

[0025] 204: Secondary transformer

[0026] 206: Front-end integrated circuits

[0027] 208: Sudden Wave

[0028] 210: Overcurrent

[0029] CS1, CS2, CS3: Control signals

[0030] TX: Differential Transmitter Output

[0031] N: Transmitter output node

[0032] AVDD: First voltage

[0033] AVSS: Second voltage

[0034] AVDD33: Power supply pin

[0035] AVSS33: Ground pin

[0036] V REF Reference voltage

[0037] TXP: Positive transmitter differential output pin

[0038] TXN: Differential output pin of negative transmitter

[0039] R1, R2, R3: Current path Detailed Implementation

[0040] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0041] Figure 1 This is a schematic diagram of a first type of on-chip surge protection circuit according to an embodiment of the present invention. The on-chip surge protection circuit 100 and at least one protected device 101 are integrated on the same chip. For example, the on-chip surge protection circuit 100 and at least one protected device 101 can be integrated in a front-end integrated circuit (FEIC). Figure 2 This is a schematic diagram of a front-end integrated circuit containing an on-chip surge protection circuit according to an embodiment of the present invention. Figure 2 As shown, the electronic device may include a primary-side transformer 202, a secondary-side transformer 204, and a front-end integrated circuit 206, wherein the front-end integrated circuit 206 employs... Figure 1 The chip-side surge protection circuit 100 is shown. The differential transmitter output (TX) of the front-end integrated circuit 206 includes a positive signal output from the positive transmitter differential output pin TXP and a negative signal output from the negative transmitter differential output pin TXN. Furthermore, the supply voltage of the front-end integrated circuit 206 is received from the power supply pin AVDD33, and the ground voltage is received from the ground pin AVSS33. Figure 2 As shown, the surge 208 is coupled from the primary transformer 202 to the secondary transformer 204, and induces an overcurrent 210 in the secondary transformer 204, which then flows through the transmitter output of the front-end integrated circuit 206.

[0042] The purpose of this invention is to implement the on-chip surge protection circuit 100 inside the front-end integrated circuit 206, such as... Figure 1As shown, the surge protection circuit 100 on the chip may include a voltage rail (labeled "Power Bus") 102, a voltage rail (labeled "GND Bus") 104, a voltage rail (labeled "EBUS") 106, a coupling circuit 108, a protection circuit 110, a surge detection circuit 112, and a reference voltage generator circuit (labeled "V"). REF The circuit includes a generator circuit 114, an electrostatic discharge (ESD) detection circuit 116, a logic circuit 118, a pull-up circuit 120, and a pull-down circuit 122.

[0043] Voltage rail 102 is a high-voltage rail coupled to power pin AVDD33. Therefore, after the front-end integrated circuit 206 is powered on, a first voltage (i.e., supply voltage) AVDD can be provided through voltage rail 102. Voltage rail 104 is a low-voltage rail coupled to ground pin AVSS33. Therefore, after the front-end integrated circuit 206 is powered on, a second voltage (i.e., ground voltage) AVSS can be provided through voltage rail 104, where AVSS is lower than AVDD. In this embodiment, each protected device 101 is coupled between voltage rail 102 and voltage rail 104. Therefore, the first voltage (i.e., supply voltage) AVDD is provided to each protected device 101 through voltage rail 102, and the second voltage (i.e., ground voltage) AVSS is provided to each protected device 101 through voltage rail 104.

[0044] The on-chip surge protection circuit 100 proposed in this invention uses an additional voltage rail (i.e., voltage rail 106) separate from voltage rail 102. Compared to a protection circuit coupled between voltage rails 102 and 104 to provide a bypass path between them, the protection circuit 110 of the on-chip surge protection circuit 100 proposed in this invention is coupled between voltage rails 106 and 104 and provides a bypass path between them, wherein voltage rail 106 is not responsible for transmitting the supply voltage AVDD used by the protected circuit 101. Furthermore, compared to a surge detection circuit coupled between voltage rails 102 and 104 to detect surge events on voltage rail 102 (which transmits the supply voltage AVDD used by the protected device 101), the surge detection circuit 112 of the on-chip surge protection circuit 100 proposed in this invention is coupled between voltage rails 106 and 104 to detect surge events on voltage rail 106 (which is not responsible for transmitting the supply voltage AVDD used by the protected device 101). For example, the surge detection circuit 112 can be implemented using a voltage detection circuit that receives a reference voltage V generated by a reference voltage generator circuit 114. REF Furthermore, the reference voltage generator circuit 114 is coupled between voltage rail 102 and voltage rail 104, wherein the reference voltage V REF It is generated based on the first voltage (i.e., the supply voltage) AVDD and the second voltage (i.e., the ground voltage) AVSS. In this embodiment, the surge detection circuit 112 is used to detect the occurrence of a surge event on the voltage rail 106 and generate a control signal CS1, wherein the protection circuit (e.g., a clamp transistor) 110 is controlled at least according to the control signal CS1, that is, the trigger signal of the protection circuit (e.g., the clamp transistor) 110 is at least partially set based on the control signal CS1.

[0045] like Figure 1 As shown, pull-up circuit 120 is coupled between voltage rail 106 and transmitter output node N (e.g., N=TXP) of protected device 101, and pull-down circuit 122 is coupled between transmitter output node N (e.g., N=TXP) of protected device 101 and voltage rail 104. For example, both pull-up circuit 120 and pull-down circuit 122 can be implemented using diodes.

[0046] Please refer to this as well. Figure 1 and Figure 3 . Figure 3 yes Figure 1The diagram illustrates the operation of the on-chip surge protection circuit 100. When a surge event occurs on the differential transmitter output (TX) of the front-end integrated circuit 206, this surge event (especially the positive surge voltage caused by this surge event) can be transmitted to the voltage rail 106 via a pull-up circuit (e.g., a forward-biased diode) 120. Therefore, when the voltage on the voltage rail 106 suddenly increases due to the surge event, the surge detection circuit 112 detects the occurrence of the surge event on the voltage rail 106 by voltage sensing and generates a control signal CS1 (e.g., CS1=0) indicating the occurrence of the surge event. Since the protection circuit 110 is controlled by the control signal CS1, the protection circuit (e.g., a clamping transistor) 110 is enabled / triggered by the control signal CS1 (e.g., CS1=0) to activate a bypass path to divert most of the abnormal current caused by the surge event from the voltage rail 106 to the voltage rail 104.

[0047] When no surge event occurs at the transmitter output of the front-end integrated circuit 206, the voltage on the voltage rail 106 will remain at a predetermined voltage level. Furthermore, the surge detection circuit 112, by sensing the voltage, does not detect a surge event on the voltage rail 106 and generates a control signal CS1 (e.g., CS1=1) indicating the absence of a surge event. Since the protection circuit 110 is controlled by the control signal CS1, the protection circuit (e.g., clamping transistor) 110 is not activated / triggered by the control signal CS1 (e.g., CS1=1), resulting in no bypass path being activated between the voltage rail 106 and the voltage rail 104. Therefore, each protected device 101 will operate normally when the surge protection is not activated. In other words, the on-chip surge protection circuit 100 proposed in this invention has no impact on the normal operation of each protected circuit 101 (e.g., the front-end integrated circuit 206) integrated in the same chip.

[0048] In this embodiment, the coupling circuit 108 is coupled between voltage rails 102 and 106 to prevent voltage rail 106 from being in a floating state. For example, the coupling circuit 108 can be implemented using a resistor. Therefore, during periods when no surge event occurs on voltage rail 106, the coupling circuit 108 ensures that a fixed voltage relationship is maintained between the voltage on voltage rail 106 and the supply voltage AVDD on voltage rail 102. After a surge event occurs on voltage rail 106, the voltage sensing function of the surge detection circuit 112 can operate correctly to detect the occurrence of the surge event. Furthermore, the coupling circuit (e.g., resistor) 108 can limit the current flowing between voltage rails 106 and 102, thereby preventing the voltage of voltage rail 102 from being disturbed (e.g., dropping to a voltage level far below the rated supply voltage value) during the occurrence of a surge event.

[0049] Figure 4 This is a schematic diagram of a surge current path according to an embodiment of the present invention. Assume a pull-up circuit (e.g., diode) 120 is coupled between voltage rail 106 and transmitter differential output pin TXP, and a pull-down circuit (e.g., diode) 122 is coupled between transmitter differential output pin TXP and voltage rail 104. When a surge event occurs on the differential transmitter output (TX) of the front-end integrated circuit 206, a negative surge voltage may be induced on transmitter differential output pin TXN, and a positive surge voltage may be induced on transmitter differential output pin TXP. The surge event (especially the positive surge voltage induced by the surge event) is transmitted to voltage rail 106 through pull-up circuit (e.g., diode) 120, such as current path R3 ( As shown in the diagram. The surge detection circuit 112 detects surge events on voltage rail 106 to set the control signal CS1 (e.g., CS1=0). Furthermore, the protection circuit (e.g., clamping transistor) 110 is enabled / triggered by a trigger signal (which can be set by the inverted signal of control signal CS1), thereby initiating a bypass path between voltage rail 106 and voltage rail 104, as shown in current path R2. Since the additional voltage rail 106 is separate from the voltage rail 102 that provides the supply voltage AVDD to the circuit elements within the protected device 101, and most of the abnormal current caused by a surge event bypasses from voltage rail 106 to voltage rail 104, surge-induced disturbances on the supply voltage AVDD of voltage rail 102 can be reduced or eliminated. Furthermore, the remaining portion of the abnormal current caused by the surge event can be bypassed through current path R1 ( The current is directed to voltage rail 104. Since the coupling circuit (e.g., a resistor) 108 can limit the current flowing between voltage rail 106 and voltage rail 102, disturbances caused by surges on the supply voltage AVDD of voltage rail 102 can also be protected by the coupling circuit (e.g., a resistor) 108. It should be noted that the coupling circuit 108 can be implemented using circuit elements other than resistors; that is, the actual implementation of the coupling circuit 108 can depend on design considerations.

[0050] In this embodiment, surge protection and ESD protection can share the same protection circuit (e.g., clamping transistor) 110. Figure 1As shown, the ESD detection circuit 116 is used to detect the occurrence of ESD events on the voltage rail 106 and generate a control signal CS2. For example, when an ESD event occurs on the voltage rail 106, the ESD detection circuit 116 generates a control signal CS2 indicating that an ESD event has occurred (e.g., CS2=0); when there is no ESD event on the voltage rail 106, the ESD detection circuit 116 generates a control signal CS2 indicating that an ESD event does not exist (e.g., CS2=1). The protection circuit 110 is jointly controlled by the control signals CS1 and CS2. For example, the trigger signal of the protection circuit 110 is set based on the control signals CS1 and CS2. Figure 1 As shown, logic circuit 118 receives control signals CS1 and CS2, performs logical operations on CS1 and CS2 to generate and output control signal CS3 to protection circuit 110. Control signal CS3 serves as the trigger signal for protection circuit 110. For example, logic circuit 118 can be implemented using NAND gates. Therefore, during the detection of either a surge event or an ESD event, the bypass path between voltage rail 106 and voltage rail 104 is activated by protection circuit (e.g., clamping transistor) 110. It is important to note that ESD events are different from surge events. For example, an ESD event occurs before the front-end integrated circuit 206 is powered on (i.e., before the power supply pin AVDD33 receives the supply voltage AVDD from the voltage source and the ground pin AVSS33 receives the ground voltage AVSS from the voltage source), while a surge event occurs after the front-end integrated circuit 206 is powered on (i.e., after the power supply pin AVDD33 receives the supply voltage AVDD from the voltage source and the ground pin AVSS33 receives the ground voltage AVSS from the voltage source).

[0051] exist Figure 1 In the illustrated embodiment, logic circuit 118 can be implemented using NAND gates; however, this is merely an example and not intended to limit the invention. Figure 5 This is a schematic diagram of a second type of on-chip surge protection circuit according to an embodiment of the present invention. The main difference between on-chip surge protection circuit 100 and on-chip surge protection circuit 500 is that logic circuit 518 can be implemented using an inverter.

[0052] exist Figure 1 In the illustrated embodiment, both pull-up circuit 120 and pull-down circuit 122 can be implemented using diodes; however, this is merely an example and not intended to limit the invention. Figure 6This is a schematic diagram of a third type of on-chip surge protection circuit according to an embodiment of the present invention. The main difference between the on-chip surge protection circuit 100 and the on-chip surge protection circuit 600 is that the pull-up circuit (labeled "GD PMOS") 620 can be implemented using a gate-VDD P-channel metal-oxide-semiconductor (GD PMOS) transistor 620, while the pull-down circuit (labeled "GGNMOS") 622 can be implemented using a gate-grounded N-channel metal-oxide-semiconductor (GN NMOS) transistor 620.

[0053] about Figure 1 , Figure 5 and Figure 6 In the illustrated embodiments, each of the on-chip surge protection circuits 100, 500, and 600 proposed in this invention employs a first technical feature (which utilizes an additional voltage rail 106 and coupling circuit 108 to reduce or eliminate surge-induced disturbances on the supply voltage) and a second technical feature (which shares the same protection circuit (e.g., a clamping transistor) between surge protection and ESD protection). However, these are merely illustrative examples and are not intended to limit the invention. In some embodiments of this invention, the on-chip surge protection circuits 100 / 500 / 600 proposed in this invention may be modified to omit one of the first and second technical features. In fact, any on-chip surge protection circuit employing one or both of the first and second technical features falls within the scope of this invention.

[0054] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully understand the various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. An on-chip surge protection circuit, comprising: A first voltage rail is used to provide a first voltage to at least one protected device; A second voltage rail is provided to supply a second voltage to the at least one protected device, wherein the second voltage is lower than the first voltage; Third voltage rail; A coupling circuit is coupled between the first voltage rail and the third voltage rail; as well as A protection circuit is coupled between the third voltage rail and the second voltage rail; The surge protection circuit and the at least one protected device are integrated into the same chip.

2. The on-chip surge protection circuit as described in claim 1, wherein the coupling circuit is a resistor.

3. The on-chip surge protection circuit as described in claim 1 further comprises: A surge detection circuit is coupled between the third voltage rail and the second voltage rail, wherein the surge detection circuit is used to detect the occurrence of a surge event on the third voltage rail and generate a first control signal, wherein the protection circuit is controlled by at least the first control signal.

4. The on-chip surge protection circuit as described in claim 3 further comprises: A reference voltage generator circuit is coupled between the first voltage rail and the second voltage rail, wherein the reference voltage generator circuit is used to generate and output a reference voltage to the surge detection circuit.

5. The on-chip surge protection circuit as described in claim 3 further comprises: An electrostatic discharge detection circuit is used to detect the occurrence of an electrostatic discharge event on the third voltage rail and generate a second control signal, wherein the protection circuit is jointly controlled by the first control signal and the second control signal.

6. The on-chip surge protection circuit as described in claim 5 further comprises: A logic circuit is used to receive the first control signal and the second control signal, and to perform logical operations on the first control signal and the second control signal to generate and output a third control signal to the protection circuit.

7. The on-chip surge protection circuit as described in claim 6, wherein the logic circuit is a NAND gate.

8. The on-chip surge protection circuit as described in claim 6, wherein the logic circuit is an inverter.

9. The on-chip surge protection circuit as described in claim 1, further comprising: Pull-up circuit, coupled between the third voltage rail and the transmitter output node of the at least one protected device; and A pull-down circuit is coupled between the transmitter output node of the at least one protected device and the second voltage rail.

10. The on-chip surge protection circuit of claim 9, wherein each of the pull-up circuit and the pull-down circuit is a diode.

11. The on-chip surge protection circuit of claim 9, wherein the pull-up circuit is a P-channel metal-oxide-semiconductor transistor with its gate connected to the power supply, and the pull-down circuit is an N-channel metal-oxide-semiconductor transistor with its gate grounded.

12. An on-chip surge protection circuit, comprising: A surge detection circuit is used to detect the occurrence of a surge event on the first voltage rail and generate a first control signal; An electrostatic discharge detection circuit is used to detect the occurrence of an electrostatic discharge event on the first voltage rail and generate a second control signal. as well as A protection circuit is coupled between the first voltage rail and the second voltage rail, wherein the protection circuit is jointly controlled by the first control signal and the second control signal.

13. The on-chip surge protection circuit as described in claim 12, further comprising: A logic circuit is used to receive the first control signal and the second control signal, and to perform logical operations on the first control signal and the second control signal to generate and output a third control signal to the protection circuit.

14. The on-chip surge protection circuit as described in claim 13, wherein the logic circuit is a NAND gate.

15. The on-chip surge protection circuit of claim 13, wherein the logic circuit is an inverter.

16. The on-chip surge protection circuit as described in claim 12, further comprising: A pull-up circuit is coupled between the first voltage rail and at least one protected transmitter output node; as well as A pull-down circuit is coupled between the transmitter output node of the at least one protected device and the second voltage rail; The surge protection circuit and the at least one protected device are integrated into the same chip.

17. The on-chip surge protection circuit of claim 16, wherein each of the pull-up circuit and the pull-down circuit is a diode.

18. The on-chip surge protection circuit of claim 16, wherein the pull-up circuit is a P-channel metal-oxide-semiconductor transistor with its gate connected to the power supply, and the pull-down circuit is an N-channel metal-oxide-semiconductor transistor with its gate grounded.

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