A substation analog load flexible regulation method based on single-phase independent control

Abstract

The application discloses a transformer substation simulation load flexible adjustment method based on single-phase independent control and relates to the electrical test technical field.The method comprises the following steps: controlling a three-phase independent excitation source to respectively perform independent impedance characteristic identification on three-phase loops of the transformer substation, and analyzing equivalent resistance components and equivalent inductive reactance components; calculating a compensation capacitance value, performing capacitance switching, and completing hardware loop tuning; constructing a simulation load target sequence composed of multiple continuous time periods; in the current time period, real-time acquisition of secondary side vector information is compared with a target vector parameter group to obtain amplitude error and phase error, cross-phase feedforward decoupling calculation is combined with preset interphase magnetic circuit mutual inductance matrix coefficients, and three-phase control instructions after decoupling correction are output; when time period switching is performed, flexible control is performed on the three-phase target vector parameter group through a preset flexible transition window.The application can eliminate main transformer interphase magnetic circuit coupling interference and transient impact of working condition switching, and guarantee test safety and high precision.

Description

Technical Field

[0001] This invention relates to the field of electrical testing technology for substations, and in particular to a method for flexible adjustment of simulated loads in substations based on single-phase independent control. Background Technology

[0002] After a substation's infrastructure is built and put into operation or a technical upgrade project is implemented, load testing using system operating voltage and load current is required according to relevant technical specifications to ensure the correctness of parameters such as voltage and current polarity, phase sequence, and turns ratio of primary and secondary equipment. This post-construction verification method is highly susceptible to the influence of objective factors such as grid operation mode and the lack of load current limitations for dedicated users, leading to insufficient test thoroughness. To address this issue, off-grid load testing technology is being promoted. Before the substation is put into operation, this technology uses a three-phase excitation source of a testing device to apply current and voltage to the primary conductors to simulate the actual load.

[0003] However, existing off-grid simulated load testing technologies typically employ three-phase integrated linkage control logic, which cannot accurately simulate the complex single-phase asymmetrical load or unbalanced fault conditions in actual power grid operation. When attempting to independently regulate the output of a single phase through the control channel, due to the strong physical phase-to-phase magnetic coupling in the main transformer core within the substation, changes in the excitation current of the regulated phase will induce huge electromotive forces and transient inrush currents in the primary windings of other adjacent non-regulated phases, resulting in a significant decrease in the vector control accuracy of the entire station's simulated load. Simultaneously, at the moment of timing switching between different simulated load conditions, conventional hard switching is highly likely to trigger severe transient overvoltage surges in the limited capacity system of the off-grid, causing sensitive protection equipment within the station to malfunction or damage primary and secondary circuit equipment.

[0004] In summary, the existing technology has the following technical problems when used: Problem 1: Existing technologies lack effective phase-to-phase decoupling methods when simulating off-grid loads in substations. During single-phase independent regulation, it is impossible to eliminate or counteract the induced back electromotive force interference generated on the primary windings of adjacent non-regulated phases due to the strong magnetic circuit coupling inside the main transformer core. This results in severe amplitude and phase distortion of the voltage and current vectors ultimately output to the secondary side of the substation, making it impossible to achieve high-precision single-phase independent decoupling control. Question 2: Existing technologies employ discrete hard switching modes when simulating the time-series evolution and switching of complex load conditions. At the boundary of sudden changes in simulated load vectors at different time periods, step-like jumps in large current or high voltage can easily induce electromagnetic transient inrush currents and overvoltage risks in the system, causing magnetic saturation of the main transformer that is not in operation or burning out high-precision voltage / current transformers (PT / CT), thus failing to guarantee the equipment safety of the off-grid fully automated testing process. Summary of the Invention

[0005] To address the shortcomings of the existing technologies, this invention aims to provide a method for flexible adjustment of substation simulated load based on single-phase independent control, which can effectively eliminate magnetic circuit coupling interference between main transformer phases and transient impacts during operating condition switching, ensuring test safety and high accuracy.

[0006] The technical solution provided by this invention is, as one aspect of this invention, a method for flexible regulation of simulated load in a substation based on single-phase independent control, which includes the following steps: The impedance characteristics of the three-phase circuits in the substation are identified independently by controlling the three-phase independent excitation sources, and the equivalent resistance components and equivalent inductive reactance components of each of the three-phase circuits are analyzed. Based on the equivalent resistance component and the equivalent inductive reactance component, calculate the compensation capacitor value of each phase at the rated frequency. After switching the capacitor based on the compensation capacitor value, determine whether the hardware circuit tuning is completed. After completing the hardware loop tuning, a simulated load target sequence consisting of multiple consecutive time periods is constructed. The simulated load target sequence contains the three-phase target vector parameter set corresponding to each time period. Within the current time period, the real-time vector information of the substation secondary side is acquired and compared with the three-phase target vector parameter group to obtain the independent amplitude error scalar and phase error scalar of each of the three phases. Combined with the preset interphase magnetic circuit mutual inductance matrix coefficient, cross-phase feedforward decoupling calculation is performed, and the decoupling corrected three-phase control command is output. Based on the three-phase control command, the three-phase independent excitation source is driven to output the simulated load. When switching time periods, the three-phase target vector parameter group is flexibly controlled through a preset flexible transition window.

[0007] This invention provides a method for flexible load regulation of simulated substations based on single-phase independent control. It has the following beneficial effects: Implementing the embodiments of the present invention has the following beneficial effects: This invention overcomes the interference bottleneck caused by the inherent interphase magnetic circuit coupling of the main transformer core in substations by introducing a cross-phase feedforward decoupling calculation method at the low-voltage level. In the simulated load regulation process of the current time period, it not only uses a proportional resonant controller to amplify the amplitude and phase error scalars without steady-state error, but also collects the instantaneous value of the AC current of the physical output terminal lead of the primary side of the test device in real time and calculates its rate of change. By performing matrix multiplication with the coefficients of the interphase magnetic circuit mutual inductance matrix that quantitatively characterizes the interphase magnetic circuit coupling strength of the main transformer, the predicted scalar of the induced back electromotive force on the adjacent non-regulated phases is accurately and quantitatively analyzed. This scalar is then dynamically injected into the control voltage reference command of the adjacent phases with opposite polarity as a feedforward control voltage quantity, actively applying a reverse suppression excitation voltage on the physical line to eliminate interphase interference. This invention achieves true complete decoupling and independent control of three-phase high-power output, thereby ensuring the high accuracy of the secondary side output when the simulated load of the entire station is independently regulated by a single phase.

[0008] This invention proposes a vector flexible blanking and establishment superposition control based on a time-series transition window for the transient boundary section of multi-condition automated switching, fundamentally eliminating the safety hazards of transient overvoltage in off-grid conditions. When the test timing changes over a period of time, the main control core unit no longer executes a step-type hard switching command, but instead dynamically calculates the linearly decreasing dynamic attenuation coefficient and the linearly increasing dynamic growth coefficient in real time within a preset flexible transition window based on the current running time. These two coefficients are used to perform flexible blanking processing on the three-phase target vector parameter group of the old condition and flexible establishment processing on the three-phase target vector parameter group of the new condition. Finally, the blanked old vector and the established new vector are vector superimposed in the complex space to synthesize a smoothly evolving temporary flexible control target parameter group and flow to the regulation closed loop. This process limits the amplitude change rate and phase continuity, realizing a smooth transition of fully automatic simulated load conditions without transient voltage and current impacts, ensuring the safety of primary and secondary equipment in the station. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, obtaining other drawings based on these drawings without creative effort still falls within the scope of the present invention. Figure 1 This is a main flowchart of an embodiment of a substation simulated load flexible adjustment method based on single-phase independent control according to the present invention; Figure 2 for Figure 1 A more detailed flowchart is provided. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0011] like Figure 1 A method for flexible load regulation of substations based on single-phase independent control, the method includes: Step S1 involves controlling three independent excitation sources to independently identify the impedance characteristics of each of the three-phase circuits in the substation, resolving the equivalent resistance and equivalent inductive reactance components of each circuit. Before the test begins, impedance characteristic identification actively identifies the actual physical impedance boundaries introduced by the primary and secondary lines, primary windings, and physical leads of the substation, providing accurate physical parameter benchmarks for subsequent reactive power compensation and hardware tuning. The equivalent resistance component characterizes the active power loss characteristics of the entire circuit under the test signal, caused by conductor resistance, contact resistance, and core losses, reflecting the degree of purely resistive attenuation in the test circuit. The equivalent inductive reactance component quantitatively determines the inherent inductance characteristics of the main transformer windings and leads, reflecting the circuit's electromagnetic impedance to changes in alternating current.

[0012] Step S2: Based on the equivalent resistance and equivalent inductive reactance components, calculate the compensation capacitor value for each phase at the rated frequency. After switching the capacitors based on the compensation capacitor values, determine whether hardware circuit tuning is complete. By calculating the compensation capacitor values, the capacitance required to offset the inherent equivalent inductive reactance component of the system identified in step S1 is quantitatively calculated, thus providing a precise control target for eliminating reactive power and improving energy transmission efficiency at the source. Through capacitor switching, the calculated compensation capacitor values ​​are used to connect capacitor banks of specific capacities to the corresponding physical circuits using the action of physical switches, thereby dynamically changing the physical reactance distribution of the hardware circuits and making the entire network approach a purely resistive state. The completion of hardware circuit tuning indicates that the reactive component of the circuit has been offset to the maximum extent, the energy output from the excitation source can be converted into the simulated load required for the test without loss, and the phases have reached an impedance matching ready state at the physical level, meeting the safety boundary for conducting high-precision high-power tests.

[0013] Step S3: After completing the hardware loop tuning, a simulated load target sequence consisting of multiple consecutive time periods is constructed. The simulated load target sequence includes the three-phase target vector parameter set corresponding to each time period. By constructing the simulated load target sequence, the discrete and static substation protection verification requirements are transformed into a continuously evolving test target data stream with multiple time sequences under a unified clock reference. This allows for a complete simulation of the entire process of the real power grid evolving from normal operation to dynamic processes such as single-phase grounding faults and phase-to-phase faults, providing continuous control targets for closed-loop regulation.

[0014] Step S4: Within the current time period, the real-time vector information of the substation secondary side is acquired and compared with the three-phase target vector parameter set to obtain the independent amplitude error scalar and phase error scalar of each phase. Combined with the preset interphase magnetic circuit mutual inductance matrix coefficients, cross-phase feedforward decoupling calculation is performed, and the decoupling-corrected three-phase control command is output. Based on the three-phase control command, the three-phase independent excitation sources are driven to output simulated load. By calculating the error scalar, the deviation between the actual output load state of the substation secondary side and the expected target is quantified in real time, reflecting the control distortion caused by system nonlinearity, temperature drift, or external transient interference. This serves as the input source for the feedback regulation system to perform precise correction. The output three-phase control command is the final voltage control signal after cross-phase feedforward decoupling correction, which is used to directly act on the drive circuit to drive the three-phase independent excitation sources to adjust their output. This not only eliminates the closed-loop error of the current phase but also physically cancels the interference electromotive force induced in the current phase due to changes in adjacent phase currents, ensuring complete decoupling of the three-phase output.

[0015] Step S5: When switching time periods, the three-phase target vector parameter group is flexibly controlled through a preset flexible transition window. By setting a flexible transition window, the traditional hard switching mode is broken. A buffer is established on the time axis, allowing the data from the old test condition to gradually decay while the data from the new test condition increases synchronously and linearly. This achieves a smooth transition in the spatial vector, fundamentally suppressing high-frequency transient overvoltages and current surges on the primary side caused by control quantity steps, protecting the precision primary and secondary tested equipment within the station from damage.

[0016] The following will be combined Figure 2 The various steps of the method provided by the present invention will be described in detail with specific examples.

[0017] In this embodiment, the implementation steps of controlling the three-phase independent excitation sources to independently identify the impedance characteristics of the three-phase circuits of the substation in step S1 include: Step S101: The three-phase circuit of the substation includes phase A, phase B, and phase C circuits, and the three-phase independent excitation sources include phase A, phase B, and phase C independent excitation sources. These three-phase circuits correspond to three independent physical channels of the substation's main transformer and connecting lines. Each phase circuit carries its own current and forms an independent voltage drop. In terms of physical structure and electromagnetic characteristics, due to the three-phase column structure of the transformer core, although there is magnetic coupling between the three phases, the primary windings and leads are physically separated. This scheme utilizes this physical separation to achieve independent identification of the electrical parameters of each phase circuit and independent control of the subsequent simulated load. The three-phase independent excitation source is a power supply system composed of three structurally independent and mutually non-interfering single-phase inverter bridges and drive circuits. Each receives independent commands from the main control core unit and independently outputs AC power with freely adjustable amplitude, phase, and frequency to the A, B, and C phase circuits for single-phase independent control.

[0018] A separate A-phase independent excitation source outputs a sinusoidal detection signal of preset frequency and low amplitude to the primary circuit of the substation, while simultaneously blocking the outputs of the B-phase and C-phase independent excitation sources. Instantaneous voltage and current signals at the output terminals of the A-phase circuit are acquired online. To eliminate mutual interference between phase magnetic circuits when multiple phases output simultaneously and to ensure that the acquired signals are purely determined by the physical characteristics of the currently tested phase, during impedance characteristic identification of the A-phase circuit, a full-shutdown hardware blocking signal is first sent to the inverter bridges of the B-phase and C-phase circuits. This forces the power switches of phases B and C to be completely off, switching their output terminals to a high-impedance isolation state, ensuring that no current flows through the B and C-phase circuits. Then, based on the principles of electromagnetic induction and resistive voltage division, a high-precision resistive voltage divider network is connected in parallel at the output of phase A circuit to collect voltage, and a high-frequency Hall current sensor is connected in series to collect current. The collected analog signal is filtered by a low-pass filter to remove high-frequency noise. The low-pass filter is a second-order Butterworth active low-pass filter with a cutoff frequency set to 150Hz. It is sent to a synchronous analog-to-digital converter and subjected to high-frequency discrete sampling at fixed time intervals. For example, if the sampling frequency is set to 12.8kHz, it corresponds to 256 sampling points per cycle, generating digital sequences of instantaneous voltage and instantaneous current signals, providing the most original real-time waveform data for subsequent Fourier transform.

[0019] The sinusoidal detection signal is generated by a digital signal generator inside the main control core unit by looking up a sine table and then performing digital-to-analog conversion and pre-amplification. It is an AC sinusoidal voltage signal with a known initial phase, constant amplitude, and extremely low waveform distortion. Its preset frequency is set to 50Hz, consistent with the rated power frequency of the power grid, and the low amplitude range is usually set to 5% to 10% of the rated output voltage (e.g., 10V to 20V). The preset frequency is chosen to ensure that the identified impedance characteristics conform to the power frequency operating environment, and the low amplitude is chosen to prevent the detection signal from triggering the station's protection devices to malfunction, thus ensuring safety in the early stages of the test.

[0020] Discrete Fourier Transform (DFT) is performed on the instantaneous voltage and current signals to calculate and separate the fundamental voltage amplitude, fundamental current amplitude, and phase difference angle between the voltage and current in phase A circuit. Through DFT, the amplitude and phase information of the component with a frequency equal to the sinusoidal probe signal frequency (50Hz) is accurately extracted from the instantaneous voltage and current signals, which contain various components such as noise and harmonics. First, multiple instantaneous voltage and current data points collected within a complete cycle (e.g., 20 milliseconds) are multiplied point by point with internally generated sine and cosine tables at a frequency of 50 Hz and accumulated to calculate the real and imaginary parts of the voltage vector and the current vector. Then, based on the real and imaginary parts, the fundamental amplitude is calculated by taking the square root of the sum of squares, thereby calculating the fundamental voltage amplitude and fundamental current amplitude. By taking the arctangent of the ratio of the imaginary part to the real part, the absolute phase angle of the voltage and the absolute phase angle of the current are obtained. Subtracting the absolute phase angle of the current from the absolute phase angle of the voltage generates the phase difference angle.

[0021] The fundamental voltage amplitude refers to the peak value of the voltage component at the sinusoidal detection signal frequency (50Hz), reflecting the magnitude of the detection voltage applied to the circuit. The fundamental current amplitude refers to the peak value of the current component at the same 50Hz frequency, reflecting the magnitude of the response current of the circuit under this voltage drive. The phase difference angle between the voltage and current refers to the lead or lag angle between the fundamental voltage waveform and the fundamental current waveform on the time axis, reflecting the inductive or capacitive characteristics of the circuit's equivalent impedance.

[0022] The current phase is sequentially blocked while the next phase is opened. Using the same control and analysis process, the fundamental voltage amplitude, fundamental current amplitude, and corresponding phase difference angle of phases B and C are calculated respectively. By sequentially calculating the fundamental voltage amplitude, fundamental current amplitude, and phase difference angle of phases A, B, and C, complete and independent original electrical characteristic data for each phase circuit are obtained. This facilitates the independent calculation of the required compensation capacitor value and independent control parameters for each phase in subsequent steps.

[0023] The primary circuit of a substation refers to the high-voltage, high-current main power circuit (such as the main transformer winding, high-voltage busbar, etc.) in the substation, which is used to carry the main test current to simulate a high-load environment; the secondary circuit of a substation refers to the low-voltage, low-current control and measurement circuit that connects the secondary winding of the voltage / current transformer, protection devices, and measuring instruments, which is used to collect sampled data streams reflecting the primary side status for the protection devices to perform fault diagnosis.

[0024] In this embodiment, step S1, the implementation steps of analyzing the equivalent resistance and equivalent inductive reactance components of each of the three-phase circuits, include: Step S102: Divide the fundamental voltage amplitude of each phase obtained from the analysis by the corresponding fundamental current amplitude to calculate the equivalent impedance amplitude of each of the three-phase circuits. The equivalent impedance amplitude is the ratio of the total fundamental voltage amplitude to the fundamental current amplitude, which includes the combined impediment effect of resistance and reactance in the circuit. As the total modulus of impedance decomposition, it reflects the overall impediment capability of the entire physical circuit to alternating current.

[0025] By combining the phase difference angles of each phase circuit, the corresponding equivalent impedance amplitudes are orthogonally decomposed in the impedance space using trigonometric function mapping relationships, and the equivalent resistance and equivalent inductive reactance components of phase A, phase B, and phase C circuits are independently extracted. Based on the phase difference angles calculated in step S101, the cosine and sine function tables are retrieved from the memory, and the corresponding cosine and sine values ​​are obtained by looking up the values ​​of the phase difference angles. The equivalent resistance component is calculated by multiplying the calculated equivalent impedance amplitude by the cosine value of the phase difference angle; the equivalent inductive reactance component is calculated by multiplying the calculated equivalent impedance amplitude by the sine value of the phase difference angle.

[0026] The equivalent resistance component is the part of the impedance that consumes active power. It is the projection of the equivalent impedance magnitude onto the horizontal axis (real axis), representing the pure physical property of the circuit that consumes active power, and reflecting the energy consumption characteristics of the conductor and iron loss. The equivalent inductive reactance component is the part of the impedance that stores and releases magnetic field energy. It is the projection of the equivalent impedance magnitude onto the vertical axis (imaginary axis), representing the pure physical property of the circuit that stores magnetic field energy, and reflecting the inductive effect of the winding.

[0027] The cosine and sine function tables are pre-calculated and stored in memory by the main control core unit at a resolution of 1024 points per cycle during system initialization. When looking up the tables, if the required phase difference angle falls exactly on the pre-stored point, the corresponding sine and cosine values ​​are read directly. If it is between two pre-stored points, the sine and cosine values ​​of that point are calculated by linear difference or quadratic difference.

[0028] Impedance space is defined as a complex plane characterized by a Cartesian coordinate system, where the horizontal axis represents the pure resistive component and the vertical axis represents the pure reactive component. During orthogonal decomposition, the main control core unit establishes a vector in the impedance space using the equivalent impedance magnitude as the length of the vector and the phase difference angle as the angle between the vector and the horizontal axis. This vector is then projected onto the horizontal and vertical axes, thereby spatially separating the mixed impedance modulus into mutually perpendicular and non-interfering equivalent resistive and equivalent reactive components.

[0029] In this embodiment, step S2, after switching the capacitor based on the compensation capacitor value, includes the following steps: Step S201: Obtain the rated angular frequency of the current test power supply. Combined with the equivalent inductive reactance component, calculate the required compensation capacitor values ​​for each of the A-phase, B-phase, and C-phase circuits. Read the rated angular frequency of the current test power supply, square it, multiply the squared value by the equivalent inductive reactance component obtained in step S102, and finally take the reciprocal of the product to calculate the compensation capacitor value. The compensation capacitor value is the physical capacitance required for the circuit to reach resonance. It includes the nominal capacitance value and the corresponding stepped configuration combination, used to guide the hardware reactive power compensation circuit to perform precise capacitance switching. The formula for calculating the compensation capacitor value is... ; in, This indicates the compensation capacitor value required for phase m (m can be A, B, or C), expressed in farads. This indicates the rated angular frequency of the test power supply, and its value is... (in (Rated frequency 50Hz). This represents the equivalent inductive reactance component value of the m-phase circuit identified in step S102, in Henry. The rated frequency and rated angular frequency are set according to the standard power frequency of the national power system, and are directly read from the non-volatile memory of the main control core unit. The rated frequency is 50Hz, and the rated angular frequency is equal to... The product of the operating frequency is strictly limited to a very small drift range centered at 314.16 radians per second.

[0030] The main control core unit converts the compensation capacitor value into a capacitor encoding command and sends it to the reactive power compensation circuit. This changes the capacitance of each phase circuit's physical connection circuit, allowing phase A, phase B, and phase C circuits to independently reach their preset resonance states on the physical lines. First, the main control core unit compares the calculated compensation capacitor value with the preset standard capacitance values ​​for each position of the capacitor bank (e.g., 1μF, 2μF, 5μF, 10μF, etc.). Through a combination matching algorithm, it selects the optimal capacitor hardware combination, ensuring that the total capacitance of these capacitor banks connected in parallel is closest to the calculated target value. The selected combination is mapped to the corresponding switch pin's drive level (1 or 0), concatenated into a binary code, and sent via SPI or CAN bus. For example, if the capacitor banks are "connected to groups 1 and 3, disconnected to groups 2 and 4," this is encoded into a specific digital command, such as a 16-bit integer, where each bit corresponds to the switch of a capacitor bank. Then, the receiving chip of the reactive power compensation circuit decodes the capacitor encoding instruction and outputs a high level to drive a specific thyristor to conduct, physically connecting the corresponding capacitor into the circuit, while keeping other thyristors off, adjusting the total impedance characteristics of the circuit so that its inductive reactance is completely canceled by the capacitive reactance.

[0031] The preset total capacity configuration principle for the capacitor bank is that the capacitance values ​​of each level are configured using a binary weighted average or a 1-2-4-8 sequence to ensure that combined switching can cover capacitance values ​​ranging from the smallest level to any integer multiple of the total capacity. For example, configuring six levels of 1μF, 2μF, 4μF, 8μF, 16μF, and 32μF allows for combined switching of any integer microfarad capacitance value within the range of 1μF to 63μF, with a step accuracy of 1μF. The total capacity of the capacitor bank (i.e., the sum of the capacitance values ​​of all levels) should not be less than the maximum value that the compensation capacitance value calculated in step S201 can reach (usually 1.2 times the theoretical resonant capacitance value corresponding to the equivalent inductive reactance component of the phase circuit, with a 20% margin) to ensure accurate compensation under any operating condition.

[0032] A capacitor-encoded instruction is a binary digital control word composed of high and low level combinations. It contains information on which capacitor banks should be closed (connected) and which capacitor banks should be disconnected (disconnected) in order to achieve the compensation capacitance value.

[0033] The reactive power compensation circuit is a hardware network consisting of multiple sets of capacitors of different capacities, power electronic switching tubes (or switching thyristors), and discharge resistors. It is used to receive capacitor encoding instructions and execute physical switching actions. Physically, it is connected between the output terminal of the three-phase independent excitation source and the primary circuit of the substation to change the total physical capacitance connected to the test circuit in real time.

[0034] Changing the capacitance of each phase circuit's physical connection is based on the physical law that "capacitors connected in parallel have their total capacitance added together." The main control unit calculates the required additional compensation capacitance and then issues a capacitance-coded command to close the corresponding switch, connecting more capacitors to the circuit. Conversely, it opens the switch to disconnect the capacitors. The main control unit issues a capacitance-coded command, which, after being amplified by the isolation drive circuit, directly controls the gate of the thyristor switch for the corresponding phase. When a zero-voltage or zero-current crossing is detected, the thyristor switch conducts, physically connecting the capacitor bank corresponding to that switch to the primary circuit conductors. The connected capacitor bank then begins charging and discharging, changing the overall capacitive reactance of that phase circuit, thus physically realizing the theoretically calculated reactive power compensation.

[0035] The preset resonance state refers to the state in which the energy of the inductor's magnetic field and the energy of the capacitor's electric field are completely equal and exchange with each other. At this time, the circuit exhibits pure resistance. Reaching the preset resonance state reduces the reactive power of the entire test system to zero, and the voltage output by the excitation source is used entirely to generate effective current, which greatly improves the output capacity and adjustment response speed of the equipment.

[0036] In this embodiment, step S1, the step of determining whether hardware circuit tuning has been completed, includes: In step S202, after the capacitor switching in the reactive power compensation circuit is completed, the fundamental voltage amplitude and fundamental current amplitude at the output terminals of each phase circuit are collected in real time, and the real-time power factor of each phase circuit after tuning is calculated. The main control core unit calculates the real-time phase difference angle between the extracted fundamental voltage amplitude and fundamental current amplitude according to the method in step S101; then, it retrieves the cosine value of the phase difference angle from the cosine function table in the memory. This cosine value is the real-time power factor. The real-time power factor refers to the ratio of the actual active power consumed to the apparent power under the current operating state. It reflects the degree of in-phase relationship between voltage and current in the circuit and the residual amount of reactive power. As the final criterion for whether the hardware tuning is qualified, the closer it is to 1, the better the inductive reactance and capacitive reactance are canceled, and the closer the circuit is to pure resistivity.

[0037] The real-time power factor of each of the three-phase circuits is compared with a preset factor threshold. The preset factor threshold is set according to the strict limitation requirements of reactive power loss in high-precision power tests, and is generally set between 0.90 and 0.99. The recommended value in this embodiment is 0.95 to ensure that the impact of reactive power component on amplitude control is negligible.

[0038] If the real-time power factors of all three phases are greater than or equal to the preset factor threshold, the hardware circuit tuning is deemed complete. The test lockout is released, a physical circuit ready state word is generated, and the current rated frequency of 50Hz is latched as the station-wide synchronization clock reference, completing the hardware-level single-phase independent impedance matching. This station-wide synchronization clock reference is used for time axis division in step S3. The physical circuit ready state word and the station-wide synchronization clock reference are then transferred to step S301. The test lockout is a hardware-level safety protection state that prohibits power output, effectively preventing power devices from mis-conducting and causing equipment damage before the hardware circuit tuning is complete.

[0039] The main control core unit monitors the auxiliary contact status feedback of the hardware switches in the reactive power compensation circuit, or delays for a preset mechanical / electronic dead time (e.g., 50 milliseconds) after issuing the capacitor encoding command. Following the same method as steps S101 and S102, it recalculates the equivalent resistance and equivalent inductive reactance components of each phase circuit in real time, and further calculates the current real-time power factor. Only when the real-time power factor is consistently greater than or equal to the preset factor threshold after multiple consecutive measurements (e.g., 10 consecutive cycles), confirming that all switch states are stable and no longer fluctuating, is it determined that the capacitor switching has been successfully completed, the hardware circuit tuning is qualified, and the physical switching action is complete.

[0040] If the real-time power factor of any phase is less than the preset threshold, the hardware circuit tuning of that phase is deemed unqualified, and the following specific steps are executed: First, the main control core unit records the information of this tuning failure and the currently detected real-time power factor, equivalent resistance component, and equivalent inductive reactance component of this phase into the log. Then, based on the current equivalent inductive reactance component, a corrected compensation capacitor value is recalculated. For example, if the power factor is capacitive, the target capacitor value is decreased; if it is inductive, the target capacitor value is increased. Finally, the new compensation capacitor value is converted into a new capacitor encoding instruction, which drives the reactive power compensation circuit to perform a new round of capacitor switching. Repeat the acquisition and judgment process in step S202. If successful within the predetermined number of attempts (e.g., 3 times), proceed to the tuning completion process; if all attempts fail, the main control core unit determines that the physical hardware of that phase may have a fault (e.g., capacitor damage, switch sticking, or open circuit), and then takes the following measures: Immediately block the drive pulses of the three-phase independent excitation sources and switch the system to a safe shutdown state to prevent power devices from being mis-conducted in an untuned state, which could cause equipment damage. Disconnect all capacitor banks (restore to the initial zero capacitance configuration) and keep the test locked; An audible and visual alarm is then triggered, the test process is stopped, and a clear message is displayed on the human-machine interface: "Hardware tuning of phase XX failed. Please check the reactive power compensation circuit and primary wiring." The system remains in a stopped state due to the fault until the operator manually intervenes to reset it or the fault is resolved and the test process is restarted.

[0041] In this embodiment, step S3, the implementation steps of constructing a simulated load target sequence consisting of multiple consecutive time periods, include: Step S301: Using the station-wide synchronized clock as the basic step size for evolution, the timeline is sequentially divided into multiple different test time periods. The overall test process is set up by these time periods. Time period To the time period The test time period is divided according to the minimum operating condition maintenance time required for the verification of the operating characteristics of the power system protection device. By dividing the test time period, the complex and dynamic evolution process of power grid faults is discretized into controllable sequential execution conditions, which facilitates the control system to load control targets segment by segment. The division process is as follows: First, the preset total verification duration (e.g., 5 seconds) is read and converted into a total count sequence containing 250 basic time steps (20 milliseconds); then, a state switching split point is set in the total count sequence, dividing the total technical sequence into three continuous digital intervals, where the first 100 step intervals are defined as the "normal operation segment", the 101st to 200th step intervals are defined as the "single-phase ground fault simulation segment", and the last 50 step intervals are defined as the "fault clearing and recovery segment"; finally, the hardware clock counter of the main control core unit is configured with segmented overflow interrupts, so that the time axis is sequentially represented as interconnected test time periods with independent index numbers.

[0042] The state switching points are configured according to the various fault simulation requirements specified in the national standards and industry specifications for dynamic simulation tests of power system relay protection. The duration of the normal operation phase is set based on the steady-state monitoring cycle requirements of the tested protection device under normal operating conditions, generally not less than 100 power frequency cycles (i.e., 2000 milliseconds) to ensure the protection device completes its self-check and steady-state data recording before startup. The duration of the fault simulation phase is set according to the type of fault being simulated and the operating time characteristics of the protection device. For single-phase ground faults, the fault duration is generally set to 1.5 to 2 times the operating time of the protection device's first stage (e.g., if the operating time of the protection's first stage is 20 milliseconds, then the fault simulation phase duration is set to 40 milliseconds). For phase-to-phase faults, the same principle can be applied. The duration of the fault clearing and recovery phase is set according to the circuit breaker's operating time and the system's transient recovery characteristics, generally not less than 5 power frequency cycles (100 milliseconds) to ensure the system voltage and current recover to their steady-state values. For example, the total test duration is set to 5 seconds (250 basic time steps, each step is 20 milliseconds), of which the first 100 steps (2000 milliseconds) are the normal operation segment, the 101st to 140th steps (800 milliseconds) are the single-phase ground fault simulation segment, and the 141st to 250th steps (2200 milliseconds) are the fault clearing and recovery segment.

[0043] The station-wide synchronous clock reference is set based on the high-frequency pulse period of the hardware crystal oscillator latched at the moment of successful tuning in step S202. Numerically, it is represented by a hardware-level microsecond-level timer counting cycle that is completely synchronized with the actual power frequency of the system. Its basic time step is generally set to 20 milliseconds, which is the time of one complete cycle of a 50Hz power grid. This provides a unified time axis scale for all control behaviors of the entire test system, ensuring that the three-phase waveforms do not experience phase drift during long-term operation. The main control core unit uses a temperature-compensated crystal oscillator (TCXO) as its hardware clock source, with a frequency stability better than ±50ppm (parts per million). Under ambient temperature of 25℃, the typical frequency error does not exceed ±0.0025Hz (corresponding to a phase drift of approximately 0.018° / second at a 50Hz power frequency). To further suppress frequency drift caused by ambient temperature changes during long-term operation, the main control core unit incorporates a digital phase-locked loop (DPLL). During testing, it continuously monitors the zero-crossing signal of the grid voltage fed back from the substation's secondary side, comparing the frequency division coefficient of the hardware clock counter with the measured power frequency cycle in real time. Through closed-loop adjustment, the internal clock reference always tracks changes in the external power grid frequency, ensuring that the cumulative phase drift of the three-phase waveform does not exceed ±0.5° within a test duration of several seconds to tens of seconds. When the external power grid frequency deviates (e.g., deviating from 50Hz by more than ±0.5Hz), the system automatically pauses the test and alerts the operator.

[0044] Step S302: Under the constraint of the station-wide synchronous clock reference, ensure that the fundamental frequency of the waveform in each time period is strictly equal to 50Hz. The main control core unit calls the preset substation protection verification timing database and configures a three-phase target vector parameter group for each test time period. The three-phase target vector parameter group includes the target fundamental amplitude and target absolute phase angle of each of the A-phase circuit, B-phase circuit, and C-phase circuit. For example, in the normal operation section... Within the simulation, the target fundamental wave amplitudes of phases A, B, and C are configured to be equal, and the absolute phase angles of the targets differ by 120 degrees on the time axis. This is in the single-phase ground fault simulation section. Inside, the target fundamental amplitude of phase A is increased to the preset fault value, while phases B and C maintain the normal operating parameters.

[0045] The three-phase target vector parameter set is configured based on the simulated real power system operating conditions during the current test period. The configuration is determined by judging the current clock counter interval. Specifically: If it is determined to be a "normal operating period", the main control core unit will uniformly assign the target fundamental amplitude variables of the three phases A, B and C to the rated symmetrical value (such as 57.7V), and assign the target absolute phase angle variables of the three phases A, B and C to 0 degrees, -120 degrees and +120 degrees respectively in memory to ensure that the three phases are 120 degrees apart on the time axis. If the clock counter is determined to enter the "single-phase ground fault simulation segment", the main control core unit keeps the target fundamental amplitude and phase angle variables of phases B and C unchanged, and at the same time reads the preset fault multiple in the database, modifies the target fundamental amplitude variable of phase A to a specified multiple of the original rated value (such as increasing it to 1.5 times the rated value), and completes the target vector update for the fault condition; similarly, phases A and B can be kept unchanged and phase C can be configured, and phases A and C can be kept unchanged and phase B can be configured.

[0046] If the clock counter is determined to have entered the "fault clearing and recovery phase", the amplitude of the faulty phase will be quickly restored to the normal value to simulate the state after the circuit breaker trips.

[0047] The substation protection verification database refers to the structured data table stored in the non-volatile memory (such as Flash or solid-state drive) of the main control core unit. It is used to provide pre-arranged target waveform parameters of three-phase voltage and current that evolve over time for different substation protection verification projects. Its internal data comes from the fault simulation model data in the national or industry relay protection test standards and specifications, and is pre-written into the test device by technicians through the host computer software.

[0048] The three-phase target vector parameter set refers to a digital control target set describing the ideal waveform characteristics of phases A, B, and C within a specific time period. It includes the target fundamental amplitude and the target absolute phase angle on the time axis for each of the three phases, serving as the static expected value benchmark for the entire system's closed-loop regulation. Based on the current test item being executed, the main control core unit retrieves the data records for the corresponding time period from the database, reads the stored amplitude and angle nominal values ​​into the running variable area of ​​memory, and assigns them to the control loop as a reference benchmark.

[0049] In this embodiment, step S4, which involves comparing the real-time vector information of the substation secondary side with the three-phase target vector parameter set to obtain the independent amplitude error scalar and phase error scalar for each of the three phases, includes the following steps: Step S401: During the current time period, acquire the AC instantaneous sampling data stream output by the secondary protection device of the substation under test in real time. The substation secondary protection device is a microcomputer relay protection automation device used in the substation to automatically identify power system anomalies and drive circuit breakers to trip to protect the main equipment. The output AC instantaneous sampling data stream refers to the sequence of digital current and voltage instantaneous sampling points transmitted in real time on the internal data bus or network interface of the device, reflecting the high current and high voltage on the primary side of the substation after being proportionally converted to the secondary side. It includes the analog quantized value (such as a 16-bit or 32-bit integer) of each sampling instant, which is used by the control system to evaluate the response of the actual load on site. The acquisition process is as follows: the communication module of the test device is connected to the test port of the secondary protection device through a digital fiber optic patch cord. Using a standard power communication protocol (such as the IEC 61850 protocol), the network data packets are monitored in real time. The packaged AC instantaneous sampling point data frames are decoded at the physical layer and link layer to restore the continuous A, B, and C three-phase secondary side instantaneous voltage and current values, which are written to the memory buffer in real time to obtain the AC instantaneous sampling data stream.

[0050] The acquired instantaneous AC sampling data stream is segmented according to a set sampling window. A Fast Fourier Transform (FFT) is then performed on each segment to extract the real-time fundamental amplitude and corresponding real-time absolute phase angle of phases A, B, and C on the secondary side. First, starting with the latest sampling point, the data stream is traced back to the preset sampling window length (e.g., the number of data points corresponding to 20 milliseconds; if the sampling rate is 4kHz, this would be 80 sampling points). An independent continuous buffer is allocated in memory, and the data from these 80 points is copied into this buffer. This ensures that the data used in subsequent analysis is always a complete waveform closest to the current moment, providing a static data segment with clear time-domain boundaries and no waveform breaks for subsequent frequency domain transformation. Then, the main control core unit calls the 80 sampled data points extracted from memory. Using a radix-2 algorithm with time-decimation, it decomposes the time-domain sequence into a series of combinations of odd and even terms. After multiple levels of complex multiplication and addition butterfly operations, it finally outputs a set of complex arrays representing different frequency components, efficiently decomposing the complex instantaneous waveform in the time domain and extracting the real and imaginary parts of the 50Hz component. Finally, the real and imaginary parts of the output 50Hz component are calculated, and the sum of the squares of the real and imaginary parts is taken as the square root, then multiplied by a conversion factor to obtain the real-time fundamental amplitude. The values ​​of the imaginary and real parts are extracted, their ratio is calculated, and an arctangent operation is performed on this ratio to obtain the real-time absolute phase angle. The conversion factor is obtained from the inherent mathematical properties of the Fast Fourier Transform. According to the symmetry theorem of the Discrete Fourier Transform, the complex modulus of the output after the transform is N / 2 times the peak value of the time-domain signal waveform, where N is the number of sampled points. The conversion factor is directly provided by the underlying signal processing software of the main control unit.

[0051] The extracted real-time fundamental amplitude and real-time absolute phase angle are combined to obtain real-time vector information. Real-time vector information refers to a complex vector on the complex plane that quantitatively describes the magnitude and direction of the current power frequency voltage or current on the secondary side of the substation. As the current actual measurement value of the feedback control system, it reflects the real-time power receiving state of the secondary side of the substation under the drive of the primary side excitation source.

[0052] When setting the sampling window, ensure that the length of the sampling window is exactly an integer multiple of the fundamental period of the signal being measured, in order to avoid measurement errors caused by spectral leakage. For a 50Hz system, the fundamental period is 20 milliseconds. The general range is usually 1 to 8 fundamental periods, with a typical value of 4 periods, or 80 milliseconds. In this embodiment, 1 fundamental period, or 20 milliseconds, is used.

[0053] The real-time fundamental amplitude refers to the peak value of the sinusoidal component with a frequency of exactly 50Hz in the secondary signal at the current moment. The real-time absolute phase angle refers to the angle by which the fundamental component leads or lags behind a fixed reference cosine wave generated internally by the device and strictly synchronized with the station's synchronous clock reference.

[0054] In this embodiment, step S4, the implementation steps of obtaining the independent amplitude error scalar and phase error scalar for each of the three phases, include: Step S402: The target fundamental amplitude of each phase circuit in the three-phase target vector parameter group corresponding to the current time period is calculated by subtracting the real-time fundamental amplitude of each phase circuit in the real-time vector information to obtain the independent amplitude error scalar of each of the three phase circuits. The amplitude error scalar quantifies the difference between the current output simulated load and the target load; a positive value reflects insufficient output (needs to be increased), and a negative value reflects overshoot (needs to be reduced); for example, if the target amplitude is 50A and the real-time amplitude is 48A, then the amplitude error scalar is +2A.

[0055] The target absolute phase angle of each phase loop in the three-phase target vector parameter group is simultaneously subtracted from the real-time absolute phase angle of each phase loop in the real-time vector information to calculate the independent phase error scalar of each of the three phase loops. The phase error scalar is used to guide the controller to fine-tune the left and right offset of the sine wave on the time axis, reflecting the current phase lag or lead of the loop. When calculating, attention should be paid to the periodicity of the phase angle (e.g., -10 degrees and 350 degrees are not significantly different in reality). Normalization within ±180 degrees is usually performed first to quantify the difference between the current output simulated load "time position" and the target "time position" for lead or lag. Positive values ​​indicate that the output phase lags behind the target (lead compensation is required), while negative values ​​indicate that the output phase leads the target (lag compensation is required).

[0056] The amplitude and phase error scalars of each phase circuit are input to independent proportional resonant controllers for steady-state error-free amplification, outputting preliminary control voltage reference commands for each of the three phase circuits. The proportional resonant controller is a digital filter with an infinitely large control gain for AC signals of a specific frequency (50Hz in this scheme). Its internal architecture includes a parallel proportional element (composed of proportional gain coefficients) and an AC resonant element (composed of a second-order discrete digital bandpass filter built for the 50Hz center frequency), used to completely eliminate steady-state errors in the AC control system.

[0057] The process of zero steady-state error amplification by a proportional resonant controller is as follows: First, the input error scalar (such as the amplitude error scalar) is directly multiplied by a preset proportional gain coefficient to obtain the proportional control component. Then, the same error scalar is sent to the delay register of a second-order digital bandpass filter, and a weighted sum is performed with the historical errors and historical outputs from the previous two calculation cycles. Utilizing the filter's pole characteristics at 50Hz, an inductor-capacitor resonant energy accumulation is generated, resulting in the resonant control component. Finally, the proportional control component and the resonant control component are added together in a digital summer to output an amplified control quantity. This control quantity continues to act until the input error approaches zero, thereby achieving extremely high forward channel gain at the 50Hz power frequency and realizing zero steady-state error amplification. The proportional gain coefficient ranges from 0.5 to 10.0, with a default value of 2.0. It is adaptively adjusted based on the equivalent impedance amplitude of the circuit. When the equivalent impedance amplitude is large (e.g., greater than 10 ohms), a larger proportional gain coefficient is used to ensure sufficient response speed; conversely, a smaller value is used to prevent system oscillation.

[0058] The main control core unit uses the value of the amplitude error scalar output by the proportional resonant controller as the target amplitude, and the value of the phase error scalar output by the controller as the target phase. These two values ​​are modulated into a discrete sinusoidal voltage data stream under the current synchronous clock using a digital sine wave generator. This data stream generates the preliminary control voltage reference command. The preliminary control voltage reference command refers to the ideal nominal control quantity of the output voltage calculated solely based on the closed-loop feedback of this phase, without considering inter-phase mutual inductance interference. It includes the instantaneous amplitude and initial phase command of the target voltage, reflecting the voltage adjustment required to compensate for the phase error under ideal conditions without considering inter-phase magnetic circuit coupling interference.

[0059] In this embodiment, the implementation steps of performing cross-phase feedforward decoupling calculations based on preset inter-phase magnetic circuit mutual inductance matrix coefficients and outputting decoupling-corrected three-phase control commands in step S4 include: Step S403: Read the nameplate parameters of the main transformer under test on site, perform data mapping and combination in memory space, and initialize the phase-to-phase magnetic circuit mutual inductance matrix coefficients used to quantitatively characterize the phase-to-phase magnetic circuit coupling strength of the main transformer. The nameplate parameters include nominal parameters of the connection group (e.g., Ynd11, indicating star grounding on the high-voltage side and delta grounding on the low-voltage side, with a phase difference of 30 degrees between the high and low voltage sides) and nominal parameters of the short-circuit impedance (e.g., Uk=10.5%, indicating the percentage of short-circuit voltage). The nameplate parameters refer to the nominal technical data on the metal nameplate of the main transformer casing, used to define its inherent electromagnetic characteristics, provide boundary conditions for constructing the magnetic circuit coupling model, and reflect the physical arrangement structure and leakage magnetic impedance of the internal windings of the main transformer. These parameters are either manually read on-site and entered into the host computer, or automatically obtained by the main control core unit from the substation's equipment asset management system via a data interface.

[0060] When constructing the phase-to-phase magnetic circuit mutual inductance matrix coefficients, the main control core unit first reads the input nominal parameters of the wiring group and the nominal parameters of the short-circuit impedance; then, it determines the sign relationship of the phase-to-phase mutual inductance based on the wiring group parameters (e.g., under the Ynd11 connection, the induction of phase B by the change of current in phase A is opposite in direction to the induction in phase C); next, it estimates the magnitude of the mutual inductance based on the short-circuit impedance parameters; finally, it fills these sign relationships and estimated magnitudes into the corresponding positions of a 3x3 matrix, completing the initialization of the matrix. The phase-to-phase magnetic circuit mutual inductance matrix coefficients are second-order multivariate constant matrices used to quantitatively characterize the degree of mutual coupling and interference of magnetic flux between the phase windings inside the main transformer. They include the main self-inductance coefficient and the mutual inductance coefficients between phases AB, BC, and CA, reflecting the spatial geometric relationship and magnetic reluctance distribution of the three-phase core magnetic circuit. The matrix form of the phase-to-phase magnetic circuit mutual inductance matrix coefficients is as follows: Where M represents the mutual inductance matrix coefficients of the interphase magnetic circuit, and the diagonal elements are... , , For each phase winding, the self-inductance coefficient is denoted as ; off-diagonal elements are denoted as . , , , , , Represents the mutual inductance coefficient between phases, such as This represents the mutual inductance coefficient between phases A and B. Ideally, if the three-phase transformer core structure is perfectly symmetrical (the geometric dimensions, magnetic circuit length, and number of turns of each phase core column are identical), then the mutual inductance matrix between phases possesses symmetry, i.e. , , And the diagonal elements are equal, that is However, in actual engineering, due to factors such as the geometrical differences in the three-phase core columns (different magnetic circuit lengths between the edge phases and the middle phase), winding manufacturing tolerances, and local non-uniformity of the magnetic permeability of the core material, the matrix exhibits asymmetry, resulting in… ,and , , In this scheme, the matrix coefficients are initially estimated based on the connection group and short-circuit impedance in the nameplate parameters. For higher accuracy, the matrix coefficients can be adaptively corrected through online parameter identification during system operation. For example, a 10MVA, 35kV / 10.5kV, Ynd11 connected three-phase oil-immersed power transformer is used as an example. The unit is Henry (H), where the self-inductance is about 11.5 to 12.2H and the mutual inductance is about 0.5 to 1.2H. The sign depends on the wiring group (e.g., in the Ynd11 wiring, the current change of phase A induces phase B in the opposite direction to the current change of phase C). The specific sign relationship is determined by the wiring group parameters.

[0061] The instantaneous AC current value of the three-phase circuit leads at the primary side physical output terminal of the test device is acquired in real time. Based on the instantaneous AC current value, the real-time rate of change of the three-phase lead current is calculated. The real-time rate of change refers to the instantaneous rate of change of the output current of the measured phase (e.g., phase A) per unit time. It provides the core input quantity for calculating the interphase mutual inductance electromotive force and reflects the drastic degree of current change in that phase. The real-time rate of change is acquired at the beginning of the current control cycle and calculated based on the final output current value of the previous cycle. It is used to predict the feedforward compensation quantity of the current cycle. The calculation process is as follows: the main control core unit acquires the instantaneous current signal from the Rogowski coil at a sampling rate of not less than 1MHz (i.e., the sampling period is not greater than 1 microsecond); then, within a very short time window (e.g., 10 microseconds), the current value at the end of the window is subtracted from the current value at the beginning of the window, and then divided by the window duration (10 microseconds). The quotient is the real-time rate of change of that phase. This calculation is repeated in each sampling cycle. The primary side of the test device refers to the physical high-power circuit (such as the filtered lead section of the inverter bridge output) that directly outputs high-power, power frequency AC test current. It is used to inject high-power load current into the main transformer of the substation. The instantaneous value of the output AC current is acquired in real time by a high-precision through-core Hall current sensor connected in series on the lead. This data is used to provide real-time dynamic independent variables for feedforward control and reflects the transient intensity of the current evolution over time in the primary side circuit.

[0062] The real-time rate of change of the three-phase lead current is used as an input vector, and matrix multiplication is performed with the initially configured interphase magnetic circuit mutual inductance matrix coefficients to calculate the predicted scalar of the induced back electromotive force generated on the primary windings of other adjacent non-regulated phases due to the current change in the current of the current-regulated phase. According to Faraday's law of electromagnetic induction, the induced electromotive force is proportional to the product of the mutual inductance coefficient and the rate of change of current. During matrix multiplication, the main control core unit first combines the real-time rate of change of the lead currents of phases A, B, and C into a 3x3 input column vector. Then, the constructed 3x3 interphase magnetic circuit mutual inductance matrix coefficients are multiplied by this input column vector using a standard row-to-column summation operation (matrix multiplication), outputting a 3x3 result column vector containing three elements. Finally, these three elements are mapped to the predicted scalar of the induced back electromotive force for each of the phases A, B, and C circuits. The induced back electromotive force prediction scalar refers to the false voltage prediction value induced on the current phase winding by the iron core magnetic circuit due to the dynamic changes of adjacent phase currents, which interferes with the independent adjustment of this phase. It includes the induced voltage amplitude and polarity calculated for each phase, and is used as a feedforward compensation quantity to cancel physical electromagnetic interference, reflecting the strength of interphase cross interference.

[0063] The predicted scalar value of the induced back EMF is used as the feedforward control voltage, and injected into the preliminary control voltage reference command of the adjacent non-regulated phase with opposite polarities to generate the decoupled and corrected three-phase control command. The main control core unit takes the mathematical inverse of the predicted scalar value of the induced back EMF of each phase, that is, reverses the polarity by 180 degrees, to form the feedforward compensation voltage; then, the feedforward compensation voltage is digitally superimposed and injected into the preliminary control voltage reference command of the corresponding phase generated in step S402. Through addition and subtraction operations, the decoupled and corrected three-phase control command is generated. The final control voltage commands of the A, B, and C phases after feedforward decoupling and correction are converted into independent sinusoidal pulse width modulation (SPWM) signals to drive the corresponding independent excitation sources of the A, B, and C phases, realizing the precise adjustment of the analog load output vector of each phase.

[0064] In this embodiment, step S5, the implementation steps of flexibly controlling the three-phase target vector parameter group through a preset flexible transition window when switching time periods, include: Step S501: When switching time periods, a flexible transition window of a preset duration is set. At the instant the operating condition switching control command is issued, the flexible transition window of the preset duration is started in the internal time counter, and the current running time within the transition window is acquired in real time. The flexible transition window is set based on the transient overvoltage time constant (i.e., component energy release cycle) generated by the winding inductance during a step switching of operating conditions. The typical setting range is 10 milliseconds to 100 milliseconds. In this embodiment, the specific setting is 40 milliseconds, which is exactly two full-cycle power frequency cycles, achieving a smooth transition without causing an excessively long switching process. The preset duration is consistent with the lifespan of the flexible transition window, set to 40 milliseconds. The current running time is read in real time from the high-precision hardware timer register inside the main control core unit. This timer is reset to zero and triggers a high-frequency self-incrementing count the instant the operating condition switching control command is received. The read count value multiplied by the crystal oscillator period is the current running time.

[0065] The ratio of the current running time to the preset duration is calculated to obtain the dynamic growth coefficient, and then the dynamic decay coefficient is obtained by subtracting the dynamic growth coefficient from the numerical value. The dynamic growth coefficient is a dimensionless value that linearly increases from 0 to 1 within the transition window, reflecting the physical establishment progress of the new operating condition waveform; the dynamic decay coefficient is a dimensionless value that linearly decays from 1 to 0. They serve as digital levers for control weights, reflecting the physical blanking progress of the old operating condition waveform. A real-time quotient is calculated based on the current running time and the preset duration (40 milliseconds), and this quotient is used as the dynamic growth coefficient; subsequently, the dynamic decay coefficient is obtained by linearly subtracting the growth coefficient from the numerical value 1.

[0066] Within a flexible transition window, the three-phase target vector parameter group of the old operating condition is flexibly blanked to obtain the old vector with flexible blanking. All amplitude and phase data in the old three-phase target vector parameter group corresponding to the current test time period are multiplied by a dynamic attenuation coefficient, so that the magnitude of the old vector shrinks linearly to complete the flexible blanking. The three-phase target vector parameter group of the synchronous control new operating condition is flexibly established to obtain the established new vector; all amplitude and phase data in the new three-phase target vector parameter group corresponding to the next test time period are multiplied by the dynamic growth coefficient, so that the new vector expands linearly outward from zero to complete the flexible establishment.

[0067] In step S502, the old vector after flexible blanking is superimposed with the newly established vector to synthesize a temporary flexible control target parameter set, which is then used as the input source for the current moment and transferred to the proportional resonant controller in real time.

[0068] When performing vector superposition, the main control core unit first transforms the old vector after flexible blanking into real and imaginary parts in the complex space; then, it synchronously transforms the newly established vector into the corresponding real and imaginary parts; then, it algebraically adds the real parts of the old vector and the real parts of the new vector to obtain a temporary real part; it algebraically adds the imaginary parts of the old vector and the imaginary parts of the new vector to obtain a temporary imaginary part; finally, it resynthesizes the temporary real parts and the temporary imaginary parts into a new complex vector, that is, it synthesizes a temporary flexible control target parameter set, which realizes a smooth physical connection between two independent operating conditions in the complex frequency domain and eliminates the inflection point of abrupt waveform changes.

[0069] The temporary flexible control target parameter set refers to a set of transient control target complex parameters that are generated by the superposition of old and new vectors during the validity period of the transition window and evolve dynamically over time. These parameters include the instantaneous synthetic equivalent amplitude and synthetic equivalent phase, which temporarily replace the static target vector as the input source. After generating this parameter set, the main control core unit no longer reads the static target from the original database. Instead, it continuously inputs the temporary flexible control target parameter set to the setpoint input terminal of the proportional resonant controller in step S402, with the current control interruption cycle as the frequency. This directly replaces the original target variable in the error difference calculation until the 40-millisecond transition window is completely closed and the dynamic growth coefficient reaches 1. At this point, the system automatically switches back to the static control of the new operating condition.

[0070] In this embodiment, in actual use, the system must at least include the following high-power and low-voltage signal processing hardware devices in its physical architecture: The main control core unit adopts a high-performance digital signal processor (DSP) or programmable gate array (FPGA) as the latch for the whole station synchronous clock reference, the calculation core for Fourier transform, and the computing carrier for feedforward decoupling and flexible transition window algorithms.

[0071] The three-phase independent inverter power bridge cabinet, also known as the three-phase independent excitation source, consists of three completely independent single-phase full-bridge inverter circuits (including IGBT power switching transistors and isolation drive circuits). The input terminal is connected to the DC bus, and the output terminal is independently connected to the primary side circuit of the substation.

[0072] The reactive power compensation circuit capacitor bank includes multiple sets of power capacitor banks configured in binary ratios, thyristor switching (TSC) switches, and decoding drive boards; it receives capacitor encoding instructions from the main control unit and is physically connected to the three-phase circuit.

[0073] The high-frequency signal sampling and conditioning module includes a resistor voltage divider network (voltage measurement) connected in parallel at the output, a series Hall current sensor (current measurement), a low-pass anti-aliasing filter, and a multi-channel synchronous analog-to-digital converter (ADC) to provide time-domain digital streams to the main control core.

[0074] The digital fiber optic communication interface module is used to establish communication with the secondary protection devices in the substation through physical fiber optic patch cords, and to intercept and capture the instantaneous AC sampling data stream on the secondary side in real time based on standard power protocols (such as IEC 61850).

[0075] Furthermore, in its specific implementation, the technology and software used in this invention rely on the software architecture of modern computers / embedded systems for logical implementation. The key technologies and corresponding software implementation methods are as follows: Time-frequency domain conversion and Fast Fourier Transform (FFT) technology: Based on embedded C language, it can utilize existing high-level signal processing mathematical libraries (such as the Cortex-M or CMSIS-DSP library of the DSP standard); in the software code, it can directly call ready-made complex fast Fourier transform functions (such as arm_cfft_f32). After compilation, the function runs through the Single Instruction Multiple Data (SIMD) hardware instruction set, directly performing butterfly summation on the truncated sample array, thereby solving the fundamental component in microseconds, avoiding the need to manually write low-level algorithms.

[0076] Matrix multiplication and feedforward decoupling technology: Utilizing the linear algebra arithmetic library in computer software, a two-dimensional floating-point array is defined in the software initialization code of the main control core to map the mutual inductance matrix coefficients constructed from the nameplate parameters; in the real-time control loop, the general matrix multiplication function is called to perform row multiplication and column weighted summation of the current current change rate column vector with the two-dimensional array, and the software logic directly outputs the predicted induced electromotive force.

[0077] Substation protection verification timing database technology: At the system software layer of the test device, a lightweight embedded database system (such as SQLite software or structured file mapping technology) can be used; by writing SQL query statements or structure pointer addressing in the software, according to the progress instructions of the test project, the preset three-phase amplitude and angle configuration records are automatically read across rows within a specific clock interruption and transferred to the running memory.

[0078] Proportional Resonance (PR) control technology: Based on automatic control theory, it is implemented using software methods that process first- / second-order difference equations. In the timer interrupt service routine of the main control unit, the transfer function in the control theory is discretized into an algebraic difference equation with respect to the current error, historical error, and the control output at the previous moment through bilinear transformation. In software, only a few lines of simple addition and multiplication code are needed to update the register state, and the initial control voltage reference command can be output through software iteration.

[0079] In practical use, in addition to the aforementioned hardware and software, corresponding hardware and software technologies can be selected and adjusted according to actual usage needs to achieve the technical solution content of this application.

[0080] In this embodiment, by introducing a cross-phase feedforward decoupling calculation method at the weak current level, the interference bottleneck caused by the inherent interphase magnetic circuit coupling of the main transformer core in the substation is completely overcome. In the simulated load regulation process of the current time period, not only is the amplitude and phase error scalar amplified without steady-state error using a proportional resonant controller, but the instantaneous value of the AC current of the physical output terminal lead of the primary side of the test device is also collected in real time and its rate of change is calculated. By performing matrix multiplication with the phase magnetic circuit mutual inductance matrix coefficients that are initialized and quantitatively characterize the interphase magnetic circuit coupling strength of the main transformer, the predicted scalar of the induced back electromotive force on the adjacent non-regulated phase is accurately and quantitatively analyzed. This scalar is used as the feedforward control voltage quantity and dynamically injected into the control voltage reference command of the adjacent phase with opposite polarity. The reverse suppression excitation voltage is actively applied on the physical line, eliminating interphase interference. This invention realizes true complete decoupling and independent control of three-phase high-power output, thereby ensuring the high accuracy of the secondary side output when the simulated load of the whole station is independently regulated by a single phase.

[0081] This invention proposes a vector flexible blanking and establishment superposition control based on a time-series transition window for the transient boundary section of multi-condition automated switching, fundamentally eliminating the safety hazards of transient overvoltage in off-grid conditions. When the test timing changes over a period of time, the main control core unit no longer executes a step-type hard switching command, but instead dynamically calculates the linearly decreasing dynamic attenuation coefficient and the linearly increasing dynamic growth coefficient in real time within a preset flexible transition window based on the current running time. These two coefficients are used to perform flexible blanking processing on the three-phase target vector parameter group of the old condition and flexible establishment processing on the three-phase target vector parameter group of the new condition. Finally, the blanked old vector and the established new vector are vector superimposed in the complex space to synthesize a smoothly evolving temporary flexible control target parameter group and flow to the regulation closed loop. This process limits the amplitude change rate and phase continuity, realizing a smooth transition of fully automatic simulated load conditions without transient voltage and current impacts, ensuring the safety of primary and secondary equipment in the station.

[0082] This application also provides an electronic device. The electronic device may include one or more processors and one or more memories. The memories store computer-readable code that, when executed by the one or more processors, can perform the substation simulated load flexible regulation method based on single-phase independent control as described above.

[0083] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 Units that specify functions within one or more boxes.

[0084] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for flexible load regulation of substations based on single-phase independent control, characterized in that, The method includes: Step S1: Control the three-phase independent excitation source to perform independent impedance characteristic identification on the three-phase circuits of the substation, and analyze the equivalent resistance component and equivalent inductive reactance component of each of the three-phase circuits. Step S2: Calculate the compensation capacitor value of each phase at the rated frequency based on the equivalent resistance component and the equivalent inductive reactance component. After switching the capacitor based on the compensation capacitor value, determine whether the hardware circuit tuning is completed. Step S3: After completing the hardware loop tuning, construct a simulated load target sequence consisting of multiple consecutive time periods. The simulated load target sequence includes a three-phase target vector parameter set corresponding to each time period. Step S4: In the current time period, the real-time vector information of the secondary side of the substation is obtained and compared with the three-phase target vector parameter group to obtain the independent amplitude error scalar and phase error scalar of each of the three phases. Combined with the preset interphase magnetic circuit mutual inductance matrix coefficient, cross-phase feedforward decoupling calculation is performed, and the decoupling corrected three-phase control command is output. Based on the three-phase control command, the three-phase independent excitation source is driven to output the simulated load. Step S5: When switching time periods, the three-phase target vector parameter group is flexibly controlled through a preset flexible transition window.

2. The method according to claim 1, characterized in that, In step S1, the control of the three-phase independent excitation source to independently identify the impedance characteristics of the three-phase circuits of the substation includes: The three-phase circuit of the substation includes phase A circuit, phase B circuit and phase C circuit, and the three-phase independent excitation source includes phase A independent excitation source, phase B independent excitation source and phase C independent excitation source; The A-phase independent excitation source is controlled to output a sinusoidal detection signal with a preset frequency and low amplitude to the primary circuit of the substation, while the output of the B-phase and C-phase independent excitation sources is blocked simultaneously. The instantaneous voltage and instantaneous current signals of the A-phase circuit at the output end are collected online. Perform Discrete Fourier Transform on the instantaneous voltage signal and instantaneous current signal to calculate and separate the fundamental voltage amplitude, fundamental current amplitude, and phase difference angle between voltage and current of the A-phase circuit; By sequentially blocking the current phase and opening the next phase, and through the same control and analysis process, the fundamental voltage amplitude, fundamental current amplitude, and corresponding phase difference angle of the B-phase circuit and the C-phase circuit are calculated respectively.

3. The method according to claim 2, characterized in that, In step S1, the analysis of the equivalent resistance and equivalent inductive reactance components of each of the three-phase circuits includes: Divide the fundamental voltage amplitude of each phase obtained from the analysis by the corresponding fundamental current amplitude to calculate the equivalent impedance amplitude of each of the three phase circuits. By combining the phase difference angle of each phase circuit, the corresponding equivalent impedance amplitude is orthogonally decomposed in the impedance space, and the equivalent resistance component and equivalent inductive reactance component of each phase circuit (A, B, and C) are independently extracted.

4. The method according to claim 3, characterized in that, In step S2, after switching the capacitor based on the compensation capacitor value, determining whether hardware circuit tuning is complete includes: Obtain the rated angular frequency of the current test power supply, and calculate the compensation capacitor values ​​required for each of the A-phase circuit, B-phase circuit, and C-phase circuit by combining the equivalent inductive reactance component. The compensation capacitor value is converted into a capacitor encoding instruction and sent to the reactive power compensation circuit to change the capacitance of each phase circuit physically connected to the circuit, so that the A phase circuit, B phase circuit and C phase circuit can independently reach the preset resonance state on the physical line.

5. The method according to claim 4, characterized in that, The determination of whether hardware circuit tuning is complete includes: After the capacitor switching is completed in the reactive power compensation circuit, the fundamental voltage amplitude and fundamental current amplitude at the output terminal of each phase circuit are collected in real time, and the real-time power factor of each phase circuit after tuning is calculated. The real-time power factor of each of the three-phase circuits is compared with the preset factor threshold. If the real-time power factor of all three phases is greater than or equal to the preset factor threshold, the test lockout is released, a physical circuit ready state word is generated, and the current power frequency is latched as the station synchronization clock reference.

6. The method according to claim 5, characterized in that, In step S3, constructing the simulated load target sequence consisting of multiple consecutive time periods includes: Using the station-wide synchronous clock reference as the basic step size for evolution, the time axis is sequentially divided into multiple different test time periods; A three-phase target vector parameter group is configured for each test time period. The three-phase target vector parameter group includes the target fundamental amplitude and target absolute phase angle of each of the A-phase circuit, B-phase circuit and C-phase circuit.

7. The method according to claim 6, characterized in that, In step S4, the real-time vector information of the substation secondary side is compared with the three-phase target vector parameter set to obtain the independent amplitude error scalar and phase error scalar for each of the three phases, including: During the current time period, the AC instantaneous sampling data stream output by the secondary protection device of the substation under test is acquired in real time. The acquired instantaneous AC sampling data stream is segmented according to the set sampling window, and the segmented instantaneous AC data is processed by Fast Fourier Transform to separate and extract the real-time fundamental amplitude and corresponding real-time absolute phase angle of phase A, phase B, and phase C on the secondary side. The real-time fundamental amplitude and real-time absolute phase angle extracted separately are combined to obtain real-time vector information.

8. The method according to claim 7, characterized in that, The process of obtaining independent amplitude error scalars and phase error scalars for each of the three phases includes: The target fundamental amplitude of each phase circuit in the three-phase target vector parameter group corresponding to the current time period is calculated by subtracting the real-time fundamental amplitude of each phase circuit in the real-time vector information to obtain the independent amplitude error scalar of each of the three phase circuits. The target absolute phase angle of each phase loop in the three-phase target vector parameter group is simultaneously subtracted from the real-time absolute phase angle of each phase loop in the real-time vector information to calculate the independent phase error scalar of each of the three phase loops. The amplitude error scalar and phase error scalar of each phase circuit are respectively input to independent proportional resonant controllers for zero steady-state error amplification, and the initial control voltage reference commands of each of the three phase circuits are output.

9. The method according to claim 8, characterized in that, In step S4, the cross-phase feedforward decoupling calculation is performed by combining the preset interphase magnetic circuit mutual inductance matrix coefficients, and the three-phase control command after decoupling correction is output, including: Read the nameplate parameters of the main transformer under test on site, and initialize and construct the phase-to-phase magnetic circuit mutual inductance matrix coefficients; the nameplate parameters include the nominal parameters of the connection group and the nominal parameters of the short-circuit impedance; The instantaneous value of AC current in the three-phase circuit leads at the physical output terminal of the primary side of the test device is acquired in real time, and the real-time rate of change of the three-phase lead current is calculated based on the instantaneous value of AC current. The real-time rate of change of the three-phase lead current is used as the input vector, and matrix multiplication is performed with the coefficients of the phase-to-phase magnetic circuit mutual inductance matrix configured in the initialization to calculate the scalar of the induced back electromotive force. The predicted scalar of the induced back electromotive force is used as the feedforward control voltage quantity and injected into the preliminary control voltage reference command of the adjacent non-regulated phase with opposite polarities to generate the decoupled and corrected three-phase control command.

10. The method according to claim 9, characterized in that, In step S5, when switching time periods, the three-phase target vector parameter group is flexibly controlled through a preset flexible transition window, including: When switching time periods, a flexible transition window of preset duration is set. Within the flexible transition window, the three-phase target vector parameter group of the old operating condition is flexibly blanked to obtain the old vector with flexible blanking. Simultaneously, the three-phase target vector parameter group of the new operating condition is flexibly established to obtain the new vector after establishment. The old vector after flexible blanking is superimposed with the newly established vector to synthesize a temporary flexible control target parameter set, which is then used as the input source for the current moment and transferred to the proportional resonant controller in real time.

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