A minimalist passive multi-path power seamless switching system

Abstract

The application discloses a kind of minimal passive multipath power seamless switching system, including power supply V1, power supply V2, power supply V3, MOS tube Q1, MOS tube Q2, MOS tube Q3, MOS tube Q4, MOS tube Q5, MOS tube Q6, MOS tube Q7, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and resistance R6;Three-way power supply is according to main secondary classification, power supply V1 priority is highest, second power supply V2, power supply V3 again.This application has the characteristics of simple circuit, high reliability, low cost, even if the load appears too heavy, steady voltage normal work, will not suddenly load power too big, not to suddenly power off damage to the load or damage chip etc..Can realize the effect of preventing reverse connection;When the abnormality of rear load, such as accident, Vout output is higher than input, this scheme can also be realized from system design to prevent the possibility of damage caused by backflow to power itself.

Description

Technical Field

[0001] This invention belongs to the field of multi-power switching technology, specifically relating to a minimalist passive multi-power seamless switching system. Background Technology

[0002] In existing technologies, multi-power supply systems with more than two power sources primarily rely on chips to monitor and control the different power sources to achieve power switching. Currently, the most common approach is a dual-power switching system, which uses a switching circuit to switch between an external power source and an internal power source. While relatively simple, dual-power switching systems have limited scalability. Furthermore, in terms of circuit implementation, external USB power supplies typically provide 5V, while batteries provide 4.2V, leading to voltage differences. For multi-power supply systems where the input and output are identical (i.e., all power sources have the same input voltage), multi-power switching is generally achieved through chips, manual switches, or chip-controlled switches, resulting in a complex structure. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a minimalist passive multi-channel power seamless switching system that effectively solves the aforementioned problems.

[0004] The technical solution adopted in this invention is as follows:

[0005] This invention provides a minimalist passive multi-power seamless switching system, including power supplies V1, V2, and V3; MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, and Q7; and resistors R1, R2, R3, R4, R5, and R6. MOSFETs Q1, Q2, Q3, and Q7 are NMOS transistors; while MOSFETs Q4, Q5, and Q6 are PMOS transistors.

[0006] The output port of power supply V1 is connected to the drain (D) terminal of MOSFET Q5, the source (S) terminal of MOSFET Q5 is connected to the drain (D) terminal of MOSFET Q6, and the source (S) terminal of MOSFET Q6 is connected to the system output side, forming the power supply branch of power supply V1.

[0007] The output port of power supply V2 is connected to the drain (D) terminal of MOSFET Q4. The source (S) terminal of MOSFET Q4 is connected to the source (S) terminal of MOSFET Q5 and the drain (D) terminal of MOSFET Q6, respectively, so that the power supply branch of power supply V2 is connected to the power supply branch of power supply V1.

[0008] The output port of power supply V3 is connected to the source (S) terminal of MOSFET Q3, and the drain (D) terminal of MOSFET Q3 is connected to the system output side, forming the power supply branch of power supply V3.

[0009] The output port of power supply V1 is also connected to the gate of MOSFET Q7. The drain of MOSFET Q7 is connected to GND, and the source of MOSFET Q7 is connected to the gate of MOSFET Q5 to control the on / off state of MOSFET Q5.

[0010] The output port of power supply V1 is also connected to resistor R5 to GND and to the gate of MOSFET Q4 to control the on / off state of MOSFET Q4; the gate of MOSFET Q4 is also connected to resistor R5 to GND.

[0011] The output port of power supply V1 is also connected to the gate of MOSFET Q1 to control the on / off state of MOSFET Q1; the drain of MOSFET Q1 is connected to resistor R1 to GND, and the source of MOSFET Q1 is simultaneously connected to the source of MOSFET Q2, the gate of MOSFET Q3, and the gate of MOSFET Q6 through resistor R6 to control the on / off state of MOSFET Q3 and MOSFET Q6; resistor R6 is also connected to the gate of MOSFET Q3.

[0012] The output port of power supply V2 is also connected to the gate of MOSFET Q2 to control the on / off state of MOSFET Q2; the drain of MOSFET Q2 is connected to resistor R2 to GND, and the source of MOSFET Q2 is connected to the gate of MOSFET Q3 and the gate of MOSFET Q6 through resistor R6 to control the on / off state of MOSFET Q3 and MOSFET Q6.

[0013] The output port of power supply V3 is also grounded through a voltage divider between resistors R3 and R4.

[0014] Furthermore, the power supply voltage VCC of power supplies V1, V2, and V3 is the same.

[0015] Furthermore, the resistance values ​​of resistors R1, R2, and R5 are all 1MΩ; the resistance values ​​of resistors R3, R4, and R6 are all 10MΩ.

[0016] The minimalist passive multi-power seamless switching system provided by this invention has the following advantages:

[0017] (1) Suitable for all fields with multi-power supply equipment, it features extremely simple circuit, high reliability and low cost. In the case of instantaneous overload, the other power supplies will automatically turn on to help the main power supply to power the downstream circuit. If the downstream load returns to normal, the other two power supplies will automatically turn off, providing a guarantee for the circuit in extreme cases. Even when the load is too heavy, the voltage will be stabilized and the circuit will work normally. There will be no sudden power loss, so as not to damage the downstream load or the chip, etc.

[0018] (2) It can prevent reverse connection. When the power supply and GND are reversed, there is no risk of burning out the device. Directly reversing the connection in this system will have no effect and will not damage the subsequent circuits or other devices such as chips.

[0019] (3) When the downstream load is abnormal, such as an accident, and the Vout output is higher than the input, this solution can also prevent the backflow from causing possible damage to the power supply itself from the system design. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 The circuit diagram of the minimalist passive multi-channel power seamless switching system provided by the present invention. Detailed Implementation

[0022] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0023] The circuit principle is explained briefly below:

[0024] In this invention, the circuit can operate with a single power supply V1. For ease of explanation, it can be assumed that the minimum system output voltage Vout for normal module operation is 5V, normally provided by power supply V1. Additionally, there are two other power supplies, V2 and V3, for subsequent protection. Under normal circumstances, power supply V1 alone is sufficient to allow the circuit to operate normally. Power supplies V2 and V3, due to the reverse isolation of the MOSFETs, will not input positive voltage into the circuit.

[0025] In this circuit system, the three power supplies are ranked according to their priority, with power supply V1 having the highest priority, followed by power supply V2, and then power supply V3.

[0026] Under normal operating conditions, as long as power supply V1 is present, regardless of the states of power supply V2 and power supply V3, the system output voltage Vout is provided by power supply V1, including the following typical cases:

[0027] First, when power supply V1 is present, and power supply V2 and power supply V3 are also present, power supply V1 will automatically prioritize supplying Vout output.

[0028] Second, when power supply V1 is present, power supply V2 is absent, and power supply V3 is present. Power supply V1 automatically prioritizes supplying Vout output, while V3 is the backup.

[0029] Third, when power supply V1 and power supply V2 are present and power supply V3 is absent, power supply V1 will automatically prioritize supplying Vout output, with V2 as a backup.

[0030] Of course, if power supply V1 exists and power supplies V2 and V3 disappear, then power supply V1 will inevitably supply Vout output.

[0031] If power supply V1 disappears, and power supplies V2 and V3 are present, power supply V2 will automatically prioritize supplying Vout output, while power supply V3 will be the backup.

[0032] In this invention, the power switching system also has the following characteristics:

[0033] When power supply V1 supplies power to the downstream stage, if a sudden large load current occurs, the excessive load current will pull down the Vout voltage. When the output voltage Vout is more than 1V lower than the input voltage, it may cause various ICs to malfunction due to voltage instability. At this time, power supply V2 or power supply V3 can automatically take over with the help of the body diode. Power supply V2 prioritizes supplying power to the downstream load. If power supply V2 temporarily has no voltage or is damaged, power supply V3 will automatically take over to provide multiple protections for the downstream stage. When the large current of the downstream load disappears, power supply V2 or power supply V3 will also automatically shut down due to insufficient voltage difference of the MOSFET, and the system will resume supplying power to the downstream stage via power supply V1. Because the system switches seamlessly and automatically, there is no power-off and power-on process, which effectively protects the normal operation of the circuit and improves the system or user experience.

[0034] Please see Figure 1 The circuit connection structure of the minimalist passive multi-source seamless power switching system of the present invention is as follows:

[0035] The minimalist passive multi-power seamless switching system includes power supply V1, power supply V2, power supply V3, MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7, resistors R1, R2, R3, R4, R5, and R6.

[0036] Power supplies V1, V2, and V3 serve as three power inputs, while Vout serves as the system output, providing operating voltage to the downstream load.

[0037] Assuming all three power supplies are 5V during operation (though any voltage value is acceptable, we'll assume 5V for easier analysis of each stage of the system), we'll leave it as is.

[0038] Among them, MOSFETs Q1, Q2, Q3, and Q7 are NMOS transistors; MOSFETs Q4, Q5, and Q6 are PMOS transistors; NMOS transistors are turned on at high level; PMOS transistors are turned on at low level.

[0039] The output port of power supply V1 is connected to the drain (D) terminal of MOSFET Q5, the source (S) terminal of MOSFET Q5 is connected to the drain (D) terminal of MOSFET Q6, and the source (S) terminal of MOSFET Q6 is connected to the system output side, forming the power supply branch of power supply V1.

[0040] The output port of power supply V2 is connected to the drain (D) terminal of MOSFET Q4. The source (S) terminal of MOSFET Q4 is connected to the source (S) terminal of MOSFET Q5 and the drain (D) terminal of MOSFET Q6, respectively, so that the power supply branch of power supply V2 is connected to the power supply branch of power supply V1.

[0041] The output port of power supply V3 is connected to the source (S) terminal of MOSFET Q3, and the drain (D) terminal of MOSFET Q3 is connected to the system output side, forming the power supply branch of power supply V3.

[0042] The output port of power supply V1 is also connected to the gate of MOSFET Q7. The drain of MOSFET Q7 is connected to GND, and the source of MOSFET Q7 is connected to the gate of MOSFET Q5 to control the on / off state of MOSFET Q5.

[0043] The output port of power supply V1 is also connected to resistor R5 to GND and to the gate of MOSFET Q4 to control the on / off state of MOSFET Q4; the gate of MOSFET Q4 is also connected to resistor R5 to GND.

[0044] The output port of power supply V1 is also connected to the gate of MOSFET Q1 to control the on / off state of MOSFET Q1; the drain of MOSFET Q1 is connected to resistor R1 to GND, and the source of MOSFET Q1 is simultaneously connected to the source of MOSFET Q2, the gate of MOSFET Q3, and the gate of MOSFET Q6 through resistor R6 to control the on / off state of MOSFET Q3 and MOSFET Q6; resistor R6 is also connected to the gate of MOSFET Q3.

[0045] The output port of power supply V2 is also connected to the gate of MOSFET Q2 to control the on / off state of MOSFET Q2; the drain of MOSFET Q2 is connected to resistor R2 to GND, and the source of MOSFET Q2 is connected to the gate of MOSFET Q3 and the gate of MOSFET Q6 through resistor R6 to control the on / off state of MOSFET Q3 and MOSFET Q6.

[0046] The output port of power supply V3 is also grounded through a voltage divider between resistors R3 and R4.

[0047] In this invention, power supplies V1, V2, and V3 all have the same power supply voltage VCC. Resistors R1, R2, and R5 all have a resistance of 1 MΩ; resistors R3, R4, and R6 all have a resistance of 10 MΩ. It should be emphasized that this invention does not limit the resistance values ​​of the resistors; the description here is merely an example.

[0048] Let's analyze the specific details of how the circuit works:

[0049] The minimalist passive multi-source seamless power switching system of the present invention has the following four significant operating characteristics:

[0050] The first operating characteristic: The three power supplies have a priority order:

[0051] In this invention, the operation of each power supply has a priority order, combined with... Figure 1 The following seven situations will be discussed in detail:

[0052] 1. When power supplies V1, V2, and V3 are present simultaneously, the system output voltage is the voltage provided by power supply V1:

[0053] Power supply V1 is connected to the gate of Q7. Since Q7 is an NMOS, it is turned on when the level is high. Therefore, power supply V1 turns on Q7, and the source and drain of Q7 are connected. The drain is grounded, so the source of Q7 is pulled low to GND. At the same time, the source of Q7 is connected to the gate of Q5, and the gate of Q5 is pulled low to GND. Since Q5 is a PMOS, it is turned on when the level is low. So, because the gate of Q5 is pulled low to GND, the PMOS of Q5 is turned on, and the source and drain of Q5 are connected.

[0054] Power supply V1 is connected to both resistor R5 to GND and the PMOS gate of Q4. Therefore, because of the presence of power supply V1, Q4 cannot be turned on; thus, the drain and source terminals of Q4 cannot be turned on.

[0055] Power supply V1 is also connected to the gate of Q1. Q1 is an NMOS, so Q1 is turned on. After the source and drain of Q1 are turned on, the source is grounded through the drain via resistor R1, and the source is pulled low. The source of Q1 is connected to the gate of Q6 through resistor R6. Q6 is a PMOS, so Q6 is turned on.

[0056] In this way, power supply V1 first passes through the conducting Q5, and then through the conducting Q6, and is output to Vout;

[0057] Looking back at power supply V2, it is connected to the gate of Q2. Q2 is an NMOS transistor, so its source (S) and drain (D) are conducting. Since the drain of Q2 is grounded through resistor R2, the source of Q2 is pulled low to GND. The source of Q2 is connected to resistor R6 to the gate of Q6. One end of resistor R6 is pulled low to GND by the conducting Q2. This is equivalent to resistor R6 being pulled low to GND by both Q1 and Q2, so Q6 is conducting.

[0058] Looking back at power supply V3, because the gate of Q3 is pulled low to GND after being turned on by Q1 and Q2, Q3 cannot properly control the conduction of the MOS.

[0059] Note the orientation of the body diodes of Q4 and Q3: Although it appears that power supplies V2 and V3 can conduct the body diodes of Q4 and Q3 respectively, note that power supplies V1, V2, and V3 have the same voltage. The voltage difference between the body diodes is about 1V. Because the voltage values ​​of power supplies V1, V2, and V3 are the same, there cannot be a voltage difference. Therefore, power supply V2 cannot be conducted to the other end through the body diode of Q4, and power supply V3 cannot be conducted to the other end through the body diode of Q3. Thus, in this case, power supply V1 is supplying power to Vout.

[0060] 2. When power supplies V1 and V2 exist, and power supply V3 is 0, the output is power supply V1:

[0061] Because of the presence of power supply V1, Q7 and Q5 are turned on, and power supply V1 suppresses the conduction of Q4. Since power supply V1 is connected to the gate of Q1 and power supply V2 is connected to the gate of Q2, after the NMOS of Q1 and Q2 are turned on, they are connected to ground by a resistor. The source of both Q1 and Q2 is pulled low. Since they are both connected to the gate of Q6 through resistor R6, the PMOS of Q6 can conduct normally. Therefore, power supply V1 can output Vout. Since power supply V3 is 0, Q3 is not turned on. So the total output is power supply V1.

[0062] Note that the body diodes of Q4 and Q3 are reversed, so power supply V1 cannot flow back to power supply V2 because the voltage difference between power supply V1 and power supply V2 is the same; power supply V1 also cannot flow back to power supply V3, even though V3 is 0, the body diode prevents it from flowing in the opposite direction.

[0063] Therefore, in this case, power supply V1 is supplying power to Vout.

[0064] 3. When power supplies V1 and V3 exist, and power supply V2 is 0, the output is power supply V1:

[0065] Because of the presence of power supply V1, Q4 cannot be turned on. Power supply V2 is 0, so Q2 cannot be turned on. However, Q1 is turned on because of the presence of power supply V1. The source of Q1 is pulled low to GND, so the voltage of resistor R6 is 0. Q6 is turned on because of the PMOS, while Q3 cannot be turned on because of the NMOS. Therefore, the output is still V1.

[0066] Note that the body diode of Q3 is forward-biased, and there is voltage in power supply V3. However, since the voltage values ​​of power supply V3 and power supply V1 are the same, there is no voltage difference exceeding 1V. Therefore, the body diode of Q3 cannot be turned on, so power supply V3 will not output to Vout.

[0067] 4. When power supplies V2 and V3 exist, and power supply V1 is 0, the output is power supply V2:

[0068] When power supply V1 is 0, Q7 is not conducting, the gate of Q5 is disconnected from GND, and Q5 is not conducting. Because the gate of Q4 is connected to resistor R5, it is pulled to GND, so Q4 is conducting. Power supply V2 has a normal voltage, so Q2, being an NMOS transistor, is conducting. After Q2 conducts, resistor R6 is pulled low to GND. Although Q1 cannot conduct because power supply V1 is 0, this does not affect the voltage across resistor R6 being pulled low to GND by Q2. Therefore, after the gate of Q6 is pulled low, the PMOS transistor of Q6 conducts. Thus, power supply V2 first passes through the conducting Q4, then through the conducting Q6, and outputs to Vout, which is power supply V2. Because Q3 is an NMOS transistor, its gate is pulled low to GND, so Q3 cannot conduct, and therefore the output Vout is power supply V2.

[0069] Note that the body diode of Q5 is oriented in the opposite direction to the output direction, so the voltage of power supply V2 will not flow back to power supply V1. The body diode of Q3 is oriented towards Vout. However, when the voltage values ​​of power supply V2 and power supply V3 are the same, the body diode does not have enough voltage difference to conduct. Due to the orientation of the body diode of Q3, backflow will not occur, Q3 is completely cut off, and the output is power supply V2.

[0070] 5. When power supply V1 is present, and power supplies V2 and V3 are both zero, the output is power supply V1:

[0071] Because of the high voltage value of power supply V1, Q5 and Q7 are turned on. Power supply V1 is also connected to the gate of the NMOS of Q1, causing Q1 to turn on. The source and drain of Q1 are pulled low to GND. At this time, the voltage of resistor R6 is 0V, Q6 starts to turn on, and both Q5 and Q6 are turned on. Vout is the voltage of power supply V1.

[0072] When power supply V2 is 0, Q2 and Q4 cannot be turned on, and it will not affect the subsequent stage;

[0073] When power supply V3 is 0, Q3 cannot conduct normally and will not affect Vout;

[0074] Therefore, when only power supply V1 exists, the output is power supply V1.

[0075] 6. When power supply V2 is present, and power supplies V1 and V3 are both zero, the output is power supply V2:

[0076] When power supply V1 is 0, Q5 and Q7 are not conducting. The gate of Q4 is connected to GND by resistor R5 and is conducting, outputting power supply V2. At this time, Q2 is conducting because it is connected to power supply V2. The source and drain of Q2 are pulled low to GND. Therefore, the gate of Q6 is 0 and Q6 is conducting. Thus, power supply V2 first passes through the conducting Q4, and then through the conducting Q6, and is output to Vout, which is power supply V2.

[0077] Because of the presence of power supply V2, power supply V3 pulls the gate of Q3 low, preventing Q3 from conducting. Since power supply V3 is 0, it does not affect the output. Therefore, the output is power supply V2 at this time.

[0078] 7. When power supply V3 is present while power supplies V1 and V2 are both zero, the output is power supply V3.

[0079] Because of the presence of power supply V3, power supplies V1 and V2 are both 0, and neither can conduct Q1 and Q2. Through the voltage division of resistors R3 and R4, power supply V3 conducts Q3, and the output is power supply V3.

[0080] In other words, the priority order of the three power supplies, V1, V2, and V3, is as follows: V1 has the highest priority, followed by V2, and then V3.

[0081] The second working characteristic: high stability and security

[0082] When power supplies V1, V2, and V3 are present, the output Vout is power supply V1. If the downstream load is too heavy, it will cause a voltage drop. At this time, other ICs may cause signal errors due to the voltage being lower than the pre-designed value or the digital signal level threshold. When the voltage difference between Vout and power supply V1 exceeds 1V, power supply V2 starts to conduct due to the body diode of Q4, and together with power supply V1, it supplies power to the downstream load. At this time, Vout is power supply V1 plus power supply V2.

[0083] If the voltage difference continues to increase, power supply V3 will also provide power supply current to the subsequent stage Vout through the unidirectional conduction of the body diode of Q3, instead of directly cutting off the system power, thus maximizing the stability of the circuit operation.

[0084] The third working characteristic: anti-reverse connection or ignoring reverse connection.

[0085] In terms of design principles, if any VCC and GND are reversed, VCC becomes GND, and GND becomes VCC. Let's analyze this below:

[0086] 1. When power supply V1 and GND are reversed, power supply V2 and power supply V3 remain unchanged.

[0087] When power supply V1 becomes GND, GND becomes power supply V1. Because of the NMOS, the gate voltage of Q7 is low, and the NMOS cannot conduct normally. The drain of Q7 is now connected to VCC, but because the NMOS cannot conduct and the negative terminal of the body diode is facing VCC, it cannot conduct from the drain to the source. The source of Q7 is connected to the gate of Q5, so the gate of Q5 cannot be pulled low, and Q5 cannot conduct. The gate of Q4 is now connected to GND. Because of the PMOS, the drain and source of Q4 can conduct, but the drain of Q4 is now connected to power supply V2. Power supply V2 is normal, so Q4 can conduct. With the gate of Q1 at GND, Q1 cannot conduct normally. Resistor R1, previously grounded, is now connected to VCC. However, due to the orientation of the body diode in Q1, Q1 cannot conduct from the drain (D) to the source (S). Q2 conducts because its gate is connected to power supply V2, which is normal. Resistor R2 is connected to VCC, and resistor R6 is connected to R2 through the conducting Q2. The left side of resistor R2 is connected to VCC, so the gate of Q6, connected to resistor R6, is at a high level. Q6 is a PMOS and cannot conduct. The source (S) voltage of Q2 is also VCC, and the drain (D) voltage of Q2 is also VCC. The potential energy on both sides is equal, and no current flows normally. The gate voltage of Q3 is VCC, and the source voltage is also VCC. There is no voltage difference between VGS, so the MOS of Q3 cannot turn on normally. However, because Q3 has a body diode, it can output voltage to Vout in the forward direction through the body diode. At this time, the system Vout voltage is equal to VCC-1V (the voltage drop of the body diode is approximately 1V). If the circuit does not require high precision, it can still be turned on and function normally. The operating voltage is low, but it will not short-circuit or overheat and burn out the circuit.

[0088] 2. When power supply V2 and GND are reversed, the other power supplies V1 and V3 remain unchanged.

[0089] When power supply V2 becomes GND, GND becomes power supply V2. Because power supply V1 is also VCC, Q4 does not conduct. However, due to the presence of power supply V1, Q7 conducts normally. But because the drain of Q7 is connected to VCC, after it conducts, the gate voltage of Q5 is VCC. At this time, Q5 cannot conduct normally. However, power supply V1 outputs a voltage VCC-1V to the next stage through the body diode of Q5. Q4 does not conduct and is unaffected. In addition, the body diode of Q4 is reversed, so the conduction voltage of V1 is not as high as that of power supply V2 at this time, and there will be no reverse voltage flow to power supply V2. Q2 is not conducting because its gate is connected to V2 and then to GND. However, because of the presence of V1, Q1 can conduct normally. After resistor R1 is connected to VCC, it is at a high level relative to resistor R6. At this time, Q6 cannot conduct normally, but because the body diode of Q6 is forward-biased, Q6 is equivalent to a diode. The power supply V1 outputs to Vout through the body diodes of Q5 and Q6. Looking at Q3, since both its gate and source are VCC, there is no voltage difference at Vgs, so Q3 will not conduct. V3 outputs to Vout through the forward-biased body diode of Q3. At this time, the circuit outputs to the subsequent stage through power supplies V1 and V3. Note that at this point, the external voltage Vout of V1 is the voltage drop after passing through the two body diodes Q5 and Q6. The external output of Q3 is Vout after passing through the body diode of Q3, and the voltage at this time is VCC-1V (body diode forward voltage drop). Therefore, the voltage V3-1V (Q3 body diode voltage drop) must be greater than V1-1V (Q6 body diode voltage drop)-1V (Q6 body diode voltage drop). At this time, the power supply V1 will not actually output externally due to the voltage drop. At this time, the circuit outputs Vout from V3-1V, which is a positive output. The circuit operating voltage is low, but it will not short-circuit or burn out the circuit due to excessive voltage.

[0090] 3. When power supply V3 and GND are reversed, the other power supplies V1 and V2 remain unchanged.

[0091] When power supply V3 becomes GND, and GND is power supply V3, power supply V1 turns on Q7. However, the drain of Q7 is connected to VCC, so after Q7 turns on, it pulls up the gate voltage of Q5, preventing Q5 from turning on normally. However, the voltage drop across the body diode of Q5 (V1-1V) can still be output. Q4 cannot turn on, and Q1 can turn on. However, Q1 is connected to resistor R1 and then to VCC, which pulls up the gate voltage of Q6, preventing Q6 from turning on normally. The drain voltage of Q6 continues to be output through the body diode. The voltage drop is V1 - 1V (Q5 body diode voltage drop) - 1V (Q6 body diode voltage drop). The power supply V2 is turned on because Q4 is turned off. It can only conduct to the outside through the body diode of Q4. Since the voltage drop is the same, V2 remains unchanged. Q3 does not conduct because there is no voltage difference between the gate and the source. The source of Q3 is 0. At this time, Vout is V1 - 1V (Q5 body diode voltage drop) - 1V (Q6 body diode voltage drop). The circuit operating voltage is low, but it will not short-circuit or burn out the circuit due to excessive voltage.

[0092] 4. Even when power supplies V1, V2, and V3 are all connected in reverse to GND, the circuit will not be damaged.

[0093] When all three power supplies are reversed, Q7 will not conduct, so Q5 will also be unable to conduct normally. Q4 can conduct because its gate is grounded, but since power supply V2 is also connected to GND, it will not output any voltage. Since power supplies V1 and V2 are both grounded, Q1 and Q2 will not conduct. Q6's gate is connected to VCC via resistor R6, and it will not conduct even when pulled high. Q3 can conduct when its gate is pulled high, but since power supply V3 is grounded, it cannot output Vout voltage, so Vout is 0. The circuit will simply not work due to lack of voltage, but it will not burn out the subsequent circuits.

[0094] In summary, reversing any power supply will not damage the circuit, achieving the effect of reverse connection protection. Even if all three power supplies are reversed, it will not cause harm or damage to subsequent circuits, achieving the effect of reverse connection protection.

[0095] The fourth operating feature: preventing backflow of voltage from the downstream stage to the upstream stage.

[0096] In circuit operation, if an unexpected event occurs, assuming the voltage Vout of the subsequent stage suddenly increases without damaging the preceding stage, the specific analysis is as follows:

[0097] If the Vout voltage suddenly and abnormally increases due to a fault in the load circuit, because the body diode of Q6 is reversed, it will not flow into power supply V1 or power supply V2 through the source and drain of Q6. Power supply V2 will also not be damaged because of the reverse protection of the body diode of Q4. The body diode of Q3 is also reversed, so Q3 will not be affected by the sudden increase in Vout. The three-way design will not be affected by the backflow after the Vout increases.

[0098] Therefore, the present invention provides a multi-channel (3-channel) automatic power switching system that can realize automatic switching of three power sources and output without voltage difference. It can also be regarded as an ideal diode, but it far exceeds the concept of an ideal diode.

[0099] This solution has the following characteristics: it is suitable for all fields with multi-powered equipment, featuring extremely simple circuitry, high reliability, and low cost. In cases of sudden high load, a large instantaneous voltage drop can cause the chip to operate at an abnormal voltage. In such situations, other normal solutions typically disconnect the downstream circuit immediately, waiting for the load to stabilize and reach a set threshold before reconnecting the downstream circuit to allow it to continue operating normally. This system's solution is that if a normally operating power supply experiences a voltage drop exceeding 1V due to a sudden excessive load, the other power supplies will automatically turn on to assist the main power supply in powering the downstream circuit. Once the downstream load returns to normal, the other two power supplies will automatically shut down, providing a safety net for the circuit under extreme conditions. Even under excessive load, the voltage is stabilized for normal operation, preventing sudden power outages that could damage downstream loads or chips.

[0100] This solution also prevents reverse connection. When the power supply and GND are reversed, there is no risk of burning out the components. In this system, direct reversal is ineffective and will not damage subsequent circuits or other components such as chips.

[0101] In addition, this solution can also prevent backflow from potentially damaging the power supply itself when there is an abnormal load in the downstream stage, such as an unexpected situation where the Vout output is higher than the input.

[0102] In summary, the present invention has the following advantages:

[0103] This invention presents a basic circuit composed of passive resistors and field-effect transistors. Its structure is simple and stable. Compared to other existing chip-controlled discharge protection circuits, this invention uses fewer components, has a minimally simplistic structure, and requires no software, minimizing the possibility of logic bugs in the software. It offers better stability than complex MCUs that require software-controlled I / O circuits, and is more cost-effective while maintaining reliability.

[0104] Compared to typical passive circuits, this invention only uses resistors and MOSFETs. Typical passive circuits also include capacitors, which are known to be the most prone to failure among passive components. This circuit design, however, only uses MOSFETs and resistors, eliminating the possibility of failure from the outset. Its stability far surpasses that of some commercially available products. Typical consumer products have a design lifespan of 2-3 years due to capacitors, with slightly better performance reaching five years, all limited by capacitor failure. This design, however, eliminates capacitors, maximizing product lifespan and resulting in extremely high stability.

[0105] From another perspective, this system is not only applicable to multi-channel power supply circuit systems, but also to circuits that control three primary and secondary signals. By prioritizing the three signals, the same effect of chip circuit control can be achieved.

[0106] Finally, from an economic perspective, a MOSFET costs only a few cents and a resistor costs less than a cent. This design system solution costs less than 20 cents, and can replace the chip control circuit system at the lowest cost, providing the ultimate cost-performance competitiveness for various products on the market.

[0107] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A minimalist passive multi-source seamless power switching system, characterized in that, It includes power supply V1, power supply V2, power supply V3, MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, and Q7, and resistors R1, R2, R3, R4, R5, and R6; among them, MOSFETs Q1, Q2, Q3, and Q7 are NMOS transistors; and MOSFETs Q4, Q5, and Q6 are PMOS transistors. The output port of power supply V1 is connected to the drain (D) terminal of MOSFET Q5, the source (S) terminal of MOSFET Q5 is connected to the drain (D) terminal of MOSFET Q6, and the source (S) terminal of MOSFET Q6 is connected to the system output side, forming the power supply branch of power supply V1. The output port of power supply V2 is connected to the drain (D) terminal of MOSFET Q4. The source (S) terminal of MOSFET Q4 is connected to the source (S) terminal of MOSFET Q5 and the drain (D) terminal of MOSFET Q6, respectively, so that the power supply branch of power supply V2 is connected to the power supply branch of power supply V1. The output port of power supply V3 is connected to the source (S) terminal of MOSFET Q3, and the drain (D) terminal of MOSFET Q3 is connected to the system output side, forming the power supply branch of power supply V3. The output port of power supply V1 is also connected to the gate of MOSFET Q7. The drain of MOSFET Q7 is connected to GND, and the source of MOSFET Q7 is connected to the gate of MOSFET Q5 to control the on / off state of MOSFET Q5. The output port of power supply V1 is also connected to resistor R5 to GND and to the gate of MOSFET Q4 to control the on / off state of MOSFET Q4; the gate of MOSFET Q4 is also connected to resistor R5 to GND. The output port of power supply V1 is also connected to the gate of MOSFET Q1 to control the on / off state of MOSFET Q1; the drain of MOSFET Q1 is connected to resistor R1 to GND, and the source of MOSFET Q1 is simultaneously connected to the source of MOSFET Q2, the gate of MOSFET Q3, and the gate of MOSFET Q6 through resistor R6 to control the on / off state of MOSFET Q3 and MOSFET Q6; resistor R6 is also connected to the gate of MOSFET Q3. The output port of power supply V2 is also connected to the gate of MOSFET Q2 to control the on / off state of MOSFET Q2; the drain of MOSFET Q2 is connected to resistor R2 to GND, and the source of MOSFET Q2 is connected to the gate of MOSFET Q3 and the gate of MOSFET Q6 through resistor R6 to control the on / off state of MOSFET Q3 and MOSFET Q6. The output port of power supply V3 is also grounded through a voltage divider between resistors R3 and R4.

2. The minimalist passive multi-channel power seamless switching system according to claim 1, characterized in that, The power supply voltage VCC of power supply V1, power supply V2 and power supply V3 is the same.

3. The minimalist passive multi-channel power seamless switching system according to claim 1, characterized in that, Resistors R1, R2, and R5 all have a resistance of 1 MΩ; resistors R3, R4, and R6 all have a resistance of 10 MΩ.

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