Energy storage converter and control system therefor

Abstract

The application relates to an energy storage converter and a control system thereof, and belongs to the field of energy storage converter control. The chip of the energy storage converter control system is an SOC chip, which comprises two ARMs and an FPGA. The first ARM is used for uploading operation data of the energy storage converter and receiving control instructions, the second ARM is used for generating corresponding modulation waves according to the control instructions, and the FPGA is used for outputting final PWM signals according to the modulation waves. Since the function of three original chips is realized by using one chip, the hardware design is easier to realize.

Description

Technical Field

[0001] This invention relates to an energy storage converter and its control system, belonging to the field of energy storage converter control. Background Technology

[0002] my country's energy structure adjustment is accelerating, and the gradual replacement of traditional fossil fuels by new energy sources is an inevitable historical trend. my country possesses abundant solar and wind energy resources, but these resources are characterized by intermittency and fluctuation. Furthermore, there are temporal and spatial mismatches in electricity supply and demand, primarily manifested as imbalances across time and regions. Energy storage technology is a crucial approach to addressing these issues.

[0003] The Power Control System (PCS), a core component of an energy storage system, controls the charging and discharging process of batteries and performs AC / DC conversion. The PCS consists of a DC / AC bidirectional converter and a control system. The PCS control system receives control commands from the backend via communication and controls the energy storage converter to charge or discharge the batteries according to the sign and magnitude of the power commands, thereby regulating the active and reactive power of the power grid. The PCS controller communicates with the Battery Management System (BMS) through a CAN / 485 interface to obtain battery status information, enabling protective charging and discharging of the batteries and ensuring their safe operation.

[0004] Currently, the control system architecture of energy storage converters is mainly implemented using DSP+FPGA+ARM. The ARM handles communication with the backend and BMS, uploading energy storage converter operating data to the backend and receiving control commands. The DSP generates PWM pulses and calculates control algorithms, using PWM pulses to adjust various output parameters of the energy storage converter based on its operating data or control commands, and performs protective actions based on input signals and generates output signals. The FPGA handles peripheral analog and digital signal acquisition and control, converting the acquired energy storage converter operating data to digital and sending it to the ARM, performing over-limit judgment based on the operating data and sending the judgment result back to the ARM, and generating output commands based on the output signals generated by the DSP to drive downstream devices for opening and closing.

[0005] The control system architecture uses three independent chips, each with different peripheral circuits, resulting in a complex and costly hardware design. Data interaction and synchronization between the three chips are required, and the different interfaces and speeds of chips from different manufacturers complicate the hardware and software design. The data buses for the three independent chips need to be routed externally, posing a risk of data interference. Furthermore, the three independent chips require three different software development environments and supporting software, making development, production, and engineering application upgrades cumbersome and requiring a variety of supporting tools. Summary of the Invention

[0006] The purpose of this invention is to provide an energy storage converter and its control system to solve the problem of complex hardware design in the control system of the energy storage converter.

[0007] To achieve the above objectives, the present invention includes: The present invention provides a control system for an energy storage converter, comprising a SOC chip, which includes an FPGA, a first ARM, and a second ARM. The first ARM is used to forward the operating data of the energy storage converter and transmit the received control commands to the second ARM. The second ARM is used to generate a corresponding modulation wave signal based on the control commands, sampled values, and a corresponding control algorithm and transmit it to the FPGA. The FPGA is used to create a carrier wave and compare the carrier wave with the modulation wave to output a PWM signal.

[0008] Furthermore, the sampled value is a digital sampled value; the FPGA also converts the analog sampled value into a digital sampled value, and then passes the digital sampled value to the second ARM.

[0009] Furthermore, the second ARM is also used to determine protection actions based on the digital input signals transmitted from the FPGA. When a protection action is required, it transmits the corresponding output signal to the FPGA.

[0010] Furthermore, the FPGA also generates opening commands for opening and closing the circuit based on the opening signal.

[0011] Furthermore, the FPGA compares the carrier wave with the modulated wave to generate a PWM pulse. After performing narrow pulse filtering, dead-time processing, and interlocking logic processing on the PWM pulse, it outputs the PWM signal.

[0012] An energy storage converter is disclosed. The control system of the energy storage converter uses a SOC chip, which includes an FPGA, a first ARM, and a second ARM. The first ARM is used to forward the operating data of the energy storage converter and transmit the received control commands to the second ARM. The second ARM is used to generate a corresponding modulation wave signal based on the control commands, sampled values, and corresponding control algorithms and transmit it to the FPGA. The FPGA is used to create a carrier wave, compare the carrier wave with the modulation wave, and output a PWM signal.

[0013] Furthermore, the sampled value is a digital sampled value; the FPGA also converts the analog sampled value into a digital sampled value, and then passes the digital sampled value to the second ARM.

[0014] Furthermore, the second ARM is also used to determine protection actions based on the digital input signals transmitted from the FPGA. When a protection action is required, it transmits the corresponding output signal to the FPGA.

[0015] Furthermore, the FPGA also generates opening commands for opening and closing the circuit based on the opening signal.

[0016] Furthermore, the FPGA compares the carrier wave with the modulated wave to generate a PWM pulse. After performing narrow pulse filtering, dead-time processing, and interlocking logic processing on the PWM pulse, it outputs the PWM signal.

[0017] The beneficial effects of this invention are as follows: This invention is a pioneering invention. The chip of the energy storage converter control system of this invention is a SOC chip, which includes two ARM processors and an FPGA. The first ARM processor is used to upload and receive control commands for the energy storage converter's operation data. The second ARM processor is used to generate corresponding modulation waves based on the control commands. The FPGA is used to output the final PWM signal based on the modulation waves. Because this invention uses one chip to achieve the functions of three chips, the hardware design is much easier to implement. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a control system according to the present invention; Figure 2 This is a control logic diagram of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0020] The concept of this invention is to design a control system for an energy storage converter based on a System On Chip (SOC). This chip includes a dual-core ARM and an FPGA. One ARM is used to implement some of the functions of a DSP in the prior art, but the function of generating PWM signals is performed by the FPGA. The other ARM is used to implement the functions of an ARM in the prior art. In addition to implementing the functions of an FPGA in the prior art, the FPGA also adds the function of generating PWM signals.

[0021] System Implementation Example: This embodiment provides an energy storage converter control system, such as Figure 1As shown, the control system includes a SOC core board and a SOC expansion board. The SOC core board circuitry includes: SOC chips (dual-core ARM + FPGA), DDR, OCM, QSPI-FLASH, SD card, power IC, and other components. The SOC expansion board circuitry includes: a DC24V power input circuit, an analog signal conditioning and acquisition circuit, an isolated digital input circuit, an isolated digital output circuit, a PWM pulse output circuit, a half-duplex 485 communication circuit, a CAN communication circuit, a 100 / 1000m Ethernet communication circuit, a real-time clock (RTC) circuit, and a serial fiber optic communication circuit. High-speed data flow between the dual-core ARM (ARM0H and ARM1) and the FPGA is achieved using shared memory within the devices' own OCMs; large-capacity data exchange is implemented using shared-cassette DDR memory. Configuration and data storage are implemented using FLASH and SD cards.

[0022] Signal conditioning and analog-to-digital conversion enable the conditioning and sampling of battery voltage signals, DC current signals, DC voltage signals, AC current signals, AC voltage signals, and NTC temperature signals in the energy storage converter. Digital input enables the sampling and conversion of switch status, position signals, action signals, and protection signals of the energy storage converter. Digital output enables the operation of opening and closing AC / DC switches, putting on / taking off soft-start resistors, and controlling fan speed in the energy storage converter. PWM pulse output enables the comparison of the FPGA carrier signal with the ARM1 (second ARM) modulation wave signal to generate an initial pulse, which is then processed by narrow pulse filtering, dead-time processing, and interlocking logic before being output to the IGBT power unit. Fiber optic signaling enables carrier signal synchronization and data communication between multiple energy storage converters.

[0023] like Figure 2As shown, when the control system is powered on, the SOC chip's ARM0 (first ARM), ARM1, and FPGA load their respective executable files and bitstreams from the FLASH and start. ARM0 loads the Linux system and switching chip driver to expand one Ethernet port within ARM0 into four independent Ethernet MAC units. These, after passing through four independent PHY chips, form four independent Ethernet interfaces for communication with different backends. It loads the 485 driver and CAN driver to establish communication with the local HMI and BMS. It loads the JSFF2 driver to partition the QSPI-FLASH, creating configuration files and application power-off storage space. It loads the SPI-RTC real-time clock driver to establish a precise clock source. It mounts an SD card partition to save waveform recordings under power-off conditions. After the Linux system runs in ARM0, it creates application processes and threads. Depending on the communication application, it loads IEC104, MMS, GOOSE, or MODBUS TCP server threads. After the communication thread starts, it waits for connections from the backend and clients. Upon successful connection, it actively or responds to requests to send the current real-time data of the energy storage converter and responds to control commands issued by the backend, transmitting them to ARM1 via the OCM.

[0024] After the SOC starts, the FPGA drives the AD chip to perform analog-to-digital conversion, converting the analog sampled values ​​into digital sampled values. Then, the digital and analog sampled values ​​are passed to the ARM1 via the OCM. The digital input level is read and converted into a digital input signal, which is then passed to the ARM1 via the OCM. The output signal from the ARM1 is read and converted into a digital output level (output command) to drive the lower-level relays or switches to perform opening and closing operations. A carrier wave is generated and compared with the modulation wave generated by the ARM1 to output the initial PWM pulse. The initial PWM is then processed by narrow pulse filtering, dead-time handling, and interlocking logic before being output as a PWM signal. The analog sampled values ​​are judged in real time for over-limit detection, and the judgment result is sent to the ARM1. The operation fiber optic module and other converter SOC control systems are synchronized to achieve multi-machine parallel carrier synchronization.

[0025] After the SOC starts, the ARM1 loads the FPGA's timer interrupt signal to enter the interrupt + loop working mode. The interrupt program reads digital sample values, analog sample values, and digital input signals. Based on the control instructions, digital sample values, and corresponding control algorithms, it generates corresponding modulation wave signals, filters and judges protection actions on the digital input signals, and generates output signals based on the current integrated calculation results to realize the operation of the switch for action or protection.

[0026] After the SOC is fully operational, ARM0 is responsible for communicating and interacting with the local HMI and remote backend to upload real-time data of the energy storage converter and receive HMI or backend commands to ARM1; ARM1 is responsible for the energy storage converter control algorithm, control logic, fault diagnosis, and modulation wave generation, and adjusts various output parameters of the converter according to the ARM0 commands, and judges the current status and fault protection of the converter based on the analog and digital signals transmitted by the FPGA; the FPGA is responsible for peripheral analog-to-digital conversion, digital input signals, digital output actions, PWM signal output, and fiber optic communication, etc.

[0027] Using the chip's internal OCM greatly reduces EMC interference issues with external signal traces in existing technologies. PWM pulse generation is implemented in software, making it easier to adapt and adjust to different application scenarios.

[0028] Energy storage converter example: This embodiment provides an energy storage converter. When controlling the energy storage converter, the energy storage converter control system described in the system embodiment is adopted. Since the description of the control system is clear enough, it will not be repeated here.

[0029] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A control system for an energy storage converter, characterized in that, The system includes a SOC chip, which comprises an FPGA, a first ARM, and a second ARM. The first ARM is used to forward the operating data of the energy storage converter and transmit the received control commands to the second ARM. The second ARM is used to generate a corresponding modulation wave signal based on the control commands, sampled values, and corresponding control algorithms and transmit it to the FPGA. The FPGA is used to create a carrier wave and compare the carrier wave with the modulation wave to output a PWM signal.

2. The energy storage converter control system according to claim 1, characterized in that, The sampled value is a digital sampled value; the FPGA also converts the analog sampled value into the digital sampled value, and then passes the digital sampled value to the second ARM.

3. The energy storage converter control system according to claim 1, characterized in that, The second ARM is also used to determine protection actions based on the digital input signals transmitted from the FPGA. When protection actions are required, it transmits the corresponding output signals to the FPGA.

4. The energy storage converter control system according to claim 2, characterized in that, The FPGA also generates opening commands for opening and closing the circuit based on the opening signal.

5. The energy storage converter control system according to claim 1, characterized in that, The FPGA compares the carrier wave with the modulated wave to generate a PWM pulse. After performing narrow pulse filtering, dead-time processing, and interlocking logic processing on the PWM pulse, it outputs the PWM signal.

6. An energy storage converter, characterized in that, The control system of the energy storage converter uses a SOC chip, which includes an FPGA, a first ARM, and a second ARM. The first ARM is used to forward the operating data of the energy storage converter and transmit the received control commands to the second ARM. The second ARM is used to generate a corresponding modulation wave signal based on the control commands, sampled values, and corresponding control algorithms and transmit it to the FPGA. The FPGA is used to create a carrier wave and compare the carrier wave with the modulation wave to output a PWM signal.

7. The energy storage converter according to claim 6, characterized in that, The sampled value is a digital sampled value; the FPGA also converts the analog sampled value into a digital sampled value, and then passes the digital sampled value to the second ARM.

8. The energy storage converter according to claim 6, characterized in that, The second ARM is also used to determine protection actions based on the digital input signals transmitted from the FPGA. When protection actions are required, it transmits the corresponding output signals to the FPGA.

9. The energy storage converter according to claim 7, characterized in that, The FPGA also generates opening commands for opening and closing the circuit based on the opening signal.

10. The energy storage converter according to claim 6, characterized in that, The FPGA compares the carrier wave with the modulated wave to generate a PWM pulse. After performing narrow pulse filtering, dead-time processing, and interlocking logic processing on the PWM pulse, it outputs the PWM signal.

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