Multiple output voltage converter

Abstract

A multi-output voltage converter includes a first conversion circuit, a second conversion circuit, a strength adjustment signal generator, a first driving circuit, and a second driving circuit. The first conversion circuit includes a first power transistor and generates a first output voltage by converting an input voltage based on a first driving signal. The second conversion circuit includes a second power transistor and generates a second output voltage by converting the input voltage based on a second driving signal. The strength adjustment signal generator generates a strength adjustment signal based on a first transition timing of a first internal driving signal and a second transition timing of a second internal driving signal. When the first transition timing is synchronized with the second transition timing, the first driving circuit and the second driving circuit reduce driving strengths of the first driving signal and the second driving signal by the strength adjustment signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0037244, filed on March 24, 2025, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to multi-output voltage converters. Background Technology

[0003] Voltage converters that convert high direct current (DC) voltage to low DC voltage can be used to supply power to electronic devices. Voltage converters can be included in a variety of devices and systems, such as mobile devices, electric vehicles, etc.

[0004] Voltage converters can be designed to have high performance and high efficiency. Voltage converters can include buck converters for lowering voltage levels, boost converters for raising voltage levels, and buck-boost converters for either lowering or raising voltage levels. For example, when a voltage converter is used in a mobile device, it can rapidly charge its battery by efficiently converting a high DC voltage to a low DC voltage. In multi-output voltage converters, simultaneous switching operations due to sudden current inflows can lead to excessive power supply noise, which can impair the operating efficiency of the voltage converter. Summary of the Invention

[0005] Some example embodiments can provide multi-output voltage converters that can reduce noise when power transistors are simultaneously on or off.

[0006] According to an example embodiment, a multi-output voltage converter includes: a first conversion circuit configured to generate a first output voltage by converting an input voltage, the first conversion circuit including a first power transistor configured to pull up a first switching node based on a first drive signal; a second conversion circuit configured to generate a second output voltage by converting an input voltage, the second conversion circuit including a second power transistor configured to pull up a second switching node based on a second drive signal; an intensity adjustment signal generator configured to generate an intensity adjustment signal based on a first transition timing of a first internal drive signal and a second transition timing of a second internal drive signal; a first drive circuit configured to generate a first drive signal that dynamically adjusts the drive intensity of the first power transistor based on the intensity adjustment signal and the first internal drive signal; and a second drive circuit configured to generate a second drive signal that dynamically adjusts the drive intensity of the second power transistor based on the intensity adjustment signal and the second internal drive signal, wherein the intensity adjustment signal indicates that the second transition timing of the second internal drive signal is simultaneous with the first transition timing of the first internal drive signal.

[0007] According to an example embodiment, a multi-output voltage converter includes: a plurality of conversion circuits, each of which includes an inductor and a power transistor and is configured to generate an output voltage at a corresponding output node by converting an input voltage based on a corresponding drive signal; each power transistor of the plurality of conversion circuits is configured to pull up a corresponding switching node based on the corresponding drive signal; each switching node of the plurality of conversion circuits is coupled to a first terminal of the corresponding inductor; an intensity adjustment signal generator configured to generate a plurality of intensity adjustment signals based on the transition timing of a plurality of internal drive signals including a first internal drive signal and a second internal drive signal; and a plurality of drive circuits, including a first drive circuit and a second drive circuit. The first driving circuit and the second driving circuit are configured to generate a first driving signal and a second driving signal based on a first internal driving signal and a second internal driving signal, wherein the first driving signal drives a first power transistor and the second driving signal drives a second power transistor, wherein when a first transition timing of the first internal driving signal and a second transition timing of the second internal driving signal are detected to be simultaneous, each of the first driving circuit associated with the first driving signal and the second driving circuit associated with the second driving signal is configured to: reduce the driving intensity of the corresponding power transistor in the first power transistor and the second power transistor based on the first internal driving signal, the second internal driving signal and a first intensity adjustment signal indicating that the first transition timing and the second transition timing are simultaneous.

[0008] According to an example embodiment, a multi-output voltage converter includes: a first conversion circuit including a first inductor and a first power transistor, the first conversion circuit being configured to generate a first output voltage at a first output node by converting an input voltage based on a first drive signal, the first power transistor being configured to pull up a first switching node based on the first drive signal, the first switching node being coupled to a first terminal of the first inductor; a second conversion circuit including a second inductor and a second power transistor, the second conversion circuit being configured to generate a second output voltage at a second output node by converting an input voltage based on a second drive signal, the second power transistor being configured to pull up a second switching node based on the second drive signal, the second switching node being coupled to a first terminal of the second inductor; a shift signal generator being configured to generate a shift signal based on a first transition timing of a first internal drive signal and a second transition timing of a second internal drive signal; a first drive circuit being configured to generate a first drive signal based on the first internal drive signal; and a second drive circuit being configured to generate a second drive signal by shifting the second transition timing of the second internal drive signal based on a shift signal indicating that the first transition timing and the second transition timing are simultaneous.

[0009] According to an example embodiment, a method for operating a multi-output voltage converter is provided. The multi-output voltage converter includes a first driving circuit, a second driving circuit, a first conversion circuit, a second conversion circuit, and an intensity adjustment signal generator. According to the method, based on determining that a first internal driving signal and a second internal driving signal are simultaneously activated, the intensity adjustment signal generator determines whether the first internal driving signal and the second internal driving signal are simultaneously activated; based on the intensity adjustment signal, a corresponding driving signal among the first driving signal and the second driving signal is generated by reducing the driving intensity of the corresponding internal driving signal among the first internal driving signal and the second internal driving signal; based on determining that the first internal driving signal and the second internal driving signal are not simultaneously activated, the corresponding driving signal among the first driving signal and the second driving signal is applied to the corresponding high-side switch of the first conversion circuit and the corresponding high-side switch of the second conversion circuit; based on the intensity adjustment signal, the corresponding driving signal among the first driving signal and the second driving signal is generated by maintaining the driving intensity of the corresponding internal driving signal among the first internal driving signal and the second internal driving signal; the corresponding driving signal among the first driving signal and the second driving signal is applied to the corresponding high-side switch of the first conversion circuit and the corresponding high-side switch of the second conversion circuit.

[0010] In the multi-output voltage converter according to the example embodiment, when the first transition timing of the first internal drive signal is synchronized with the second transition timing of the second internal drive signal and the first power transistor and the second power transistor are simultaneously turned on or off, the drive strength of each of the first power transistor and the second power transistor is reduced. Therefore, ground noise generated at the ground node of the multi-output voltage converter can be reduced, and switching losses can be reduced. Attached Figure Description

[0011] Exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0013] Figure 2 This illustrates an example embodiment. Figure 1 A circuit diagram of an example of the first drive circuit in a multi-output voltage converter.

[0014] Figure 3 This illustrates an example embodiment. Figure 1 A circuit diagram of an example of the second drive circuit in a multi-output voltage converter.

[0015] Figure 4 This illustrates the relationship between the example embodiment and Figure 2 The table of signals associated with the first drive circuit.

[0016] Figure 5A This illustrates an example embodiment. Figure 1 A circuit diagram of an example SAS generator in a multi-output voltage converter.

[0017] Figure 5B This illustrates an example embodiment. Figure 1 A circuit diagram of an example SAS generator in a multi-output voltage converter.

[0018] Figure 6A This illustrates an example embodiment. Figure 5A The timing diagram of the operation of the SAS generator.

[0019] Figure 6B This illustrates an example embodiment. Figure 5B The timing diagram of the operation of the SAS generator.

[0020] Figure 7 This illustrates an example embodiment. Figure 1 A block diagram of an example control circuit in a multi-output voltage converter.

[0021] Figure 8This illustrates an example embodiment. Figure 5A The timing diagram of the operation of the SAS generator.

[0022] Figure 9 This illustrates an example embodiment. Figure 5A The timing diagram of the operation of the SAS generator.

[0023] Figure 10A This illustrates an example embodiment. Figure 1 Timing diagram of example operation of the multi-output voltage converter 10a.

[0024] Figure 10B This illustrates an example embodiment. Figure 1 Timing diagram of example operation of the multi-output voltage converter 10a.

[0025] Figure 11A This indicates that when the multi-output voltage converter does not generate an intensity adjustment signal... Figure 1 Timing diagram of example operation of a multi-output voltage converter.

[0026] Figure 11B This indicates that when the multi-output voltage converter does not generate an intensity adjustment signal... Figure 1 Timing diagram of example operation of a multi-output voltage converter.

[0027] Figure 12 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0028] Figure 13 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0029] Figure 14 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0030] Figure 15 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0031] Figure 16 This illustrates an example embodiment. Figure 15 Timing diagram of example operation of a multi-output voltage converter.

[0032] Figure 17 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0033] Figure 18 This illustrates an example embodiment. Figure 17 Timing diagram of example operation of a multi-output voltage converter.

[0034] Figure 19This is a flowchart illustrating a method for operating a multi-output voltage converter according to an example embodiment.

[0035] Figure 20 This is a block diagram illustrating an electronic device including a multi-output voltage converter according to an example embodiment.

[0036] Figure 21 This is a block diagram illustrating a wireless communication device according to an example embodiment.

[0037] Figure 22 This is a diagram illustrating a system including a multi-output voltage converter according to an example embodiment. Detailed Implementation

[0038] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. In the drawings, the same reference numerals always denote the same elements. Repeated descriptions may be omitted.

[0039] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements and / or components, regions, these elements and / or components should not be limited by these terms. Unless the context otherwise indicates, these terms are used only (e.g., as a naming convention) to distinguish one element or component from another. Therefore, without departing from the teachings of the invention, the first element or first component discussed below in one part of the specification may be referred to as the second element or second component in another part of the specification or in the claims. Furthermore, in certain cases, even if the terms "first," "second," etc., are not used to describe the invention in the specification, they may still be referred to as "first" or "second" in the claims in order to distinguish the different claimed elements from each other.

[0040] As can be seen, for example, in the accompanying figures, items described herein in the singular may be provided in the plural. Therefore, unless the context otherwise indicates, a description of a single item provided in the plural should be understood to apply to the remaining multiple items.

[0041] Throughout this specification, unless the context otherwise indicates, when a component is described as “comprising” a particular element or group of elements, it will be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component.

[0042] When referring to shape, size, quantity, or other measure, terms such as “identical” or “equal” as used herein do not necessarily mean exactly the same shape, size, quantity, or other measure, but are intended to cover substantially identical shapes, sizes, quantities, or other measures within typical variations that may occur due to conventional manufacturing processes. Unless otherwise indicated by context or other statements, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical” or “substantially equal” may be exactly the same or equal, or may be the same or equal within acceptable variations that may occur, for example, due to manufacturing processes.

[0043] Figure 1 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0044] Reference Figure 1 The multi-output voltage converter 10a may include a first drive circuit 100a, a second drive circuit 150a, a first conversion circuit 210a, a second conversion circuit 220a, a first feedback circuit 230a, a second feedback circuit 240a, a control circuit 270a, and an intensity modulation signal (SAS) generator 300a. The multi-output voltage converter 10a may also include a reference voltage generator 350a.

[0045] exist Figure 1 For ease of explanation, a load 250a connected to the first output node NO1 of the multi-output voltage converter 10a and a load 260a connected to the second output node NO2 of the multi-output voltage converter 10a are also shown.

[0046] A first conversion circuit 210a may be connected between a voltage node VN and a ground node GN, and may include a first power transistor 211, a third power transistor 213, a first inductor La, and a first capacitor C1. The voltage node VN may be connected to an input voltage VIN (e.g., receiving the input voltage VIN), and the ground node GN may be connected to a ground voltage VSS (e.g., receiving the ground voltage VSS). The first conversion circuit 210a may generate a first output voltage Vout1 at a first output node NO1 by converting the voltage level of the input voltage VIN to a first voltage level based on a first drive signal DS11 and a third drive signal DS12. The first voltage level of the first output voltage Vout1 may be less than the voltage level of the input voltage VIN.

[0047] A first power transistor 211 may be coupled between the input voltage VIN and the first switching node SN1, and may have a gate for receiving a first drive signal DS11. The first power transistor 211 may be implemented using an n-channel metal-oxide-semiconductor (NMOS) transistor. A third power transistor 213 may be coupled between the first switching node SN1 and ground voltage VSS (e.g., ground node GN receiving ground voltage VSS), and may have a gate for receiving a third drive signal DS12. The third power transistor 213 may be implemented using an NMOS transistor. A first inductor La may be coupled between the first switching node SN1 and the first output node NO1, and a first capacitor C1 may be coupled between the first output node NO1 and the ground voltage VSS.

[0048] In response to the activation of the first drive signal DS11 at a logic high level, the first power transistor 211 is turned on and pulls up the first switching node SN1. In response to the activation of the third drive signal DS12 at a logic high level, the third power transistor 213 is turned on and pulls down the first switching node SN1. Each of the first power transistor 211 and the third power transistor 213 can be a power switch that drives the first output voltage Vout1.

[0049] The first inductor La and the first capacitor C1 can operate as a low-pass filter, and can output a first output voltage Vout1 at the first output node NO1 by filtering out high-frequency components from the voltage at the first switching node SN1. The first inductor current IL1 can flow from the first switching node SN1 to the first output node NO1. The first switching node SN1 can be connected to a first terminal of the first inductor La, and the first output node NO1 can be connected to a second terminal of the first inductor La.

[0050] The first feedback circuit 230a can generate a first feedback voltage VFB1 proportional to the first output voltage Vout1, and can provide the first feedback voltage VFB1 to the control circuit 270a. For example... Figure 1 As shown, the first feedback circuit 230a can generate a first feedback voltage VFB1 corresponding to the ratio of the resistance values ​​of the voltage divider resistors R11 and R12.

[0051] Voltage divider resistors R11 and R12 can be connected in series between the first output node NO1 and the ground voltage VSS, and can be connected to each other at the first feedback node FN1. The first feedback circuit 230a can output the first feedback voltage VFB1 at the first feedback node FN1.

[0052] The second conversion circuit 220a can be connected between the voltage node VN and the ground node GN, and may include a second power transistor 221, a fourth power transistor 223, a second inductor Lb, and a second capacitor C2. The second conversion circuit 220a can generate a second output voltage Vout2 at the second output node NO2 by converting the input voltage VIN based on the second drive signal DS21 and the fourth drive signal DS22.

[0053] A second power transistor 221 may be connected between the input voltage VIN and the second switching node SN2, and may have a gate for receiving a second drive signal DS21. The second power transistor 221 may be implemented using an NMOS transistor. A fourth power transistor 223 may be connected between the second switching node SN2 and the ground voltage VSS, and may have a gate for receiving a fourth drive signal DS22. The fourth power transistor 223 may be implemented using an NMOS transistor. A second inductor Lb may be connected between the second switching node SN2 and the second output node NO2, and a second capacitor C2 may be connected between the second output node NO2 and the ground voltage VSS.

[0054] In response to the activation of the second drive signal DS21 at a logic high level, the second power transistor 221 can be turned on and pull up the second switching node SN2. In response to the activation of the fourth drive signal DS22 at a logic high level, the fourth power transistor 223 can be turned on and pull down the second switching node SN2. Each of the second power transistor 221 and the fourth power transistor 223 can be a power switch driving the second output voltage Vout2.

[0055] The second inductor Lb and the second capacitor C2 can operate as a low-pass filter, and can output a second output voltage Vout2 at the second output node NO2 by filtering out high-frequency components from the voltage at the second switching node SN2. The second inductor current IL2 can flow from the second switching node SN2 to the second output node NO2. The second switching node SN2 can be connected to the first terminal of the second inductor Lb, and the second output node NO2 can be connected to the second terminal of the second inductor Lb.

[0056] The second feedback circuit 240a can generate a second feedback voltage VFB2 that is proportional to the second output voltage Vout2, and can provide the second feedback voltage VFB2 to the control circuit 270a. For example... Figure 1 As shown, the second feedback circuit 240a can generate a second feedback voltage VFB2 corresponding to the ratio of the resistance values ​​of the voltage divider resistors R21 and R22.

[0057] Voltage divider resistors R21 and R22 can be connected in series between the second output node NO2 and the ground voltage VSS, and can be connected to each other at the second feedback node FN2. The second feedback circuit 240a can output the second feedback voltage VFB2 at the second feedback node FN2.

[0058] The first load current ILD1 can flow into the load 250a based on the first output voltage Vout1, and the second load current ILD2 can flow into the load 260a based on the second output voltage Vout2.

[0059] The first drive circuit 100a, the first conversion circuit 210a, and the first feedback circuit 230a can constitute a first buck converter, and the second drive circuit 150a, the second conversion circuit 220a, and the second feedback circuit 240a can constitute a second buck converter.

[0060] The reference voltage generator 350a can generate a first reference voltage VREF1 and a second reference voltage VREF2, and can provide the first reference voltage VREF1 and the second reference voltage VREF2 to the control circuit 270a.

[0061] The control circuit 270a can receive a first feedback voltage VFB1, a second feedback voltage VFB2, a first reference voltage VREF1, and a second reference voltage VREF2. It can generate a first internal drive signal IDS11 and a third internal drive signal IDS12 by comparing the first feedback voltage VFB1 with the first reference voltage VREF1, and can generate a second internal drive signal IDS21 and a fourth internal drive signal IDS22 by comparing the second feedback voltage VFB2 with the second reference voltage VREF2. The first drive circuit 100a can generate a first drive signal DS11 based on the first internal drive signal IDS11, and a third drive signal DS12 based on the third internal drive signal IDS12. The second drive circuit 150a can generate a second drive signal DS21 based on the second internal drive signal IDS21, and a fourth drive signal DS22 based on the fourth internal drive signal IDS22.

[0062] The control circuit 270a can provide the first internal drive signal IDS11 and the third internal drive signal IDS12 to the first drive circuit 100a, provide the second internal drive signal IDS21 and the fourth internal drive signal IDS22 to the second drive circuit 150a, and provide the first internal drive signal IDS11 and the second internal drive signal IDS21 to the SAS generator 300a.

[0063] The SAS generator 300a can receive a first internal drive signal IDS11 and a second internal drive signal IDS21, monitor the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21, generate an intensity adjustment signal SAS based on the synchronization of the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21, and provide the intensity adjustment signal SAS to the first drive circuit 100a and the second drive circuit 150a. When the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous, the intensity adjustment signal SAS can transition to a first logic level (e.g., a logic low level). The SAS generator 300a can generate an intensity adjustment signal SAS with a first logic level when it detects that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are substantially simultaneous.

[0064] The transition timing may include the activation timing of each of the first internal drive signal IDS11 and the second internal drive signal IDS21, and the deactivation timing of each of the first internal drive signal IDS11 and the second internal drive signal IDS21. For example, the first transition timing may include a first activation timing or a first deactivation timing of the first internal drive signal IDS11, and the second transition timing may include a second activation timing or a second deactivation timing of the second internal drive signal IDS21. Therefore, simultaneous transitions of the first internal drive signal IDS11 and the second internal drive signal IDS21 may indicate that the first activation timing of the first internal drive signal IDS11 and the second activation timing of the second internal drive signal IDS21 occur simultaneously, or that the first deactivation timing of the first internal drive signal IDS11 and the second deactivation timing of the second internal drive signal IDS21 occur simultaneously.

[0065] The first driving circuit 100a can generate a first driving signal DS11 based on a first internal driving signal IDS11, and a third driving signal DS12 based on a third internal driving signal IDS12. Furthermore, it can dynamically (or selectively) adjust the driving intensity of the first power transistor 211 by controlling the signal slope of the first driving signal DS11 based on an intensity adjustment signal SAS and the first internal driving signal IDS11. When the intensity adjustment signal SAS indicates that the first transition timing of the first internal driving signal IDS11 is simultaneous with the second transition timing of the second internal driving signal IDS21, the slope of the first driving signal DS11 at the gate of the first power transistor 211 becomes less steep, causing a decrease in the driving intensity of the first power transistor 211.

[0066] For example, based on an intensity adjustment signal SAS indicating that the first transition timing of the first internal drive signal IDS11 is synchronized (e.g., simultaneous) with the second transition timing of the second internal drive signal IDS21, the first drive circuit 100a can reduce the drive strength of the first power transistor 211 based on the intensity adjustment signal SAS and the first internal drive signal IDS11. Based on an intensity adjustment signal SAS indicating that the first transition timing of the first internal drive signal IDS11 is not simultaneous with the second transition timing of the second internal drive signal IDS21, the first drive circuit 100a can maintain the normal drive strength of the first power transistor 211 by controlling the signal slope of the first drive signal DS11 based on the intensity adjustment signal SAS and the first internal drive signal IDS11.

[0067] The second driving circuit 150a can generate a second driving signal DS21 based on the second internal driving signal IDS21, generate a fourth driving signal DS22 based on the fourth internal driving signal IDS22, and dynamically reduce the driving intensity of the second power transistor 221 by controlling the signal slope of the second driving signal DS21 based on the intensity adjustment signal SAS and the second internal driving signal IDS21.

[0068] When the intensity adjustment signal SAS indicates that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous, the second drive circuit 150a can reduce the drive intensity of the second power transistor 221 by controlling the signal slope of the second drive signal DS21 based on the intensity adjustment signal SAS and the second internal drive signal IDS21. When the intensity adjustment signal SAS indicates that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are not simultaneous, the second drive circuit 150a can maintain the normal drive intensity of the second power transistor 221 by controlling the signal slope of the second drive signal DS21 based on the intensity adjustment signal SAS and the second internal drive signal IDS21.

[0069] Therefore, when the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous, and the first power transistor 211 and the second power transistor 221 are simultaneously turned on or off, the drive strength of each of the first power transistor 211 and the second power transistor 221 can be reduced. Consequently, the ground power supply noise generated at the ground node GN of the multi-output voltage converter 10a can be reduced, resulting in an overall reduction in the switching losses of the multi-output voltage converter.

[0070] Figure 2 This illustrates an example embodiment. Figure 1A circuit diagram of an example of the first drive circuit in a multi-output voltage converter.

[0071] Reference Figure 2 The first driving circuit 100a may include a first inverter 105, a logic circuit 110, a gate driver 120, and a buffer 130.

[0072] Buffer 130 can generate a third drive signal DS12 by buffering the third internal drive signal IDS12. The first inverter 105 can output a first inverted internal drive signal IDS11B by inverting the first internal drive signal IDS11. Gate driver 120 may include a first driver 120-1 and a second driver 120-2.

[0073] Based on the first inverting internal drive signal IDS11B, the first control signal TP11, and the second control signal TP12, the gate driver 120 can adjust the drive strength of the first power transistor 211 by activating both the first driver 120-1 and the second driver 120-2, or by activating the first driver 120-1 and deactivating the second driver 120-2, thereby controlling the slope of the first drive signal DS11 by charging or discharging the first node N11 where the first drive signal DS11 is provided. When both the first driver 120-1 and the second driver 120-2 are activated, the gate driver 120 can maintain the normal drive strength of the first power transistor 211; when the first driver 120-1 is activated and the second driver 120-2 is deactivated, the gate driver 120 can reduce the drive strength of the first power transistor 211.

[0074] The gate driver 120 may include a first p-channel metal-oxide-semiconductor (PMOS) transistor 121, a first NMOS transistor 123, a second PMOS transistor 125, and a second NMOS transistor 127. The first PMOS transistor 121 and the first NMOS transistor 123 may form a first driver 120-1, and the second PMOS transistor 125 and the second NMOS transistor 127 may form a second driver 120-2.

[0075] A first PMOS transistor 121 may be connected between the power supply voltage VDD and the first node N11, and may have a gate for receiving a first inverted internal drive signal IDS11B. A first NMOS transistor 123 may be connected between the first node N11 and the ground voltage VSS, and may have a gate for receiving the first inverted internal drive signal IDS11B. A second PMOS transistor 125 may be connected in parallel with the first PMOS transistor 121 between the power supply voltage VDD and the first node N11, and may have a gate for receiving a first control signal TP11. A second NMOS transistor 127 may be connected in parallel with the first NMOS transistor 123 between the first node N11 and the ground voltage VSS, and may have a gate for receiving a second control signal TP12.

[0076] Logic circuit 110 can generate a first control signal TP11 and a second control signal TP12 based on the first inverted internal drive signal IDS11B and the intensity adjustment signal SAS.

[0077] The logic circuit 110 may include an OR gate 111, an AND gate 113, and a second inverter 115.

[0078] The second inverter 115 inverts the intensity adjustment signal SAS. The OR gate 111 generates the first control signal TP11 by performing an OR operation on the first inverted internal drive signal IDS11B and the output of the second inverter 115. The AND gate 113 generates the second control signal TP12 by performing an AND operation on the first inverted internal drive signal IDS11B and the intensity adjustment signal SAS.

[0079] For example, in response to an intensity adjustment signal SAS with a logic low level, the first control signal TP11 may have a logic high level (regardless of the logic level of the first inverting internal drive signal IDS11B), and the second control signal TP12 may have a logic low level (regardless of the logic level of the first inverting internal drive signal IDS11B). In this case, the second driver 120-2 can be deactivated, so the second PMOS transistor 125 can be turned off based on the first control signal TP11 (regardless of the input logic level of the first inverting internal drive signal IDS11B), and the second NMOS transistor 127 can be turned off based on the second control signal TP12 (regardless of the input logic level of the first inverting internal drive signal IDS11B). Therefore, the second PMOS transistor 125 does not charge the first node N11, the second NMOS transistor 127 does not discharge the first node N11, and the first drive signal DS11 can transition relatively slowly at the first node N11. Conversely, when both the second PMOS transistor 125 and the second NMOS transistor 127 are activated in response to the logic level of the first inverted internal drive signal IDS11B and drive the first node N11, the first drive signal DS11 can change relatively quickly.

[0080] For example, in response to the intensity adjustment signal SAS having a logic high level, each of the first control signal TP11 and the second control signal TP12 may have the same logic level as the first inverted internal drive signal IDS11B. Therefore, because the second driver 120-2 can be activated to charge or discharge the first node N11 based on the logic level of the first internal drive signal IDS11 or the first inverted internal drive signal IDS11B, the normal drive intensity of the first power transistor 211 driven by the first drive signal DS11 can remain normal.

[0081] Figure 3 This illustrates an example embodiment. Figure 1 A circuit diagram of an example of the second drive circuit in a multi-output voltage converter.

[0082] Reference Figure 3 The second driving circuit 150a may include a first inverter 155, a logic circuit 160, a gate driver 170, and a buffer 180.

[0083] Buffer 180 can generate a fourth drive signal DS22 by buffering the fourth internal drive signal IDS22. First inverter 155 can output a second inverted internal drive signal IDS21B by inverting the second internal drive signal IDS21. Gate driver 170 may include a third driver 170-1 and a fourth driver 170-2.

[0084] Based on the second inverting internal drive signal IDS21B, the third control signal TP21, and the fourth control signal TP22, the gate driver 170 can adjust the drive strength of the second power transistor 221 by activating both the third driver 170-1 and the fourth driver 170-2, or by activating the third driver 170-1 and deactivating the fourth driver 170-2, thereby controlling the slope of the second drive signal DS21 by charging or discharging the second node N12 where the second drive signal DS21 is provided. When both the third driver 170-1 and the fourth driver 170-2 are activated, the gate driver 120 can maintain the normal drive strength of the second power transistor 221, and when the third driver 170-1 is activated and the fourth driver 170-2 is deactivated, the gate driver 120 can reduce the drive strength of the second power transistor 221.

[0085] The gate driver 170 may include a first PMOS transistor 171, a first NMOS transistor 173, a second PMOS transistor 175, and a second NMOS transistor 177. The first PMOS transistor 171 and the first NMOS transistor 173 may form a third driver 170-1, and the second PMOS transistor 175 and the second NMOS transistor 177 may form a fourth driver 170-2.

[0086] A first PMOS transistor 171 may be connected between the power supply voltage VDD and the second node N12, and may have a gate for receiving a second inverted internal drive signal IDS21B. A first NMOS transistor 173 may be connected between the second node N12 and the ground voltage VSS, and may have a gate for receiving the second inverted internal drive signal IDS21B. A second PMOS transistor 175 may be connected in parallel with the first PMOS transistor 171 between the power supply voltage VDD and the second node N12, and may have a gate for receiving a third control signal TP21. A second NMOS transistor 177 may be connected in parallel with the first NMOS transistor 173 between the second node N12 and the ground voltage VSS, and may have a gate for receiving a fourth control signal TP22.

[0087] The logic circuit 160 can generate the third control signal TP21 and the fourth control signal TP22 based on the second inverting internal drive signal IDS21B and the intensity adjustment signal SAS.

[0088] The logic circuit 160 may include an OR gate 161, an AND gate 163, and a second inverter 165.

[0089] The second inverter 165 inverts the intensity adjustment signal SAS. The OR gate 161 generates the third control signal TP21 by performing an OR operation on the second inverter's internal drive signal IDS21B and the output of the second inverter 165. The AND gate 163 generates the fourth control signal TP22 by performing an AND operation on the second inverter's internal drive signal IDS21B and the intensity adjustment signal SAS.

[0090] For example, in response to an intensity adjustment signal SAS with a logic low level, the third control signal TP21 may have a logic high level (independent of the logic level of the second inverting internal drive signal IDS21B), and the fourth control signal TP22 may have a logic low level (independent of the logic level of the second inverting internal drive signal IDS21B). In this case, the fourth driver 170-2 can be deactivated, so the second PMOS transistor 175 can be turned off based on the third control signal TP21, and the second NMOS transistor 177 can be turned off based on the fourth control signal TP22 (regardless of the input logic level of the second inverting internal drive signal IDS21B). Therefore, the second PMOS transistor 175 does not charge the second node N12, the second NMOS transistor 177 does not discharge the second node N12, and the second drive signal DS21 can transition relatively slowly at the second node N12. Conversely, when both the second PMOS transistor 175 and the second NMOS transistor 177 are activated in response to the logic level of the second inverted internal drive signal IDS21B and drive the second node N12, the second drive signal DS21 can change relatively quickly.

[0091] For example, in response to the intensity adjustment signal SAS having a logic high level, each of the third control signal TP21 and the fourth control signal TP22 may have the same logic level as the second inverted internal drive signal IDS21B. Therefore, because the fourth driver 170-2 can be activated to charge or discharge the second node N12 based on the logic level of the second internal drive signal IDS21 or the second inverted internal drive signal IDS21B, the normal drive intensity of the second power transistor 221 driven by the second drive signal DS21 can remain normal.

[0092] Figure 4 This illustrates the relationship between the example embodiment and Figure 2 The table of signals associated with the first drive circuit.

[0093] exist Figure 4 In Table TB1, the logic levels of the first internal drive signal IDS11, the first control signal TP11, and the second control signal TP12 are shown as being related to the logic level of the intensity adjustment signal SAS.

[0094] Reference Figure 2 and Figure 4 In response to the intensity adjustment signal SAS having a logic low level, the first control signal TP11 may have a logic high level (independent of the logic level of the first inverting internal drive signal IDS11B), and the second control signal TP12 may have a logic low level (independent of the logic level of the first inverting internal drive signal IDS11B). In response to the intensity adjustment signal SAS having a logic high level, each of the first control signal TP11 and the second control signal TP12 may have the same logic level as the first inverting internal drive signal IDS11B.

[0095] Figure 5A This illustrates an example embodiment. Figure 1 A circuit diagram of an example SAS generator in a multi-output voltage converter.

[0096] Reference Figure 5A The SAS generator 300a may include a first flip-flop 311, a first timer 313, a second flip-flop 315, a second timer 317, and a NAND gate 318.

[0097] The first flip-flop 311 may include a set terminal S for receiving a first internal drive signal IDS11, a reset terminal R for receiving a first delayed latch signal RSD11, and an output terminal Q for outputting the first latch signal RS11. The first flip-flop 311 can provide the first latch signal RS11 at the output terminal Q by latching the first internal drive signal IDS11. The first timer 313 can generate the first delayed latch signal RSD11 by delaying the first latch signal RS11 by a first delay time (e.g., a first time delay) DLY1, and can provide the first delayed latch signal RSD11 to the reset terminal R of the first flip-flop 311. Therefore, the first latch signal RS11 can have a pulse shape with a duration corresponding to the first delay time DLY1 and being at a logic high level in response to a rise in the first internal drive signal IDS11. Therefore, the first flip-flop 311 can generate the first latch signal RS11 when a rise in the first internal drive signal IDS11 is detected, and the first latch signal RS11 can have a duration corresponding to the first delay time DLY1.

[0098] The second flip-flop 315 may include a set terminal S for receiving the second internal drive signal IDS21, a reset terminal R for receiving the second delayed latch signal RSD21, and an output terminal Q for outputting the second latch signal RS21. The second flip-flop 315 can provide the second latch signal RS21 at the output terminal Q by latching the second internal drive signal IDS21. The second timer 317 can generate the second delayed latch signal RSD21 by delaying the second latch signal RS21 by a second delay time (e.g., a second time delay) DLY2 that is substantially equal to the first delay time DLY1, and can provide the second delayed latch signal RSD21 to the reset terminal R of the second flip-flop 315. Therefore, the second latch signal RS21 may have a pulse shape with a duration corresponding to the second delay time DLY2 and being at a logic high level, based on the second internal drive signal IDS21. Therefore, the second flip-flop 315 can generate the second latch signal RS21 when activation of the second internal drive signal IDS21 is detected, and the second latch signal RS21 may have a duration corresponding to the second delay time DLY2.

[0099] NAND gate 318 can generate an intensity adjustment signal SAS by performing a NAND operation on the first latch signal RS11 and the second latch signal RS21. Therefore, NAND gate 318 can generate an intensity adjustment signal SAS with a logic low level corresponding to the overlapping period between the activation periods of the first latch signal RS11 and the second latch signal RS21. Specifically, SAS generator 300a can generate an intensity adjustment signal SAS with a third duration at a logic low level based on the first activation time point of the first latch signal RS11 and the second activation time point of the second latch signal RS21. The third duration can be changed according to the time proximity between the first activation time point of the first latch signal RS11 and the second activation time point of the second latch signal RS21.

[0100] The first delay time DLY1 and the second delay time DLY2 can be adjusted according to the estimated power supply noise (e.g., noise settling timing) generated when the first power transistor 211 and the second power transistor 221 are simultaneously turned on or simultaneously turned off.

[0101] Figure 5B This illustrates an example embodiment. Figure 1 A circuit diagram of an example SAS generator in a multi-output voltage converter.

[0102] Reference Figure 5B The SAS generator 300a_1 may include a first trigger 311, a first timer 313, a second trigger 315, a second timer 317, a NAND gate 318, and a duration regulator 319.

[0103] exist Figure 5B In, with Figure 5A Duplicate descriptions will be omitted.

[0104] The duration regulator 319 can generate a first intensity adjustment signal SAS1 by adjusting the duration of the logic low level of the intensity adjustment signal SAS. The duration of the first intensity adjustment signal SAS1 being held at a logic low level can be adjusted by the duration regulator 319 according to the power supply noise generated when the first power transistor 211 and the second power transistor 221 are simultaneously turned on or off.

[0105] Figure 6A This illustrates an example embodiment. Figure 5A The timing diagram of the operation of the SAS generator.

[0106] Reference Figure 5A and Figure 6A When the first internal drive signal IDS11 is activated at a logic high level at the first time point T11 and the second internal drive signal IDS21 is activated at a logic high level at the second time point T12 after the first time point T11, because the current flows into Figure 1 The current IGND of the ground node GN is dispersed due to the time interval between the first time point T11 and the second time point T12, so the power supply noise generated from the operation of the first power transistor 211 and the second power transistor 221 can be dispersed. The intensity adjustment signal SAS remains at a logic high level between the first time point T11 and the second time point T12.

[0107] When the first internal drive signal IDS11 and the second internal drive signal IDS21 are simultaneously received at time point T13, the intensity adjustment signal SAS can have a logic low level during the first time interval INT1 between time point T13 and time point T14. Therefore, by Figure 2 The driving strength of each of the first power transistor 211 and the second power transistor 221 driven by the first internal drive signal IDS11 and the second internal drive signal IDS21 can be reduced, and at time point T13, the current flows into the first power transistor 211 and the second power transistor 221, respectively. Figure 1 The current IGND of the ground node GN can also be reduced to no greater than the current IGND flowing into the ground node GN at the first time point T11. Therefore, when the first power transistor 211 and the second power transistor 221 are simultaneously activated and turned on based on the first internal drive signal IDS11 and the second internal drive signal IDS21, the noise generated at the ground node GN can be reduced.

[0108] exist Figure 6AThe diagram shows that the first power transistor 211 and the second power transistor 221 are simultaneously turned on. Furthermore, when the first power transistor 211 and the second power transistor 221 are simultaneously turned off in response to the simultaneous deactivation of the first internal drive signal IDS11 and the second internal drive signal IDS21, the power supply noise generated at the ground node GN can be reduced by adjusting the drive intensity of the first power transistor 211 and the second power transistor 221 using the intensity adjustment signal SAS.

[0109] Figure 6B This illustrates an example embodiment. Figure 5B The timing diagram of the operation of the SAS generator.

[0110] Reference Figure 5B and Figure 6B When the first internal drive signal IDS11 is activated at a logic high level at the first time point T11 and the second internal drive signal IDS21 is activated at a logic high level at the second time point T12 after the first time point T11, due to the flow into Figure 1 The current IGND at the ground node GN generates power supply noise. The first intensity adjustment signal SAS1 remains at a logic high level between the first time point T11 and the second time point T12.

[0111] When the first internal drive signal IDS11 and the second internal drive signal IDS21 are simultaneously activated at time point T13, the first intensity adjustment signal SAS1 has a logic low level during the second time interval INT2 between time point T13 and time point T15. Therefore, by Figure 2 The driving strength of each of the first power transistor 211 and the second power transistor 221 driven by the first internal drive signal IDS11 and the second internal drive signal IDS21 can be reduced, and at time point T13, the current flows into the first power transistor 211 and the second power transistor 221, respectively. Figure 1 The current IGND at ground node GN can also be reduced to no greater than the current IGND flowing into ground node GN at the first time point T11. Therefore, when the first power transistor 211 and the second power transistor 221 are simultaneously activated and turned on based on the first internal drive signal IDS11 and the second internal drive signal IDS21, the power supply noise generated at ground node GN can be reduced.

[0112] The second time interval INT2 can be greater than the first time interval INT1, and the second time interval INT2 can be variable.

[0113] Figure 7 This illustrates an example embodiment. Figure 1 A block diagram of an example control circuit in a multi-output voltage converter.

[0114] Reference Figure 7 The control circuit 270a may include a first pulse signal generator 280, a first drive signal generator 290, a second pulse signal generator 295, and a second drive signal generator 297.

[0115] The first pulse signal generator 280 can generate a first pulse width modulation (PWM) signal SPWM1 based on the first feedback voltage VFB1 and the first reference voltage VREF1, and can provide the first PWM signal SPWM1 to the first drive signal generator 290. The first drive signal generator 290 can generate a first internal drive signal IDS11 and a third internal drive signal IDS12 based on the first PWM signal SPWM1.

[0116] The second pulse signal generator 295 can generate a second PWM signal SPWM2 based on the second feedback voltage VFB2 and the second reference voltage VREF2, and can provide the second PWM signal SPWM2 to the second drive signal generator 297. The second drive signal generator 297 can generate a second internal drive signal IDS21 and a fourth internal drive signal IDS22 based on the second PWM signal SPWM2.

[0117] Figure 8 This illustrates an example embodiment. Figure 5A The timing diagram of the operation of the SAS generator.

[0118] Reference Figure 8 The intensity adjustment signal SAS can change to a logic low level and remain at a logic low level for a period of time in response to the simultaneous occurrence of the activation transition of the first internal drive signal IDS11 and the activation transition of the second internal drive signal IDS21.

[0119] exist Figure 8 In the middle, the TRED signal indicates that... Figure 1 In the multi-output voltage converter 10a, the activation transition of the first internal drive signal IDS11 and the activation transition of the second internal drive signal IDS21 occur simultaneously.

[0120] Figure 9 This illustrates an example embodiment. Figure 5A The timing diagram of the operation of the SAS generator.

[0121] Reference Figure 9 The intensity adjustment signal SAS remains at a logic low level during the period when the deactivation period of the first internal drive signal IDS11 overlaps with the deactivation period of the second internal drive signal IDS21.

[0122] exist Figure 9 In the middle, the TRED signal indicates that... Figure 1In the multi-output voltage converter 10a, the deactivation transition of the first internal drive signal IDS11 and the deactivation transition of the second internal drive signal IDS21 occur simultaneously.

[0123] Figure 10A This illustrates an example embodiment. Figure 1 Timing diagram of example operation of the multi-output voltage converter 10a.

[0124] exist Figure 10A The diagram shows the waveforms of the first drive signal DS11, the second drive signal DS21, the third drive signal DS12, the fourth drive signal DS22, the first inductor current IL1, the second inductor current IL2, the noise current INOISE, the signal TRED, and the drain-source voltage VDS of each of the third power transistor 213 and the fourth power transistor 223.

[0125] The signal TRED is used to indicate that the activation transition of the first internal drive signal IDS11 and the activation transition of the second internal drive signal IDS21 occur simultaneously.

[0126] Depending on whether the corresponding drive signal among the first drive signal DS11, the second drive signal DS21, the third drive signal DS12, and the fourth drive signal DS22 is activated or deactivated, each of the first inductor current IL1 and the second inductor current IL2 can be increased or decreased respectively.

[0127] At the point when the first drive signal DS11 or the second drive signal DS21 is activated, the noise current INOISE generated by the parasitic inductance and parasitic capacitance can reach its peak.

[0128] As indicated by reference numeral 361a, according to the embodiment, the peak value of the noise current INOISE when the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are simultaneous is controlled to be substantially similar to the peak value of the noise current INOISE when the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are not simultaneous. When the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are simultaneous, the first drive circuit 100a reduces the drive strength of the first drive signal DS11 (e.g., the drive strength of the first power transistor 211 driven by the first drive signal DS11) based on the intensity adjustment signal SAS, and the second drive circuit 150a reduces the drive strength of the second drive signal DS21 (e.g., the drive strength of the second power transistor 221 driven by the second drive signal DS21) based on the intensity adjustment signal SAS. Therefore, the peak value of the noise current INOISE when the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are simultaneous can be controlled to be similar to the peak value of the noise current INOISE when the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are not simultaneous.

[0129] exist Figure 10A In the reference numeral 363a, the drain-source voltage of the third power transistor 213 is indicated, and the drain-source voltage of the fourth power transistor 223 is indicated, as is the reference numeral 365a.

[0130] Figure 10B This illustrates an example embodiment. Figure 1 Timing diagram of example operation of the multi-output voltage converter 10a.

[0131] exist Figure 10B The diagram shows the waveforms of the first drive signal DS11, the second drive signal DS21, the third drive signal DS12, the fourth drive signal DS22, the first inductor current IL1, the second inductor current IL2, the noise current INOISE, the signal TRED, and the drain-source voltage VDS of each of the third power transistor 213 and the fourth power transistor 223.

[0132] The signal TRED is used to indicate that the deactivation interval of the first internal drive signal IDS11 and the deactivation interval of the second internal drive signal IDS21 occur simultaneously.

[0133] Depending on whether the corresponding drive signal among the first drive signal DS11, the second drive signal DS21, the third drive signal DS12, and the fourth drive signal DS22 is deactivated or activated, each of the first inductor current IL1 and the second inductor current IL2 can be decreased or increased respectively.

[0134] At the point when the first drive signal DS11 or the second drive signal DS21 is deactivated, the noise current INOISE generated by the parasitic inductance and parasitic capacitance can reach its peak.

[0135] As indicated by reference numeral 361b, the peak value of the noise current INOISE when the first deactivation time of the first drive signal DS11 and the second deactivation time of the second drive signal DS21 are simultaneous can be controlled to be substantially similar to the peak value of the noise current INOISE when the first deactivation time of the first drive signal DS11 and the second deactivation time of the second drive signal DS21 are not simultaneous. When the first deactivation time of the first drive signal DS11 and the second deactivation time of the second drive signal DS21 are simultaneous, the first drive circuit 100a reduces the drive strength of the first power transistor 211 driven by the first drive signal DS11 based on the intensity adjustment signal SAS, and the second drive circuit 150a reduces the drive strength of the second power transistor 221 driven by the second drive signal DS21 based on the intensity adjustment signal SAS. Therefore, the peak value of the noise current INOISE when the first deactivation time point of the first drive signal DS11 and the second deactivation time point of the second drive signal DS21 are simultaneous can be controlled to be similar to the peak value of the noise current INOISE when the first deactivation time point of the first drive signal DS11 and the second deactivation time point of the second drive signal DS21 are not simultaneous.

[0136] exist Figure 10B In the reference numeral 363b, the drain-source voltage of the third power transistor 213 is indicated, and the drain-source voltage of the fourth power transistor 223 is indicated by the reference numeral 365b.

[0137] For reference Figure 10A and Figure 10BAs mentioned, when the first transition timing of the first drive signal DS11 and the second transition timing of the second drive signal DS21 are simultaneous, the first drive circuit 100a reduces the drive intensity of the first power transistor 211 driven by the first drive signal DS11 based on the intensity adjustment signal SAS, and the second drive circuit 150a reduces the drive intensity of the second power transistor 221 driven by the second drive signal DS21 based on the intensity adjustment signal SAS. Therefore, the peak value of the noise current INOISE when the first transition timing of the first drive signal DS11 and the second transition timing of the second drive signal DS21 are simultaneous can be controlled to be similar to the peak value of the noise current INOISE when the first transition timing of the first drive signal DS11 and the second transition timing of the second drive signal DS21 are not simultaneous.

[0138] Figure 11A This indicates that when the multi-output voltage converter 10a does not generate the intensity adjustment signal SAS... Figure 1 Timing diagram of example operation of the multi-output voltage converter 10a.

[0139] exist Figure 11A The diagram shows the waveforms of the first drive signal DS11, the second drive signal DS21, the third drive signal DS12, the fourth drive signal DS22, the first inductor current IL1, the second inductor current IL2, the noise current INOISE, the signal TRED, and the drain-source voltage VDS of each of the third power transistor 213 and the fourth power transistor 223.

[0140] Depending on whether the corresponding drive signal among the first drive signal DS11, the second drive signal DS21, the third drive signal DS12, and the fourth drive signal DS22 is activated or deactivated, each of the first inductor current IL1 and the second inductor current IL2 can be increased or decreased respectively.

[0141] At the point when the first drive signal DS11 or the second drive signal DS21 is activated, the noise current INOISE generated by the parasitic inductance and parasitic capacitance has a peak value.

[0142] As indicated by reference numeral 371a, the peak value of the noise current INOISE when the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are simultaneous is greater than the peak value of the noise current INOISE when the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are not simultaneous. Note that when the first activation time of the first drive signal DS11 and the second activation time of the second drive signal DS21 are simultaneous, a significant level of noise can be generated.

[0143] exist Figure 11A In the reference numeral 373a, the drain-source voltage of the third power transistor 213 is indicated, and the drain-source voltage of the fourth power transistor 223 is indicated, as indicated by reference numeral 375a.

[0144] Figure 11B This indicates that when the multi-output voltage converter 10a does not generate the intensity adjustment signal SAS... Figure 1 Timing diagram of example operation of the multi-output voltage converter 10a.

[0145] Depending on whether the corresponding drive signal among the first drive signal DS11, the second drive signal DS21, the third drive signal DS12, and the fourth drive signal DS22 is deactivated or activated, each of the first inductor current IL1 and the second inductor current IL2 can be decreased or increased respectively.

[0146] At the point when the first drive signal DS11 or the second drive signal DS21 is deactivated, the noise current INOISE generated by the parasitic inductance and parasitic capacitance has a peak value.

[0147] As indicated by reference numeral 371b, the peak value of the noise current INOISE when the first deactivation time of the first drive signal DS11 and the second deactivation time of the second drive signal DS21 are simultaneous is greater than the peak value of the noise current INOISE when the first deactivation time of the first drive signal DS11 and the second deactivation time of the second drive signal DS21 are not simultaneous. Note that a significant level of noise is generated when the first deactivation time of the first drive signal DS11 and the second deactivation time of the second drive signal DS21 are simultaneous.

[0148] exist Figure 11B In the reference numeral 373b, the drain-source voltage of the third power transistor 213 is indicated, and the drain-source voltage of the fourth power transistor 223 is indicated by the reference numeral 375b.

[0149] Figure 12 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0150] exist Figure 12 In order to facilitate explanation, and Figure 1 Duplicate descriptions will be omitted.

[0151] Reference Figure 12The multi-output voltage converter 10b may include a first drive circuit 100b, a second drive circuit 150b, a first conversion circuit 210b, a second conversion circuit 220b, a first feedback circuit 230b, a second feedback circuit 240b, a control circuit 270b, and a SAS generator 300b. The multi-output voltage converter 10b may also include a reference voltage generator 350b.

[0152] exist Figure 12 For ease of explanation, a load 250b connected to the first output node NO1 of the multi-output voltage converter 10b and a load 260b connected to the second output node NO2 of the multi-output voltage converter 10b are also shown.

[0153] The first conversion circuit 210b can be connected between voltage node VN and ground node GN, and may include a first power transistor 211, a diode 214, a first inductor La, and a first capacitor C1. Voltage node VN can be connected to input voltage VIN, and ground node GN can be connected to ground voltage VSS. The first conversion circuit 210b can generate a first output voltage Vout1 at the first output node NO1 by converting the voltage level of input voltage VIN to a first voltage level based on a first drive signal DS1.

[0154] A first power transistor 211 may be coupled between the input voltage VIN and the first switching node SN1, and may have a gate for receiving a first drive signal DS1. The first power transistor 211 may be implemented using an NMOS transistor. A diode 214 may be coupled between the first switching node SN1 and the ground voltage VSS. A first inductor La may be coupled between the first switching node SN1 and the first output node NO1, and a first capacitor C1 may be coupled between the first output node NO1 and the ground voltage VSS.

[0155] In response to the first drive signal DS1 being activated by a logic high level, the first power transistor 211 can be turned on and pull up the first switching node SN1.

[0156] The first feedback circuit 230b can generate a first feedback voltage VFB1 that is proportional to the first output voltage Vout1, and can provide the first feedback voltage VFB1 to the control circuit 270b.

[0157] The second conversion circuit 220b can be connected between voltage node VN and ground node GN, and may include a second power transistor 221, a diode 224, a second inductor Lb, and a second capacitor C2. The second conversion circuit 220b can generate a second output voltage Vout2 at the second output node NO2 by converting the input voltage VIN based on the second drive signal DS2.

[0158] A second power transistor 221 may be coupled between the input voltage VIN and the second switching node SN2, and may have a gate for receiving a second drive signal DS2. The second power transistor 221 may be implemented using an NMOS transistor. A diode 224 may be coupled between the second switching node SN2 and ground voltage VSS. A second inductor Lb may be coupled between the second switching node SN2 and the second output node NO2, and a second capacitor C2 may be coupled between the second output node NO2 and ground voltage VSS.

[0159] In response to the second drive signal DS21 being activated by a logic high level, the second power transistor 221 can be turned on and pull up the second switching node SN2.

[0160] The second feedback circuit 240b can generate a second feedback voltage VFB2 that is proportional to the second output voltage Vout2, and can provide the second feedback voltage VFB2 to the control circuit 270b.

[0161] The reference voltage generator 350b can generate a first reference voltage VREF1 and a second reference voltage VREF2, and can provide the first reference voltage VREF1 and the second reference voltage VREF2 to the control circuit 270b.

[0162] Control circuit 270b can receive a first feedback voltage VFB1, a second feedback voltage VFB2, a first reference voltage VREF1, and a second reference voltage VREF2. It can generate a first internal drive signal IDS1 by comparing the first feedback voltage VFB1 with the first reference voltage VREF1, and generate a second internal drive signal IDS2 by comparing the second feedback voltage VFB2 with the second reference voltage VREF2. First drive circuit 100b can generate a first drive signal DS1 based on the first internal drive signal IDS1. Second drive circuit 150b can generate a second drive signal DS2 based on the second internal drive signal IDS2.

[0163] The control circuit 270b can provide the first internal drive signal IDS1 to the first drive circuit 100b, provide the second internal drive signal IDS2 to the second drive circuit 150b, and provide the first internal drive signal IDS1 and the second internal drive signal IDS2 to the SAS generator 300b.

[0164] The SAS generator 300b can receive a first internal drive signal IDS1 and a second internal drive signal IDS2, monitor the first transition timing of the first internal drive signal IDS1 and the second transition timing of the second internal drive signal IDS2, and generate an intensity adjustment signal SASa that transitions to a first logic level based on the first transition timing of the first internal drive signal IDS1 and the second transition timing of the second internal drive signal IDS2. The intensity adjustment signal SASa can be provided to the first drive circuit 100b and the second drive circuit 150b. When the first internal drive signal IDS1 and the second internal drive signal IDS2 simultaneously transition to the same logic level, the intensity adjustment signal SASa can transition to a logic low level. The SAS generator 300b can generate the intensity adjustment signal SASa with a logic low level when it detects that the first transition timing of the first internal drive signal IDS1 and the second transition timing of the second internal drive signal IDS2 are substantially simultaneous.

[0165] The first driving circuit 100b can generate a first driving signal DS1 based on a first internal driving signal IDS1, and can dynamically reduce the driving intensity of the first power transistor 211 driven by the first driving signal DS1 based on the intensity adjustment signal SASa and the first internal driving signal IDS1.

[0166] The second drive circuit 150b can generate a second drive signal DS2 based on the second internal drive signal IDS2, and can selectively reduce the drive intensity of the second power transistor 221 driven by the second drive signal DS2 based on the intensity adjustment signal SASa and the second internal drive signal IDS2.

[0167] Based on an intensity adjustment signal SAsa indicating that the first transition timing of the first internal drive signal IDS1 and the second transition timing of the second internal drive signal IDS2 are simultaneous, the first drive circuit 100 can reduce the drive intensity of the first power transistor 211 driven by the first drive signal DS1 based on the intensity adjustment signal SAsa and the first internal drive signal IDS1, and the second drive circuit 150b can reduce the drive intensity of the second power transistor 221 driven by the second drive signal DS2 based on the intensity adjustment signal SAsa and the second internal drive signal IDS2.

[0168] Therefore, when the first transition timing of the first internal drive signal IDS1 and the second transition timing of the second internal drive signal IDS2 are simultaneous, and the first power transistor 211 and the second power transistor 221 are simultaneously turned on or off, the drive strength of each of the first drive signal DS1 and the second drive signal DS2 is reduced. Consequently, the ground noise generated at the ground node GN of the multi-output voltage converter 10b can be reduced, resulting in an overall reduction in the switching losses of the multi-output voltage converter.

[0169] Figure 13 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0170] exist Figure 13 In order to facilitate explanation, and Figure 1 Duplicate descriptions will be omitted.

[0171] Reference Figure 13 The multi-output voltage converter 10c may include a first drive circuit 100c, a second drive circuit 150c, a first conversion circuit 210c, a second conversion circuit 220c, a first feedback circuit 230c, a second feedback circuit 240c, a control circuit 270c, and a SAS generator 300c. The multi-output voltage converter 10c may also include a reference voltage generator 350c.

[0172] exist Figure 13 For ease of explanation, a load 250c connected to the first output node NO1a of the multi-output voltage converter 10c and a load 260c connected to the second output node NO2a of the multi-output voltage converter 10c are also shown.

[0173] The first conversion circuit 210c can be connected between the first output node NO1a and the ground node GN, and may include a first power transistor 211, a third power transistor 213, a first inductor La coupled to the input voltage VIN, and a first capacitor C1. The ground node GN can be connected to the ground voltage VSS. The first conversion circuit 210c can generate a first output voltage Vout1a at the first output node NO1a by converting the input voltage VIN based on the first drive signal DS11a and the third drive signal DS12a. The voltage level of the first output voltage Vout1a may be lower than the voltage level of the input voltage VIN.

[0174] A first power transistor 211 may be connected between the first output node NO1a and the first switching node SN1, and may have a gate for receiving a first drive signal DS11a. The first power transistor 211 may be implemented using an NMOS transistor. A third power transistor 213 may be connected between the first switching node SN1 and the ground voltage VSS, and may have a gate for receiving a third drive signal DS12a. The third power transistor 213 may be implemented using an NMOS transistor. A first inductor La may be connected between the input voltage VIN and the first switching node SN1, and a first capacitor C1 may be connected between the first output node NO1a and the ground voltage VSS.

[0175] In response to the first drive signal DS11a being activated by a logic high level, the first power transistor 211 is turned on and can provide the energy stored in the first inductor La as the first output voltage Vout1a at the first output node NO1a. In response to the third drive signal DS12a being activated by a logic high level, the third power transistor 213 is turned on and pulls down the first switching node SN1.

[0176] The first inductor La can store energy based on the input voltage VIN. The first inductor current IL1a can flow from the first inductor La to the first switching node SN1. The first capacitor C1 can store the first output voltage Vout1a.

[0177] The first feedback circuit 230c can generate a first feedback voltage VFB1a that is proportional to the first output voltage Vout1a, and can provide the first feedback voltage VFB1a to the control circuit 270c.

[0178] The second conversion circuit 220c can be connected between the second output node NO2a and the ground node GN, and may include a second power transistor 221, a fourth power transistor 223, a second inductor Lb coupled to the input voltage VIN, and a second capacitor C2. The second conversion circuit 220c can generate a second output voltage Vout2a at the second output node NO2a by converting the input voltage VIN based on the second drive signal DS2a1 and the fourth drive signal DS22a.

[0179] A second power transistor 221 may be connected between the second output node NO2a and the second switching node SN2, and may have a gate for receiving the second drive signal DS21a. The second power transistor 221 may be implemented using an NMOS transistor. A fourth power transistor 223 may be connected between the second switching node SN2 and the ground voltage VSS, and may have a gate for receiving the fourth drive signal DS22a. The fourth power transistor 223 may be implemented using an NMOS transistor. A first inductor La may be connected between the input voltage VIN and the second switching node SN2, and a second capacitor C2 may be connected between the second output node NO2a and the ground voltage VSS.

[0180] In response to the second drive signal DS21a being activated by a logic high level, the second power transistor 221 is turned on and can provide the energy stored in the second inductor Lb as the second output voltage Vout2a at the second output node NO2a. In response to the fourth drive signal DS22a being activated by a logic high level, the fourth power transistor 223 is turned on and pulls down the second switching node SN2.

[0181] The second inductor Lb can store energy based on the input voltage VIN. The second inductor current IL2a can flow from the second inductor Lb to the second switching node SN2. The second capacitor C2 can store the second output voltage Vout2a.

[0182] The second feedback circuit 240c can generate a second feedback voltage VFB2a that is proportional to the second output voltage Vout2a, and can provide the second feedback voltage VFB2a to the control circuit 270c.

[0183] The first load current ILD1a can flow into the load 250c based on the first output voltage Vout1a, and the second load current ILD2a can flow into the load 260c based on the second output voltage Vout2a.

[0184] The first driving circuit 100c, the first conversion circuit 210c, and the first feedback circuit 230c can constitute a first boost converter, and the second driving circuit 150c, the second conversion circuit 220c, and the second feedback circuit 240c can constitute a second boost converter.

[0185] The reference voltage generator 350c can generate a first reference voltage VREF1 and a second reference voltage VREF2, and can provide the first reference voltage VREF1 and the second reference voltage VREF2 to the control circuit 270c.

[0186] The control circuit 270c can receive a first feedback voltage VFB1a, a second feedback voltage VFB2a, a first reference voltage VREF1, and a second reference voltage VREF2. It can generate a first internal drive signal IDS11a and a third internal drive signal IDS12a based on comparing the first feedback voltage VFB1a with the first reference voltage VREF1, and can generate a second internal drive signal IDS21a and a fourth internal drive signal IDS22a based on comparing the second feedback voltage VFB2a with the second reference voltage VREF2. The first internal drive signal IDS11a can be associated with the first drive signal DS11a, the third internal drive signal IDS12a can be associated with the third drive signal DS12a, the second internal drive signal IDS21a can be associated with the second drive signal DS21a, and the fourth internal drive signal IDS22a can be associated with the fourth drive signal DS22a.

[0187] The control circuit 270c can provide the first internal drive signal IDS11a and the third internal drive signal IDS12a to the first drive circuit 100c, provide the second internal drive signal IDS21a and the fourth internal drive signal IDS22a to the second drive circuit 150c, and provide the first internal drive signal IDS11a and the second internal drive signal IDS21a to the SAS generator 300c.

[0188] The SAS generator 300c can receive a first internal drive signal IDS11a and a second internal drive signal IDS21a, monitor the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a, and generate an intensity adjustment signal SASb that transitions to a first logic level in response to detecting that the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a are simultaneous. The intensity adjustment signal SASb can be provided to the first drive circuit 100c and the second drive circuit 150c. The SAS generator 300c can generate the intensity adjustment signal SASb at a logic low level based on whether the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a are simultaneous.

[0189] The implementation of SAS generator 300c can be compared with Figure 5A SAS Generator 300a or Figure 5B The implementation method is the same as that of the SAS generator 300a_1.

[0190] The first driving circuit 100c can generate a first driving signal DS11a based on a first internal driving signal IDS11a, generate a third driving signal DS12a based on a third internal driving signal IDS12a, and dynamically reduce the driving intensity of the first power transistor 211 driven by the first driving signal DS11a based on the intensity adjustment signal SASb and the first internal driving signal IDS11a.

[0191] Based on an intensity adjustment signal SASb indicating that the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a are simultaneous, the first drive circuit 100c can reduce the drive intensity of the first power transistor 211 driven by the first drive signal DS11a based on the intensity adjustment signal SASb and the first internal drive signal IDS11a. Based on an intensity adjustment signal SASb indicating that the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a are not simultaneous, the first drive circuit 100c can maintain the normal drive intensity of the first power transistor 211 driven by the first drive signal DS11a based on the intensity adjustment signal SASb and the first internal drive signal IDS11a.

[0192] The second driving circuit 150c can generate a second driving signal DS21a based on the second internal driving signal IDS21a, generate a fourth driving signal DS22a based on the fourth internal driving signal IDS22a, and selectively reduce the driving intensity of the second power transistor 221 driven by the second driving signal DS21a based on the intensity adjustment signal SASb and the second internal driving signal IDS21a.

[0193] Based on an intensity adjustment signal SASb indicating that the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a are simultaneous, the second drive circuit 150c can reduce the drive intensity of the second power transistor 221 driven by the second drive signal DS21a based on the intensity adjustment signal SASb and the second internal drive signal IDS21a. Based on an intensity adjustment signal SASb indicating that the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a are not simultaneous, the second drive circuit 150c can maintain the drive intensity of the second power transistor 221 driven by the second drive signal DS21a based on the intensity adjustment signal SASb and the second internal drive signal IDS21a.

[0194] Therefore, when the first transition timing of the first internal drive signal IDS11a and the second transition timing of the second internal drive signal IDS21a are simultaneous, and the first power transistor 211 and the second power transistor 221 are simultaneously turned on or off, the drive strength of each of the first power transistor 211 and the second power transistor 221 driven by the first drive signal DS11a and the second drive signal DS21a, respectively, is reduced. Consequently, the ground noise generated at the ground node GN of the multi-output voltage converter 10c can be reduced, resulting in an overall reduction in the switching losses of the multi-output voltage converter.

[0195] Figure 14 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0196] exist Figure 14 In order to facilitate explanation, and Figure 1 Duplicate descriptions will be omitted.

[0197] Reference Figure 14 The multi-output voltage converter 10d may include a first drive circuit 100d, a second drive circuit 150d, a first conversion circuit 210d, a second conversion circuit 220d, a first feedback circuit 230d, a second feedback circuit 240d, a control circuit 270d, and a SAS generator 300d. The multi-output voltage converter 10d may also include a reference voltage generator 350d.

[0198] A first conversion circuit 210d may be connected between a voltage node VN and a ground node GN, and may include a first power transistor 211, a third power transistor 213, a fifth power transistor 215, a seventh power transistor 217, a first inductor La, and a first capacitor C1b. The voltage node VN may be connected to the input voltage VIN, and the ground node GN may be connected to the ground voltage VSS. The first conversion circuit 210d may generate a first output voltage Vout1b at a first output node NO1b by converting the input voltage VIN based on a first set of drive signals DS11, DS12, DS13, and DS14 (e.g., first drive signal DS11, third drive signal DS12, fifth drive signal DS13, and seventh drive signal DS14). The voltage level of the first output voltage Vout1b may be less than or greater than the voltage level of the input voltage VIN.

[0199] A first power transistor 211 may be coupled between the input voltage VIN and the first switching node SN1, and may have a gate for receiving a first drive signal DS11. The first power transistor 211 may be implemented using an NMOS transistor. A third power transistor 213 may be coupled between the first switching node SN1 and the ground voltage VSS, and may have a gate for receiving a third drive signal DS12. The third power transistor 213 may be implemented using an NMOS transistor.

[0200] A fifth power transistor 215 may be connected between the third switching node SN1b and the ground voltage VSS, and may have a gate for receiving the fifth drive signal DS13. The fifth power transistor 215 may be implemented using an NMOS transistor. A seventh power transistor 217 may be connected between the third switching node SN1b and the first output node NO1b, and may have a gate for receiving the seventh drive signal DS14. The seventh power transistor 217 may be implemented using an NMOS transistor.

[0201] A first inductor La can be connected between a first switching node SN1 and a third switching node SN1b, and a first capacitor C1b can be connected between a first output node NO1b and ground voltage VSS. A first inductor current IL1 can flow from the first inductor La to the third switching node SN1b.

[0202] In response to the first drive signal DS11 being activated by a logic high level, the first power transistor 211 is turned on and pulls up the first switching node SN1. In response to the third drive signal DS12 being activated by a logic high level, the third power transistor 213 is turned on and pulls down the first switching node SN1.

[0203] In response to the fifth drive signal DS13 being activated by a logic high level, the fifth power transistor 215 is turned on and pulls down the third switching node SN1b. In response to the seventh drive signal DS14 being activated by a logic high level, the seventh power transistor 217 is turned on and can provide the voltage of the third switching node SN1b to the first output node NO1b as the first output voltage Vout1b.

[0204] The first feedback circuit 230d can generate a first feedback voltage VFB1 that is proportional to the first output voltage Vout1b, and can provide the first feedback voltage VFB1 to the control circuit 270d.

[0205] The second conversion circuit 220d can be connected between the voltage node VN and the ground node GN, and may include a second power transistor 221, a fourth power transistor 223, a sixth power transistor 225, an eighth power transistor 227, a second inductor Lb, and a second capacitor C2b. The second conversion circuit 220d can generate a second output voltage Vout2b at the second output node NO2b by converting the input voltage VIN based on a second set of drive signals DS21, DS22, DS23, and DS24 (e.g., second drive signal DS21, fourth drive signal DS22, sixth drive signal DS23, and eighth drive signal DS24). The voltage level of the second output voltage Vout2b can be less than or greater than the voltage level of the input voltage VIN.

[0206] The second power transistor 221 may be coupled between the input voltage VIN and the second switching node SN2, and may have a gate for receiving the second drive signal DS21. The second power transistor 221 may be implemented using an NMOS transistor. The fourth power transistor 223 may be coupled between the second switching node SN2 and the ground voltage VSS, and may have a gate for receiving the fourth drive signal DS22. The fourth power transistor 223 may be implemented using an NMOS transistor.

[0207] A sixth power transistor 225 may be connected between the fourth switching node SN2b and the ground voltage VSS, and may have a gate for receiving the sixth drive signal DS23. The sixth power transistor 225 may be implemented using an NMOS transistor. An eighth power transistor 227 may be connected between the fourth switching node SN2b and the second output node NO2b, and may have a gate for receiving the eighth drive signal DS24. The eighth power transistor 227 may be implemented using an NMOS transistor.

[0208] The second inductor Lb can be connected between the second switching node SN2 and the fourth switching node SN2b, and the second capacitor C2b can be connected between the second output node NO2b and the ground voltage VSS. The second inductor current IL2 can flow from the second inductor Lb to the fourth switching node SN2b.

[0209] In response to the second drive signal DS21 being activated by a logic high level, the second power transistor 221 is turned on and pulls up the second switching node SN2. In response to the fourth drive signal DS22 being activated by a logic high level, the fourth power transistor 223 is turned on and pulls down the second switching node SN2.

[0210] In response to the sixth drive signal DS23 being activated by a logic high level, the sixth power transistor 225 is turned on and pulls down the fourth switching node SN2b. In response to the eighth drive signal DS24 being activated by a logic high level, the eighth power transistor 227 is turned on and can provide the voltage of the fourth switching node SN2b to the second output node NO2b as the second output voltage Vout2b.

[0211] The second feedback circuit 240d can generate a second feedback voltage VFB2 that is proportional to the second output voltage Vout2b, and can provide the second feedback voltage VFB2 to the control circuit 270d.

[0212] The first driving circuit 100d, the first conversion circuit 210d, and the first feedback circuit 230d can constitute a first buck-boost converter, and the second driving circuit 150d, the second conversion circuit 220d, and the second feedback circuit 240d can constitute a second buck-boost converter.

[0213] The reference voltage generator 350d can generate a first reference voltage VREF1 and a second reference voltage VREF2, and can provide the first reference voltage VREF1 and the second reference voltage VREF2 to the control circuit 270d.

[0214] The control circuit 270d can receive a first feedback voltage VFB1, a second feedback voltage VFB2, a first reference voltage VREF1, and a second reference voltage VREF2. It can generate a first set of internal drive signals IDS11, IDS12, IDS13, and IDS14 (e.g., first internal drive signal IDS11, third internal drive signal IDS12, fifth internal drive signal IDS13, and seventh internal drive signal IDS14) based on comparing the first feedback voltage VFB1 with the first reference voltage VREF1. It can also generate a second set of internal drive signals IDS21, IDS22, IDS23, and IDS24 (e.g., second internal drive signal IDS21, fourth internal drive signal IDS22, sixth internal drive signal IDS23, and eighth internal drive signal IDS24) based on comparing the second feedback voltage VFB2 with the second reference voltage VREF2. Each of the first set of internal drive signals IDS11, IDS12, IDS13, and IDS14 can be associated with a corresponding drive signal in the first set of drive signals DS11, DS12, DS13, and DS14, and each of the second set of internal drive signals IDS21, IDS22, IDS23, and IDS24 can be associated with a corresponding drive signal in the second set of drive signals DS21, DS22, DS23, and DS24.

[0215] The control circuit 270d can provide the first set of internal drive signals IDS11, IDS12, IDS13 and IDS14 to the first drive circuit 100d, and can provide the second set of internal drive signals IDS21, IDS22, IDS23 and IDS24 to the second drive circuit 150d. It can also provide the first internal drive signal IDS11 and the second internal drive signal IDS21 to the SAS generator 300d.

[0216] The SAS generator 300d can receive a first internal drive signal IDS11 and a second internal drive signal IDS21, detect the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21, and generate an intensity adjustment signal SASd that transitions to a first logic level in response to the detection that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous. The intensity adjustment signal SASd can be provided to the first drive circuit 100d and the second drive circuit 150d. The SAS generator 300d can generate an intensity adjustment signal SASd with a logic low level based on whether the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous.

[0217] SAS Generator 300d can be used Figure 5A SAS Generator 300a or Figure 5B SAS generator 300a_1.

[0218] The first driving circuit 100d can generate each of the first set of internal driving signals DS11, DS12, DS13 and DS14 based on the corresponding internal driving signals in the first set of internal driving signals IDS11, IDS12, IDS13 and IDS14, and can selectively reduce the driving intensity of the first power transistor 211 driven by the first driving signal DS11 based on the intensity adjustment signal SASD and the first internal driving signal IDS11.

[0219] Based on an intensity adjustment signal SASD indicating that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous, the first drive circuit 100d can reduce the drive intensity of the first power transistor 211 driven by the first drive signal IDS11 based on the intensity adjustment signal SASD and the first internal drive signal IDS11. Based on an intensity adjustment signal SASD indicating that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are not simultaneous, the first drive circuit 100d can maintain the normal drive intensity of the first power transistor 211 based on the intensity adjustment signal SASD and the first internal drive signal IDS11.

[0220] The second drive circuit 150d can generate each of the second set of internal drive signals DS21, DS22, DS23 and DS24 based on the corresponding internal drive signals in the second set of internal drive signals IDS21, IDS22, IDS23 and IDS24, and can selectively reduce the drive intensity of the second power transistor 221 driven by the second drive signal DS21 based on the intensity adjustment signal SASD and the second internal drive signal IDS21.

[0221] Based on an intensity adjustment signal SASD indicating that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous, the second drive circuit 150d can reduce the drive intensity of the second power transistor 221 driven by the second drive signal DS21 based on the intensity adjustment signal SASD and the second internal drive signal IDS21. Based on an intensity adjustment signal SASD indicating that the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are not simultaneous, the second drive circuit 150d can maintain the drive intensity of the second power transistor 221 driven by the second drive signal DS21 based on the intensity adjustment signal SASD and the second internal drive signal IDS21.

[0222] Therefore, when the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous, and the first power transistor 211 and the second power transistor 221 are simultaneously turned on or off, the drive strength of each of the first power transistor 211 and the second power transistor 221 driven by the first drive signal DS11 and the second drive signal DS21, respectively, is reduced. Consequently, the ground noise generated at the ground node GN of the multi-output voltage converter 10d can be reduced, resulting in an overall reduction in the switching losses of the multi-output voltage converter.

[0223] Figure 15This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0224] Reference Figure 15 The multi-output voltage converter 500 may include multiple drive circuits 510a, 510b, 510c and 510d, multiple conversion circuits 520, 530, 540 and 550, control circuit 560 and SAS generator 570.

[0225] The conversion circuit 520 can be connected between voltage node VN and ground voltage VSS, and may include a first power transistor 521, a fifth power transistor 523, a first inductor L11, and a first capacitor C11. Voltage node VN can be connected to input voltage VIN. The conversion circuit 520 can generate a first output voltage Vout11 at the first output node NO11 by converting the input voltage VIN based on drive signals DS11 and DS12. The voltage level of the first output voltage Vout11 may be lower than the voltage level of the input voltage VIN.

[0226] A first power transistor 521 may be connected between the input voltage VIN and the first switching node SN11, and may have a gate for receiving a drive signal DS11. A fifth power transistor 523 may be connected between the first switching node SN11 and the ground voltage VSS, and may have a gate for receiving a drive signal DS12. A first inductor L11 may be connected between the first switching node SN11 and the first output node NO11, and a first capacitor C11 may be connected between the first output node NO11 and the ground voltage VSS.

[0227] In response to the drive signal DS11 being activated by a logic high level, the first power transistor 521 is turned on and pulls up the first switching node SN11. In response to the drive signal DS12 being activated by a logic high level, the fifth power transistor 523 is turned on and pulls down the first switching node SN11.

[0228] The first inductor L11 and the first capacitor C11 can operate as a low-pass filter, and the first output voltage Vout11 can be output at the first output node NO11 by filtering out high-frequency components from the voltage at the first switching node SN11. The first inductor current IL11 can flow from the first inductor L11 to the first output node NO11.

[0229] The conversion circuit 530 can be connected between voltage node VN and ground voltage VSS, and may include a second power transistor 531, a sixth power transistor 533, a second inductor L12, and a second capacitor C12. The conversion circuit 530 can generate a second output voltage Vout12 at the second output node NO12 by converting the input voltage VIN based on drive signals DS21 and DS22. The voltage level of the second output voltage Vout12 may be lower than the voltage level of the input voltage VIN.

[0230] A second power transistor 531 may be connected between the input voltage VIN and the second switching node SN12, and may have a gate for receiving a drive signal DS21. A sixth power transistor 533 may be connected between the second switching node SN12 and the ground voltage VSS, and may have a gate for receiving a drive signal DS22. A second inductor L12 may be connected between the second switching node SN12 and the second output node NO12, and a second capacitor C12 may be connected between the second output node NO12 and the ground voltage VSS.

[0231] In response to the drive signal DS21 being activated by a logic high level, the second power transistor 531 is turned on and pulls up the second switching node SN12. In response to the drive signal DS22 being activated by a logic high level, the sixth power transistor 533 is turned on and pulls down the second switching node SN12.

[0232] The second inductor L12 and the second capacitor C12 can operate as a low-pass filter, and the second output voltage Vout12 can be output at the second output node NO12 by filtering out high-frequency components from the voltage at the second switching node SN12. The second inductor current IL12 can flow from the second inductor L12 to the second output node NO12.

[0233] The conversion circuit 540 can be connected between voltage node VN and ground voltage VSS, and may include a third power transistor 541, a seventh power transistor 543, a third inductor L13, and a third capacitor C13. The conversion circuit 540 can generate a third output voltage Vout13 at the third output node NO13 by converting the input voltage VIN based on drive signals DS31 and DS32. The voltage level of the third output voltage Vout13 may be lower than the voltage level of the input voltage VIN.

[0234] A third power transistor 541 may be connected between the input voltage VIN and the third switching node SN13, and may have a gate for receiving a drive signal DS31. A seventh power transistor 543 may be connected between the third switching node SN13 and the ground voltage VSS, and may have a gate for receiving a drive signal DS32. A third inductor L13 may be connected between the third switching node SN13 and the third output node NO13, and a third capacitor C13 may be connected between the third output node NO13 and the ground voltage VSS.

[0235] In response to the drive signal DS31 being activated by a logic high level, the third power transistor 541 is turned on and pulls up the third switching node SN13. In response to the drive signal DS32 being activated by a logic high level, the seventh power transistor 543 is turned on and pulls down the third switching node SN13.

[0236] The third inductor L13 and the third capacitor C13 can operate as a low-pass filter, and the third output voltage Vout13 can be output at the third output node NO13 by filtering out high-frequency components from the voltage at the third switching node SN13. The third inductor current IL13 can flow from the third inductor L13 to the third output node NO13.

[0237] The conversion circuit 550 can be connected between voltage node VN and ground voltage VSS, and may include a fourth power transistor 551, an eighth power transistor 553, a fourth inductor L14, and a fourth capacitor C14. The conversion circuit 550 can generate a fourth output voltage Vout14 at the fourth output node NO14 by converting the input voltage VIN based on drive signals DS41 and DS42. The voltage level of the fourth output voltage Vout14 may be lower than the voltage level of the input voltage VIN.

[0238] A fourth power transistor 551 may be connected between the input voltage VIN and the fourth switching node SN14, and may have a gate for receiving a drive signal DS41. An eighth power transistor 553 may be connected between the fourth switching node SN14 and the ground voltage VSS, and may have a gate for receiving a drive signal DS42. A fourth inductor L14 may be connected between the fourth switching node SN14 and the fourth output node NO14, and a fourth capacitor C14 may be connected between the fourth output node NO14 and the ground voltage VSS.

[0239] In response to the drive signal DS41 being activated by a logic high level, the fourth power transistor 551 is turned on and pulls up the fourth switching node SN14. In response to the drive signal DS42 being activated by a logic high level, the eighth power transistor 553 is turned on and pulls down the fourth switching node SN14.

[0240] The fourth inductor L14 and the fourth capacitor C14 can operate as a low-pass filter, and the fourth output voltage Vout14 can be output at the fourth output node NO14 by filtering out high-frequency components from the voltage at the fourth switching node SN14. The fourth inductor current IL14 can flow from the fourth inductor L14 to the fourth output node NO14.

[0241] The control circuit 560 can receive output voltages Vout11, Vout12, Vout13, and Vout14, and reference voltages VREF1, VREF2, VREF3, and VREF4. It can generate internal drive signals IDS11 and IDS12 based on comparing the output voltage Vout11 with the reference voltage VREF1, internal drive signals IDS21 and IDS22 based on comparing the output voltage Vout12 with the reference voltage VREF2, internal drive signals IDS31 and IDS32 based on comparing the output voltage Vout13 with the reference voltage VREF3, and internal drive signals IDS41 and IDS42 based on comparing the output voltage Vout14 with the reference voltage VREF4. Control circuit 560 can provide internal drive signals IDS11 and IDS12 to drive circuit 510a, internal drive signals IDS21 and IDS22 to drive circuit 510b, internal drive signals IDS31 and IDS32 to drive circuit 510c, internal drive signals IDS41 and IDS42 to drive circuit 510d, and can provide internal drive signals IDS11, IDS21, IDS31, and IDS41 to SAS generator 570. Internal drive signals IDS11, IDS21, IDS31, and IDS41 can be high-side internal drive signals.

[0242] The SAS generator 570 can receive high-side internal drive signals IDS11, IDS21, IDS31, and IDS41, monitor the transition timing of each of the high-side internal drive signals IDS11, IDS21, IDS31, and IDS41, generate an intensity adjustment signal SAS11 that transitions to a logic low level based on the simultaneous transition timing of internal drive signal IDS11 and internal drive signal IDS31, generate an intensity adjustment signal SAS12 that transitions to a logic low level based on the simultaneous transition timing of internal drive signal IDS21 and internal drive signal IDS41, and provide the intensity adjustment signal SAS11 to the drive circuits 510a and 510c associated with the internal drive signals IDS11 and IDS21, and provide the intensity adjustment signal SAS12 to the drive circuits 510b and 510d.

[0243] A driving circuit (e.g., a first driving circuit) 510a can generate driving signals DS11 and DS12 based on internal driving signals IDS11 and IDS12, and can selectively reduce the driving intensity of the first power transistor 521 based on the intensity adjustment signal SAS11 and the internal driving signal IDS11. A driving circuit (e.g., a second driving circuit) 510c can generate driving signals DS31 and DS32 based on internal driving signals IDS31 and IDS32, and can selectively reduce the driving intensity of the third power transistor 541 based on the intensity adjustment signal SAS11 and the internal driving signal IDS31.

[0244] Drive circuit 510b can generate drive signals DS21 and DS22 based on internal drive signals IDS21 and IDS22, and can maintain the normal drive strength of the second power transistor 531 based on intensity adjustment signal SAS12 and internal drive signal IDS21. Drive circuit 510d can generate drive signals DS41 and DS42 based on internal drive signals IDS41 and IDS42, and can maintain the normal drive strength of the fourth power transistor 551 based on intensity adjustment signal SAS12 and internal drive signal IDS41.

[0245] Therefore, when the first transition timing of the internal drive signal IDS11 and the second transition timing of the internal drive signal IDS21 are simultaneous, and the first power transistor 521 and the second power transistor 531 are simultaneously turned on or off, the drive strength of each of the first power transistor 521 and the second power transistor 531 driven by the drive signals DS11 and DS21, respectively, can be reduced. Consequently, the ground noise generated at the ground node of the ground voltage VSS of the multi-output voltage converter 500 can be reduced, resulting in an overall reduction in the switching losses of the multi-output voltage converter.

[0246] Figure 16 This illustrates an example embodiment. Figure 15 Timing diagram of example operation of a multi-output voltage converter.

[0247] Reference Figure 15 and Figure 16 When the activation timing of the internal drive signal IDS11 at time point T21 is simultaneous with the activation timing of the internal drive signal IDS31, the intensity adjustment signal SAS11 has a logic low level between time points T21 and T22, and the drive intensity of each of the first power transistor 521 and the third power transistor 541 is reduced based on the intensity adjustment signal SAS11. Furthermore, because the intensity adjustment signal SAS12 is held at a logic high level, the drive intensity of each of the second power transistor 531 and the fourth power transistor 551 can be maintained.

[0248] Figure 17 This is a block diagram illustrating an example of a multi-output voltage converter according to an exemplary embodiment.

[0249] exist Figure 17 In order to facilitate explanation, and Figure 1 Duplicate descriptions will be omitted.

[0250] Reference Figure 17 The multi-output voltage converter 10e may include a first drive circuit 100e, a second drive circuit 150e, a first conversion circuit 210a, a second conversion circuit 220a, a first feedback circuit 230a, a second feedback circuit 240a, a control circuit 270a, and a shift signal generator 330. The multi-output voltage converter 10e may also include a reference voltage generator 350a.

[0251] Figure 17 Multi-output voltage converter 10e and Figure 1 The difference between the multi-output voltage converter 10a and the multi-output voltage converter 10e is that the multi-output voltage converter 10e includes a shift signal generator 330 (instead of the SAS generator 300a). Therefore, a description of the shift signal generator 330 will be included, and descriptions of other components will be omitted.

[0252] The shift signal generator 330 can receive a first internal drive signal IDS11 and a second internal drive signal IDS21, monitor the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21, generate a shift signal SHT based on the simultaneous occurrence of the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21, and provide the shift signal SHT to the first drive circuit 100e or the second drive circuit 150e. Figure 17 In this context, it is explained that the shift signal generator 330 provides the shift signal SHT to the second drive circuit 150e.

[0253] The first driving circuit 100e can generate a first driving signal DS11 based on a first internal driving signal IDS11, and can generate a third driving signal DS12 based on a third internal driving signal IDS12.

[0254] The second driving circuit 150e can generate a second driving signal DS21 based on the second internal driving signal IDS21, and can generate a fourth driving signal DS22 based on the fourth internal driving signal IDS22. The transition timing of the second internal driving signal IDS21 can be delayed based on the shift signal SHT and the second internal driving signal IDS21, so that the transition timing of the second internal driving signal IDS21 is not simultaneous with the transition timing of the first internal driving signal IDS11.

[0255] Therefore, when the first transition timing of the first internal drive signal IDS11 and the second transition timing of the second internal drive signal IDS21 are simultaneous, the transition timing of the second drive signal DS21 is delayed from the transition timing of the first drive signal DS11 by the shift signal SHT. Thus, the first power transistor 211 and the second power transistor 221 may not be turned on or off simultaneously. Consequently, the ground noise generated at the ground node GN of the multi-output voltage converter 10e can be reduced, resulting in an overall reduction in the switching losses of the multi-output voltage converter.

[0256] Figure 18 This illustrates an example embodiment. Figure 17 Timing diagram of example operation of a multi-output voltage converter.

[0257] Reference Figure 17 and Figure 18 When the activation timing of the first internal drive signal IDS11 is simultaneous with the activation timing of the second internal drive signal IDS21, the activation timing of the second drive signal DS21 can be delayed by a third time interval INT3 based on the shift signal SHT, so that it is not simultaneous with the activation timing of the first drive signal DS11.

[0258] exist Figure 18 The diagram shows that the activation timing of the first internal drive signal IDS11 is simultaneous with the activation timing of the second internal drive signal IDS21. In an example embodiment, when the deactivation timing of the first internal drive signal IDS11 is simultaneous with the deactivation timing of the second internal drive signal IDS21, the deactivation timing of the second drive signal DS21 can be delayed by a third time interval INT3 based on the shift signal SHT, so that it is not simultaneous with the deactivation timing of the first drive signal DS11.

[0259] Figure 19 This is a flowchart illustrating a method for operating a multi-output voltage converter according to an example embodiment.

[0260] Reference Figures 1 to 10B and Figure 19 A method for operating a multi-output voltage converter 10a is provided. The multi-output voltage converter 10a includes a first drive circuit 100a, a second drive circuit 150a, a first conversion circuit 210a, a second conversion circuit 220a, and a SAS generator 300a. According to the method, the SAS generator 300a determines whether a first internal drive signal IDS11 and a second internal drive signal IDS21 are simultaneously activated (e.g., enabled) (operation S110).

[0261] When the first internal drive signal IDS11 and the second internal drive signal IDS21 are activated simultaneously ("Yes" in operation S110), each of the first drive circuit 100a and the second drive circuit 150a generates a corresponding drive signal in the first drive signal DS11 and the second drive signal DS21, and reduces the drive intensity of the corresponding power transistor in the first power transistor 211 and the second power transistor 221 based on the intensity adjustment signal SAS (operation S120). Each of the first drive circuit 100a and the second drive circuit 150a applies the corresponding drive signal in the first drive signal DS11 and the second drive signal DS21 to the corresponding power transistor in the first power transistor 211 of the first conversion circuit 210a and the second power transistor 221 of the second conversion circuit 220a (operation S130).

[0262] When the first internal drive signal IDS11 and the second internal drive signal IDS21 are not activated simultaneously (No in operation S110), each of the first drive circuit 100a and the second drive circuit 150a generates a corresponding drive signal in the first drive signal DS11 and the second drive signal DS21, and maintains the drive strength of the corresponding power transistor in the first power transistor 211 and the second power transistor 221a based on the intensity adjustment signal SAS (operation S140). Each of the first drive circuit 100a and the second drive circuit 150a applies the corresponding drive signal in the first drive signal DS11 and the second drive signal DS21 to the corresponding power transistor in the first power transistor 211 of the first conversion circuit 210a and the second power transistor 221 of the second conversion circuit 220a (operation S150).

[0263] Figure 20 This is a block diagram illustrating an electronic device including a multi-output voltage converter according to an example embodiment.

[0264] Reference Figure 20 The electronic device 600 includes a power management integrated circuit (PMIC) 610 comprising a multi-output voltage converter (MOVC) 615, a memory controller 620, and multiple memory devices 631, 633, and 635 (memory device 1 531, memory device 2 533, and memory device 3 535). The electronic device 600 may be an SSD or memory module for use in a server.

[0265] The multi-output voltage converter 615 can generate multiple output voltages Vout based on a DC voltage (PW) received from an external source, and can provide the multiple output voltages Vout to multiple memory devices 631, 633, and 635. The memory controller 620 can control the multiple memory devices 631, 633, and 635, and can exchange data with the multiple memory devices 631, 633, and 635.

[0266] Each of the plurality of memory devices 631, 633, and 635 may be a volatile memory device or a non-volatile memory device. For example, the volatile memory device may be dynamic random access memory (DRAM), and the non-volatile memory device may be a flash memory device.

[0267] Figure 21 This is a block diagram illustrating a wireless communication device according to an example embodiment.

[0268] Reference Figure 21 The wireless communication device 700 illustrates a user equipment (UE) (or terminal) to which power is supplied by a battery 750. In some example embodiments, the wireless communication device 700 may be included in a wireless communication system using a cellular network (such as a fifth-generation (5G) communication system, a long-term evolution (LTE) communication system), or may be included in a wireless local area network (WLAN) or any other wireless communication system. In the wireless communication device 700, a multiple output voltage converter (MOVC) 745 according to an example embodiment may be used to provide variable power to a power amplifier 716.

[0269] like Figure 21 As shown, the wireless communication device 700 may include a transceiver 710, a baseband processor 720, an antenna 730, a power supply circuit 740, and a battery 750.

[0270] Transceiver 710 may include antenna interface (IF) circuitry 711, input circuitry 712, low-noise amplifier (LNA) 713, receive (RX) circuitry 714, transmit (TX) circuitry 715, power amplifier (PA) 716, and output circuitry 717. Antenna interface circuitry 711 may combine a transmitter or receiver with antenna 730 depending on the transmit or receive mode. In some example embodiments, input circuitry 712 may include matching circuitry or a filter, low-noise amplifier 713 may amplify the output signal of input circuitry 712, and RX circuitry 714 may include a mixer for down-conversion. In some example embodiments, TX circuitry 715 may include a mixer for up-conversion, power amplifier 716 may amplify the output signal of TX circuitry 715, and output circuitry 717 may include matching circuitry or a filter.

[0271] The baseband processor 720 can transmit and receive baseband signals with the transceiver 710, and can perform modulation / demodulation, encoding / decoding, etc. In some example embodiments, the baseband processor 720 may be referred to as a modem. The baseband processor 720 can generate a setting signal SET for setting the average power tracking mode or the envelope tracking mode, and can also generate a setting signal SET for changing the level of the output voltage Vout.

[0272] The power supply circuit 740 can receive an input voltage VIN from the battery 750 and can generate an output voltage Vout, which supplies power to the power amplifier 716. The power supply circuit 740 may include a multi-output voltage converter 745.

[0273] Figure 22 This is a diagram illustrating a system including a multi-output voltage converter according to an example embodiment.

[0274] Reference Figure 22 The system 2000 may include a mobile device 2100 (such as a smartphone) and an AC-DC wall adapter or travel adapter 70 for supplying power to the mobile device 2100. The travel adapter 70 can be connected to the connector 2200 of the mobile device 2100 via a cable 71 and a jack 72 to supply power to the mobile device 2100.

[0275] The mobile device 2100 may include a charging control circuit (CHGC) 2300, a load switching circuit (LSW) 2400, a battery (BAT) 2500, and internal circuitry 2600.

[0276] The charging control circuit 2300 can change the DC voltage from the travel adapter 70 to provide charging power to the battery 2500 and / or operating power to the internal circuit 2600. When the travel adapter 70 is removed, the charging power in the battery can be provided to the internal circuit 2600.

[0277] The charging control circuit 2300 may include a multi-output voltage converter (MOVC) 2350 according to the example embodiment described above. The MOVC 2350 can provide an output voltage to the internal circuitry 2600. Based on the high-side switch that is simultaneously turned on or off, the MOVC 2350 reduces the drive strength of the drive signal applied to the high-side switch, thereby reducing ground noise generated at the ground node and reducing switching losses.

[0278] exist Figure 20 , Figure 21 and Figure 22This document provides a description of various applications employing a multi-output voltage converter according to exemplary embodiments. The multi-output voltage converter according to exemplary embodiments can be used in any electronic device and system requiring voltage conversion.

[0279] This disclosure can be applied to any electronic device and system that requires voltage conversion. For example, this disclosure can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, and the like.

[0280] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A multi-output voltage converter, comprising: A first conversion circuit is configured to generate a first output voltage by converting an input voltage. The first conversion circuit includes a first power transistor configured to pull up a first switching node based on a first drive signal. The second conversion circuit is configured to generate a second output voltage by converting the input voltage. The second conversion circuit includes a second power transistor configured to pull up the second switching node based on a second drive signal. An intensity adjustment signal generator is configured to generate an intensity adjustment signal based on a first transition timing of a first internal drive signal and a second transition timing of a second internal drive signal. The first driving circuit is configured to generate a first driving signal that dynamically adjusts the driving intensity of the first power transistor based on an intensity adjustment signal and a first internal driving signal. as well as The second drive circuit is configured to generate a second drive signal that dynamically adjusts the drive intensity of the second power transistor based on the intensity adjustment signal and the second internal drive signal. The intensity adjustment signal indicates that the second transition timing of the second internal drive signal is simultaneous with the first transition timing of the first internal drive signal.

2. The multi-output voltage converter as described in claim 1, wherein, The intensity adjustment signal generator is configured as follows: A first latch signal with a first duration is generated in response to the activation of a first internal drive signal; A second latch signal with a second duration is generated in response to activation of a second internal drive signal, wherein the second duration is equal to the first duration; and An intensity adjustment signal is generated at a first logic level for a third duration, wherein the third duration is defined by the overlap between the first duration of the first latch signal and the second duration of the second latch signal.

3. The multi-output voltage converter as described in claim 2, wherein, The third duration is dynamically changed based on the temporal proximity between the first transition timing of the first internal drive signal and the second transition timing of the second internal drive signal.

4. The multi-output voltage converter as described in claim 3, wherein, The intensity adjustment signal generator includes: The first trigger includes a first set terminal that receives a first internal drive signal, a first output terminal that outputs a first latch signal generated by latching the first internal drive signal, and a first reset terminal that receives a first delayed latch signal. A first timer is configured to generate a first delayed latch signal by delaying a first latch signal by a first time delay; The second trigger includes a second set terminal that receives a second internal drive signal, a second output terminal that outputs a second latch signal generated by latching the second internal drive signal, and a second reset terminal that receives a second delayed latch signal. The second timer is configured to generate a second delayed latch signal by delaying the second latch signal by a second time delay; and The NAND gate is configured to generate an intensity adjustment signal by performing a NAND operation on the first latch signal and the second latch signal.

5. The multi-output voltage converter as described in claim 4, wherein, The NAND gate is configured to generate an intensity-adjusted signal at a first logic level for a third duration, based on a first duration of a first latch signal and a second duration of a second latch signal.

6. The multi-output voltage converter as described in claim 4, wherein, The first time delay and the second time delay are set based on estimates of power supply noise generated when the first power transistor and the second power transistor are simultaneously turned on or simultaneously turned off.

7. The multi-output voltage converter as claimed in claim 1, wherein, The first driving circuit includes: The first inverter is configured to generate a first inverted internal drive signal by inverting a first internal drive signal; The logic circuit is configured to generate a first control signal and a second control signal based on a first inverting internal drive signal and an intensity adjustment signal; and The gate driver is configured to generate a first drive signal based on a first inverted internal drive signal, a first control signal, and a second control signal, and to adjust the drive strength of the first power transistor by controlling the slope of the first drive signal.

8. The multi-output voltage converter as claimed in claim 7, wherein, The gate driver includes a first driver and a second driver, wherein the first driver is configured to operate based on a first inverted internal drive signal, and the second driver is configured to operate based on the first inverted internal drive signal, a first control signal, and a second control signal.

9. The multi-output voltage converter as claimed in claim 8, wherein, The logic circuit includes: The second inverter is configured to invert the intensity adjustment signal; An OR gate is configured to generate a first control signal by performing an OR operation on the outputs of a first inverter internal drive signal and a second inverter; and The AND gate is configured to generate a second control signal by performing an AND operation on a first inverting internal drive signal and an intensity adjustment signal.

10. The multi-output voltage converter as claimed in claim 9, wherein, In response to an intensity adjustment signal having a first logic level, an OR gate is configured to output a first control signal at a second logic level, and an AND gate is configured to output a second control signal at the first logic level, thereby deactivating the second driver and reducing the drive intensity of the first power transistor. and In response to an intensity adjustment signal having a second logic level, an OR gate is configured to output a first control signal at the same logic level as the first inverted internal drive signal, and an AND gate is configured to output a second control signal at the same logic level as the first inverted internal drive signal, thereby activating the second driver and maintaining the drive intensity of the first power transistor.

11. The multi-output voltage converter as claimed in claim 8, wherein, The first driver includes: a first p-channel metal-oxide-semiconductor (PMOS) transistor connected between a power supply voltage and a first node, and having a gate for receiving a first inverted internal drive signal; and a first n-channel metal-oxide-semiconductor (NMOS) transistor connected between the first node and ground voltage, and having a gate for receiving the first inverted internal drive signal; and The second driver includes: a second PMOS transistor connected in parallel with the first PMOS transistor between a power supply voltage and a first node, and having a gate for receiving a first control signal; and a second NMOS transistor connected in parallel with the first NMOS transistor between the first node and a ground voltage, and having a gate for receiving a second control signal.

12. The multi-output voltage converter as claimed in claim 11, wherein, The gate driver is configured to reduce the drive strength of the first power transistor in response to a strength adjustment signal at a logic low level by activating the second PMOS transistor via a first control signal at a logic high level and by activating the second NMOS transistor via a second control signal at a logic low level.

13. The multi-output voltage converter as claimed in claim 11, wherein, The gate driver is configured to maintain the drive strength of the first power transistor in response to a strength adjustment signal at a logic high level by activating the second PMOS transistor and the second NMOS transistor via a first control signal and a second control signal having the same logic level as the first inverted internal drive signal.

14. The multi-output voltage converter as described in claim 1, in, The first conversion circuit further includes: a third power transistor connected between the first switching node and ground voltage, and configured to pull down the first switching node based on a third drive signal; The second conversion circuit further includes a fourth power transistor connected between the second switching node and ground voltage, and configured to pull down the second switching node based on a fourth drive signal.

15. The multi-output voltage converter as described in claim 14, in, The first driving circuit is configured to generate the third driving signal by buffering the third internal driving signal, and The second driving circuit is configured to generate the fourth driving signal by buffering the fourth internal driving signal.

16. The multi-output voltage converter according to any one of claims 1 to 15, further comprising: Control circuit, wherein the control circuit is configured as follows: A first internal drive signal is generated based on a first reference voltage and a first feedback voltage, wherein the first feedback voltage is proportional to the first output voltage; and A second internal drive signal is generated based on a second reference voltage and a second feedback voltage, wherein the second feedback voltage is proportional to the second output voltage.

17. The multi-output voltage converter according to any one of claims 1 to 15, wherein, Each of the first and second conversion circuits corresponds to one of the buck converter, boost converter, and buck-boost converter.

18. A multi-output voltage converter, comprising: A plurality of conversion circuits, each comprising an inductor and a power transistor, and configured to generate a corresponding output voltage at a corresponding output node by converting an input voltage based on a corresponding drive signal, wherein the power transistor of each of the plurality of conversion circuits is configured to pull up a corresponding switching node based on a corresponding drive signal, and the switching node of each of the plurality of conversion circuits is coupled to a first terminal of a corresponding inductor. An intensity adjustment signal generator is configured to generate multiple intensity adjustment signals based on the transition timing of multiple internal drive signals, including a first internal drive signal and a second internal drive signal. as well as Multiple driving circuits, including a first driving circuit and a second driving circuit, are configured to generate a first driving signal and a second driving signal based on a first internal driving signal and a second internal driving signal, wherein the first driving signal drives a first power transistor and the second driving signal drives a second power transistor. Wherein, when the first transition timing of the first internal drive signal and the second transition timing of the second internal drive signal are detected to be simultaneous, each of the first drive circuit associated with the first drive signal and the second drive circuit associated with the second drive signal is configured to: reduce the drive intensity of the corresponding power transistor in the first power transistor and the second power transistor based on the first internal drive signal, the second internal drive signal and a first intensity adjustment signal indicating that the first transition timing and the second transition timing are simultaneous.

19. The multi-output voltage converter as claimed in claim 18, wherein, The driving circuits among the plurality of driving circuits, excluding the first driving circuit and the second driving circuit, are configured to maintain the driving intensity of the corresponding power transistors based on a second intensity adjustment signal, the second intensity adjustment signal indicating that the transition timing of the internal driving signals other than the first driving signal and the second driving signal is not simultaneous.

20. A multi-output voltage converter, comprising: A first conversion circuit includes a first inductor and a first power transistor. The first conversion circuit is configured to generate a first output voltage at a first output node by converting an input voltage based on a first drive signal. The first power transistor is configured to pull up a first switching node based on the first drive signal. The first switching node is coupled to a first terminal of the first inductor. The second conversion circuit includes a second inductor and a second power transistor. The second conversion circuit is configured to generate a second output voltage at a second output node by converting the input voltage based on a second drive signal. The second power transistor is configured to pull up a second switching node based on the second drive signal. The second switching node is connected to a first terminal of the second inductor. A shift signal generator is configured to generate a shift signal based on a first transition timing of a first internal drive signal and a second transition timing of a second internal drive signal. The first driving circuit is configured to generate a first driving signal based on a first internal driving signal; as well as The second driving circuit is configured to generate a second driving signal by shifting the second transition timing of the second internal driving signal based on a shift signal indicating that the first transition timing and the second transition timing are simultaneous.

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