A control method and control circuit of a four-switch buck-boost converter

Abstract

The application discloses a control method and a corresponding control circuit of a four-switch buck-boost converter. The method establishes a mapping table between a voltage gain (M) and a Buck side duty ratio (D1) and a Boost side duty ratio (D2) offline and stores the mapping table as a preset lookup table; input voltage (Vin) and output voltage (Vo) are collected in real time, and a current actual voltage gain (M) is calculated; mode determination is performed through a preset lower hysteresis threshold (ML) and an upper hysteresis threshold (MH), if M<ML, the converter works in a Buck mode and D2=0 is fixed to obtain D1 through lookup table, if M>MH, the converter works in a Boost mode and D1=1 is fixed to obtain D2 through lookup table, if ML≤M≤MH, the converter works in a mixed mode and D1 and D2 are obtained through synchronous lookup table; linear interpolation correction is performed on non-discrete index points; and finally, four-way complementary PWM driving signals with a dead zone are generated.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter control technology, specifically to a control method and control circuit for a four-switch buck-boost converter. Background Technology

[0002] The four-switch Buck-Boost converter combines Buck buck and Boost voltage capabilities, enabling stable voltage output under wide input voltage fluctuations. It features small size, low loss, and high efficiency, and is widely used in photovoltaic energy storage systems, industrial wide-voltage power supplies, automotive power supplies, and other applications.

[0003] Currently, the mainstream control scheme for four-switch Buck-Boost converters generally adopts a real-time iterative calculation method for the duty cycle, that is, solving for the Buck-side and Boost-side duty cycles in real time using a volt-second balance equation combined with a closed-loop PI controller. This type of control scheme has the following shortcomings in practical applications: On the one hand, this scheme requires real-time calculation of voltage gain, closed-loop deviation iteration, and side duty cycle coupling solution, which places high demands on the computing power of the microcontroller or DSP. On low-end processors, it is prone to control lag, waveform distortion, and response delay, which limits its application in cost-sensitive products.

[0004] On the other hand, the gain characteristics of the converter vary significantly under different input voltages and load conditions. The parameters of traditional PI controllers are not very universal, and it is often necessary to tune multiple sets of PI parameters and switch them for various operating conditions, which leads to a complicated debugging process and a longer development cycle.

[0005] To address the shortcomings of the existing technologies, a control scheme for a four-switch buck-boost converter that requires low computing power, is easy to debug, and can achieve smooth mode switching needs to be proposed. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a control method and control circuit for a four-switch buck-boost converter.

[0007] To achieve the foregoing objective, the present invention provides a control method for a four-switch buck-boost (Buck-Boost) converter. The control method establishes a mapping table between the current actual voltage gain M, the Buck-side duty cycle D1 and the Boost-side duty cycle D2 based on the steady-state volt-second balance relationship Vo / Vin=D1 / (1-D2) of the four-switch buck-boost Buck-Boost converter, and stores the mapping table as a preset voltage gain lookup table. Wherein, Vo represents the output voltage of the four-switch buck-boost Buck-Boost converter, Vin represents the input voltage of the four-switch buck-boost Buck-Boost converter, and the current actual voltage gain M is M=Vo / Vin.

[0008] In the actual control process, the input voltage Vin and the output voltage Vo are collected in real time, and the current actual voltage gain M is calculated according to the input voltage Vin and the output voltage Vo; a lower hysteresis threshold ML and an upper hysteresis threshold MH are preset, and ML<1<MH; the operation mode of the converter is determined according to the relationship between the current actual voltage gain M, the lower hysteresis threshold ML and the upper hysteresis threshold MH, and the corresponding Buck-side duty cycle D1 and / or Boost-side duty cycle D2 are determined in the preset voltage gain lookup table according to the current actual voltage gain M.

[0009] Specifically, when M<ML, it is determined that the four-switch buck-boost Buck-Boost converter operates in Buck mode, the Boost-side duty cycle D2 is fixed to 0, and the Buck-side duty cycle D1 is determined in the preset voltage gain lookup table according to the current actual voltage gain M; when M>MH, it is determined that the four-switch buck-boost Buck-Boost converter operates in Boost mode, the Buck-side duty cycle D1 is fixed to 1, and the Boost-side duty cycle D2 is determined in the preset voltage gain lookup table according to the current actual voltage gain M; when ML≤M≤MH, it is determined that the four-switch buck-boost Buck-Boost converter operates in Buck-Boost hybrid mode, and the Buck-side duty cycle D1 and the Boost-side duty cycle D2 are determined in the preset voltage gain lookup table according to the current actual voltage gain M.

[0010] When the current actual voltage gain M falls between two adjacent discrete voltage gain points, linear interpolation is performed according to the two adjacent discrete voltage gain points and their corresponding Buck-side duty cycle D1 and / or Boost-side duty cycle D2 to obtain the Buck-side duty cycle D1 and / or Boost-side duty cycle D2 for output. Then, according to the determined operation mode, Buck-side duty cycle D1 and Boost-side duty cycle D2, four complementary pulse width modulation driving signals with dead time are generated to drive the four-switch buck-boost Buck-Boost converter to operate.

[0011] The present invention also provides a control circuit for implementing the above-described control method. This control circuit includes a voltage sampling circuit 300, an MCU control circuit 400, and a drive circuit 500. The voltage sampling circuit 300 includes an input voltage sampling circuit 310 and an output voltage sampling circuit 320. The input voltage sampling circuit 310 is used to acquire the input voltage Vin of the four-switch buck-boost converter and output the input voltage sampling signal V_IN; the output voltage sampling circuit 320 is used to acquire the output voltage Vo of the four-switch buck-boost converter and output the output voltage sampling signal V_OUT.

[0012] The MCU control circuit 400 is connected to the input voltage sampling circuit 310 and the output voltage sampling circuit 320, respectively. It calculates the current actual voltage gain M based on the input voltage sampling signal V_IN and the output voltage sampling signal V_OUT, and determines the Buck-side duty cycle D1 and / or the Boost-side duty cycle D2 in a preset voltage gain lookup table based on the current actual voltage gain M. The MCU control circuit 400 also determines the operating mode based on the relationship between the current actual voltage gain M and the hysteresis lower threshold ML and hysteresis upper threshold MH, and outputs PWM1, PWM1_1, PWM2, and PWM2_1. The drive circuit 500 is connected to the MCU control circuit 400 and drives the four-switch buck-boost main power circuit 600 to operate according to the aforementioned pulse width modulation signals.

[0013] In one specific embodiment, the MCU control circuit 400 includes a microcontroller chip U1. The microcontroller chip U1 has PA0, PA2, PA8, PA9, PA10, and PA11 pins. PA0 serves as an input voltage sampling terminal, connected to the input voltage sampling circuit 310, for receiving the input voltage sampling signal V_IN. PA2 serves as an output voltage sampling terminal, connected to the output voltage sampling circuit 320, for receiving the output voltage sampling signal V_OUT. PA8, PA9, PA10, and PA11 serve as multiple pulse width modulation (PWM) output terminals, connected to the drive circuit 500, for outputting PWM1, PWM1_1, PWM2, and PWM2_1 to the drive circuit 500, respectively.

[0014] In one specific embodiment, the input voltage sampling circuit 310 includes a first operational amplifier unit U2A, resistors R3, R4, R10, R12, R8, and a clamping diode group D1. One end of resistor R3 is connected to the negative input terminal IN-, and the other end is connected to the inverting input terminal of the first operational amplifier unit U2A; resistor R4 is connected between the output terminal and the inverting input terminal of the first operational amplifier unit U2A; one end of resistor R10 is connected to the positive input terminal IN+, and the other end is connected to the non-inverting input terminal of the first operational amplifier unit U2A; resistor R12 is connected between the non-inverting input terminal and the ground terminal of the first operational amplifier unit U2A; the output terminal of the first operational amplifier unit U2A outputs the input voltage sampling signal V_IN through resistor R8; the clamping diode group D1 is connected between the input voltage sampling signal V_IN, the power supply terminal VCC_3V3, and the ground terminal to limit the voltage range of the input voltage sampling signal V_IN.

[0015] In one specific embodiment, the output voltage sampling circuit 320 includes a second operational amplifier unit U2B, resistors R5, R6, R11, R13, R9, and a clamping diode group D2. One end of resistor R5 is connected to the output negative terminal OUT-, and the other end is connected to the inverting input terminal of the second operational amplifier unit U2B; resistor R6 is connected between the output terminal and the inverting input terminal of the second operational amplifier unit U2B; one end of resistor R11 is connected to the output positive terminal OUT+, and the other end is connected to the non-inverting input terminal of the second operational amplifier unit U2B; resistor R13 is connected between the non-inverting input terminal and the ground terminal of the second operational amplifier unit U2B; the output terminal of the second operational amplifier unit U2B outputs the output voltage sampling signal V_OUT through resistor R9; the clamping diode group D2 is connected between the output voltage sampling signal V_OUT, the power supply terminal VCC_3V3, and the ground terminal to limit the voltage range of the output voltage sampling signal V_OUT.

[0016] In one specific embodiment, the drive circuit 500 includes drive chip U4, drive chip U6, drive chip U3, and drive chip U5. The control signal input terminal of drive chip U4 is connected to the MCU control circuit 400 to receive PWM1, and the drive output terminal of drive chip U4 is connected to the control terminal of the first switch Q3 on the Buck side. The control signal input terminal of drive chip U6 is connected to the MCU control circuit 400 to receive PWM1_1, and the drive output terminal of drive chip U6 is connected to the control terminal of the second switch Q6 on the Buck side. The control signal input terminal of drive chip U3 is connected to the MCU control circuit 400 to receive PWM2_1, and the drive output terminal of drive chip U3 is connected to the control terminal of the first switch Q4 on the Boost side. The control signal input terminal of drive chip U5 is connected to the MCU control circuit 400 to receive PWM2, and the drive output terminal of drive chip U5 is connected to the control terminal of the second switch Q5 on the Boost side.

[0017] In one specific embodiment, the four-switch buck-boost main power circuit 600 includes a first switch Q3 on the buck side, a second switch Q6 on the buck side, a first switch Q4 on the boost side, a second switch Q5 on the boost side, a power inductor L2, an input filter capacitor C19, and an output filter capacitor C21. The first switch Q3 and the second switch Q6 on the buck side constitute the buck-side switching branch, and the first switch Q4 and the second switch Q5 on the boost side constitute the boost-side switching branch. The power inductor L2 is connected between the buck-side switching branch and the boost-side switching branch. The input filter capacitor C19 is connected between the positive input terminal VIN+ and the negative input terminal VIN-, and the output filter capacitor C21 is connected between the positive output terminal Vo+ and the negative output terminal Vo-.

[0018] Furthermore, the Buck-side switching branch has a first switching node VS1, and the Boost-side switching branch has a second switching node VS2. The Buck-side first switch Q3 is connected between the positive input terminal VIN+ and the first switching node VS1; the Buck-side second switch Q6 is connected between the first switching node VS1 and the negative input terminal VIN-; the Boost-side first switch Q4 is connected between the second switching node VS2 and the positive output terminal Vo+; the Boost-side second switch Q5 is connected between the second switching node VS2 and the negative output terminal Vo-; one end of the power inductor L2 is connected to the first switching node VS1, and the other end is connected to the second switching node VS2; the negative input terminal VIN- is connected to the negative output terminal Vo-.

[0019] The beneficial effect of this invention is that by establishing a preset voltage gain lookup table between the current actual voltage gain and the Buck-side duty cycle and the Boost-side duty cycle, the side duty cycle calculation that originally needed to be solved in real time during operation is transformed into a lookup table and interpolation process, which reduces the real-time calculation burden of the controller and is suitable for implementation in resource-constrained microcontrollers or digital signal processors.

[0020] This invention determines Buck mode, Boost mode, and Buck-Boost hybrid mode based on the relationship between the current actual voltage gain and the lower and upper hysteresis thresholds. When the current actual voltage gain is between adjacent discrete voltage gain points, linear interpolation is used to determine the side duty cycle, making the side duty cycle change more continuous. This helps to reduce frequent jumps during mode switching, reduce output waveform abrupt changes and control jitter, and improve control stability over a wide input and output voltage range.

[0021] This invention forms a complete control link by sampling input and output voltages, calculating gain, determining the duty cycle by looking up tables, and coordinating the four pulse width modulation drive outputs. It can achieve unified control between Buck mode, Boost mode, and Buck-Boost hybrid mode, which helps to simplify the system debugging process and improve the applicability and portability of the control strategy. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the overall flow of the control method of the present invention; Figure 2 This is a schematic diagram illustrating the process of establishing the preset voltage gain lookup table in this invention. Figure 3 This is a schematic diagram of the voltage sampling circuit in an embodiment of the present invention; Figure 4 This is a schematic diagram of the MCU control circuit in an embodiment of the present invention; Figure 5 This is a schematic diagram of the drive circuit and the four-switch buck-boost main power circuit in an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures 300. Voltage sampling circuit; 310. Input voltage sampling circuit; 320. Output voltage sampling circuit; 400. MCU control circuit; 500. Drive circuit; 600. Four-switch buck-boost main power circuit. Detailed Implementation

[0024] The following drawings disclose several embodiments of the present invention. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.

[0025] Furthermore, in this invention, the use of terms such as "first" and "second" is for descriptive purposes only and does not specifically refer to any order or sequence, nor is it intended to limit the invention. They are merely used to distinguish components or operations described using the same technical terms, and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If a combination of technical solutions is contradictory or impossible to implement, such a combination should be considered nonexistent and not within the scope of protection claimed by this invention.

[0026] Please refer to Figures 1 to 5 This embodiment provides a control method and control circuit for a four-switch buck-boost converter. Among them, Figure 1 The control method flow of this embodiment is shown. Figure 2 The process of creating a preset voltage gain lookup table is shown. Figure 3 The specific circuit structure of the voltage sampling circuit 300 is shown. Figure 4 The specific circuit structure of the MCU control circuit 400 is shown. Figure 5 The specific circuit structures of the drive circuit 500 and the four-switch buck-boost main power circuit 600 are shown. This solution is suitable for power conversion scenarios with a wide input voltage range where the input voltage may be lower than, close to or higher than the target output voltage, such as energy storage power supplies, photovoltaic input power supplies, industrial wide-voltage input power supplies, automotive auxiliary power supplies, and other power conversion scenarios requiring continuous buck-boost adjustment.

[0027] Existing four-switch Buck-Boost control schemes typically require real-time calculation of voltage gain, closed-loop deviation iteration, and dual-sided duty cycle coupling, placing high demands on the computing power of low-end MCUs or DSPs. Furthermore, under different input voltages and load conditions, control parameter tuning is complex, easily leading to problems such as control lag, mode switching jitter, or abrupt output waveform changes. This embodiment... Figure 1The control flow shown combines voltage gain-based mode determination, table lookup indexing, linear interpolation, and PWM drive output processes, and through... Figures 3 to 5 The hardware circuit shown implements input / output voltage sampling, MCU operation and control, drive signal amplification, and main power conversion.

[0028] In this embodiment, the control circuit includes a voltage sampling circuit 300, an MCU control circuit 400, and a drive circuit 500, and is used to connect to the four-switch buck-boost main power circuit 600. Figure 3 As shown, the voltage sampling circuit 300 includes an input voltage sampling circuit 310 and an output voltage sampling circuit 320, which are used to generate the input voltage sampling signal V_IN and the output voltage sampling signal V_OUT, respectively. Figure 4 As shown, the MCU control circuit 400 includes a microcontroller chip U1. The microcontroller chip U1 receives V_IN and V_OUT, and outputs PWM1, PWM1_1, PWM2, and PWM2_1. Figure 5 As shown, after receiving the above PWM signal, the drive circuit 500 drives the corresponding power switch in the four-switch buck-boost main power circuit 600.

[0029] like Figure 1 As shown, the control method in this embodiment includes establishing a preset voltage gain lookup table, acquiring input and output voltages in real time, calculating the current actual voltage gain, determining the mode based on the hysteresis threshold, determining the duty cycle on the corresponding side by looking up the table, performing linear interpolation between adjacent discrete voltage gain points, generating four complementary pulse width modulation drive signals with dead time, and driving the four-switch buck-boost converter to work.

[0030] Specifically, Figure 1Step S101 in corresponds to establishing a mapping table between the current actual voltage gain M, the Buck-side duty cycle D1 and the Boost-side duty cycle D2 based on the steady-state volt-second balance relationship, and storing the mapping table as a preset voltage gain lookup table; step S102 corresponds to collecting the input voltage Vin and the output voltage Vo in real time, and calculating the current actual voltage gain M=Vo / Vin; step S103 corresponds to presetting a hysteresis lower threshold ML and a hysteresis upper threshold MH, where ML<1<MH; step S104 corresponds to determining Buck mode, Boost mode or Buck-Boost hybrid mode according to the current actual voltage gain M, and determining the corresponding side duty cycle; step S105 corresponds to performing linear interpolation when the current actual voltage gain M is located between two adjacent discrete voltage gain points; step S106 corresponds to generating four complementary pulse width modulation drive signals with dead time according to the operating mode, the Buck-side duty cycle D1 and the Boost-side duty cycle D2; step S107 corresponds to driving the four-switch buck-boost converter to operate.

[0031] This embodiment establishes a control mapping relationship based on the steady-state volt-second balance relationship of the four-switch buck-boost Buck-Boost converter, and the core gain relationship is Vo / Vin=D1 / (1-D2), where Vin is the input voltage, Vo is the output voltage, D1 is the Buck-side duty cycle, D2 is the Boost-side duty cycle, and the current actual voltage gain M is M=Vo / Vin. Through this relationship, the corresponding relationship between the current actual voltage gain M, the Buck-side duty cycle D1 and the Boost-side duty cycle D2 can be established in advance, so that there is no need to re-perform complex coupled solving for double-sided duty cycles in each control cycle during the control process, and the corresponding side duty cycle is obtained through table lookup and necessary interpolation calculation.

[0032] As Figure 2 shown, the establishment process of the preset voltage gain lookup table includes steps S201 to S204. In step S201, the effective voltage gain interval of the four-switch buck-boost Buck-Boost converter is determined. The effective voltage gain interval can be determined according to the allowable input voltage range, the target output voltage range, the allowable side duty cycle range of the switching tubes and the system design margin of the converter. For example, when the input voltage has a wide fluctuation range, the minimum and maximum values of the voltage gain can be determined according to the minimum input voltage, the maximum input voltage and the target output voltage, so as to obtain the effective voltage gain interval.

[0033] In step S202, the effective voltage gain range is uniformly discretely sampled to obtain multiple discrete voltage gain points. The number of discrete points can be determined comprehensively based on control accuracy, storage capacity, and MCU computing power. A larger number of discrete points results in higher lookup accuracy but increased storage usage; a smaller number of discrete points results in lower storage usage but requires interpolation to improve the continuity of the duty cycle output. Preferably, an equal-interval discrete method can be used, enabling the MCU control circuit 400 to quickly determine the current actual voltage gain M range through simple indexing operations.

[0034] In step S203, based on each discrete voltage gain point and the steady-state volt-second balance relationship Vo / Vin=D1 / (1-D2), the Buck-side duty cycle D1 and Boost-side duty cycle D2 corresponding to each discrete voltage gain point are determined. When determining D1 and D2, the operating mode division rules can be considered. For example, for the Buck mode interval, the Boost-side duty cycle D2 can be fixed at 0, and the corresponding Buck-side duty cycle D1 can be determined; for the Boost mode interval, the Buck-side duty cycle D1 can be fixed at 1, and the corresponding Boost-side duty cycle D2 can be determined; for the Buck-Boost hybrid mode interval, D1 and D2 can be determined simultaneously, enabling the Buck-side switching branch and the Boost-side switching branch to work collaboratively.

[0035] In step S204, each discrete voltage gain point and its corresponding Buck-side duty cycle D1 and Boost-side duty cycle D2 are stored as a preset voltage gain lookup table. This preset voltage gain lookup table can be pre-generated during the product design phase, factory configuration phase, or controller initialization phase, and stored in the on-chip Flash, EEPROM, on-chip RAM, or external non-volatile memory of the microcontroller chip U1. The data in the lookup table can be stored in floating-point form or fixed-point form. For resource-constrained low-cost MCUs, fixed-point form is preferred to reduce the real-time computational burden caused by floating-point operations.

[0036] During actual operation, microcontroller chip U1 reads the input voltage sampling signal V_IN and the output voltage sampling signal V_OUT according to a preset sampling period. After analog-to-digital conversion, the corresponding digital sample values ​​are obtained, and the input voltage Vin and output voltage Vo are calculated according to the sampling ratio coefficient. Subsequently, microcontroller chip U1 calculates the current actual voltage gain M = Vo / Vin. To avoid abnormal operation when the input voltage Vin is too low, it can check whether Vin is greater than a preset effective input threshold before calculating the current actual voltage gain M. When Vin is lower than the preset effective input threshold, microcontroller chip U1 can stop PWM output or keep the system in a safe state.

[0037] After the microcontroller chip U1 calculates the current actual voltage gain M, it compares M with the lower hysteresis threshold ML and the upper hysteresis threshold MH. ML is less than 1 and MH is greater than 1. In a specific embodiment, ML can be 0.90 to 0.95, and MH can be 1.05 to 1.10. The purpose of setting the hysteresis interval is to prevent the controller from frequently switching between Buck mode and Boost mode when the input voltage is close to the output voltage, thereby improving the output stability in the critical region.

[0038] When M<ML, the microcontroller chip U1 determines that the four-switch buck-boost Buck-Boost converter operates in Buck mode. In this mode, the duty cycle D2 on the Boost side is fixed at 0, and the duty cycle D1 on the Buck side is determined in a preset voltage gain look-up table according to the current actual voltage gain M. At this time, the control focus is to adjust the energy input of the power inductor L2 through the switching branch on the Buck side, so that the output voltage is maintained within the target range.

[0039] When M>MH, the microcontroller chip U1 determines that the four-switch buck-boost Buck-Boost converter operates in Boost mode. In this mode, the duty cycle D1 on the Buck side is fixed at 1, and the duty cycle D2 on the Boost side is determined in a preset voltage gain look-up table according to the current actual voltage gain M. At this time, the control focus is to adjust the energy storage and release process of the power inductor L2 through the switching branch on the Boost side, so that the output voltage can be higher than the input voltage and remain stable.

[0040] When ML≤M≤MH, the microcontroller chip U1 determines that the four-switch buck-boost Buck-Boost converter operates in Buck-Boost hybrid mode. In this mode, the microcontroller chip U1 synchronously determines the Buck-side duty cycle D1 and the Boost-side duty cycle D2 in a preset voltage gain look-up table according to the current actual voltage gain M, so that the Buck-side switching branch and the Boost-side switching branch perform cooperative modulation. Through this hybrid mode, a smoother mode transition can be achieved in the region where the input voltage is close to the output voltage, and abrupt switching between the pure Buck mode and the pure Boost mode can be avoided.

[0041] When the current actual voltage gain M is exactly equal to a discrete voltage gain point in the lookup table, the microcontroller chip U1 can directly read D1 and D2 corresponding to that discrete voltage gain point. When the current actual voltage gain M falls between two adjacent discrete voltage gain points, the microcontroller chip U1 performs linear interpolation. Taking linear interpolation as an example, let two adjacent discrete voltage gain points be Mi and Mi+1, their corresponding Buck-side duty cycles be D1i and D1i+1, and their corresponding Boost-side duty cycles be D2i and D2i+1. Then, the interpolated D1 and D2 can be calculated based on the position ratio of M between Mi and Mi+1. Through linear interpolation, the continuity of duty cycle changes can be improved when the number of discrete points in the lookup table is limited, and the duty cycle jumps caused by discrete indexes can be reduced.

[0042] In other implementations, the lookup indexing method can be selected based on microcontroller resources and control accuracy requirements. For example, when the discrete points of voltage gain are evenly distributed, the index position can be directly calculated using the difference between M and the minimum voltage gain. When the discrete points of voltage gain are non-uniformly distributed, sequential lookup, binary lookup, or piecewise indexing can be used to determine adjacent gain points. The interpolation method is not limited to linear interpolation; piecewise linear interpolation, quadratic interpolation, spline interpolation, or a lookup table followed by closed-loop fine-tuning can also be used. For low-cost microcontrollers, an evenly spaced lookup table combined with linear interpolation is preferred to reduce multiplication, division, and complex function calculations.

[0043] like Figure 3 As shown, the voltage sampling circuit 300 includes an input voltage sampling circuit 310 located on the left side of the figure and an output voltage sampling circuit 320 located on the right side of the figure. The input voltage sampling circuit 310 is used to sample, proportionally condition, and clamp the voltage between the input terminals IN+ and IN-, and output the input voltage sampling signal V_IN; the output voltage sampling circuit 320 is used to sample, proportionally condition, and clamp the voltage between the output terminals OUT+ and OUT-, and output the output voltage sampling signal V_OUT.

[0044] The input voltage sampling circuit 310 includes a first operational amplifier unit U2A, resistors R3, R4, R10, R12, R8, and a clamping diode group D1. One end of resistor R3 is connected to the negative input terminal IN-, and the other end is connected to the inverting input terminal of the first operational amplifier unit U2A; resistor R4 is connected between the output terminal and the inverting input terminal of the first operational amplifier unit U2A; one end of resistor R10 is connected to the positive input terminal IN+, and the other end is connected to the non-inverting input terminal of the first operational amplifier unit U2A; resistor R12 is connected between the non-inverting input terminal and the ground terminal of the first operational amplifier unit U2A. The output terminal of the first operational amplifier unit U2A outputs the input voltage sampling signal V_IN through resistor R8. The clamping diode group D1 is connected between the input voltage sampling signal V_IN, the power supply terminal VCC_3V3, and the ground terminal to limit the voltage range of V_IN, ensuring that the sampling voltage input to the microcontroller chip U1 is within a safe range.

[0045] See also Figure 3 The output voltage sampling circuit 320 and the input voltage sampling circuit 310 adopt corresponding circuit structures to convert the output voltage into a low-voltage analog signal suitable for sampling by the MCU control circuit 400. The output voltage sampling circuit 320 includes a second operational amplifier unit U2B, resistors R5, R6, R11, R13, R9, and a clamping diode group D2. One end of resistor R5 is connected to the output negative terminal OUT-, and the other end is connected to the inverting input terminal of the second operational amplifier unit U2B; resistor R6 is connected between the output terminal and the inverting input terminal of the second operational amplifier unit U2B; one end of resistor R11 is connected to the output positive terminal OUT+, and the other end is connected to the non-inverting input terminal of the second operational amplifier unit U2B; resistor R13 is connected between the non-inverting input terminal and the ground terminal of the second operational amplifier unit U2B. The output of the second operational amplifier unit U2B outputs an output voltage sampling signal V_OUT through resistor R9. Clamping diode group D2 is connected between V_OUT, power supply terminal VCC_3V3 and ground terminal to limit the amplitude of the output voltage sampling signal and prevent the analog-to-digital converter port of the subsequent stage from being subjected to overvoltage impact.

[0046] In this embodiment, resistors R3, R4, R10, and R12 are matched to form the input-side voltage signal conditioning relationship, while resistors R5, R6, R11, and R13 are matched to form the output-side voltage signal conditioning relationship. By employing an operational amplifier and precision resistor matching, the linearity and consistency of input and output voltage sampling can be improved, and gain calculation deviations caused by resistor errors can be reduced. In practical applications, the precision resistors can be selected with accuracies of 0.1%, 0.5%, 1%, or other appropriate levels; the operational amplifier can be selected based on input common-mode range, output swing, bandwidth, offset voltage, supply voltage, and noise immunity.

[0047] In other alternative implementations, the input voltage sampling circuit 310 and the output voltage sampling circuit 320 are not limited to the operational amplifier conditioning structure described above. For low-voltage, common-ground scenarios with low anti-interference requirements, a structure where the voltage is directly input to the microcontroller's analog-to-digital converter port after resistor voltage division can be used. For scenarios with high input and output voltages, large common-mode voltage variations, or strong switching noise, differential amplifiers, instrumentation amplifiers, isolation amplifiers, Hall voltage sensors, optocoupler isolation sampling circuits, or dedicated voltage sampling chips can be used. The clamping diode group D1 and D2 can also be replaced by Schottky diodes, Zener diodes, transient suppression diodes, ESD protection devices, or RC filter protection networks. Resistors R8 and R9 can be used as output current limiting or isolation resistors, and in other implementations, they can also be combined with capacitors to form a low-pass filter structure to suppress the influence of switching noise on the sampling signal.

[0048] like Figure 4 As shown, the MCU control circuit 400 includes a microcontroller chip U1 and power supply, reset, decoupling, and peripheral connection lines connected to the microcontroller chip U1. The PA0 pin of the microcontroller chip U1 serves as the input voltage sampling terminal, connected to the input voltage sampling signal V_IN; the PA2 pin serves as the output voltage sampling terminal, connected to the output voltage sampling signal V_OUT; and the PA8, PA9, PA10, and PA11 pins serve as multiple pulse width modulation output terminals, outputting PWM1, PWM1_1, PWM2, and PWM2_1 respectively. Therefore, Figure 4 The MCU control circuit 400 shown can be implemented in hardware. Figure 3 The voltage sampling circuit 300 outputs a sampling signal and sends it to... Figure 5 The drive circuit 500 shown outputs a control signal.

[0049] The microcontroller chip U1 is internally or externally configured with an analog-to-digital converter (ADC), a memory unit, an arithmetic processing unit, and a PWM output unit to perform sampled value conversion, gain calculation, lookup table indexing, interpolation, and PWM updates. After the system powers on, the microcontroller chip U1 first executes an initialization program. Initialization may include clock configuration, ADC channel configuration, PWM timer configuration, dead time configuration, I / O port configuration, lookup table loading, sampling ratio coefficient loading, protection threshold loading, and initial duty cycle setting. Subsequently, the microcontroller chip U1 enters a periodic control loop.

[0050] Within each control cycle, the microcontroller chip U1 reads the analog-to-digital conversion values ​​corresponding to V_IN and V_OUT, and calculates the input voltage Vin and output voltage Vo based on the proportional gain of the sampling circuit. To improve the stability of the sampled data, mean filtering, median filtering, sliding window filtering, first-order low-pass filtering, or outlier removal can be applied to the sampled values. For scenarios with high switching frequencies, the sampling time can be set at a fixed phase position within the PWM cycle to avoid periods with high switching transient noise.

[0051] The microcontroller chip U1 generates four complementary PWM drive signals with dead time based on the determined operating mode, Buck-side duty cycle D1, and Boost-side duty cycle D2. By setting the dead time, simultaneous conduction of the upper and lower switches in the same switching branch can be avoided, thereby reducing the risk of shoot-through. The dead time can be set according to the turn-on delay, turn-off delay, gate resistance, drive capability, switching frequency, and power level of the switches, or it can be automatically generated by the advanced timer module inside the microcontroller chip U1.

[0052] The microcontroller chip U1 in this embodiment can be a single-chip microcontroller, a digital signal processor, a system-on-a-chip (SoC), a field-programmable gate array (FPGA), a programmable logic device (PLA), or a dedicated digital power control chip. As long as it has sampling input capability, data processing capability, memory lookup table capability, and PWM output capability, the control method of this invention can be implemented. For low-cost applications, a general-purpose MCU with on-chip AD and on-chip PWM timer can be used; for high-frequency, high-power-density, or multi-phase parallel applications, a DSP or FPGA can be used to improve control parallelism and response speed.

[0053] like Figure 5As shown, the drive circuit 500 includes a drive chip U4 for receiving PWM1, a drive chip U6 for receiving PWM1_1, a drive chip U3 for receiving PWM2_1, and a drive chip U5 for receiving PWM2. Drive chips U4 and U6 are located near the Buck-side switching branch and are used to drive the Buck-side first switch Q3 and the Buck-side second switch Q6, respectively. Drive chips U3 and U5 are located near the Boost-side switching branch and are used to drive the Boost-side first switch Q4 and the Boost-side second switch Q5, respectively.

[0054] Specifically, the control signal input terminal of driver chip U4 is connected to MCU control circuit 400 to receive PWM1, and the drive output terminal of driver chip U4 is connected to the control terminal of the first switch Q3 on the Buck side; the control signal input terminal of driver chip U6 is connected to MCU control circuit 400 to receive PWM1_1, and the drive output terminal of driver chip U6 is connected to the control terminal of the second switch Q6 on the Buck side; the control signal input terminal of driver chip U3 is connected to MCU control circuit 400 to receive PWM2_1, and the drive output terminal of driver chip U3 is connected to the control terminal of the first switch Q4 on the Boost side; the control signal input terminal of driver chip U5 is connected to MCU control circuit 400 to receive PWM2, and the drive output terminal of driver chip U5 is connected to the control terminal of the second switch Q5 on the Boost side.

[0055] In other alternative implementations, driver chips U4, U6, U3, and U5 can be replaced with a half-bridge driver chip, an isolated gate driver chip, an optocoupler isolated driver, a magnetically isolated driver, a pulse transformer driver circuit, or a push-pull driver circuit composed of discrete transistors and MOSFETs. For low-voltage, low-power applications, a non-isolated gate driver scheme can be used; for high-voltage, high-power, or strong electromagnetic interference environments, an isolated driver scheme can be used, coupled with an isolated power supply, gate resistor, pull-down resistor, Miller clamp circuit, overcurrent detection circuit, or undervoltage lockout circuit. The above substitutions can achieve the control objective of this invention as long as they can drive the corresponding switching transistors to turn on or off according to PWM1, PWM1_1, PWM2, and PWM2_1.

[0056] See also Figure 5The four-switch buck-boost main power circuit 600 includes an input terminal, an output terminal, a buck-side switch branch, a boost-side switch branch, a power inductor L2, an input filter capacitor C19, and an output filter capacitor C21. The input filter capacitor C19 is connected between the positive input terminal VIN+ and the negative input terminal VIN-, used to filter the input voltage and reduce the impact of input ripple on the power conversion process and sampling results. The output filter capacitor C21 is connected between the positive output terminal Vo+ and the negative output terminal Vo-, used to reduce output voltage ripple and improve output voltage stability.

[0057] The first switch Q3 on the Buck side and the second switch Q6 on the Buck side constitute the Buck-side switching branch, while the first switch Q4 and the second switch Q5 on the Boost side constitute the Boost-side switching branch. The Buck-side switching branch has a first switching node VS1, and the Boost-side switching branch has a second switching node VS2. The first switch Q3 on the Buck side is connected between the positive input terminal VIN+ and the first switching node VS1, and the second switch Q6 on the Buck side is connected between the first switching node VS1 and the negative input terminal VIN-. The first switch Q4 on the Boost side is connected between the second switching node VS2 and the positive output terminal Vo+, and the second switch Q5 on the Boost side is connected between the second switching node VS2 and the negative output terminal Vo-. One end of the power inductor L2 is connected to the first switching node VS1, and the other end is connected to the second switching node VS2. The negative input terminal VIN- is connected to the negative output terminal Vo-. With the above connection method, the power inductor L2 is located between the Buck-side switching branch and the Boost-side switching branch, enabling the main power circuit to achieve buck, boost, and buck-boost transition control according to the conduction state of the Buck-side and Boost-side switching transistors.

[0058] In an alternative implementation, the Buck-side first switch Q3, Buck-side second switch Q6, Boost-side first switch Q4, and Boost-side second switch Q5 can be N-channel MOSFETs, or they can be replaced with P-channel MOSFETs, IGBTs, gallium nitride power devices, silicon carbide power devices, or other controllable power semiconductor devices, depending on voltage rating, current, on-resistance, switching speed, heat dissipation conditions, and cost requirements. When applied to low-voltage, high-current scenarios, low-on-resistance MOSFETs can be preferred to reduce conduction losses; when applied to high-voltage or high-frequency scenarios, silicon carbide or gallium nitride devices can be used to reduce switching losses. The power inductor L2 can be a shielded power inductor, a magnetic ring inductor, a ferrite core inductor, an iron-silicon-aluminum core inductor, or other energy storage inductors; the input filter capacitor C19 and the output filter capacitor C21 can be composed of a single capacitor, or they can be composed of electrolytic capacitors, solid-state capacitors, ceramic capacitors, or film capacitors connected in parallel to balance large-capacity energy storage, high-frequency filtering, low equivalent series resistance, and ripple current handling capability.

[0059] In a more specific operational process, after the system is powered on, such as Figure 5 As shown, the input filter capacitor C19 filters the voltage between the input terminals VIN+ and VIN-, and the output filter capacitor C21 filters the voltage between the output terminals Vo+ and Vo-; Figure 3 As shown, the input voltage sampling circuit 310 acquires the input voltage information through IN+ and IN- and outputs V_IN, while the output voltage sampling circuit 320 acquires the output voltage information through OUT+ and OUT- and outputs V_OUT; Figure 4 As shown, the microcontroller chip U1 reads V_IN and V_OUT and converts them to obtain Vin and Vo; then according to... Figure 1 The process shown involves the microcontroller chip U1 calculating M = Vo / Vin, and determining the current operating mode based on the relationship between M, ML, and MH; then, according to... Figure 2 The preset voltage gain lookup table indices D1 and D2 are established as shown; interpolation is performed when M is located between adjacent gain points; finally, as shown... Figure 5 As shown, the microcontroller chip U1 updates PWM1, PWM1_1, PWM2 and PWM2_1, and drives Q3, Q6, Q4 and Q5 respectively through driver chips U4, U6, U3 and U5, thereby enabling the main power circuit to output the corresponding voltage.

[0060] To improve the system's engineering adaptability, the microcontroller chip U1 can also be configured with a startup control process. During startup, all PWM outputs can be disabled initially, waiting for the input voltage sampling signal V_IN to stabilize. Then, the output voltage sampling signal V_OUT is detected to determine if there is residual voltage at the output terminal. Next, the duty cycle on the corresponding side is gradually increased according to a preset soft-start curve, allowing the output voltage to rise smoothly. The soft-start curve can employ a linear ramp, a segmented ramp, or an exponential ramp. Soft-start reduces input inrush current and output overshoot, preventing excessive stress on the power switches, inductors, and capacitors during startup.

[0061] The microcontroller chip U1 can also execute protection logic during operation. For example, when Vin is below the undervoltage threshold, the drive output is disabled or the system enters standby mode; when Vin is above the overvoltage threshold, the PWM output is turned off and a fault is reported; when Vo exceeds the output overvoltage threshold, the duty cycle is reduced or the drive output is turned off; when Vo is below the preset range and the load changes abruptly, the control update frequency can be increased based on the lookup table or a small closed-loop compensation can be added; when an abnormal sampling of V_IN or V_OUT is detected, the drive circuit 500 can enter a safe shutdown state. The above protection logic is an engineering extension of the control strategy of this invention and does not change the core control method of determining D1 and D2 by using the current actual voltage gain M as an index and a preset voltage gain lookup table.

[0062] In an alternative implementation, a closed-loop fine-tuning amount can be superimposed on the lookup table result. For example, microcontroller chip U1 can calculate a small duty cycle correction amount based on the deviation between the target output voltage and the actual output voltage, and then superimpose this correction amount onto D1 or D2 obtained from the lookup table. This correction amount can be obtained by proportional control, proportional-integral control, or other simple closed-loop algorithms. Since the main duty cycle is still given by the lookup table, the closed-loop fine-tuning only performs a small-range correction function. It does not require real-time calculation of the dual-side duty cycle coupling relationship as in traditional solutions, nor does it require repeated tuning of multiple sets of complex parameters for different input voltages and load conditions.

[0063] The preset voltage gain lookup table can also be configured into multiple tables based on different load ranges, input voltage ranges, or temperature ranges. For example, under light, medium, and heavy load conditions, the effects of device on-state voltage drop, inductor current ripple, dead time, and switching losses on the actual voltage gain differ, and corresponding correction tables can be established for each. During operation, the microcontroller chip U1 can select the corresponding lookup table based on load current, output power, or temperature information. Even without setting multiple lookup tables, control accuracy can be improved by using a single lookup table with correction coefficients. The above extensions are all adaptive optimizations based on the core idea of ​​this invention: "determining the duty cycle by looking up the voltage gain table."

[0064] The input / output voltage sampling method, lookup table accuracy, hysteresis threshold, and PWM frequency in this embodiment can be configured according to specific products. For example, the sampling frequency can be set to an integer multiple or a division multiple of the PWM frequency; the control cycle can be synchronized with the PWM cycle, or a multi-cycle update of the duty cycle can be used; ML and MH can be adjusted according to the system's allowable mode switching range, output ripple requirements, and load dynamic characteristics; the PWM frequency can be selected based on inductor size, switching losses, electromagnetic interference requirements, and efficiency targets. These parameter adjustments do not change the technical essence of the present invention.

[0065] In summary, this embodiment acquires the input and output voltages through the voltage sampling circuit 300, calculates the current actual voltage gain M through the MCU control circuit 400, determines the Buck-side duty cycle D1 and the Boost-side duty cycle D2 through a preset voltage gain lookup table, and drives the four-switch buck-boost main power circuit 600 through the drive circuit 500. This scheme transforms the complex real-time duty cycle calculation into a sampling, indexing, interpolation, and PWM update process, enabling a smooth transition between Buck mode, Boost mode, and Buck-Boost hybrid mode, reducing the controller's computing power requirements, simplifying the parameter debugging process, and improving control stability over a wide input and output voltage range.

[0066] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A control method for a four-switch buck-boost converter, characterized in that, comprising the following steps: establishing a mapping table between the current actual voltage gain (M), the Buck-side duty cycle (D1) and the Boost-side duty cycle (D2) based on the steady-state volt-second balance relationship of the four-switch buck-boost converter: Vo / Vin=D1 / (1-D2), and storing the mapping table as a preset voltage gain lookup table; wherein the preset voltage gain lookup table comprises a plurality of discrete voltage gain points, and the Buck-side duty cycle (D1) and the Boost-side duty cycle (D2) corresponding to each of the discrete voltage gain points, Vo represents the output voltage of the four-switch buck-boost converter, Vin represents the input voltage of the four-switch buck-boost converter, and the voltage gain (M) satisfies M=Vo / Vin; collecting the input voltage (Vin) and the output voltage (Vin) in real time, and calculating the current actual voltage gain (M) according to the input voltage (Vin) and the output voltage (Vo); presetting a hysteresis lower threshold (ML) and a hysteresis upper threshold (MH), and setting ML<1<MH; if M<ML, determining that the four-switch buck-boost converter operates in Buck mode, fixing the Boost-side duty cycle (D2) to 0, and determining the Buck-side duty cycle (D1) in the preset voltage gain lookup table according to the current actual voltage gain (M); if M>MH, determining that the four-switch buck-boost converter operates in Boost mode, fixing the Buck-side duty cycle (D1) to 1, and determining the Boost-side duty cycle (D2) in the preset voltage gain lookup table according to the current actual voltage gain (M); if ML≤M≤MH, determining that the four-switch buck-boost converter operates in Buck-Boost hybrid mode, and determining the Buck-side duty cycle (D1) and the Boost-side duty cycle (D2) in the preset voltage gain lookup table according to the current actual voltage gain (M); when the current actual voltage gain (M) falls between two adjacent discrete voltage gain points, performing linear interpolation according to the two adjacent discrete voltage gain points and the corresponding Buck-side duty cycle (D1) and / or Boost-side duty cycle (D2) to obtain the Buck-side duty cycle (D1) and / or Boost-side duty cycle (D2) for output; generating four paths of complementary pulse width modulation driving signals with dead time according to the operation mode, the Buck-side duty cycle (D1) and the Boost-side duty cycle (D2), so as to drive the four-switch buck-boost converter to operate.

2. The control method for a four-switch buck-boost converter according to claim 1, characterized in that: the preset voltage gain lookup table is established by the following steps: determining an effective voltage gain interval of the four-switch buck-boost converter; The effective voltage gain range is uniformly discretely sampled to obtain multiple discrete voltage gain points; Based on each discrete voltage gain point and the steady-state volt-second balance relationship, determine the Buck-side duty cycle (D1) and Boost-side duty cycle (D2) corresponding to each discrete voltage gain point. Each discrete voltage gain point and its corresponding Buck-side duty cycle (D1) and Boost-side duty cycle (D2) are stored in the preset voltage gain lookup table.

3. The control method for the four-switch buck-boost converter according to claim 1, characterized in that: The hysteresis lower threshold (ML) ranges from 0.90 to 0.95; The hysteresis threshold (MH) ranges from 1.05 to 1.

10.

4. A control circuit for implementing the control method according to any one of claims 1 to 3, characterized in that: It includes a voltage sampling circuit (300), an MCU control circuit (400), and a drive circuit (500); The voltage sampling circuit (300) includes an input voltage sampling circuit (310) and an output voltage sampling circuit (320). The input voltage sampling circuit (310) is used to acquire the input voltage (Vin) of the four-switch buck-boost converter and output the input voltage sampling signal (V_IN). The output voltage sampling circuit (320) is used to acquire the output voltage (Vo) of the four-switch buck-boost converter and output the output voltage sampling signal (V_OUT). The MCU control circuit (400) is connected to the input voltage sampling circuit (310) and the output voltage sampling circuit (320) respectively. It is used to calculate the current actual voltage gain (M) based on the input voltage sampling signal (V_IN) and the output voltage sampling signal (V_OUT), determine the Buck side duty cycle (D1) and / or Boost side duty cycle (D2) in a preset voltage gain lookup table based on the current actual voltage gain (M), and determine the working mode based on the relationship between the current actual voltage gain (M) and the hysteresis lower threshold (ML) and hysteresis upper threshold (MH). The driving circuit (500) is connected to the MCU control circuit (400) and is used to drive the four-switch buck-boost main power circuit (600) to work according to the four complementary pulse width modulation driving signals with dead time output by the MCU control circuit (400).

5. The control circuit according to claim 4, characterized in that: The MCU control circuit (400) includes a microcontroller chip (U1). The microcontroller chip (U1) is provided with an input voltage sampling terminal (PA0), an output voltage sampling terminal (PA2), a first pulse width modulation output terminal (PA8), a second pulse width modulation output terminal (PA9), a third pulse width modulation output terminal (PA10), and a fourth pulse width modulation output terminal (PA11). The input voltage sampling terminal (PA0) is connected to the input voltage sampling circuit (310) and is used to receive the input voltage sampling signal (V_IN). The output voltage sampling terminal (PA2) is connected to the output voltage sampling circuit (320) and is used to receive the output voltage sampling signal (V_OUT). The microcontroller chip (U1) is used to perform analog-to-digital conversion on the input voltage sampling signal (V_IN) and the output voltage sampling signal (V_OUT), and to calculate the current actual voltage gain (M) based on the converted digital sampling value. The first pulse width modulation output terminal (PA8), the second pulse width modulation output terminal (PA9), the third pulse width modulation output terminal (PA10) and the fourth pulse width modulation output terminal (PA11) are respectively connected to the driving circuit (500) and are used to output the first pulse width modulation signal (PWM1), the second pulse width modulation signal (PWM1_1), the third pulse width modulation signal (PWM2) and the fourth pulse width modulation signal (PWM2_1) to the driving circuit (500) respectively.

6. The control circuit according to claim 4, characterized in that: The input voltage sampling circuit (310) includes a first operational amplifier unit (U2A), resistors (R3), (R4), (R10), (R12), (R8), and a clamping diode group (D1). One end of the resistor (R3) is connected to the negative input terminal (IN-) of the four-switch buck-boost converter, and the other end is connected to the inverting input terminal of the first operational amplifier unit (U2A); The resistor (R4) is connected between the output terminal and the inverting input terminal of the first operational amplifier unit (U2A); One end of the resistor (R10) is connected to the positive input terminal (IN+) of the four-switch buck-boost converter, and the other end is connected to the non-inverting input terminal of the first operational amplifier unit (U2A). The resistor (R12) is connected between the non-inverting input terminal and the ground terminal of the first operational amplifier unit (U2A); The first operational amplifier unit (U2A) outputs the input voltage sampling signal (V_IN) through the resistor (R8); The clamping diode group (D1) is connected between the input voltage sampling signal (V_IN), the power supply terminal (VCC_3V3), and the ground terminal to limit the voltage range of the input voltage sampling signal (V_IN).

7. The control circuit according to claim 4, characterized in that: The output voltage sampling circuit (320) includes a second operational amplifier unit (U2B), resistors (R5), (R6), (R11), (R13), (R9), and a clamping diode group (D2). One end of the resistor (R5) is connected to the negative output terminal (OUT-) of the four-switch buck-boost converter, and the other end is connected to the inverting input terminal of the second operational amplifier unit (U2B); The resistor (R6) is connected between the output terminal and the inverting input terminal of the second operational amplifier unit (U2B); One end of the resistor (R11) is connected to the positive output terminal (OUT+) of the four-switch buck-boost converter, and the other end is connected to the non-inverting input terminal of the second operational amplifier unit (U2B). The resistor (R13) is connected between the non-inverting input terminal of the second operational amplifier unit (U2B) and the ground terminal; The output of the second operational amplifier unit (U2B) outputs the output voltage sampling signal (V_OUT) through the resistor (R9); The clamping diode group (D2) is connected between the output voltage sampling signal (V_OUT), the power supply terminal (VCC_3V3), and the ground terminal to limit the voltage range of the output voltage sampling signal (V_OUT).

8. The control circuit according to claim 4, characterized in that: The driving circuit (500) includes a driving chip (U4), a driving chip (U6), a driving chip (U3), and a driving chip (U5). The control signal input terminal of the driver chip (U4) is connected to the MCU control circuit (400) to receive the first pulse width modulation signal (PWM1), and the drive output terminal of the driver chip (U4) is connected to the control terminal of the first switch (Q3) on the Buck side. The control signal input terminal of the driver chip (U6) is connected to the MCU control circuit (400) to receive the second pulse width modulation signal (PWM1_1), and the drive output terminal of the driver chip (U6) is connected to the control terminal of the second switch (Q6) on the Buck side. The control signal input terminal of the driver chip (U3) is connected to the MCU control circuit (400) to receive the fourth pulse width modulation signal (PWM2_1), and the drive output terminal of the driver chip (U3) is connected to the control terminal of the first switch (Q4) on the Boost side. The control signal input terminal of the driver chip (U5) is connected to the MCU control circuit (400) to receive the third pulse width modulation signal (PWM2), and the drive output terminal of the driver chip (U5) is connected to the control terminal of the second switch (Q5) on the Boost side.

9. The control circuit according to claim 4, characterized in that: The control circuit is used to connect to the four-switch buck-boost main power circuit (600). The four-switch buck-boost main power circuit (600) includes a first switch (Q3) on the buck side, a second switch (Q6) on the buck side, a first switch (Q4) on the boost side, a second switch (Q5) on the boost side, a power inductor (L2), an input filter capacitor (C19), and an output filter capacitor (C21). The first switch (Q3) on the Buck side and the second switch (Q6) on the Buck side constitute the Buck side switch branch; The first switch (Q4) on the Boost side and the second switch (Q5) on the Boost side constitute the Boost side switching branch; The power inductor (L2) is connected between the Buck-side switch branch and the Boost-side switch branch; The input filter capacitor (C19) is connected between the positive input terminal (VIN+) and the negative input terminal (VIN-); The output filter capacitor (C21) is connected between the positive output terminal (Vo+) and the negative output terminal (Vo-).

10. The control circuit according to claim 9, characterized in that: The Buck-side switch branch has a first switch node (VS1), and the Boost-side switch branch has a second switch node (VS2). The first switch (Q3) on the Buck side is connected between the positive input terminal (VIN+) and the first switch node (VS1); The second switch (Q6) on the Buck side is connected between the first switch node (VS1) and the negative input terminal (VIN-); The first switch (Q4) on the Boost side is connected between the second switch node (VS2) and the positive output terminal (Vo+); The second switch (Q5) on the Boost side is connected between the second switch node (VS2) and the output negative terminal (Vo-); One end of the power inductor (L2) is connected to the first switching node (VS1), and the other end is connected to the second switching node (VS2). The negative input terminal (VIN-) is connected to the negative output terminal (Vo-).

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