A power tube segmented driving circuit based on miller platform monitoring and an automobile power supply chip

Abstract

The application discloses a power tube segmented driving circuit based on a Miller platform monitoring and an automobile power supply chip, relates to the technical field of integrated circuit design, and comprises a power tube, a drain of the power tube serving as a switching node, a Miller platform monitoring module and a driving module, wherein the Miller platform monitoring module comprises a conversion circuit and a first switch tube, whether the power tube reaches a Miller platform area is judged by detecting the change of the voltage of the switching node, the driving module provides a smaller first driving current when the Miller platform area is not reached, and a detection signal is output when the Miller platform area is reached, so that the driving module switches a larger second driving current. Since the detection signal is generated according to the actual change of the voltage of the switching node, the switching time can be adaptively adjusted, and in addition, the Miller platform monitoring module only needs the conversion circuit and the switch tube to realize the detection function, and does not need a complex analog circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a segmented power transistor drive circuit based on Miller platform monitoring and an automotive power supply chip. Background Technology

[0002] In integrated power transistor driver circuits, the switching speed of the power transistor directly affects the circuit's efficiency and electromagnetic compatibility (EMC) performance. During the power transistor's conduction process, its gate drive voltage typically experiences a Miller plateau phase. During this phase, the drain voltage and drain current change rapidly, easily generating large voltage and current change rates, thus increasing electromagnetic interference (EMI). Reducing the switching speed of the power transistor to suppress EMI prolongs the time the device spends in the Miller plateau phase, increasing switching losses. Therefore, how to adjust the gate drive current according to different conduction phases of the power transistor to reduce both EMC and switching losses becomes a problem that the gate drive module needs to solve.

[0003] In existing technologies, a segmented driving approach is typically used, adjusting the gate drive current based on the operating state of the power transistor. For example, the Miller plateau state can be determined by detecting the gate voltage of the power transistor, and the drive current can be switched based on the detection result. However, this approach is susceptible to parasitic parameters and gate ringing, leading to inaccurate Miller plateau determination. Alternatively, a current mirror structure can be used to achieve multi-stage drive current control. This approach requires high device matching accuracy, and the actual drive current is prone to deviating from the design value. Another approach is to control the turn-on time of different drive branches using a fixed delay. However, this approach cannot adaptively adjust the drive timing based on changes in load, voltage, and device parameters. Furthermore, schemes based on switching node detection of the Miller plateau typically require complex analog detection circuits such as sampling networks, filtering networks, comparators, and dynamic threshold generation circuits. If applied to switching node detection of high-side power transistors, high-voltage processes are also required, increasing circuit complexity and design difficulty. Summary of the Invention

[0004] The purpose of this invention is to provide a segmented drive circuit for power transistors based on Miller platform monitoring and an automotive power chip, in order to solve the problems of inaccurate Miller platform detection, complex circuits, and inability to adapt to load changes in existing segmented drive technologies.

[0005] To address the aforementioned technical problems, this invention provides a segmented power transistor drive circuit based on Miller platform monitoring, comprising a power transistor, wherein the drain of the power transistor serves as a switching node, and further comprising: Miller platform monitoring module and driver module; The Miller plateau monitoring module includes a conversion circuit and a first switching transistor. The input terminal of the conversion circuit is connected to the switching node and serves as the input terminal of the Miller plateau monitoring module. The output terminal of the conversion circuit is connected to the control terminal of the first switching transistor, used to convert the voltage change of the switching node into a control signal. The first terminal of the first switching transistor is connected to the power supply through a pull-up circuit and serves as the output terminal of the Miller plateau monitoring module. The second terminal of the first switching transistor is grounded and used to turn on or off according to the control signal to generate a detection signal characterizing the power transistor entering the Miller plateau region. The input terminal of the drive module is connected to the output terminal of the Miller platform monitoring module, and the output terminal of the drive module is connected to the control terminal of the power transistor. The drive module is used to provide a first drive current to the control terminal of the power transistor when the detection signal is not received, and to provide a second drive current to the control terminal of the power transistor when the detection signal is received. The current value of the first drive current is less than the current value of the second drive current.

[0006] Optionally, the driving module is further configured to: provide a third driving current to the control terminal of the power transistor before providing the first driving current to the control terminal of the power transistor to suppress the influence of the current change during the initial conduction of the power transistor on the power supply voltage; the current value of the third driving current is greater than the current value of the first driving current and less than the current value of the second driving current.

[0007] Optionally, the driving module includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a first resistor, and logic circuitry; The gate of the first NMOS transistor is used to receive the inverted drive signal, the drain of the first NMOS transistor is connected to the first terminal of the first resistor, and the source of the first NMOS transistor is connected to floating ground. The gate of the first PMOS transistor is used to receive the drive signal, the source of the first PMOS transistor is connected to the first terminal of the first resistor, and the drain of the first PMOS transistor is connected to floating ground. The two input terminals of the logic circuit are used to receive the detection signal and the drive signal, respectively. The output terminal of the logic circuit is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the first terminal of the first resistor, and the source of the second NMOS transistor is connected to floating ground. The second terminal of the first resistor is connected to the control terminal of the power transistor.

[0008] Optionally, a second PMOS transistor may also be included; The source of the second PMOS transistor is connected to the power supply, the drain of the second PMOS transistor is connected to the control terminal of the power transistor, and the gate of the second PMOS transistor is used to receive the inverted drive signal, which is used to pull up the voltage of the control terminal of the power transistor when the power transistor is turned off.

[0009] Optionally, the conversion circuit includes: The third NMOS transistor, the second resistor, and the diode; The drain of the third NMOS transistor serves as the input terminal of the conversion circuit, the gate of the third NMOS transistor is connected to an enable signal, and the source of the third NMOS transistor is connected to the first terminal of the second resistor and the cathode of the diode; the second terminal of the second resistor is grounded; and the anode of the diode is grounded.

[0010] Optional features also include: Schmitt triggers; The input of the Schmitt trigger is connected to the output of the Miller platform monitoring module, and the output of the Schmitt trigger is connected to the input of the drive module. This is used to shape the detection signal to filter out interference jitter in the detection signal.

[0011] Optionally, it may also include: a delay unit; The input terminal of the delay unit is connected to the output terminal of the Schmitt trigger, and the output terminal of the delay unit is connected to the input terminal of the drive module, which is used to output the shaped signal after a preset delay.

[0012] Optionally, the pull-up circuit includes: a third resistor; The first end of the third resistor is connected to the power supply, and the second end of the third resistor is connected to the first end of the first switching transistor.

[0013] Optionally, a DC-DC converter circuit may also be included; The DC-DC converter circuit includes: Inductors, freewheeling diodes, and capacitors; The first end of the inductor is connected to the power transistor; The cathode of the freewheeling diode is connected to the first terminal of the inductor, and the anode of the freewheeling diode is grounded; the first terminal of the capacitor is connected to the second terminal of the inductor, and the second terminal of the capacitor is grounded.

[0014] To address the aforementioned technical problems, the present invention also provides an automotive power chip, including the aforementioned segmented power transistor drive circuit based on Miller platform monitoring.

[0015] This invention provides a segmented drive circuit for a power transistor based on Miller plateau monitoring, including a power transistor, with its drain serving as a switching node, a Miller plateau monitoring module, and a drive module. The Miller plateau monitoring module includes a conversion circuit and a first switching transistor. It determines whether the power transistor has reached the Miller plateau region by detecting changes in the switching node voltage, and outputs a detection signal upon reaching the Miller plateau region, causing the drive module to switch to a second drive current. Initially, when the power transistor is turned on, the switching node voltage has not yet changed, and the drive module provides a small first drive current to reduce the current change rate during this stage. When the switching node voltage begins to change, indicating that the power transistor has reached the Miller plateau region, the conversion circuit converts the voltage change of the switching node into a control signal to drive the first switching transistor to conduct. This generates a detection signal at the output of the Miller plateau monitoring module, and the drive module then switches to providing a larger second drive current, accelerating the power transistor to complete the remaining switching process and reducing switching losses. Because the Miller platform employs a smaller drive current to reduce the rate of current change, thus reducing input power supply glitches, a larger current drive is used upon entering the Miller platform. This allows the power transistor to pass through the platform quickly, shortening the duration of the power transistor in a high-voltage, high-current state and reducing switching losses. Simultaneously, the Miller platform monitoring module detects the switching node voltage, making the judgment more reliable. Furthermore, the detection signal is generated based on the actual change in the switching node voltage, rather than using a fixed delay, allowing for adaptive adjustment of the switching timing according to changes in device parameters. Moreover, the Miller platform monitoring module only requires a switching circuit and a switching transistor to achieve the detection function, eliminating the need for complex analog circuits such as sampling networks, filtering networks, and comparators. Its simple structure makes it widely applicable to Miller platform detection of high-side power switching devices.

[0016] Furthermore, the same effect applies to the automotive power chip provided by this invention. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a segmented power transistor drive circuit based on Miller platform monitoring provided by the present invention; Figure 2 This is a schematic diagram of a Miller platform monitoring module provided by the present invention; Figure 3 Timing waveforms of key circuit nodes provided by the present invention. Detailed Implementation

[0019] The core of this invention is to provide a segmented drive circuit for power transistors based on Miller platform monitoring and an automotive power chip.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In integrated power transistor driver circuits, the switching speed of the power transistor directly affects the circuit's efficiency and electromagnetic compatibility (EMC) performance. During the power transistor's conduction process, its gate drive voltage typically experiences a Miller plateau phase. During this phase, the drain voltage and drain current change rapidly, easily generating large voltage and current change rates, thus increasing EMI. Reducing the switching speed of the power transistor to suppress EMI prolongs the time the device spends in the Miller plateau phase, increasing switching losses. Therefore, how to adjust the gate drive current according to different conduction phases of the power transistor to reduce switching losses while minimizing EMC becomes a problem that gate drive circuits need to solve.

[0022] In existing technologies, a segmented driving approach is typically used, adjusting the gate drive current based on the operating state of the power transistor. For example, the Miller plateau state can be determined by detecting the gate voltage of the power transistor, and the drive current can be switched based on the detection result. However, this approach is susceptible to parasitic parameters and gate ringing, leading to inaccurate Miller plateau determination. Alternatively, a current mirror structure can be used to achieve multi-stage drive current control. This approach requires high device matching accuracy, and the actual drive current is prone to deviating from the design value. Another approach is to control the turn-on time of different drive branches using a fixed delay. However, this approach cannot adaptively adjust the drive timing based on changes in load, voltage, and device parameters. Furthermore, schemes based on switching node detection of the Miller plateau typically require complex analog detection circuits such as sampling networks, filtering networks, comparators, and dynamic threshold generation circuits. If applied to switching node detection of high-side power transistors, high-voltage processes are also required, increasing circuit complexity and design difficulty.

[0023] To address the aforementioned technical problems, this invention provides a segmented power transistor drive circuit based on Miller platform monitoring.

[0024] For details, please see Figure 1 , Figure 1 This is a schematic diagram of a segmented drive circuit for power transistors based on Miller platform monitoring, provided by the present invention.

[0025] like Figure 1As shown, the circuit includes a power transistor, with the drain of the power transistor serving as the switching node SW, and also includes: Miller platform monitoring module 2 and drive module 1; Please see Figure 2 , Figure 2 This is a schematic diagram of a Miller platform monitoring module provided by the present invention.

[0026] like Figure 2 As shown, the Miller plateau monitoring module 2 includes a conversion circuit 3 and a first switching transistor. The input terminal of the conversion circuit 3 is connected to the switching node SW and serves as the input terminal of the Miller plateau monitoring module 2. The output terminal of the conversion circuit 3 is connected to the control terminal of the first switching transistor and is used to convert the voltage change of the switching node SW into a control signal. The first terminal of the first switching transistor is connected to the power supply through a pull-up circuit and serves as the output terminal of the Miller plateau monitoring module 2. The second terminal of the first switching transistor is grounded and is used to turn on or off according to the control signal to generate a detection signal characterizing the power transistor entering the Miller plateau region. The input terminal of the drive module 1 is connected to the output terminal of the Miller platform monitoring module 2, and the output terminal of the drive module 1 is connected to the control terminal of the power transistor. The drive module 1 is used to provide a first drive current to the control terminal of the power transistor when no detection signal is received, and to provide a second drive current to the control terminal of the power transistor when a detection signal is received. The current value of the first drive current is less than the current value of the second drive current.

[0027] Specifically, in the operation of the segmented power transistor drive circuit, the power transistor is the core component of the circuit, for example... Figure 2 The third PMOS transistor, M5, is selected as the power transistor. The switching speed of the power transistor directly affects the electromagnetic interference (EMI) performance and power loss of the circuit. During the power transistor's turn-on process, the gate voltage typically experiences a Miller plateau phase. If a large gate drive current is used before the Miller plateau, the power transistor will turn on too quickly, resulting in a large current change rate, which in turn causes fluctuations in the input power supply voltage VDD_HV and EMI. If a small drive current is used during the Miller plateau, the time the power transistor is in a high-voltage, high-current state will be prolonged, increasing switching losses. Therefore, this embodiment provides a small drive current before the Miller plateau to reduce the current change rate during the switching process, and provides a large drive current after entering the Miller plateau to quickly complete the power transistor turn-on process, thereby balancing EMI suppression and reduced switching losses.

[0028] Specifically, during the power transistor's turn-on process, the gate voltage change of the power transistor corresponds to the switch node SW voltage change. When the power transistor has not yet entered the Miller plateau, it mainly charges its gate capacitor, and the switch node SW voltage remains relatively stable. Once the power transistor enters the Miller plateau, its drain voltage begins to change rapidly, i.e., the switch node SW voltage changes. Therefore, by detecting the voltage change at the switch node SW, it is possible to indirectly determine whether the power transistor has entered the Miller plateau. Based on the above correspondence, this embodiment utilizes the switch node SW signal to achieve Miller plateau state detection.

[0029] Specifically, the input of the Miller platform monitoring module 2 is connected to the switching node SW. Through its internal conversion circuit 3, it continuously senses the voltage state of the switching node SW and converts it into a control signal, driving a corresponding change in the conduction state of the first switching transistor. This change in conduction state causes a level change at the output of the Miller platform monitoring module 2. This level change serves as a detection signal indicating that the power transistor has entered the Miller platform and is transmitted to the drive module 1. The input of the drive module 1 receives this detection signal, and its output is connected to the control terminal of the power transistor. Before receiving the detection signal, the drive module 1 determines that the power transistor has not yet entered the Miller platform and provides a first drive current to its control terminal. This first drive current is a small current drive, which can suppress electromagnetic interference during the switching process. Once the detection signal is received, the drive module 1 determines that the power transistor has entered the Miller platform and immediately switches to providing a second drive current, which is greater than the first drive current, to its control terminal. This second drive current is a large current drive, enabling the power transistor to quickly pass through the Miller platform, thereby shortening the duration of the power transistor in a high-voltage, high-current state and reducing switching losses.

[0030] As an example, the first switching transistor in the Miller platform monitoring module 2 is the fourth NMOS transistor M7, and the conversion circuit 3 includes a third NMOS transistor M6, a second resistor R2, and a diode D2. The drain of the third NMOS transistor M6 serves as the input terminal of the conversion circuit 3, the gate of the third NMOS transistor M6 is connected to the enable signal EN, and the source of the third NMOS transistor M6 is connected to the first terminal of the second resistor R2 and the cathode of the diode D2; the second terminal of the second resistor R2 is grounded; and the anode of the diode D2 is grounded. When the Miller platform monitoring module 2 is operating, the enable signal EN remains high, the third NMOS transistor M6 is turned on, and the conversion circuit 3 enters the operating state. When the power transistor has not yet entered the Miller platform, the switching node SW remains low, the voltage at the source of the third NMOS transistor M6 remains low, the fourth NMOS transistor M7 remains off, and its drain remains high due to the pull-up effect of the third resistor R3. Therefore, the Miller platform monitoring module 2 outputs a high-level signal, and the drive module 1 maintains the first drive current operating state. As the power transistor gradually turns on, when it enters the Miller plateau region, the voltage at the switching node SW changes from low to high. Since the third NMOS transistor M6 is on, the voltage change at the switching node SW is transmitted to its source via M6, causing the gate voltage of the fourth NMOS transistor M7 to rise synchronously. When the gate voltage rises above the turn-on threshold voltage of M7, M7 turns on, and its drain output node flips from high to low under the pull-down effect of M7, thus forming a detection signal characterizing the power transistor entering the Miller plateau region. The second resistor R2 provides a pull-down bias, turning off the third NMOS transistor M6 and allowing the gate of the fourth NMOS transistor M7 to quickly return to a low level. Diode D2 protects the circuit from negative voltage. Furthermore, the third NMOS transistor M6 can be a high-voltage device; its gate is controlled by a low-voltage enable signal, and its source voltage is clamped to a lower potential, thus eliminating the need for additional high-voltage processes.

[0031] As an example, the driving module 1 includes a first NMOS transistor M2, a first PMOS transistor M3, a second NMOS transistor M4, a first resistor R1, and logic circuitry. The first NMOS transistors M2, M3, and M4 serve as pathways providing the driving current, while the first resistor R1 limits the charging and discharging current of the power transistors. The logic circuitry controls the switching of the second NMOS transistor M4 based on the driving signal pre_drv1 and the detection signal output by the Miller platform monitoring module 2, thereby switching the driving current. As an example, the power transistor is a third PMOS transistor M5.

[0032] Specifically, when the drive signal pre_drv1 switches from high level to low level, the drive module 1 first enters the initial conduction stage. At this time, the first PMOS transistor M3 and the first NMOS transistor M2 are turned on, while the second NMOS transistor M4 remains off. The first PMOS transistor M3 and the first NMOS transistor M2 provide the third drive current to the gate of the third PMOS transistor M5 through the first resistor R1. The current flowing through the first PMOS transistor M3 is greater than the current flowing through the first NMOS transistor M2. The first PMOS transistor M3 plays the main driving role, causing the gate voltage of the third PMOS transistor M5 to gradually decrease.

[0033] As the gate voltage of the third PMOS transistor M5 gradually decreases, the gate-source voltage of the first PMOS transistor M3 decreases, and the drive current provided by the first PMOS transistor M3 decreases. When the current flowing through the first PMOS transistor M3 is less than the current flowing through the first NMOS transistor M2, the first NMOS transistor M2 plays a major driving role, providing the first drive current to the third PMOS transistor M5, allowing the third PMOS transistor M5 to continue conducting at a lower gate charging speed. The third drive current is greater than the first drive current, but both belong to small current drives, suppressing electromagnetic interference during the switching process. When the third PMOS transistor M5 starts to conduct, a large current change occurs, causing fluctuations in the power supply voltage VDD_HV. To reduce these fluctuations, the rate of change of current in the third PMOS transistor M5 needs to be reduced. Therefore, the third drive current provides a constant voltage change for the third PMOS transistor M5, driving it to start working. At this time, the current change in the third PMOS transistor M5 is relatively stable, thus ensuring a smooth transition of the power supply voltage VDD_HV. If the drive current is too small, it will prolong the time that the third PMOS transistor M5 is in the initial conduction state. Therefore, the third drive current is greater than the first drive current.

[0034] When the Miller platform monitoring module 2 outputs a low-level detection signal, the detection signal and the drive signal pre_drv1 are logically processed by the logic circuit to output a high-level signal, turning on the second NMOS transistor M4. At this time, the second NMOS transistor M4 provides a large current drive and plays the main driving role, while the drive module 1 provides a second drive current to the third PMOS transistor M5. Since the second drive current is greater than the first and third drive currents, it is a large current drive, which can accelerate the gate charging speed of the third PMOS transistor M5, allowing the third PMOS transistor M5 to quickly pass through the Miller platform, thereby shortening the duration of the third PMOS transistor M5 in a high-voltage, high-current state and reducing switching losses.

[0035] As can be seen, this embodiment uses a smaller drive current before the Miller platform to reduce the rate of current change, thereby reducing input power supply glitches. After entering the Miller platform, a large current drive is used to allow the power transistor to pass through the Miller platform quickly, thus shortening the duration of the power transistor in a high-voltage, high-current state and reducing switching losses. Meanwhile, the Miller platform monitoring module 2 detects the switching node SW voltage, making the judgment more reliable. Furthermore, the detection signal is generated based on the actual change of the switching node SW voltage, rather than using a fixed delay, allowing for adaptive adjustment of the switching timing according to changes in load, voltage, and device parameters. In addition, the Miller platform monitoring module 2 only requires the conversion circuit 3 and the switching transistor to achieve the detection function, eliminating the need for complex analog circuits such as sampling networks, filtering networks, and comparators. Its simple structure makes it suitable for widespread application in Miller platform detection of high-side power switching devices.

[0036] Based on the above embodiments: As an optional embodiment, the driving module 1 is further configured to: provide a third driving current to the control terminal of the power transistor before providing the first driving current to the control terminal of the power transistor to suppress the influence of the initial current change of the power transistor on the input power supply voltage VDD_HV; the current value of the third driving current is greater than the current value of the first driving current and less than the current value of the second driving current.

[0037] Specifically, in this embodiment, before providing the first drive current to the control terminal of the power transistor, the drive module 1 first provides the third drive current to the control terminal of the power transistor. The current value of the third drive current is greater than the current value of the first drive current and less than the current value of the second drive current, so that the drive module 1 sequentially experiences the third drive current stage, the first drive current stage and the second drive current stage during the power transistor's conduction process.

[0038] Specifically, when the drive signal pre_drv1 changes from high to low, drive module 1 first enters the third drive current stage. In this stage, drive module 1 provides a third drive current to the control terminal of the power transistor, causing the gate voltage of the power transistor to rise at a preset rate, and the power transistor gradually establishes a conduction channel. Since the drain current of the power transistor establishes rapidly when it first turns on, if the drive speed is too fast, it can easily lead to large voltage fluctuations in the power supply; if the drive current is too small, it will prolong the time the power transistor remains in the initial conduction state. Therefore, this embodiment uses a third drive current between the first and second drive currents to ensure smooth conduction of the power transistor in the initial stage, reducing the fluctuation of the input power supply voltage VDD_HV while ensuring the conduction speed, thus improving the system power supply stability. Subsequently, drive module 1 enters the first drive current stage. In this stage, drive module 1 provides a first drive current to the control terminal of the power transistor. Since the power transistor has completed the initial channel establishment during conduction, the subsequent main task is to continue charging the gate capacitor. Therefore, using a smaller drive current can reduce the gate voltage rise rate, decrease the voltage and current change rates during the power transistor's conduction process, thereby reducing electromagnetic interference and mitigating the current spikes generated by the reverse recovery of the freewheeling diode D1. When the Miller plateau monitoring module 2 detects that the power transistor has entered the Miller plateau region and outputs a detection signal, the drive module 1 switches to the second drive current stage, providing a second drive current to the control terminal of the power transistor. Since the second drive current is a high-current drive, it can accelerate the charging speed of the power transistor's gate, allowing the power transistor to quickly pass through the Miller plateau, shortening the duration of the power transistor in a high-voltage, high-current state, thereby reducing switching losses.

[0039] As can be seen, by adding a third drive current stage before the first drive current, this embodiment enables the power transistor to balance conduction speed and input power stability in the initial stage of conduction, while also avoiding excessive electromagnetic interference, thereby achieving comprehensive optimization of input power supply voltage VDD_HV fluctuations, electromagnetic interference, and switching losses.

[0040] As an optional embodiment, the driving module 1 includes a first NMOS transistor M2, a first PMOS transistor M3, a second NMOS transistor M4, a first resistor R1, and logic circuitry; The gate of the first NMOS transistor M2 is used to receive the inverted drive signal pre_drv1. The drain of the first NMOS transistor M2 is connected to the first terminal of the first resistor R1, and the source of the first NMOS transistor M2 is connected to the floating ground potential GND_HV. The gate of the first PMOS transistor M3 is used to receive the drive signal pre_drv1. The source of the first PMOS transistor M3 is connected to the first terminal of the first resistor R1, and the drain of the first PMOS transistor M3 is connected to the floating ground potential GND_HV. The two input terminals of the logic circuit are used to receive the detection signal and the drive signal pre_drv1, respectively. The output terminal of the logic circuit is connected to the gate of the second NMOS transistor M4. The drain of the second NMOS transistor M4 is connected to the first terminal of the first resistor R1, and the source of the second NMOS transistor M4 is connected to the floating ground potential GND_HV. The second terminal of the first resistor R1 is connected to the control terminal of the power transistor.

[0041] Specifically, taking the third PMOS transistor M5 as an example, the working process of the drive module 1 is described. The first NMOS transistor M2, the first PMOS transistor M3, and the second NMOS transistor M4 serve as drive branches providing drive current. A first resistor R1 is connected between each drive branch and the gate of the third PMOS transistor M5 to limit the gate charging and discharging current. The logic circuit controls the turn-on and turn-off of the second NMOS transistor M4 based on the drive signal pre_drv1 and the detection signal output by the Miller platform monitoring module 2, thereby switching the drive current. As an example, the logic circuit is a NOR gate.

[0042] When the drive signal pre_drv1 switches from high level to low level, the drive module 1 first enters the initial conduction stage. The drive signal pre_drv1 is converted to a high level after passing through an inverter and transmitted to the gate of the first NMOS transistor M2. At the same time, the drive signal pre_drv1 is kept at a low level after passing through a buffer and transmitted to the gate of the first PMOS transistor M3. At this time, the first PMOS transistor M3 and the first NMOS transistor M2 are turned on, and the second NMOS transistor M4 remains off. The first PMOS transistor M3 and the first NMOS transistor M2 provide a third drive current to the gate of the third PMOS transistor M5 through the first resistor R1. The current flowing through the first PMOS transistor M3 is greater than the current flowing through the first NMOS transistor M2. The first PMOS transistor M3 plays the main driving role, causing the gate voltage of the third PMOS transistor M5 to gradually decrease.

[0043] As the gate voltage of the third PMOS transistor M5 gradually decreases, the gate-source voltage of the first PMOS transistor M3 decreases, and the drive current provided by the first PMOS transistor M3 decreases. When the current flowing through the first PMOS transistor M3 is less than the current flowing through the first NMOS transistor M2, the first NMOS transistor M2 plays a major driving role, providing the first drive current to the third PMOS transistor M5, allowing the third PMOS transistor M5 to continue conducting at a lower gate charging speed. The third drive current is greater than the first drive current, but both belong to small current drives, suppressing electromagnetic interference during the switching process. When the third PMOS transistor M5 starts to conduct, a large current change occurs, causing fluctuations in the power supply voltage VDD_HV. To reduce these fluctuations, the rate of change of current in the third PMOS transistor M5 needs to be reduced. Therefore, the third drive current provides a constant voltage change for the third PMOS transistor M5, driving it to start working. At this time, the current change in the third PMOS transistor M5 is relatively stable, thus ensuring a smooth transition of the power supply voltage VDD_HV. If the drive current is too small, it will prolong the time that the third PMOS transistor M5 is in the initial conduction state. Therefore, the third drive current is greater than the first drive current.

[0044] When the Miller platform monitoring module 2 outputs a low-level detection signal, the detection signal and the drive signal pre_drv1 are logically operated through a NOR gate to output a high-level signal, turning on the second NMOS transistor M4. At this time, the second NMOS transistor M4 provides a large current drive and plays the main driving role, while the drive module 1 provides a second drive current to the third PMOS transistor M5. Since the second drive current is greater than the first and third drive currents, it is a large current drive, which can accelerate the gate charging speed of the third PMOS transistor M5, allowing the third PMOS transistor M5 to quickly pass through the Miller platform, thereby shortening the duration of the third PMOS transistor M5 in a high-voltage, high-current state and reducing switching losses.

[0045] As can be seen, in this embodiment, the first PMOS transistor M3, the first NMOS transistor M2, and the second NMOS transistor M4 participate in different driving stages. The driving capability switching between each driving branch can be achieved without complex analog control circuits. The circuit structure is simple and easy to integrate. At the same time, it can automatically switch the driving current according to the actual conduction state of the power transistor, thereby suppressing the fluctuation of the input power supply voltage VDD_HV in the early stage of conduction, suppressing electromagnetic interference before the Miller plateau, and reducing switching losses during the Miller plateau.

[0046] As an optional embodiment, a second PMOS transistor M1 is also included; The source of the second PMOS transistor M1 is connected to the power supply, the drain of the second PMOS transistor M1 is connected to the control terminal of the power transistor, and the gate of the second PMOS transistor M1 is used to receive the inverted drive signal pre_drv1, which is used to pull up the voltage of the control terminal of the power transistor when the power transistor is turned off.

[0047] Specifically, taking the third PMOS transistor M5 as an example, the working process is described as follows: During the conduction phase of the third PMOS transistor M5, the second PMOS transistor M1 remains off. When the third PMOS transistor M5 needs to be turned off, the drive signal pre_drv1 changes from low to high, and after passing through the inverter, becomes a low-level drive signal to control the second PMOS transistor M1 to conduct. This causes the power supply voltage VDD_HV to be applied to the gate of the third PMOS transistor M5 through the second PMOS transistor M1, rapidly pulling up the gate voltage of the third PMOS transistor M5. The gate-source voltage of the third PMOS transistor M5 then rapidly decreases to below the turn-off threshold, thereby achieving rapid turn-off of the third PMOS transistor M5. At the same time, the first NMOS transistor M2, the first PMOS transistor M3, and the second NMOS transistor M4 all exit the conduction state.

[0048] It can be seen that by setting the second PMOS transistor M1, a low-impedance charging path can be provided for the power transistor control terminal during the power transistor turn-off process, so that the voltage of the power transistor control terminal can be quickly restored to the turn-off potential, shortening the power transistor turn-off time and improving the circuit response speed.

[0049] As an optional embodiment, the conversion circuit 3 includes: The third NMOS transistor M6, the second resistor R2, and the diode D2; The drain of the third NMOS transistor M6 serves as the input terminal of the switching circuit 3. The gate of the third NMOS transistor M6 is connected to the enable signal EN. The source of the third NMOS transistor M6 is connected to the first terminal of the second resistor R2 and the cathode of the diode D2. The second terminal of the second resistor R2 is grounded. The anode of the diode D2 is grounded.

[0050] Specifically, the first switching transistor in the Miller platform monitoring module 2 is the fourth NMOS transistor M7. When the Miller platform monitoring module 2 is working, the enable signal EN remains at a high level, the third NMOS transistor M6 is turned on, and the conversion circuit 3 enters the working state. When the power transistor has not yet entered the Miller platform, the switching node SW remains at a low level, the source voltage of the third NMOS transistor M6 remains low, the fourth NMOS transistor M7 remains off, and its drain remains at a high level due to the pull-up effect of the third resistor R3. Therefore, the Miller platform monitoring module 2 outputs a high-level signal, and the drive module 1 maintains the first drive current working state. As the power transistor gradually turns on, when the power transistor enters the Miller platform, the voltage of the switching node SW changes from low level to high level. Since the third NMOS transistor M6 is in the on state, the voltage change at the switching node SW is transmitted to its source through the third NMOS transistor M6, causing the gate voltage of the fourth NMOS transistor M7 to rise synchronously. When the voltage rises above the turn-on threshold voltage of the fourth NMOS transistor M7, the fourth NMOS transistor M7 turns on, and its drain output node flips from a high level to a low level under the pull-down action of the fourth NMOS transistor M7, thus forming a detection signal characterizing the power transistor entering the Miller plateau region. The second resistor R2 is used to provide pull-down bias, so that the third NMOS transistor M6 is turned off, and the gate of the fourth NMOS transistor M7 can quickly return to a low level; the diode D2 is used to protect the circuit and prevent negative voltage from occurring.

[0051] As can be seen, in this embodiment, the third NMOS transistor M6, the second resistor R2, and the diode D2 together constitute a voltage conversion network, which converts the voltage change of the switching node SW into a control signal suitable for driving the first switching transistor. Thus, Miller platform detection is achieved by utilizing the conduction threshold of the first switching transistor, without the need for a complex analog detection circuit, which can effectively reduce circuit complexity and improve circuit integration.

[0052] As an optional embodiment, it also includes: a Schmitt trigger; The input of the Schmitt trigger is connected to the output of the Miller platform monitoring module 2, and the output of the Schmitt trigger is connected to the input of the drive module 1. This is used to shape the detection signal to filter out interference jitter in the detection signal.

[0053] Because the switching node SW experiences a large voltage change rate during the power transistor's conduction period, the detection signal output by the Miller platform monitoring module 2 may exhibit level jitter and glitches due to factors such as parasitic parameters, switching noise, and electromagnetic interference. Directly inputting this detection signal into the drive module 1 could lead to misjudgments of the Miller platform state, or even repeated switching of the drive current, affecting the normal drive of the power transistor. Therefore, this embodiment incorporates a Schmitt trigger between the Miller platform monitoring module 2 and the drive module 1. The Schmitt trigger has different upward and downward flip thresholds. When the detection signal rises to the upward flip threshold, the output state of the Schmitt trigger flips; when the detection signal falls to the downward flip threshold, the output state returns to normal. Because there is a hysteresis interval between the upward and downward flip thresholds, high-frequency glitches and small-amplitude voltage fluctuations in the detection signal can be effectively filtered out, resulting in a steeper rising and falling edge for the output signal, providing a stable and reliable digital control signal for the drive module 1.

[0054] As can be seen, by setting a Schmitt trigger, this embodiment can improve the anti-interference capability of the detection signal, avoid the malfunction of the drive module 1 due to the jitter of the detection signal, and improve the accuracy of drive current switching.

[0055] As an optional embodiment, it further includes: a delay unit; The input of the delay unit is connected to the output of the Schmitt trigger, and the output of the delay unit is connected to the input of the driver module 1. It is used to output the shaped signal after a preset delay.

[0056] Specifically, when the Miller platform monitoring module 2 detects that the power transistor enters the Miller platform, the voltage of the switching node SW is in a rapidly changing phase. At this time, the parasitic capacitance, parasitic inductance, and switching noise in the circuit are all quite significant. If the drive module 1 switches the drive current immediately after the detection signal is generated, the drive current switching process may overlap with the rapid change of the switching node SW voltage, thus affecting the stability of the drive module 1. Therefore, this embodiment sets a delay unit. After the Schmitt trigger outputs a stable detection signal, the detection signal is delayed for a preset time before being output to the drive module 1. This allows the drive module 1 to switch to the second drive current only after the phase of the fastest change in the switching node SW voltage has ended. Since the delay time is only a short period of time required to avoid the drastic change phase of the switching node SW, it will not affect the Miller platform detection result, nor will it change the control method of the drive module 1 to switch the drive current according to the Miller platform state.

[0057] For details, please see Figure 3 , Figure 3 Timing waveforms of key circuit nodes provided by the present invention.

[0058] like Figure 3 As shown, the following parameters are included: drive signal pre_drv1, gate drive voltage vp_hv_post of the third PMOS transistor M5, voltage VSW of switching node SW, voltage VB of the connection node B between the gate of the fourth NMOS transistor M7 and the output of the conversion circuit 3, voltage VC of the connection node between the fourth NMOS transistor M7 and the third resistor, voltage VA of the output node A after processing by the Schmitt trigger and delay unit, and gate drive voltage pre_drv2 of the second NMOS transistor M4. During the time period from t0 to t1, pre_drv1 switches from high level to low level, and drive module 1 starts to drive the power transistor to conduct. At this time, drive module 1 enters the third drive current stage, and the vp_hv_post voltage begins to decrease, so that the third PMOS transistor M5, which is the power transistor, gradually establishes a conduction channel, reducing the current change rate in the initial stage of conduction, thereby reducing the fluctuation of the input power supply voltage VDD_HV. During this stage, VSW remains unchanged, VB remains low, and the fourth NMOS transistor M7 remains off. Therefore, VC remains high, and VA and pre_drv2 remain low. From t1 to t2, drive module 1 enters the first drive current stage, providing the first drive current to the gate of the power transistor. Since the third PMOS transistor M5 has completed its initial conduction and continues to charge the gate capacitor, a smaller drive current can further reduce the rate of decrease of vp_hv_post, thereby reducing the rate of voltage and current change during power transistor conduction, reducing electromagnetic interference, and mitigating the current spike generated by the reverse recovery of the freewheeling diode D1. At this time, the third PMOS transistor M5 has not yet entered the Miller plateau, and VSW remains essentially unchanged. Therefore, VB, VC, VA, and pre_drv2 all remain low. At time t2, the gate voltage of the third PMOS transistor M5 reaches the Miller plateau, and VSW rises rapidly from low. Since the third NMOS transistor M6 is in the conducting state, VB rises synchronously. When VB is higher than the turn-on threshold of the fourth NMOS transistor M7, the fourth NMOS transistor M7 turns on, and VC changes from high level to low level. Subsequently, the VC signal is shaped and delayed by a Schmitt trigger and a delay unit. VA flips from high level to low level at time t3, which in turn causes pre_drv2 to flip from low level to high level, controlling the second NMOS transistor M4 to turn on. The drive module 1 enters the second drive current stage, increasing the charging speed of the second NMOS transistor M4, allowing the third PMOS transistor M5 to quickly pass through the Miller plateau, shortening the duration of the third PMOS transistor M5 in a high voltage and high current state, thereby reducing switching losses.

[0059] It is evident that by setting a delay unit, the simultaneous occurrence of drive current switching and drastic changes in the switching node SW voltage can be avoided, reducing interference generated during drive current switching, improving the stability and reliability of the gate drive voltage pre_drv2 of the second NMOS transistor M4, enabling drive module 1 to more smoothly complete the switching between different drive stages, and further improving the working stability of the entire switching power supply circuit.

[0060] As an optional embodiment, the pull-up circuit includes: a third resistor R3; The first end of the third resistor R3 is connected to the power supply, and the second end of the third resistor R3 is connected to the first end of the first switching transistor.

[0061] Specifically, the third resistor R3 is used to provide a pull-up voltage for the output node of the first switching transistor. When the first switching transistor is in the off state, the output node of the Miller platform monitoring module 2 remains at a high level due to the pull-up effect of the third resistor R3; when the first switching transistor is on, the output node is pulled to a low level by the first switching transistor, thereby forming a stable high and low level detection signal, which is then output to the subsequent drive module 1.

[0062] As can be seen, by using the third resistor R3 as a pull-up circuit, this embodiment can not only achieve stable switching of the output node level, but also has a simple circuit structure, is easy to integrate, and helps to reduce circuit complexity and chip area.

[0063] As an optional embodiment, a DC-DC converter circuit is also included; The DC-DC converter circuit includes: Inductor L1, freewheeling diode D1, and capacitor C1; The first terminal of inductor L1 is connected to the power transistor; The cathode of the freewheeling diode D1 is connected to the first terminal of the inductor L1, and the anode of the freewheeling diode D1 is grounded; the first terminal of the capacitor C1 is connected to the second terminal of the inductor L1, and the second terminal of the capacitor C1 is grounded.

[0064] Specifically, when the power transistor is turned on, the power supply stores energy in the inductor L1 through the power transistor; when the power transistor is turned off, the energy stored in the inductor L1 continues to be released to the load through the freewheeling diode D1 to maintain the continuity of the output current. The capacitor C1 filters the output voltage, reduces the output voltage ripple, and improves the stability of the output voltage.

[0065] As can be seen, this embodiment achieves voltage transformation by setting inductor L1, freewheeling diode D1 and capacitor C1, utilizing the energy storage and release of inductor L1, while ensuring the continuity of inductor L1 current and reducing output voltage ripple.

[0066] To address the aforementioned technical problems, the present invention also provides an automotive power chip, including the aforementioned segmented power transistor drive circuit based on Miller platform monitoring.

[0067] For an introduction to the automotive power chip provided by this invention, please refer to the embodiment of the power transistor segmented drive circuit based on Miller platform monitoring; this invention will not be described in detail here.

[0068] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0069] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

Claims

1. A segmented driving circuit for a power transistor based on Miller platform monitoring, comprising a power transistor, wherein the drain of the power transistor serves as a switching node, characterized in that, Also includes: Miller platform monitoring module and driver module; The Miller platform monitoring module includes a conversion circuit and a first switching transistor; The input terminal of the conversion circuit is connected to the switching node and serves as the input terminal of the Miller plateau monitoring module. The output terminal of the conversion circuit is connected to the control terminal of the first switching transistor, which is used to convert the voltage change of the switching node into a control signal. The first terminal of the first switching transistor is connected to the power supply through a pull-up circuit and serves as the output terminal of the Miller plateau monitoring module. The second terminal of the first switching transistor is grounded and is used to turn on or off according to the control signal to generate a detection signal characterizing the power transistor entering the Miller plateau region. The input terminal of the drive module is connected to the output terminal of the Miller platform monitoring module, and the output terminal of the drive module is connected to the control terminal of the power transistor. The drive module is used to provide a first drive current to the control terminal of the power transistor when the detection signal is not received, and to provide a second drive current to the control terminal of the power transistor when the detection signal is received. The value of the first driving current is less than the value of the second driving current.

2. The segmented power transistor drive circuit based on Miller platform monitoring as described in claim 1, characterized in that, The driving module is further configured to: provide a third driving current to the control terminal of the power transistor before providing the first driving current to the control terminal of the power transistor to suppress the influence of the current change during the initial conduction of the power transistor on the power supply voltage; the current value of the third driving current is greater than the current value of the first driving current and less than the current value of the second driving current.

3. The segmented power transistor drive circuit based on Miller platform monitoring as described in claim 2, characterized in that, The driving module includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a first resistor, and logic circuitry. The gate of the first NMOS transistor is used to receive the inverted drive signal, the drain of the first NMOS transistor is connected to the first terminal of the first resistor, and the source of the first NMOS transistor is connected to floating ground. The gate of the first PMOS transistor is used to receive the drive signal, the source of the first PMOS transistor is connected to the first terminal of the first resistor, and the drain of the first PMOS transistor is connected to floating ground. The two input terminals of the logic circuit are used to receive the detection signal and the drive signal, respectively. The output terminal of the logic circuit is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the first terminal of the first resistor, and the source of the second NMOS transistor is connected to floating ground. The second terminal of the first resistor is connected to the control terminal of the power transistor.

4. The segmented power transistor drive circuit based on Miller platform monitoring as described in claim 3, characterized in that, It also includes a second PMOS transistor; The source of the second PMOS transistor is connected to the power supply, the drain of the second PMOS transistor is connected to the control terminal of the power transistor, and the gate of the second PMOS transistor is used to receive the inverted drive signal, which is used to pull up the voltage of the control terminal of the power transistor when the power transistor is turned off.

5. The segmented power transistor drive circuit based on Miller platform monitoring as described in claim 1, characterized in that, The conversion circuit includes: The third NMOS transistor, the second resistor, and the diode; The drain of the third NMOS transistor serves as the input terminal of the conversion circuit, the gate of the third NMOS transistor is connected to an enable signal, and the source of the third NMOS transistor is connected to the first terminal of the second resistor and the cathode of the diode; the second terminal of the second resistor is grounded; and the anode of the diode is grounded.

6. The segmented power transistor drive circuit based on Miller platform monitoring as described in claim 1, characterized in that, Also includes: Schmitt trigger; The input of the Schmitt trigger is connected to the output of the Miller platform monitoring module, and the output of the Schmitt trigger is connected to the input of the drive module. This is used to shape the detection signal to filter out interference jitter in the detection signal.

7. The segmented power transistor drive circuit based on Miller platform monitoring as described in claim 6, characterized in that, Also includes: Delay unit; The input terminal of the delay unit is connected to the output terminal of the Schmitt trigger, and the output terminal of the delay unit is connected to the input terminal of the drive module, which is used to output the shaped signal after a preset delay.

8. The segmented power transistor drive circuit based on Miller platform monitoring as described in claim 1, characterized in that, The pull-up circuit includes: a third resistor; The first end of the third resistor is connected to the power supply, and the second end of the third resistor is connected to the first end of the first switching transistor.

9. The segmented power transistor drive circuit based on Miller platform monitoring as described in any one of claims 1 to 8, characterized in that, It also includes a DC-DC converter circuit; The DC-DC converter circuit includes: Inductors, freewheeling diodes, and capacitors; The first end of the inductor is connected to the power transistor; The cathode of the freewheeling diode is connected to the first terminal of the inductor, and the anode of the freewheeling diode is grounded; the first terminal of the capacitor is connected to the second terminal of the inductor, and the second terminal of the capacitor is grounded.

10. An automotive power supply chip, characterized in that, Includes the power transistor segmented drive circuit based on Miller platform monitoring as described in any one of claims 1 to 9.

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