A complementary PWM dead-time dynamic allocation method and system based on pulse width and dead-time comparison

Abstract

The application discloses a complementary PWM dead-time dynamic allocation method and system based on pulse width and dead-time comparison, and belongs to the technical field of pulse width modulation control of power electronic converters. The method constructs a feature vector and a pulse width sequence; the pulse width sequence is input into a long short-term memory network to predict the pulse width of the next period; after time domain features and pulse width difference frequency domain features are fused through cross attention and self-calibration gating, a dead-time allocation coefficient and a mode flag are output; according to the mode flag, symmetric allocation or asymmetric allocation based on the allocation coefficient is selected, and the dead-time is written into a PWM dead-time register; a physical basic compensation duty ratio and a residual compensation amount are calculated, the two are superimposed to form a three-phase duty ratio compensation amount, and the three-phase duty ratio compensation amount is added to an original duty ratio instruction; finally, six-way complementary PWM driving signals with asymmetric dead-time are generated. The application is helpful to improve the output voltage waveform quality, reduce switching loss and improve the adaptability of the system to different operating conditions under dynamic conditions.

Description

Technical Field

[0001] This invention relates to the field of pulse width modulation control technology for power electronic converters, and specifically to a complementary PWM dead-time dynamic allocation method and system based on pulse width and dead-time comparison. Background Technology

[0002] In voltage source inverters, to prevent shoot-through short circuits between the upper and lower power switches on the same bridge arm during commutation, a dead time is typically inserted into the complementary PWM signal, delaying the turn-on of the switch that is about to conduct. However, the introduction of dead time causes the actual output voltage of the inverter to deviate from the voltage corresponding to the ideal modulation wave, resulting in voltage drop and waveform distortion. The dead time effect is particularly pronounced at low modulation ratios, low switching frequencies, or near the zero-crossing point of the output current.

[0003] Traditional dead-time compensation methods are mostly based on the average voltage equivalence principle, calculating the compensation voltage according to current polarity and a fixed dead time, and then superimposing it onto the modulation wave or duty cycle command. This approach is effective when the dead time is symmetrically allocated and the operating conditions are relatively stable. However, when operating conditions vary widely and load fluctuations are significant, the fixed-parameter compensation strategy struggles to adapt well to different operating conditions, and the harmonic suppression effect and compensation accuracy of the output voltage are easily affected. Furthermore, some studies have attempted to adjust the dead time or adopt asymmetrical allocation, but most schemes require a cumbersome offline calibration process or rely on relatively simplified empirical rules. Their adaptability remains insufficient when facing complex scenarios with coupled changes in modulation ratio, load, and temperature.

[0004] In recent years, data-driven control methods have been explored in the field of power electronics. Some schemes attempt to learn dead-time compensation using neural networks. However, these schemes often directly learn end-to-end compensation values, failing to fully utilize the physical mechanisms. This results in difficulties in ensuring the model's generalization ability and reliability under unseen operating conditions. Therefore, how to combine the prior knowledge of the physical model with the learning capabilities of data-driven systems to allocate the dead time of the upper and lower bridge arms in real time and reasonably under dynamically changing operating conditions, and to effectively compensate for voltage distortion caused by the dead time, has become a technical problem that needs further resolution in this field.

[0005] To address the aforementioned issues, there is an urgent need for a complementary PWM dead-time dynamic allocation method and system based on pulse width and dead-time comparison to solve the problems existing in traditional methods. Summary of the Invention

[0006] The purpose of this invention is to provide a complementary PWM dead-time dynamic allocation method and system based on pulse width and dead-time comparison, which helps to improve the output voltage waveform quality, reduce switching losses, and enhance the system's adaptability to different operating conditions under dynamic operating conditions.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison includes: Step 1: Acquire real-time parameters in each control cycle, preprocess them, construct a real-time feature vector, and construct a time-series pulse width sequence from the pulse widths of the most recent N control cycles. Step 2: Input the temporal pulse width sequence into the pre-trained temporal feature-enhanced long short-term memory network, and output the predicted pulse width for the next control cycle; Step 3: Concatenate the real-time feature vector, the current pulse width, and the predicted pulse width to form a time-domain feature. Construct a frequency-domain feature of the difference sequence between the predicted pulse width and the current pulse width. The time-domain feature and the frequency-domain feature are bidirectionally interacted through the cross-attention fusion module. After the self-calibration gating module dynamically modulates the decision confidence based on the input uncertainty, the dead zone allocation coefficient and mode flag are output through the dual-head output layer respectively. Step 4: When the mode flag indicates standard dead time mode, the preset total dead time is symmetrically allocated to the upper bridge arm dead time and the lower bridge arm dead time; when the mode flag indicates dead time optimization mode, the preset total dead time is asymmetrically allocated to the upper bridge arm dead time and the lower bridge arm dead time according to the dead time allocation coefficient, and the allocated dead time is written into the dead time register of the PWM module. Step 5: Based on the equivalent model of dead zone voltage average value, calculate the basic compensation duty cycle of the physical model using the difference between the dead time of the upper and lower bridge arms, current polarity, DC bus voltage and switching cycle. Obtain the residual compensation duty cycle based on the physical guided residual network. Calculate the three-phase duty cycle compensation amount based on the basic compensation duty cycle and residual compensation duty cycle of the physical model. Then, superimpose the three-phase duty cycle compensation amount onto the original three-phase duty cycle command output by the current loop controller to obtain the compensated three-phase duty cycle command. Step 6: Calculate the PWM comparison value based on the compensated three-phase duty cycle instruction, use the PWM module to delay the conduction edge of the original PWM signal according to the dead time in the dead time register, generate six complementary PWM drive signals with asymmetric dead time, and control the power switching transistor after passing through the drive circuit.

[0008] Furthermore, in step 1, the real-time parameters include the current pulse width, the preset total dead time, the instantaneous value and polarity of the three-phase current, the DC bus voltage, the current switching frequency, the power device temperature, and the current modulation ratio.

[0009] Further, in step 2, the temporal feature-enhanced long short-term memory network extracts local time-frequency features of the pulse width sequence through a multi-scale convolutional preprocessing layer, extracts the temporal dependencies of the sequence through a two-layer bidirectional long short-term memory encoding layer, adaptively adjusts the retention degree of each time step information according to the rate of change of the encoding vector along the time direction through a temporal decay gating layer, and performs weighted summation of the encoding vectors of each time step through an attention output layer to output the predicted pulse width of the next control cycle.

[0010] Furthermore, the multi-scale convolutional preprocessing layer includes three parallel convolutional branches with kernel sizes of 2, 4, and 8, respectively. Each branch has 8 kernels and a stride of 1. The outputs of the three branches are aligned along the end of the time dimension and then concatenated in the feature dimension to form local time-frequency features.

[0011] Furthermore, the temporal decay gating layer calculates an adaptive decay factor for each coding time step, specifically as follows: The rate of change of the coding vector along the time direction is quantified by the L2 norm of the difference between the coding vectors of adjacent time steps. The rate of change is then mapped to an adaptive decay factor through an exponential function with a learnable decay scale parameter, and the decay factor of the first time step is fixed at 1. The adaptive decay factor is multiplied by the coding vector of the corresponding time step to obtain the decay-corrected coding matrix.

[0012] Furthermore, in step 3, the frequency domain features of the difference sequence between the predicted pulse width and the current pulse width are constructed, specifically as follows: Maintain a circular buffer of length K to store the difference between the predicted pulse width and the current pulse width in the most recent K control cycles. Window the sequence of the difference values ​​and calculate the K-point discrete Fourier transform. Encode the one-sided amplitude spectrum to obtain the frequency domain features.

[0013] Furthermore, in step 3, the time-domain features and frequency-domain features are bidirectionally interacted through a cross-attention fusion module, specifically as follows: Using time-domain and frequency-domain features as queries, and another domain feature as key and value, attention weights are generated by scaling the dot product and then passing it through the Sigmoid function. The value vector is then weighted using these attention weights to obtain enhanced time-domain and frequency-domain features. The original time-domain features, original frequency-domain features, enhanced time-domain features, and enhanced frequency-domain features are then concatenated to obtain a fused feature vector.

[0014] Further, in step 5, the physical-guided residual network includes a temporal convolutional residual learning module. The temporal convolutional residual learning module extracts local patterns from the temporal feature matrix through two layers of causal-filled one-dimensional convolutional layers. After being compressed into a temporal aggregated feature vector by a global average pooling layer, it is concatenated with the current real-time feature vector, auxiliary feature vector, and physical model basic compensation duty cycle. The residual compensation duty cycle is then output through a multi-layer fully connected network.

[0015] The present invention also provides a complementary PWM dead-time dynamic allocation system based on pulse width and dead-time comparison, which is applied to the above-mentioned complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison, including: a current sensor, a voltage sensor, a temperature sensor, a signal conditioning circuit, an analog-to-digital conversion unit, a digital processor, a PWM peripheral unit, a drive circuit, and a three-phase inverter power bridge. The digital processor is internally equipped with a data acquisition and feature extraction module, a pulse width change trend prediction module, a hybrid domain adaptive decision-making module, a dead zone allocation execution module, a deep compensation network inference module, and a PWM signal generation and control module. The current sensor, voltage sensor, and temperature sensor are connected to the digital processor via a signal conditioning circuit and an analog-to-digital converter. The digital processor outputs six complementary PWM logic signals to the drive circuit via a PWM peripheral unit. The drive circuit is connected to the gate of each power switch in the three-phase inverter power bridge.

[0016] In summary, the present invention has at least one of the following beneficial technical effects: Firstly, by modeling and predicting pulse width sequences through time-series feature-enhanced long short-term memory networks, the changing trend of pulse width can be perceived in advance, providing reference information for subsequent dead zone allocation decisions. This helps to adjust the control strategy in a timely manner when there are sudden load changes or rapid changes in modulation ratio, reducing voltage deviation caused by response lag.

[0017] Secondly, the time-domain operating characteristics and the frequency-domain characteristics of pulse width difference are fused through cross-attention, and the decision confidence is dynamically modulated by a self-calibration gating mechanism. This allows the dead-zone allocation coefficient and mode flag to adaptively adjust according to the reliability of the current operating state. When the feature quality degrades due to noise or disturbance, the network output can tend towards a relatively conservative safe default value, which is beneficial to improving the robustness of the system.

[0018] Third, the duty cycle compensation is calculated by combining physical model feedforward with data-driven residual learning. The physical model provides basic compensation terms that conform to the equivalent relationship of the dead zone voltage average value. The residual network only needs to learn nonlinear and non-ideal factors that the model fails to cover, thus taking into account the interpretability and accuracy of the compensation to a certain extent. It also helps to maintain relatively stable compensation performance under unseen operating conditions.

[0019] Fourth, by distinguishing between standard dead zone mode and dead zone optimization mode by mode flags, the system can adopt a simplified symmetric allocation strategy in steady-state low-disturbance scenarios, and adaptively switch to asymmetric allocation in scenarios requiring fine adjustment, which helps to achieve a certain balance between efficiency improvement and control complexity.

[0020] Fifth, the overall solution integrates pulse width prediction, dead zone dynamic allocation, dead zone voltage compensation, and PWM signal generation into a complete link executed cycle by cycle. The modules work together to reduce the total harmonic distortion rate of the inverter output voltage and reduce switching losses over a wide operating range, and has a certain adaptability to parameter changes and operating condition drift. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the method flow of the present invention; Figure 2 A bar chart comparing THD and switching losses; Figure 3 A biaxial schematic diagram showing the variation of α and THD with load rate; Figure 4 This is a magnified waveform diagram showing the comparison between the actual pulse width and the predicted pulse width. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0023] like Figure 1 As shown, this invention provides a complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison, comprising: Step 1: Acquire real-time parameters in each control cycle, preprocess them, construct a real-time feature vector, and construct a time-series pulse width sequence from the pulse widths of the most recent N control cycles. Step 2: Input the temporal pulse width sequence into the pre-trained temporal feature-enhanced long short-term memory network, and output the predicted pulse width for the next control cycle; Step 3: Concatenate the real-time feature vector, the current pulse width, and the predicted pulse width to form a time-domain feature. Construct a frequency-domain feature of the difference sequence between the predicted pulse width and the current pulse width. The time-domain feature and the frequency-domain feature are bidirectionally interacted through the cross-attention fusion module. After the self-calibration gating module dynamically modulates the decision confidence based on the input uncertainty, the dead zone allocation coefficient and mode flag are output through the dual-head output layer respectively. Step 4: When the mode flag indicates standard dead time mode, the preset total dead time is symmetrically allocated to the upper bridge arm dead time and the lower bridge arm dead time; when the mode flag indicates dead time optimization mode, the preset total dead time is asymmetrically allocated to the upper bridge arm dead time and the lower bridge arm dead time according to the dead time allocation coefficient, and the allocated dead time is written into the dead time register of the PWM module. Step 5: Based on the equivalent model of dead zone voltage average value, calculate the basic compensation duty cycle of the physical model using the difference between the dead time of the upper and lower bridge arms, current polarity, DC bus voltage and switching cycle. Obtain the residual compensation duty cycle based on the physical guided residual network. Calculate the three-phase duty cycle compensation amount based on the basic compensation duty cycle and residual compensation duty cycle of the physical model. Then, superimpose the three-phase duty cycle compensation amount onto the original three-phase duty cycle command output by the current loop controller to obtain the compensated three-phase duty cycle command. Step 6: Calculate the PWM comparison value based on the compensated three-phase duty cycle instruction, use the PWM module to delay the conduction edge of the original PWM signal according to the dead time in the dead time register, generate six complementary PWM drive signals with asymmetric dead time, and control the power switching transistor after passing through the drive circuit.

[0024] Next, the present invention will provide a detailed description of the above steps in conjunction with specific parameter settings and embodiments: In step 1, real-time parameters are acquired in each control cycle and preprocessed to construct a real-time feature vector. Simultaneously, the pulse widths of the most recent N control cycles are constructed into a time-series pulse width sequence, specifically: Step 1, as the input stage of the entire method, is responsible for acquiring and preprocessing all the raw signals and parameters required for subsequent steps. Its output is directly used by the Long Short-Term Memory network in Step 2 and the Hybrid Domain Adaptive Decision Network in Step 3. The following is a detailed explanation of Step 1, which includes: 1. Current pulse width Acquisition Current pulse width This is provided directly by the PWM timer module of a digital signal processor or microcontroller. At the beginning of each control cycle, the PWM timer module calculates the duty cycle instruction based on vector control or other higher-level control algorithms. ,Will Multiplying this value by the PWM carrier period register value yields the desired on-time of the current channel, i.e., the pulse width. . The value is expressed as a timer count or directly converted to nanoseconds and stored in the compare register of the PWM module. It is obtained by the main program of the method by reading this register without the need for additional hardware.

[0025] 2. Preset dead time Acquisition Preset dead time This is a fixed time constant determined during the inverter design phase based on the turn-on and turn-off delay characteristics of the power switches, and is stored in the dead-time configuration register of the digital signal processor. Step 1 obtains this by reading the register. Its value is written during the system initialization phase and remains unchanged during normal operation.

[0026] 3. Acquisition of inverter operating parameters Inverter operating parameters are acquired through sensors and conditioning circuits, converted into digital quantities by an analog-to-digital converter, and then sent to a digital signal processor. The specific methods for acquiring each parameter are as follows: Instantaneous value of three-phase current , , The current is detected by Hall effect current sensors installed on the three-phase output lines. The sensor output voltage is scaled to the input range of the analog-to-digital converter by a proportional conditioning circuit composed of operational amplifiers. The analog-to-digital converter samples synchronously at the control frequency, and the sampling result is transmitted to the processor memory through direct memory access.

[0027] Current polarity , , The sign of the three-phase current instantaneous values ​​obtained in step 1.3 is determined by a digital signal processor; the positive current corresponds to... Negative current corresponds to Zero current corresponds to .

[0028] DC bus voltage The voltage detection circuit, consisting of a resistor divider network connected across the DC bus capacitor and a differential amplifier, obtains the voltage divider signal. After sampling by one channel of the analog-to-digital converter, the voltage divider signal is multiplied by the voltage divider ratio in the processor to convert it into the actual bus voltage value.

[0029] Current switching frequency : Read from the PWM clock configuration register of the digital signal processor, it is the reciprocal of the carrier period register, and the unit is Hertz.

[0030] Power device temperature The voltage is detected by a negative temperature coefficient thermistor mounted on the heat sink of the power module. The thermistor and pull-up resistor form a voltage divider circuit. The voltage divider value is sampled by one channel of the analog-to-digital converter, and then the processor converts it into an approximate junction temperature value by looking up a table based on the thermistor's resistance-temperature characteristic curve.

[0031] Current modulation ratio The variable calculated and stored by the upper-level control algorithm in the digital signal processor is directly read and defined as the ratio of the fundamental amplitude of the output phase voltage to half of the DC bus voltage. , among which This represents the current fundamental amplitude of the output voltage.

[0032] 4. Preprocessing and construction of real-time feature vectors The collected raw parameters are preprocessed before being fed into subsequent networks to construct real-time feature vectors. .

[0033] The preprocessing procedure is as follows: The instantaneous three-phase current values ​​are first digitally filtered by a second-order Butterworth low-pass filter with a cutoff frequency of one-tenth of the switching frequency to eliminate switching ripple and high-frequency noise; the filtered current values ​​are then normalized by dividing by the calibrated rated value of the current sensor. The DC bus voltage is normalized by dividing by the calibrated rated bus voltage of the inverter. The power device temperature is then subtracted. The current switching frequency is normalized by dividing the current temperature by the difference between the maximum allowable junction temperature of the power module and the room temperature reference. The current modulation ratio is also normalized by dividing the current switching frequency by the inverter's maximum switching frequency. In itself Within this range, no additional normalization is required. Current polarity is a discrete value. , or , keep it directly.

[0034] The preprocessed parameters are concatenated into a real-time feature vector in the following order. : ; in , , These are the normalized three-phase current values. This is the normalized DC bus voltage. The normalized switching frequency. The normalized power device temperature is indicated by the superscript. This indicates transpose. The dimension is fixed at 10, which serves as part of the input to the hybrid domain adaptive decision network in step 3 and the deep compensation network in step 5.

[0035] 5. Construction of temporal pulse width sequences To meet the input requirements of the Long Short-Term Memory network in step 2, step 1 also requires constructing a temporal pulse width sequence. .

[0036] The digital signal processor maintains a length of in the system memory. A circular buffer, specifically used to store the most recently accessed data. Pulse width value per control cycle At the end of each control cycle, the current... Values ​​are written to the end of the buffer, and the oldest value is removed. When step 1 is executed, all values ​​in the circular buffer are... The values ​​are read out in chronological order to form a time-series pulse width sequence: ; in This indicates the pulse width of the current cycle. This indicates the pulse width of the previous cycle, and so on. In this method... The typical value is 16. The units of each element are all the same as Consistent, no additional normalization is needed, because the LSTM network will adaptively learn the appropriate data scaling during the training process.

[0037] 6. Data validity check After constructing the feature vectors and time series, step 1 also performs a basic data validity check. Specifically, this check involves determining the DC bus voltage. The system checks whether the voltage is below the undervoltage protection threshold and whether the three-phase current exceeds the hardware overcurrent protection threshold. If any of these abnormal conditions are met, step 1 will output an error flag signal to the PWM blocking module, directly blocking all switching transistor drive pulses, and subsequent steps 2 to 6 will not be executed. This check ensures that subsequent inference steps always operate on valid data.

[0038] Finally, the output of step 1 includes the following four items: First output: Current pulse width The input is passed to the hybrid domain adaptive decision network in step 3 as one of the inputs; Second output: Preset dead time The dead time allocation execution module in step 4 is passed to the subsequent dead time calculation. Third output: Real-time feature vector The inputs are respectively passed to the hybrid domain adaptive decision network in step 3 and the deep compensation network in step 5; Fourth output: Timing pulse width sequence The input is passed to the Long Short-Term Memory network in step 2.

[0039] In step 2, the temporal pulse width sequence is input into the pre-trained temporal feature-enhanced long short-term memory network, which outputs the predicted pulse width for the next control cycle, specifically: Step 2 follows the timing pulse width sequence output from Step 1. The pulse width of the next control cycle is predicted by a pre-trained temporal feature-enhanced long short-term memory network, and the predicted value is output. This is used by the hybrid domain adaptive decision network in step 3. The following is a detailed explanation of step 2: 1. Overall Network Structure The temporal feature-enhanced Long Short-Term Memory (LSTM) network consists of four layers, arranged in order of data flow: a multi-scale convolutional preprocessing layer, a two-layer bidirectional LSM encoding layer, a temporal decay gating layer, and an attention output layer. The total number of parameters is approximately 4.2K, and the computational cost per inference is approximately 16.8K multiply-accumulate operations, which can be completed within one control cycle of a typical digital signal processor. The following sections will provide a detailed description of each layer: (1) Multi-scale convolutional preprocessing layer This layer receives the timing pulse width sequence output from step 1. ,in The preprocessing layer contains three parallel convolutional branches, each of which is a one-dimensional convolutional structure with ReLU activation. First branch: Kernel size Number of convolution kernels The step size is 1. This branch captures the pulse width abrupt change features between adjacent cycles, and the output tensor dimension is... .

[0040] Second branch: Kernel size Number of convolution kernels The step size is 1. This branch captures periodic pulse width fluctuation patterns near the carrier frequency, and the output tensor dimension is... .

[0041] Third branch: Kernel size Number of convolution kernels The step size is 1. This branch captures the pulse width trend change on the order of the fundamental frequency period, and the output tensor dimension is... .

[0042] The outputs of the three branches are aligned along the end of the time dimension, the headers of longer tensors are truncated to unify the time steps of each branch to 9, and then concatenated along the feature dimension to obtain a result with dimension . Multiscale feature tensor ,in This process can be formalized as follows: ; in This represents a one-dimensional convolution operation. , , These are the convolution kernel weights for the three branches. , , For bias, This indicates splicing along the feature dimension.

[0043] (2) Two-layer bidirectional long short-term memory coding layer Multiscale feature tensor according to Each time step is sequentially fed into a two-layer bidirectional long short-term memory (LSM) coding layer. This layer consists of two stacked LSM layers, with the hidden state of the first layer serving as the input to the second layer. Each LSM layer contains two branches: forward and backward, processing the sequence in forward and reverse order, respectively. The hidden state of the forward branch... and the hidden state of the back branch By splicing the data at each time step, a bidirectional implicit representation of that layer is obtained.

[0044] The implicit dimension of the first layer of long short-term memory units The second layer of implicit dimensions After two-layer bidirectional encoding, each time step Output dimension is The encoding vectors. The encoding vectors from all time steps form the encoding matrix. .

[0045] The standard gating calculation within a Long Short-Term Memory (LSTM) unit is as follows: ; in For the Sigmoid function, Represents element-wise product. , , These are the forget gate, input gate, and output gate, respectively. Candidate memory units, For memory units, This is a hidden state. and For weights and biases, Enter the current time step.

[0046] (3) Temporal decay gating layer Following the two-layer bidirectional coding layer, this network introduces a temporal decay gating layer, which is one of the key innovations that distinguishes it from standard long short-term memory networks. The design of this layer is based on the following observation: the reference value of the historical values ​​of the pulse width sequence for future values ​​does not decay uniformly. When the modulation ratio changes rapidly or the load changes abruptly, the earlier pulse width history should be quickly forgotten; while in steady-state operation, the more distant history is still of reference value for prediction.

[0047] The timing decay gating layer is for each coding time step Calculate an adaptive attenuation factor This is used to weight and correct the encoded vector. The specific calculation method is as follows: ; in The attenuation scale parameter is a learnable parameter, with an initial value of 1.0; For the first The encoding vector changes along the time direction at each time step. Norm, approximated by the difference between the encoded vectors of adjacent time steps: ; The initial time step difference is set to 0. The decay factor is... The attenuation-corrected coding matrix is ​​obtained by directly applying the corresponding coding vector. : ; ; When the encoding vector changes drastically between adjacent time steps, When the value approaches 0, information at that moment is significantly suppressed, and predictions rely more on periods of gradual change; in steady state... Approaching 1, all historical information is retained with equal weight.

[0048] (4) Attention output layer Attenuation-corrected coding matrix It is fed into the attention output layer for final prediction.

[0049] The attention output layer first will Mapped to query vector Key matrix Sum matrix : ; in , , , , , Take the row vector of the last row of the query matrix as the single query vector. Calculate the attention weights of the dot product between the key matrix and each row vector of the key matrix: ; in Let be the attention weight vector at each time step. The scaling factor is used. The attention weights are summed with the value matrix using a weighted average to obtain the context vector. : ; Context vector Mapped to scalar predictions via a fully connected layer: ; in , This is a scalar bias. This is the final output of step 2, which is then passed to step 3.

[0050] 2. Construction of offline training dataset The training dataset is derived from closed-loop simulations of power electronics models under different operating conditions. The simulation model is a three-phase two-level voltage source inverter with a rated power of 15kW, a switching frequency range of 2kHz to 20kHz, a DC bus voltage range of 200V to 800V, a modulation ratio range of 0.02 to 1.0, and load types covering three mechanical characteristics: constant torque, constant power, and fan / pump.

[0051] The data sampling method is as follows: the duty cycle command value output by the PWM module is recorded in each control cycle and converted into pulse width. Simultaneously, the modulation ratio, load torque, and speed at corresponding moments are recorded. This data is then used to record 1024 consecutive control cycles. A sample segment is formed, with the pulse width values ​​of the first 16 cycles constituting the input sequence, and the pulse width values ​​of the subsequent cycles serving as the prediction target.

[0052] The training set contains 8000 sample segments, covering the complete operating condition space from low modulation ratio to high modulation ratio and from steady state to dynamic mutation. The input sequence dimension for each sample is [dimension missing]. The target for prediction is the true pulse width value of the 17th cycle.

[0053] 3. Offline training process and parameters Training to minimize the predicted value Compared with the true value The mean squared error loss is used as the optimization objective, and two auxiliary loss terms are introduced to enhance the network's response to sudden changes in operating conditions.

[0054] Main loss function for: ; in The batch size is set to 128.

[0055] First auxiliary loss The accuracy of the constrained predicted values ​​in tracking the trend of pulse width changes: ; in , This refers to the difference between the predicted change and the actual change.

[0056] Second auxiliary loss For timing decay gating layer parameters Regular terms: ; in This is the weighting coefficient, set to 0.01.

[0057] The total loss function is the weighted sum of the three: ; Training was performed using the AdamW optimizer with an initial learning rate of [missing information]. Weight decay coefficient Cosine annealing learning rate scheduling is used, with a total of 300 training epochs and a batch size of 128. In each training epoch, the input sequence is subjected to a learning rate with a mean of 0 and a standard deviation of 1. Gaussian noise is used for data augmentation to improve the network's robustness to sampling jitter and measurement noise.

[0058] After training convergence, the root mean square error of the predictions on the reserved 1000 test samples is: The full-scale performance is 1.7%, and the single-step prediction delay is 4.3 microseconds as measured on a digital signal processor, which meets the requirements for real-time control.

[0059] 4. Forward reasoning process During the online inference phase, step 2 performs a forward computation once per control cycle. The input is the timing pulse width sequence output from step 1. The output is the predicted pulse width for the next cycle. The network weights have been trained offline and fixed-point quantized to 16-bit precision, and stored in the program flash memory of the digital signal processor. Forward inference is executed sequentially in a four-layer structure, and the output... Along with step 1 and They are then fed into the hybrid domain adaptive decision network in step 3.

[0060] In step 3, the real-time feature vector, the current pulse width, and the predicted pulse width are concatenated to form a time-domain feature. A frequency-domain feature is constructed from the difference sequence of the predicted pulse width and the current pulse width. The time-domain and frequency-domain features are bidirectionally interacted through a cross-attention fusion module. After the self-calibration gating module dynamically modulates the decision confidence based on the input uncertainty, the dead-zone allocation coefficient and mode flag are output through a dual-head output layer. Specifically: Step 3 takes the real-time feature vector output from Step 1. Current pulse width and the predicted pulse width output in step 2 Dead zone allocation coefficients are generated through a pre-trained hybrid domain adaptive decision network. and pattern flags These are used for dead time allocation calculation in step 4 and mode switching control in step 6, respectively. The following is a detailed explanation of the content involved in step 3: 1. Input The input for step 3 consists of three parts, all of which come from the previous steps: Part 1: Real-time Feature Vectors .

[0061] Part Two: Current Pulse Width .

[0062] Part 3: Predicting Pulse Width .

[0063] Will and Concatenate into a two-dimensional vector , and then with Concatenate to form an extended time-domain feature vector. : ; in, and They are respectively and The result is normalized by dividing by the inverter's rated pulse width reference value, which is taken as half of the inverter's rated switching cycle.

[0064] 2. Overall Network Structure The hybrid domain adaptive decision network consists of the following modules in sequence: a time-domain feature encoding module, a frequency-domain feature generation and encoding module, a cross-attention fusion module, a self-calibrating gating module, and a dual-head output module. The total number of parameters is approximately 6.8K, and the computational cost per inference is approximately 13.6K multiply-accumulate operations, meeting real-time requirements. The following sections will provide a detailed description of each module: (1) Temporal feature coding module This module is a Layer 4 fully connected network used to... High-level temporal representations are extracted from this. The layers are configured as follows: First layer: Input dimension 12, output dimension 32, activation function is ReLU.

[0065] The second layer has an input dimension of 32, an output dimension of 64, and uses ReLU as the activation function.

[0066] The third layer has an input dimension of 64, an output dimension of 64, and uses ReLU as the activation function.

[0067] Fourth layer: Input dimension 64, output dimension 32, no activation function.

[0068] The 32-dimensional vector output from the fourth layer is denoted as... , as a time-domain feature encoding.

[0069] (2) Frequency domain feature generation and coding module Frequency domain branching explicitly extracts frequency features from pulse width variations through difference operations and discrete Fourier transform.

[0070] Maintain a memory of length 10 ... A circular buffer that stores the most recently accessed data. The difference sequence between the predicted pulse width and the actual pulse width for each control cycle. ,in This difference sequence reflects the first-order non-stationary characteristics of the pulse width.

[0071] right Calculation after adding Han Ming window Point-wise real discrete Fourier transform, taking the first side of the amplitude spectrum Each frequency point value is used as the original feature in the frequency domain, denoted as... : ; in This represents the Hamming window coefficient.

[0072] Will The network uses a two-layer fully connected subnetwork. The first layer has an input dimension of 4 and an output dimension of 8, with ReLU activation; the second layer has an input dimension of 8 and an output dimension of 16, with no activation function. The output vector... As a frequency domain feature encoding.

[0073] (3) Cross-attention fusion module This module implements cross-enhancement of time-domain and frequency-domain features. As a query As keys and values, scaled dot product attention is calculated, and vice versa, resulting in a unified hybrid domain representation through bidirectional cross-fusion.

[0074] First of all and Mapped to the same dimension through linear projection layers respectively : ; Calculate the attention weights of the time-domain query on the frequency-domain key. Since both the query vector and the key vector are 16-dimensional, the dot product yields a scalar, which is then normalized using the sigmoid function. : ; The frequency domain value vector is weighted to obtain the time-domain enhanced frequency domain information: ; Similarly, by generating queries using frequency domain features and using time domain features as keys and values, frequency-enhanced time domain information can be obtained: ; Final fused feature vector This is the concatenation of four vectors: ; Where [;] indicates vector concatenation.

[0075] (4) Self-calibration gating module Considering that occasional sensor noise or load fluctuations during inverter operation may lead to a decrease in feature quality, this network is designed with a self-calibrating gating module. This module enables the network to adaptively reduce the confidence of the decision when the feature uncertainty is high, and encodes the confidence as an auxiliary variable to feed back to the subsequent dual-head output.

[0076] Fusion features First, a two-layer fully connected network is used to generate two vectors: one is the intermediate decision vector. The other is a gating signal. : ; in For the Sigmoid function, , , , .

[0077] The final control characteristics are obtained by element-wise modulation of the intermediate decision vector using a gating signal: ; in This is an element-wise product. It is fed into the dual-head output module. (Gated vector) When each element is close to 1, all information is transmitted; when it is close to 0, the information is suppressed, and the output tends to be a conservative safe default value, which is injected by the safe prior during training.

[0078] (5) Dual-head output module The output module is divided into two parallel branches that share the same control features. The dead zone allocation coefficients are generated respectively. and pattern flags .

[0079] First branch (continuous output): will... Mapped to a scalar through a fully connected layer, and then compressed to a scalar value using the sigmoid function. : ; in , This is a scalar bias. This is the dead zone allocation coefficient.

[0080] Second branch (binary classification output): ... The data is mapped to a 2D logits vector via another fully connected layer, and then the probability distribution is obtained through Softmax. ; in , Pattern flag Take the index of the one with the higher probability: ; Indicates standard dead-zone mode, This indicates the dead zone optimization mode, which corresponds to the mode management logic in step 6.

[0081] 3. Construction of offline training dataset The training data for the hybrid domain adaptive decision network is generated through power electronics simulation and is sourced from the same place as the training data in step 2. In the simulation environment, the current feature vector, current pulse width, and future true pulse width are recorded for each control cycle. At the same time, an exhaustive search is performed to obtain the optimal dead zone allocation coefficient and the optimal mode flag under this operating condition as supervision labels.

[0082] optimal Label generation method: in the interval with a step size of 0.05 Inner traversal of candidates For each candidate value, a closed-loop simulation is performed using the dead-zone execution and compensation link composed of steps 4 and 5. The total harmonic distortion of the output voltage and the switching loss of the power devices are measured within one fundamental cycle to construct a comprehensive index. , choose to smallest As a label. To normalize to Switching losses.

[0083] optimal The rule for determining the label: If the search yields... Minimum value corresponding to Less than 0.2, or If the difference between the label and the previous period exceeds 0.5, then... This indicates that you need to switch to optimization mode for quick adjustments; otherwise... Maintain the standard model.

[0084] The training set contains 6000 work condition segments, each segment containing 12-dimensional input features, a frequency domain buffer of the predicted pulse width difference sequence (directly calculated in the simulation), and the corresponding... Tags and Tags. To handle class imbalance, for The samples were resampled twice.

[0085] 4. Training process and loss function The training employs a multi-task loss function, simultaneously optimizing the prediction of continuous allocation coefficients and discrete pattern flags.

[0086] for For prediction, using smoothed L1 loss provides better robustness to outliers: ; in like otherwise .

[0087] for Predictions using weighted cross-entropy loss increase... Class weights are used to emphasize security-related decisions: ; in , .

[0088] The total loss function is the sum of the above two terms: ; The training optimizer is AdamW, and the initial learning rate is... Weight decay Cosine annealing scheduling was used, with a total of 250 rounds and a batch size of 64. Gaussian noise with a standard deviation of 0.01 was applied to the input features during each training round to enhance generalization. After training convergence, the results were applied to the test set. The mean absolute error is less than 0.05. The classification accuracy rate reached 96.3%.

[0089] 5. Forward reasoning process During online operation, step 3 receives the data from step 1 in each control cycle. and and step 2 First, the difference sequence buffer is updated and the frequency domain features are calculated. Then, the forward computation of the network is performed sequentially, and the output is... and The network weights have been fixed-point quantized to 16-bit precision and stored in the program's flash memory. Inference takes approximately 5.1 microseconds.

[0090] It is passed to step 4, where it is determined according to the preset dead time. Calculate the actual allocated dead time for the upper and lower pipes. and . It is passed to step 6 to drive the mode selection logic, which determines whether to use the deep compensation network output from step 5.

[0091] In step 4, when the mode flag indicates standard dead-time mode, the preset total dead-time is symmetrically allocated to the upper and lower bridge arm dead-times; when the mode flag indicates dead-time optimization mode, the preset total dead-time is asymmetrically allocated to the upper and lower bridge arm dead-times according to the dead-time allocation coefficient, and the allocated dead-times are written into the dead-time register of the PWM module. Specifically: Step 4 receives the dead zone allocation coefficients output from Step 3. and pattern flags Combined with the preset total dead time The actual dead time of the upper and lower bridge arms is calculated, and the corresponding PWM dead time insertion instruction is directly generated to realize the dynamic asymmetric allocation of dead time between the first PWM signal and its complementary second PWM signal. The output of this step is the updated PWM module dead time configuration parameter, which directly affects the turn-on and turn-off timing of the switching devices, and provides the currently used dead time value for the deep compensation network in step 5. Step 4 will be explained in detail below: 1. Determining the preset total dead time Total dead time It is a safety time margin set based on the switching characteristics of the inverter power devices, the DC bus voltage level, and the hardware circuit delay. Its value is pre-stored in the system parameter table. The specific calculation basis is as follows: ; in This refers to the turn-off delay time of the power device. The tail current fall time. For the conduction delay time, This includes the propagation delay difference and safety margin in the hardware circuitry. The total dead time ensures that no shoot-through short circuit will occur in the upper and lower bridge arms under any operating condition, therefore regardless of… How to allocate the dead time of the upper management system? With the dead time of the lower tube The sum of them is always equal to That is, asymmetric allocation does not change the total safety interval, but only adjusts the distribution ratio of the safety interval on the two switching transistors.

[0092] 2. Mode flags control the allocation logic Pattern Flag The current strategy for determining dead time allocation: when At this time, the system is running in standard dead-time mode. The output of step 3 is ignored. The value is assigned using a symmetrical distribution method, with the total dead time evenly divided between the upper and lower bridge arms: ; This mode is suitable for systems in a steady state with weak dead zone effects, and can simplify control logic and avoid unnecessary frequent adjustments.

[0093] when At this point, the system enters dead-zone optimization mode, based on the real-time allocation coefficients output in step 3. Perform asymmetric allocation: ; in The allocation coefficients output by the hybrid domain adaptive decision network reflect the allocation of more dead zone margin to the upper arm under the current operating conditions. ) or lower bridge arm ( The degree of optimization. When At that time, it degenerates into a symmetrical distribution.

[0094] 3. Generation of dead-time allocation instructions and configuration of PWM module Directly and The on-time delay times of the upper and lower transistors are written into the PWM dead-time register. The digital PWM module inserts an asymmetric dead time into the complementary PWM signal based on these two values. For a bridge arm, the on-time delay time of the upper transistor corresponds to the delay of the upper transistor's turn-on edge, and the on-time delay time of the lower transistor corresponds to the delay of the lower transistor's turn-on edge. The deep compensation network in subsequent step 5 will learn accurate voltage compensation by combining information such as current polarity, eliminating the need to exchange delay times based on current direction during the dead-time allocation stage, thus avoiding logic redundancy.

[0095] Assume the timer counting frequency of the PWM module is... Convert the dead time into a count value in the dead time register: ; In a PWM module with independent rising edge dead time and falling edge dead time configuration capability, Write to the upper transistor's on-delay register, Write the turn-on delay register of the lower transistor. For PWM modules that only support bilateral symmetrical dead time, asymmetric effects can be indirectly achieved by overloading the comparison value, but this solution prefers PWM units with independent bilateral dead time configuration.

[0096] Finally, step 4 outputs a dead-time allocation instruction, which takes effect in the next PWM cycle, causing the first PWM signal and its complementary second PWM signal to be automatically inserted into the specified asymmetric dead time during each commutation.

[0097] After completing the dead zone allocation in step 4, the actual dead zone will be used. and The state variable is output to step 5 for use by the deep compensation network in calculating the dead-zone voltage compensation. Simultaneously, the mode flag is... and allocation coefficient It is passed to step 6 for mode switching consistency monitoring and smooth transition logic.

[0098] In step 5, based on the equivalent model of dead-zone voltage average value, the basic compensation duty cycle of the physical model is calculated using the difference between the dead time of the upper and lower bridge arms, current polarity, DC bus voltage, and switching cycle. The residual compensation duty cycle is obtained based on the physical guided residual network. The three-phase duty cycle compensation is calculated based on the basic compensation duty cycle and the residual compensation duty cycle of the physical model. The three-phase duty cycle compensation is then superimposed onto the original three-phase duty cycle command output by the current loop controller to obtain the compensated three-phase duty cycle command, specifically: Step 5: After completing the asymmetric dead zone allocation in Step 4, receive the dead zone allocation coefficient. Pattern Marker Real-time feature vectors And the actual dead time from step 4 and The three-phase duty cycle compensation is output through a pre-trained deep compensation network. This is then superimposed on the original duty cycle command generated by the current loop controller. The corrected duty cycle is obtained to compensate for the voltage distortion introduced by the dead zone. Next, step 5 will be explained in detail: 1. Structure of deep compensation networks The overall network architecture consists of four modules: an input feature preprocessing module, a physical model feedforward module, a temporal convolutional residual learning module, and an output fusion module. These will be described in detail below: (1) Input feature preprocessing module The input includes the following: the real-time feature vector from step 1. Allocation coefficients from step 3 and pattern flags And the actual dead time from step 4 and Simultaneously, to incorporate timing information, a sequence of lengths is maintained. A circular buffer stores the data from the most recent 16 control cycles. Sequences, forming a time-series feature matrix .

[0099] Will , , and Normalized and concatenated to form auxiliary feature vectors : ; in , This auxiliary feature conveys the current dead zone allocation state and decision-making pattern, enabling the network to... and The intensity and direction of different adjustment and compensation behaviors.

[0100] (2) Physical model feedforward module This module explicitly calculates a base compensation duty cycle based on the average equivalent model of dead zone voltage. This serves as the physical prior of the network. The basic compensation formula is: ; in For the switching cycle, This is the DC bus voltage. This is the nominal DC voltage reference value. This formula reflects the compensation principle for voltage losses caused by asymmetrical half-cycle distribution due to unbalanced dead-zone assignment. This basic compensation value degenerates to zero in steady-state symmetrical distribution and provides the primary compensation reference in asymmetrical distribution.

[0101] With real-time features and auxiliary features The residual learning module is fed in together, enabling the network to use the physical model output as an anchor point and learn only the nonlinear residuals.

[0102] (3) Temporal Convolutional Residual Learning Module This module outputs a physical model. and time series feature matrix As the primary input, learn to compensate for residuals. The module structure is as follows: The first layer is a one-dimensional convolutional layer with 10 input channels (feature dimension) and 32 output channels. The kernel size is 3, the stride is 1, causal padding is used to maintain the temporal dimension length, and the activation function is GELU. This layer extracts local patterns from the feature sequence along the temporal dimension and outputs a feature matrix. .

[0103] Second layer: One-dimensional convolutional layer, 32 input channels, 32 output channels, kernel size of 3, stride of 1, causal padding, GELU activation function, output... .

[0104] Third layer: Global average pooling layer, which performs pooling along the temporal dimension. Averaging yields the time-series aggregated feature vector. This operation compresses variable historical information into a fixed-length representation and reduces sensitivity to sequence length.

[0105] Will With the current moment (from Extract the last row (dimension 10) and auxiliary features. (Dimension 4) Physical Compensation Value (Dimension 3) Concatenate to form a hybrid feature vector : ; Fourth layer: Fully connected layer, with an input dimension of 49 and an output dimension of 64, and the activation function is ReLU.

[0106] Fifth layer: Fully connected layer, with an input dimension of 64 and an output dimension of 32, and the activation function is ReLU.

[0107] Sixth layer (residual output layer): Fully connected layer, input dimension 32, output dimension 3, no activation function, output residual compensation. .

[0108] (4) Output fusion module The final three-phase duty cycle compensation is obtained by adding the feedforward value of the physical model to the residual learning value: ; This addition operation ensures that when the residual network is uncertain, the output at least degenerates to the result of the physical model. Element limit at Internally, this prevents excessive compensation from causing overmodulation or oscillation.

[0109] 2. Construction of the training dataset The training dataset was generated using a high-precision power electronics simulation model. The simulation covers a wide range of operating conditions: load from 10% to 150% of rated current, power factor from 0.5 lagging to 0.5 leading, switching frequency from 2kHz to 20kHz, DC voltage fluctuation ±15%, ambient temperature from -20°C to 85°C, and asymmetric dead zone distribution factor. Traverse with a step size of 0.05 For each operating point, the system records operating data for 500 consecutive control cycles, performs current closed-loop control within the step size, and collects the deviation between the actual output voltage and the ideal sinusoidal reference voltage.

[0110] Label The generation employs a reverse solution: in each control cycle, the injected duty cycle compensation is iteratively adjusted to minimize the weighted RMS value of the output voltage error in the next cycle. The iteration stops when the error change is less than [a certain value]. The resulting compensation amount is the supervision label. This reverse engineering solution is performed offline and does not require online computation.

[0111] The dataset contains approximately 85,000 samples, each containing a 16-step historical feature sequence. Current auxiliary features Physical model output and three-phase labels The dataset is divided into training, validation, and test sets in a 7:2:1 ratio to ensure that the test set contains unseen combinations of load and frequency to evaluate generalization performance.

[0112] 3. Training process and loss function The training uses a composite loss function to balance compensation accuracy and voltage waveform quality.

[0113] The main loss is the mean square error of the compensation amount: ; Introducing a physical consistency loss to penalize outputs that cause the compensation direction to deviate from the assumed direction of current polarity: ; Introducing a smoothing regularization term to suppress drastic fluctuations in the compensation amount between adjacent control cycles: ; The total loss is the weighted sum of the above three items: ; The training optimizer uses AdamW with an initial learning rate of [missing information]. Weight decay The training employed cosine annealing learning rate scheduling with a batch size of 128 and a total of 300 training epochs. During training, Gaussian noise with a standard deviation of 0.02 was added to the input features, and 10% of the elements in the temporal feature matrix were randomly masked (set to zero) to simulate instantaneous sensor failures or data loss. The model terminated early when the MSE no longer decreased on the validation set.

[0114] After training, the average THD of the compensated output voltage on the test set decreased to 1.2% (approximately 5.8% without compensation), and the magnitude of the residual compensation accounted for approximately 12% to 18% of the physical model output.

[0115] 4. Forward reasoning process During online operation, in each control cycle, step 5 receives data from step 1. From step 3 and From step 4 and First, update the temporal feature buffer and extract... ; Calculate auxiliary features and physical model feedforward Then, perform the forward computation of the temporal convolution and fully connected layers, and output the residual. and Adding them together gives The output, after being clipped, is superimposed onto the original duty cycle instruction. ; The data is written to the PWM compare register and takes effect in the next switching cycle. The network weights and biases are stored in 16-bit fixed-point format, and the inference time is approximately 8.2 microseconds per cycle.

[0116] Corrected duty cycle It directly controls the switching state of the inverter's power devices. Simultaneously, step 5 will output the actual power... The magnitude and rate of change are transmitted as monitoring signals to step 6, so that the mode management module can determine whether the compensation status is normal and whether it is necessary to trigger mode switching or compensation freeze.

[0117] In step 6, the PWM comparison value is calculated based on the compensated three-phase duty cycle instruction. The PWM module delays the on-edge of the original PWM signal according to the dead time in the dead time register, generating six complementary PWM drive signals with asymmetrical dead time. These signals then control the power switching transistors via the drive circuit. Specifically: Step 6 receives the compensated three-phase duty cycle command provided in Step 5. And the dead time allocation instruction output in step 4 (including the upper tube dead time) Dead time of pipe installation and pattern mark The process involves using a digital PWM peripheral to generate a complementary drive signal with asymmetric dead-time characteristics. After being amplified by the drive circuit, this signal directly controls the power switching devices of the three-phase bridge arm. Step 6 will be explained in detail below: 1. Input signal aggregation synchronized with PWM cycle At the beginning of each control cycle, step 6 obtains the updated duty cycle from step 5. Obtain the updated dead-time configuration parameters from step 4. All parameters take effect synchronously at the PWM cycle loading time to ensure that the duty cycle and dead time used within a switching cycle remain consistent.

[0118] The time base of the PWM module is generated by a high-resolution timer, employing an increment / decrement counting mode to generate a center-aligned symmetrical triangular carrier wave. Let the timer counting frequency be... The switching frequency is Then the period register count value is: ; The counter increments from 0 to The value then decreases to 0, constituting a complete switching cycle. .

[0119] 2. Conversion from duty cycle to comparison value For each of the three phases The final duty cycle (Normalization range) The comparison value is converted to the PWM comparator register. : ; This comparison value determines the duty cycle of the original PWM signal without a dead time. During the increment phase, the count value rises from 0 to... If it reaches Then the upper tube changes from on to off; during the countdown phase, the count value changes from... Descending to At this time, the upper transistor changes from off to on. This generates a symmetrical original upper transistor PWM signal, and its complementary lower transistor original PWM signal is inverted.

[0120] 3. Asymmetric dead-time insertion logic Dead-time insertion directly uses the parameter values ​​written to the PWM module's dead-time register in step 4, and is automatically completed by hardware. The PWM dead-time control unit has two sets of independent dead-time parameters preset internally: the upper transistor's turn-on delay time... and the conduction delay time of the lower tube (All have been converted to count values) and When the original upper MOSFET PWM signal changes from low to high, the conduction edge is delayed. During the clock cycle delay, the upper transistor remains off while the lower transistor remains on; when the original lower transistor PWM signal changes from low to high, the conduction edge is delayed. One clock cycle. Execution is performed directly on the shutdown edge without delay. This mechanism achieves asymmetric dead time: final drive signal of upper tube : Delay at the original on-edge of the upper tube It then goes high, and immediately goes low at the original turn-on edge of the lower transistor.

[0121] Final drive signal of the lower tube : Delay at the original lower tube conduction edge It then goes high, and immediately goes low at the original on-edge of the upper transistor.

[0122] When the mode flag is output in step 4 hour, It degenerates into a symmetrical dead zone; when At that time, dead zone allocation follows the optimization coefficient. Dynamic adjustments.

[0123] 4. Generation and synchronous output of three-phase PWM signals The three-phase PWM signals execute the above process independently, but share the same time base to ensure three-phase carrier synchronization. Six drive signals. , , , , , The corresponding I / O pins of the PWM module output simultaneously. The fault signal built into the PWM module can directly block the output at the hardware level to achieve protection.

[0124] 5. Drive circuit interface and power transistor control The six PWM logic signals are converted into drive voltages suitable for the gates of the power switching transistors by an isolation drive circuit, and the signals are amplified and isolated. Finally, the drive signals are applied to the gates of the power switching transistors to control their on and off states, thereby generating a modulated AC voltage at the inverter output.

[0125] 6. Status feedback closed loop Step 6 will determine the actual effective dead time. , and pattern flags The status is confirmed by feedback to steps 4 and 5 via the internal status bus. Simultaneously, step 6 monitors the fault status word of the PWM module and the feedback signal from the switching transistor. When a shoot-through warning or compensation anomaly is detected, hardware protection is immediately triggered via interrupt, and the status anomaly flag is transmitted to the mode management and monitoring unit, achieving a closed-loop process from decision-making to execution and monitoring.

[0126] Through the coordinated work of steps 1 to 6, the inverter completes the entire process from feature extraction, pulse width prediction, dead zone allocation decision, dead zone asymmetric allocation, depth compensation to the final drive signal generation in each control cycle.

[0127] This invention also provides a complementary PWM dead-time dynamic allocation system based on pulse width and dead-time comparison, applied to the aforementioned complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison. The system includes: a current sensor, a voltage sensor, a temperature sensor, a signal conditioning circuit, an analog-to-digital converter, a digital processor, a PWM peripheral unit, a drive circuit, and a three-phase inverter power bridge. Internally, the digital processor is functionally divided into a data acquisition and feature extraction module, a pulse width change trend prediction module, a hybrid domain adaptive decision-making module, a dead-time allocation execution module, a deep compensation network inference module, and a PWM signal generation and control module.

[0128] Current, voltage, and temperature sensors are installed at the inverter output, DC bus side, and power device heatsink, respectively. The outputs of each sensor are connected to the input of the signal conditioning circuit. The output of the signal conditioning circuit is connected to the analog input channel of the analog-to-digital converter (ADC). The digital interface of the ADC is connected to the data bus of the digital processor. The outputs of the data acquisition and feature extraction modules are transmitted to the pulse width variation trend prediction module and the hybrid domain adaptive decision module, respectively. The output of the pulse width variation trend prediction module is connected to the hybrid domain adaptive decision module. The output dead-time allocation coefficient and mode flag of the hybrid domain adaptive decision module are simultaneously transmitted to the dead-time allocation execution module and the deep compensation network inference module. The dead-time allocation execution module generates dead-time parameters and outputs them to the deep compensation network inference module and the PWM signal generation and control module, respectively. The deep compensation network inference module receives the dead-time from the dead-time allocation execution module and the allocation coefficient and mode flag from the hybrid domain adaptive decision module, and outputs the duty cycle compensation amount to the PWM signal generation and control module. The PWM signal generation and control module outputs six complementary PWM logic signals with dead time to the drive circuit. The six outputs of the drive circuit are connected to the gates of the power switching transistors in the upper and lower arms of the three-phase inverter power bridge, respectively. The DC input terminal of the three-phase inverter power bridge is connected to the DC bus, and the AC output terminal is connected to the load or the power grid.

[0129] The current sensor can be a Hall closed-loop current sensor, used to detect the three-phase output current in real time and provide the original current signal corresponding to the current value and current polarity sign obtained in step 1.

[0130] The voltage sensor can be a resistor divider network combined with an isolation operational amplifier or a Hall voltage sensor to detect the DC bus voltage and / or three-phase output voltage, providing voltage information for the feature vector in step 1.

[0131] The temperature sensor can be an NTC thermistor or an integrated temperature sensor chip, which is mounted on the heat dissipation substrate of the power module to obtain the device temperature, corresponding to the temperature variable in the feature vector of step 1.

[0132] The signal conditioning circuit consists of an active filter and a level offset circuit composed of operational amplifiers, used to filter, adjust the amplitude, and match the impedance of the sensor output signal.

[0133] The analog-to-digital conversion unit can use a multi-channel synchronous sampling analog-to-digital converter to convert the conditioned analog signal into a digital quantity, supporting high-precision data acquisition in step 1.

[0134] The digital processor can be a high-performance floating-point digital signal processor or an ARM Cortex-M7 / M4 core microcontroller, integrating a floating-point arithmetic unit and a dedicated neural network accelerator, or it can use an FPGA-embedded soft-core processor combined with a hardware convolution accelerator. This processor carries the following functional modules: The data acquisition and feature extraction module calculates dq-axis current, current polarity, voltage utilization, modulation ratio, temperature, and carrier ratio from the ADC results by executing step 1, thus forming a real-time feature vector.

[0135] The pulse width change trend prediction module, corresponding to step 2, uses the deployed lightweight time series model to predict the future pulse width change trend based on the historical sequence of feature vectors.

[0136] The hybrid domain adaptive decision module, corresponding to step 3, outputs the dead zone allocation coefficient α and the mode flag M based on the time domain stability factor, frequency domain harmonic distortion factor and pulse width prediction trend, using preset rules or fuzzy decision logic.

[0137] The dead-time allocation execution module, corresponding to step 4, calculates the dead time of the upper and lower bridge arms based on α, M and the total dead time, generates dead-time allocation instructions and configures the PWM dead-time register.

[0138] The deep compensation network inference module, corresponding to step 5, stores the trained physical guidance residual network weights, performs forward inference in real time, outputs the duty cycle compensation amount ΔD, and superimposes it with the original duty cycle instruction.

[0139] The PWM signal generation and control module, corresponding to step 6, generates six complementary PWM signals through the PWM peripheral unit based on the final duty cycle and dead time parameters. The PWM peripheral unit is a high-resolution PWM timer module within the digital processor, supporting dual-sided independent dead-time insertion to generate complementary PWM logic signals with dead time. The drive circuit can use an isolated gate driver chip to convert the low-voltage PWM logic signal into a gate drive voltage with sufficient drive capability and safe isolation. The three-phase inverter power bridge consists of six power switches and anti-parallel freewheeling diodes, acting as actuators to convert DC power into AC power output.

[0140] The components of the system work together, enabling the digital processor to sequentially complete feature extraction, trend prediction, dead zone decision-making, dead zone asymmetric allocation, depth compensation calculation, and PWM signal generation in each control cycle. Finally, it achieves inverter control with adaptive dead zone compensation through the drive circuit and inverter bridge.

[0141] To verify the practical effectiveness of the technical solution of this invention, tests were conducted on a three-phase two-level voltage source inverter experimental platform with a rated power of 15kW. This inverter uses IGBT power modules, a DC bus voltage of 400V, a switching frequency of 10kHz, and a preset dead time of 2μs. The control processor is a TI TMS320F28379D, which integrates a CLA coprocessor and a TMU acceleration unit for running the real-time inference of the six steps of this invention. The load is a permanent magnet synchronous motor, and different load torques are applied via a dynamometer.

[0142] The technical effects of the present invention are illustrated below through three examples: comparative experiment, working condition traversal experiment, and time series prediction accuracy test.

[0143] Example 1: Comparison of compensation effects with traditional methods This embodiment compares the steady-state performance of three schemes under rated speed and 50% rated load conditions: Scheme A is a traditional symmetrical dead zone combined with fixed compensation (based on the average voltage model), Scheme B is an asymmetrical dead zone + fixed compensation, and Scheme C is the method of this invention (asymmetrical dead zone + physically guided residual network adaptive compensation). The total harmonic distortion (THD) of the output current and the switching losses of the power devices are measured over one fundamental cycle.

[0144] Table 1 Comparison of the compensation effects of the three schemes

[0145] Switching losses are calculated by measuring the switching transient energy and switching frequency of the IGBT.

[0146] As shown in Table 1, the current THD of the method of this invention is reduced to 1.3%, which is 72.9% lower than that of scheme A and 66.7% lower than that of scheme B; the switching loss is reduced by 19.4% compared to scheme A and by 8.7% compared to scheme B. The adaptive allocation coefficient is dynamically adjusted according to the operating conditions, taking into account both waveform quality and loss. This invention also provides a bar chart comparing THD and switching loss, as shown in the figure. Figure 2 As shown.

[0147] Example 2: Verification of Adaptive Allocation Coefficients under Different Load Conditions To further demonstrate the adaptability of this invention under different loads, the motor load was varied from 20% to 120% of the rated torque under the conditions of a switching frequency of 10kHz and a dead time of 2μs. The dead time distribution coefficient α output in step S3 and the residual compensation duty cycle amplitude output in step S5 were recorded online. The output voltage THD was measured simultaneously.

[0148] Table 2 Key parameters under different load rates

[0149] pu is the duty cycle per unit value, with a base value of 1.0.

[0150] As shown in Table 2, under light load, α is biased towards 0.65, with more dead time allocated to the upper bridge arm to reduce voltage drop during the freewheeling phase of the lower bridge arm; under heavy load, α is biased towards 0.35, allocating more dead time to the lower bridge arm to ensure reliable turn-off of the upper bridge arm. The residual compensation amplitude increases with increasing load, and the duty cycle of the physical model's basic compensation increases synchronously. The residual proportion remains consistently around 12%~18%, demonstrating the rationality of the physically guided residual network design. This invention also provides biaxial plots of α and THD as a function of load rate, as shown in the figure below. Figure 3 As shown.

[0151] Example 3: Accuracy Verification of Temporal Pulse Width Prediction Network Step 2 of this invention employs a timing-enhanced LSTM network to predict the pulse width. To verify its prediction accuracy, the waveforms of the actual pulse width and the predicted pulse width were recorded during the dynamic process of sudden load application / removal of the inverter, and the prediction error was calculated. Test conditions: switching frequency 10kHz, load torque suddenly increasing from 30% to 80%, and data sampled for 1000 control cycles.

[0152] Table 3. Statistics of Prediction Errors for Dynamic Processes

[0153] The pulse width has a full-scale range of 1 μs (approximately 1% of the 100 μs switching cycle; for simplicity, this is represented by a timer count value, with a full-scale range of 1000 ns). The RMSE is only 15.2 ns, accounting for 1.52% of the full-scale range, which matches the 1.7% target in the invention description, proving that the network can accurately predict pulse width changes under dynamic conditions. This invention also provides a locally magnified waveform comparison between the actual pulse width and the predicted pulse width, as shown below. Figure 4 As shown.

[0154] Embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0155] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0156] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0157] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0158] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison, characterized in that, include: Step 1: Acquire real-time parameters in each control cycle, preprocess them, construct a real-time feature vector, and construct a time-series pulse width sequence from the pulse widths of the most recent N control cycles. Step 2: Input the temporal pulse width sequence into the pre-trained temporal feature-enhanced long short-term memory network, and output the predicted pulse width for the next control cycle; Step 3: Concatenate the real-time feature vector, the current pulse width, and the predicted pulse width to form a time-domain feature. Construct a frequency-domain feature of the difference sequence between the predicted pulse width and the current pulse width. The time-domain feature and the frequency-domain feature are bidirectionally interacted through the cross-attention fusion module. After the self-calibration gating module dynamically modulates the decision confidence based on the input uncertainty, the dead zone allocation coefficient and mode flag are output through the dual-head output layer respectively. Step 4: When the mode flag indicates the standard dead zone mode, the preset total dead zone time is symmetrically allocated to the upper arm dead zone time and the lower arm dead zone time. When the mode flag indicates dead-time optimization mode, the preset total dead time is asymmetrically allocated into upper arm dead time and lower arm dead time according to the dead-time allocation coefficient, and the allocated dead time is written into the dead-time register of the PWM module. Step 5: Based on the equivalent model of dead zone voltage average value, calculate the basic compensation duty cycle of the physical model using the difference between the dead time of the upper and lower bridge arms, current polarity, DC bus voltage and switching cycle. Obtain the residual compensation duty cycle based on the physical guided residual network. Calculate the three-phase duty cycle compensation amount based on the basic compensation duty cycle and residual compensation duty cycle of the physical model. Then, superimpose the three-phase duty cycle compensation amount onto the original three-phase duty cycle command output by the current loop controller to obtain the compensated three-phase duty cycle command. Step 6: Calculate the PWM comparison value based on the compensated three-phase duty cycle instruction, use the PWM module to delay the conduction edge of the original PWM signal according to the dead time in the dead time register, generate six complementary PWM drive signals with asymmetric dead time, and control the power switching transistor after passing through the drive circuit.

2. The complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison according to claim 1, characterized in that, In step 1, the real-time parameters include the current pulse width, preset total dead time, instantaneous value and polarity of the three-phase current, DC bus voltage, current switching frequency, power device temperature, and current modulation ratio.

3. The complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison according to claim 2, characterized in that, In step 2, the temporal feature-enhanced long short-term memory network extracts local time-frequency features of the pulse width sequence through a multi-scale convolutional preprocessing layer, extracts the temporal dependencies of the sequence through a two-layer bidirectional long short-term memory encoding layer, adaptively adjusts the degree of information retention at each time step according to the rate of change of the encoding vector along the time direction through a temporal decay gating layer, and performs weighted summation of the encoding vectors at each time step through an attention output layer to output the predicted pulse width of the next control cycle.

4. The complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison according to claim 3, characterized in that, The multi-scale convolutional preprocessing layer includes three parallel convolutional branches with kernel sizes of 2, 4, and 8, respectively. Each branch has 8 kernels and a stride of 1. The outputs of the three branches are aligned along the end of the time dimension and then concatenated in the feature dimension to form local time-frequency features.

5. The complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison according to claim 4, characterized in that, The temporal decay gating layer calculates an adaptive decay factor for each coding time step, specifically as follows: The rate of change of the coding vector along the time direction is quantified by the L2 norm of the difference between the coding vectors of adjacent time steps. The rate of change is then mapped to an adaptive decay factor through an exponential function with a learnable decay scale parameter, and the decay factor of the first time step is fixed at 1. The adaptive decay factor is multiplied by the coding vector of the corresponding time step to obtain the decay-corrected coding matrix.

6. The complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison according to claim 5, characterized in that, In step 3, the frequency domain features of the difference sequence between the predicted pulse width and the current pulse width are constructed, specifically as follows: Maintain a circular buffer of length K to store the difference between the predicted pulse width and the current pulse width in the most recent K control cycles. Window the sequence of the difference values ​​and calculate the K-point discrete Fourier transform. Encode the one-sided amplitude spectrum to obtain the frequency domain features.

7. The complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison according to claim 6, characterized in that, In step 3, the time-domain features and frequency-domain features are bidirectionally interacted through the cross-attention fusion module, specifically as follows: Using time-domain and frequency-domain features as queries, and another domain feature as key and value, attention weights are generated by scaling the dot product and then passing it through the Sigmoid function. The value vector is then weighted using these attention weights to obtain enhanced time-domain and frequency-domain features. The original time-domain features, original frequency-domain features, enhanced time-domain features, and enhanced frequency-domain features are then concatenated to obtain a fused feature vector.

8. The complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison according to claim 7, characterized in that, In step 5, the physical-guided residual network includes a temporal convolutional residual learning module. The temporal convolutional residual learning module extracts local patterns from the temporal feature matrix through two layers of causal-filled one-dimensional convolutional layers. After being compressed into a temporal aggregated feature vector by a global average pooling layer, it is concatenated with the current real-time feature vector, auxiliary feature vector, and physical model basic compensation duty cycle. The residual compensation duty cycle is then output through a multi-layer fully connected network.

9. A complementary PWM dead-time dynamic allocation system based on pulse width and dead-time comparison, applied to the complementary PWM dead-time dynamic allocation method based on pulse width and dead-time comparison as described in any one of claims 1-8, characterized in that, include: Current sensor, voltage sensor, temperature sensor, signal conditioning circuit, analog-to-digital converter, digital processor, PWM peripheral unit, drive circuit and three-phase inverter power bridge; The digital processor is internally equipped with a data acquisition and feature extraction module, a pulse width change trend prediction module, a hybrid domain adaptive decision-making module, a dead zone allocation execution module, a deep compensation network inference module, and a PWM signal generation and control module. The current sensor, voltage sensor, and temperature sensor are connected to the digital processor via a signal conditioning circuit and an analog-to-digital converter. The digital processor outputs six complementary PWM logic signals to the drive circuit via a PWM peripheral unit. The drive circuit is connected to the gate of each power switch in the three-phase inverter power bridge.

Images