A drive circuit and power converter

Abstract

The application discloses a driving circuit and a power converter. The driving circuit comprises a driving chip, a first common-mode inductor and a second common-mode inductor. The first end of the first common-mode inductor is connected to the first end of the driving chip, the second end of the first common-mode inductor is connected to the gate of a first switch tube, the third end of the first common-mode inductor is connected to the second end of the driving chip, and the fourth end of the first common-mode inductor is connected to the Kelvin source of the first switch tube. The first end of the first common-mode inductor and the third end of the first common-mode inductor are the same end. The second common-mode inductor is located between the driving chip and a second switch tube, and the connection relationship of the second common-mode inductor is similar to that of the first common-mode inductor. The drain of the first switch tube is connected to the drain of the second switch tube, and the source of the first switch tube is connected to the source of the second switch tube. The scheme can inhibit the gate-source voltage bias of the parallel switch tube, prolong the service life of the switch tube, and improve the safety of the driving circuit.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a drive circuit and a power converter. Background Technology

[0002] To increase power capacity, power electronic systems typically employ power converters that include multiple parallel-connected switching transistors. These power converters are widely used in electric drive and charging systems for new energy vehicles, data center power supplies, photovoltaic and energy storage inverters, and industrial high-frequency converter equipment. Multiple parallel-connected switching transistors operate simultaneously, effectively functioning as a single, high-power switching transistor.

[0003] However, when the source currents of parallel switches are inconsistent, or when there are differences in the parasitic inductance of their sources, the parasitic inductance voltage drops at the sources of each parallel switch will be unequal. This will cause circulating currents between the parallel switches, resulting in gate-source voltage bias. Gate-source voltage bias may lead to a mismatch in the switching speeds of the switches, accelerate the aging of the switches, and affect the safety and reliability of the drive circuit. Summary of the Invention

[0004] In view of this, this application provides a drive circuit and a power converter that can suppress the gate-source voltage bias of parallel switching transistors, extend the life of the switching transistors, and improve the safety of the drive circuit.

[0005] To solve the above problems, the technical solution provided in this application is as follows: In a first aspect of this application, a driving circuit is provided, including a driving chip, a first common-mode inductor, and a second common-mode inductor; The first terminal of the first common-mode inductor is connected to the first terminal of the driver chip, the second terminal of the first common-mode inductor is used to connect to the gate of the first switching transistor, the third terminal of the first common-mode inductor is connected to the second terminal of the driver chip, and the fourth terminal of the first common-mode inductor is used to connect to the Kelvin source of the first switching transistor; the first terminal and the third terminal of the first common-mode inductor are terminals with the same name. The first terminal of the second common-mode inductor is connected to the first terminal of the driver chip, the second terminal of the second common-mode inductor is used to connect to the gate of the second switch, the third terminal of the second common-mode inductor is connected to the second terminal of the driver chip, and the fourth terminal of the second common-mode inductor is used to connect to the Kelvin source of the second switch; the first terminal and the third terminal of the second common-mode inductor are terminals with the same name. The drain of the first switching transistor is connected to the drain of the second switching transistor, and the source of the first switching transistor is connected to the source of the second switching transistor.

[0006] In one possible implementation, the driving circuit further includes: a first source resistor and a second source resistor; The first source resistor is located between the Kelvin source of the first switching transistor and the driver chip; the second source resistor is located between the Kelvin source of the second switching transistor and the driver chip.

[0007] In one possible implementation, the driving circuit further includes: a first gate resistor and a second gate resistor; The first gate resistor is located between the gate of the first switch and the driver chip; the second gate resistor is located between the gate of the second switch and the driver chip.

[0008] In one possible implementation, the first common-mode inductor and the second common-mode inductor have the same number of winding turns in the drive circuit.

[0009] In one possible implementation, the core material of the first common-mode inductor and the second common-mode inductor in the driving circuit is ferrite.

[0010] In one possible implementation, the drive circuit further includes a controller; The controller is used to control the output of differential drive voltage at the first terminal and the second terminal of the driver chip.

[0011] In a second aspect of this application, a power converter is provided, including any of the above-mentioned drive circuits, and further including at least one half-bridge arm, wherein the half-bridge arm includes: a first switching transistor and a second switching transistor; The drain of the first switching transistor serves as the first end of the half-bridge arm, and the source of the first switching transistor serves as the second end of the half-bridge arm.

[0012] In one possible implementation, the power converter includes two half-bridge arms, which are an upper bridge arm and a lower bridge arm, respectively. The first end of the upper bridge arm is used to connect to the positive terminal of the DC source, the second end of the upper bridge arm is connected to the first end of the lower bridge arm, and the second end of the lower bridge arm is used to connect to the negative terminal of the DC source; the switching transistors of the upper bridge arm and the lower bridge arm are not turned on at the same time.

[0013] In one possible implementation, the power converter includes a half-bridge arm; The first end of the half-bridge arm is used to connect to the positive terminal of the DC source, and the second end of the half-bridge arm is used to connect to the load.

[0014] In one possible implementation, the power converter includes a half-bridge arm; The first end of the half-bridge arm is used to connect to the load, and the second end of the half-bridge arm is used to ground. The driving circuit provided in this application includes a first common-mode inductor and a second common-mode inductor. The common-mode inductor enables the source voltage drift caused by the source parasitic inductance to be synchronously coupled to the gate when the switch is turned on or off, so that the gate voltage of the switch follows the change in the source voltage, thereby keeping the gate-source voltage of the switch constant, suppressing gate-source voltage bias, and keeping the drive current flowing through the parallel switches consistent. Current balance among the parallel switches extends the lifespan of the switches and improves the safety of the driving circuit. This driving circuit achieves gate-source voltage bias suppression only through passive components, without the need for additional control logic, resulting in a simple structure, low cost, and high scalability. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a driving circuit in related technologies; Figure 2 A schematic diagram of a first type of driving circuit provided in an embodiment of this application; Figure 3 A schematic diagram of a second driving circuit provided in an embodiment of this application; Figure 4 A schematic diagram of a third driving circuit provided in an embodiment of this application; Figure 5 A schematic diagram of a fourth driving circuit provided in an embodiment of this application; Figure 6 A schematic diagram of the fifth driving circuit provided in the embodiments of this application; Figure 7 A schematic diagram of a sixth driving circuit provided in an embodiment of this application; Figure 8 A schematic diagram of a first type of power converter provided in an embodiment of this application; Figure 9 This is a schematic diagram of a second type of power converter provided in an embodiment of this application; Figure 10 This is a schematic diagram of a third type of power converter provided in an embodiment of this application. Detailed Implementation

[0016] See Figure 1 The figure is a schematic diagram of a driving circuit in the related technology.

[0017] Figure 1In this circuit, the driving circuit is used to drive the first switch Q1 and the second switch Q2 connected in parallel. The parameters of the first switch Q1 and the second switch Q2 are the same. The drain of the first switch Q1 is connected to the drain of the second switch Q2, and the source of the first switch Q1 is connected to the source of the second switch Q2 through the source parasitic inductance Ls1 and the source parasitic inductance Ls2 of the second switch Q2.

[0018] The first terminal of the driver chip 100 is connected to the gate of the first switch Q1 and the gate of the second switch Q2. The second terminal of the driver chip 100 is connected to the Kelvin source of the first switch Q1 through the Kelvin source parasitic impedance Zks1 of the first switch Q1. The second terminal of the driver chip 100 is connected to the Kelvin source of the second switch Q2 through the Kelvin source parasitic impedance Zks2 of the second switch Q2.

[0019] When the source current of the first switch Q1 is inconsistent with the source current of the second switch Q2, or when there is a difference between the source parasitic inductance Ls1 of the first switch Q1 and the source parasitic inductance Ls2 of the second switch Q2, the first source voltage drop V across the source parasitic inductance Ls1 of the first switch Q1 will occur. Ls1 The second source voltage V across the source parasitic inductance Ls2 of the second switch Q2 Ls2 The unequal values ​​result in a circulating current between the first switch Q1 and the second switch Q2.

[0020] With the first source voltage drop V Ls1 Lower than the second source voltage drop V Ls2 For example, Figure 1 The dashed arrow in the diagram indicates the direction of the circulating current. This circulating current generates the first Kelvin source voltage drop V across the Kelvin source parasitic impedance Zks1 of the first switching transistor Q1. KS1 A second Kelvin source voltage drop V is generated across the Kelvin source parasitic impedance Zks2 of the second switch Q2. KS2 First Kelvin source voltage drop V KS1 With the second Kelvin source voltage drop V KS2 The directions are opposite, which causes a difference between the source voltage of the first switch Q1 and the source voltage of the second switch Q2, that is, the gate-source voltage V of the first switch Q1. GS1 The gate-source voltage V of the second switch Q2 GS2 Inconsistent.

[0021] Inconsistent gate-source voltages lead to an imbalance in the dynamic current when the first switch Q1 and the second switch Q2 are turned on or off. This prevents the first and second switches Q1 and Q2 from turning on and off simultaneously, increasing switching losses and causing stress concentration on some switches. This can result in localized overheating in the drive circuit, current oscillations in the parasitic inductance of the switches, and even damage to the switches. These defects are particularly pronounced in wide-bandgap semiconductor devices, such as silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and gallium nitride (GaN) high-electron-mobility transistors (HEMTs), which have high switching frequencies and high current change rates.

[0022] It is understandable that the shortcomings of the above solutions are the result of the applicant's practical experience and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of this application below should be considered contributions made by the applicant to the embodiments of this application.

[0023] To address the above deficiencies, embodiments of this application provide a drive circuit and a power converter that introduce a common-mode inductor to suppress the gate-source voltage bias of the parallel switching transistors, thereby extending the lifespan of the switching transistors and improving the safety of the drive circuit.

[0024] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] See Figure 2 The figure is a schematic diagram of the first type of driving circuit provided in the embodiment of this application.

[0026] Figure 2 The driving circuit provided in the embodiment includes a driving chip 100, a first common-mode inductor CMC1, and a second common-mode inductor CMC2.

[0027] The first terminal of the first common-mode inductor CMC1 is connected to the first terminal of the driver chip 100. The second terminal of the first common-mode inductor CMC1 is connected to the gate of the first switch Q1. The third terminal of the first common-mode inductor CMC1 is connected to the second terminal of the driver chip 100. The fourth terminal of the first common-mode inductor CMC1 is connected to the Kelvin source of the first switch Q1. The first and third terminals of the first common-mode inductor CMC1 are of the same name. The first common-mode inductor CMC1 is used to suppress the gate-source voltage bias of the first switch Q1.

[0028] The first terminal of the second common-mode inductor CMC2 is connected to the first terminal of the driver chip 100. The second terminal of the second common-mode inductor CMC2 is connected to the gate of the second switch Q2. The third terminal of the second common-mode inductor CMC2 is connected to the second terminal of the driver chip 100. The fourth terminal of the second common-mode inductor CMC2 is connected to the Kelvin source of the second switch Q2. The first terminal and the third terminal of the second common-mode inductor CMC2 are of the same name. The second common-mode inductor CMC2 is used to suppress the gate-source voltage bias of the second switch Q2.

[0029] In this configuration, the drain of the first switching transistor Q1 is connected to the drain of the second switching transistor Q2, and the source of the first switching transistor Q1 is connected to the source of the second switching transistor Q2.

[0030] To facilitate understanding, the working principle of the first common-mode inductor CMC1 will be used as an example below. The first common-mode inductor CMC1 includes a first winding LC1 and a second winding LC2. The two ends of the first winding LC1 are the first and second ends of the first common-mode inductor CMC1, respectively, and the two ends of the second winding LC2 are the third and fourth ends of the first common-mode inductor CMC1, respectively.

[0031] When the first switch Q1 and the second switch Q2 are turned on or off, if a voltage drift occurs at the source of the first switch Q1, a common-mode voltage change will be formed in the source circuit of the first switch Q1. Since the first common-mode inductor CMC1 exhibits high impedance characteristics to common-mode signals, the first winding LC1 and the second winding LC2 of the first common-mode inductor CMC1 generate synchronous common-mode voltage changes under magnetic coupling. This causes the gate voltage of the first switch Q1 and the source voltage of the first switch Q1 to change approximately the same at the same time. That is, the difference between the gate voltage and the source voltage of the first switch Q1 remains unchanged, thereby suppressing the gate-source voltage bias of the first switch Q1.

[0032] The working principle of the second common-mode inductor CMC2 is the same as that of the first common-mode inductor CMC1, and will not be repeated here.

[0033] This application does not specifically limit the inductance values ​​of the first common-mode inductor CMC1 and the second common-mode inductor CMC2. To better suppress the gate-source voltage bias, the first common-mode inductor CMC1 and the second common-mode inductor CMC2 should have relatively large inductance values ​​to bear most of the voltage bias caused by the source parasitic inductance. For example, the inductance values ​​of the first common-mode inductor CMC1 and the second common-mode inductor CMC2 can be 1uH.

[0034] This application does not specifically limit the types of the first switching transistor Q1 and the second switching transistor Q2. Both the first switching transistor Q1 and the second switching transistor Q2 can be fully controllable switching transistors, meaning they can control both the switching transistor's on and off states. For example, they can include insulated gate bipolar transistors (IGBTs), MOSFETs, or gate turn-off thyristors (GTOs). In this embodiment, MOSFETs are used as an example of the first switching transistor Q1 and the second switching transistor Q2.

[0035] The driving circuit provided in this application embodiment can also be used to achieve the effect of current sharing between two or more switching transistors. The common-mode inductor in the driving circuit can be matched one-to-one with the switching transistor.

[0036] The driving circuit provided in this application includes a first common-mode inductor and a second common-mode inductor. The common-mode inductor enables the source voltage drift caused by the source parasitic inductance to be synchronously coupled to the gate when the switch is turned on or off, allowing the gate voltage of the switch to follow the changes in the source voltage. This keeps the gate-source voltage of the switch constant, suppresses gate-source voltage bias, and maintains consistent drive current flowing through the parallel switches. Current balancing among the parallel switches extends the switch lifespan and improves the safety of the driving circuit. This driving circuit achieves gate-source voltage bias suppression using only passive components, eliminating the need for additional control logic. It has a simple structure, low cost, and high scalability.

[0037] In one possible implementation, the driving circuit provided in this application embodiment further includes a first source resistor and a second source resistor.

[0038] See Figure 3 The figure is a schematic diagram of a second type of driving circuit provided in an embodiment of this application.

[0039] The first source resistor Rs1 is located between the Kelvin source of the first switch Q1 and the driver chip 100. The first source resistor Rs1 is used to suppress the source voltage fluctuation of the first switch Q1.

[0040] The second source resistor Rs2 is located between the Kelvin source of the second switch Q2 and the driver chip 100. The second source resistor Rs2 is used to suppress the source voltage fluctuation of the second switch Q2.

[0041] This application does not specifically limit the connection positions of the first source resistor Rs1 and the second source resistor Rs2. The first source resistor Rs1 can be located in the source circuit of the first switching transistor Q1. For example, the first source resistor Rs1 can be located between the Kelvin source of the first switching transistor Q1 and the second terminal of the first common-mode inductor CMC1, or it can be located between the first terminal of the first common-mode inductor CMC1 and the driver chip 100. The second source resistor Rs2 can be located in the source circuit of the second switching transistor Q2. For example, the second source resistor Rs2 can be located between the Kelvin source of the second switching transistor Q2 and the second terminal of the second common-mode inductor CMC2, or it can be located between the first terminal of the second common-mode inductor CMC2 and the driver chip 100.

[0042] Figure 3 The example uses a first source resistor Rs1 located between the Kelvin source of the first switch Q1 and the second terminal of the first common-mode inductor CMC1, and a second source resistor Rs2 located between the Kelvin source of the second switch Q2 and the second terminal of the second common-mode inductor CMC2.

[0043] Taking the first source resistor Rs1 as an example, since the parasitic inductance and parasitic capacitance in the source circuit of the first switching transistor Q1 form an LC resonant circuit, the presence of circulating current will cause ringing in the LC resonant circuit, resulting in fluctuations in the gate-source voltage of the first switching transistor Q1. Introducing the first source resistor Rs1 into the source circuit of the first switching transistor Q1 can limit the rate of change of current in the source circuit, reduce LC resonance, and thus suppress the fluctuations in the source voltage of the first switching transistor Q1.

[0044] The principle of the second source resistor Rs2 is the same as that of the first source resistor Rs1, and will not be repeated here.

[0045] The driving circuit provided in this application embodiment further includes a first source resistor and a second source resistor. The source resistor can limit the current change in the source circuit of the switching transistor and weaken the high-frequency resonance effect formed between the source circuit and the parasitic capacitance, thereby suppressing source voltage ringing and spike fluctuations, and further ensuring the stability of the gate-source voltage of the switching transistor.

[0046] In one possible implementation, the driving circuit provided in this application embodiment further includes: a first gate resistor and a second gate resistor.

[0047] See Figure 4 This figure is a schematic diagram of the third type of driving circuit provided in the embodiments of this application.

[0048] Figure 4In the driving circuit provided in the embodiment, the first gate resistor Rg1 is located between the gate of the first switch Q1 and the driving chip 100; the second gate resistor Rg2 is located between the gate of the second switch Q2 and the driving chip 100.

[0049] The first gate resistor Rg1 is used to limit the gate current flowing through the first switch Q1. By limiting the rate of change of the gate current, it suppresses the gate voltage oscillation of the first switch Q1 and improves the operational stability of the first switch Q1. The second gate resistor Rg2 has a similar effect to the first gate resistor Rg1.

[0050] The driving circuit provided in this application embodiment further includes a first gate resistor and a second gate resistor. The gate resistor can limit the gate current of the switching transistor, thereby suppressing gate voltage oscillation and improving the stability and anti-interference capability of the gate driving signal.

[0051] In one possible implementation, the driving circuit provided in this application embodiment has the same number of turns in the windings of the first common-mode inductor CMC1 and the second common-mode inductor CMC2. This scheme ensures that the suppression capability of the first common-mode inductor CMC1 on the gate-source voltage bias of the first switch Q1 is consistent with the suppression capability of the second common-mode inductor CMC2 on the gate-source voltage bias of the second switch Q2, making the common-mode synchronization modulation effect of the gate-source voltage between the first switch Q1 and the second switch Q2 symmetrical, and improving the stability and consistency of the driving circuit.

[0052] In one possible implementation, the core material of the first common-mode inductor CMC1 and the second common-mode inductor CMC2 in the driving circuit provided in this application embodiment is ferrite. Because ferrite has high permeability, it enables the first common-mode inductor CMC1 and the second common-mode inductor CMC2 to maintain high common-mode impedance and low power loss even under high-frequency operation of the first switch Q1 and the second switch Q2. This solution can effectively suppress high-frequency common-mode voltage disturbances caused by source parasitic inductance without significantly affecting the gate drive speed, thereby improving the anti-interference capability and electromagnetic compatibility of the driving circuit.

[0053] The driving circuits provided in the above embodiments exhibit excellent dynamic response under high-frequency switching (e.g., above 100 kHz) and high di / dt (e.g., above 2.5 kA / μs) conditions, effectively suppressing the uneven current distribution of the switching transistors caused by source inductive coupling. This driving circuit structure can reduce the current sharing deviation during the turn-on / turn-off of parallel switching transistors to less than 1 / 5 of that in related technologies, and reduce the dynamic current distribution unevenness of parallel switching transistors by more than 60%.

[0054] One possible implementation of the driving circuit provided in this application embodiment further includes: a controller.

[0055] See Figure 5 This figure is a schematic diagram of the fourth driving circuit provided in the embodiments of this application.

[0056] Compared to Figure 2 Example, Figure 5 The driving circuit provided in the embodiment also includes a controller 200, which is used to control the output of differential driving voltage at the first terminal and the second terminal of the driving chip 100.

[0057] Continuing with the example of the first common-mode inductor CMC1, for the differential-mode current brought about by the differential drive voltage, since the current directions on the first winding LC1 and the second winding LC2 of the first common-mode inductor CMC1 are opposite, the magnetic flux generated on the first winding LC1 and the second winding LC2 of the first common-mode inductor CMC1 cancels each other out, and the equivalent inductive reactance of the first common-mode inductor CMC1 approaches zero. Therefore, the first common-mode inductor CMC1 does not suppress the differential drive voltage, ensuring the normal driving of the first switch Q1 by the driver chip 100. Similarly, the second common-mode inductor CMC2 will not affect the normal driving of the second switch Q2 by the driver chip 100.

[0058] See Figure 6 This figure is a schematic diagram of the fifth driving circuit provided in the embodiments of this application.

[0059] Compared to Figure 3 Example, Figure 6 The driving circuit provided in the embodiment also includes a controller 200.

[0060] See Figure 7 This figure is a schematic diagram of the sixth driving circuit provided in the embodiments of this application.

[0061] Compared to Figure 4 Example, Figure 7 The driving circuit provided in the embodiment also includes a controller 200.

[0062] Figure 6 Examples and Figure 7 In the embodiments, the control logic of controller 200 is all consistent with... Figure 5 The same applies to the embodiments, and will not be repeated here.

[0063] The driving circuit provided in this application embodiment includes a controller that enables the driving chip to provide a differential driving voltage to the switching transistor. Since the common-mode inductor only has a high impedance suppression effect on common-mode voltage disturbances and does not show a significant suppression effect on differential driving voltage, this driving circuit can effectively suppress gate-source voltage bias while ensuring the normal driving capability of the driving chip for the switching transistor.

[0064] Based on the driving circuits provided in the above embodiments, this application also provides a power converter. The power converter provided in this application includes any of the driving circuits provided in the above embodiments; it also includes at least one half-bridge arm, the half-bridge arm comprising: a first switch Q1 and a second switch Q2. The drain of the first switch Q1 serves as the first end of the half-bridge arm, and the source of the first switch Q1 serves as the second end of the half-bridge arm.

[0065] The power converter provided in this application includes a first common-mode inductor and a second common-mode inductor in its drive circuit. The common-mode inductor enables the source voltage drift caused by the source parasitic inductance to be synchronously coupled to the gate when the switching transistor is turned on or off. This allows the gate voltage of the switching transistor to follow the changes in the source voltage, thereby keeping the gate-source voltage of the switching transistor constant, suppressing gate-source voltage bias, and ensuring consistent drive current flowing through the parallel switching transistors. Current balancing among the parallel switching transistors extends the lifespan of the switching transistors and improves the safety of the power converter.

[0066] One possible implementation is that the power converter provided in this application includes two half-bridge arms.

[0067] See Figure 8 The figure is a schematic diagram of the first power converter provided in the embodiment of this application.

[0068] Figure 8 In the power converter provided in the embodiment, the two half-bridge arms are the upper bridge arm H1 and the lower bridge arm L1, respectively.

[0069] The first end of the upper bridge arm H1 is connected to the positive terminal DC+ of the DC source, and the second end of the upper bridge arm H1 is connected to the first end of the lower bridge arm L1. The second end of the lower bridge arm L1 is connected to the negative terminal DC- of the DC source. The switching transistors of the upper bridge arm H1 and the lower bridge arm L1 are not turned on at the same time.

[0070] When the switch of the upper bridge arm H1 is turned on and the switch of the lower bridge arm L1 is turned off, the second terminal of the upper bridge arm H1 outputs a high level; when the switch of the upper bridge arm H1 is turned off and the switch of the lower bridge arm L1 is turned on, the second terminal of the upper bridge arm H1 outputs a low level. The controller 200 can adjust the voltage output at the second terminal of the upper bridge arm H1 by controlling the duty cycle of the switches of the upper bridge arm H1 and the lower bridge arm L1, thereby converting DC power into AC or pulse voltage signals.

[0071] The power converter provided in this application includes two half-bridge arms. By controlling the alternating conduction of the switching transistors of the upper and lower bridge arms, the output terminal can achieve periodic switching within the DC bus voltage range, thereby converting DC power into adjustable AC or pulse voltage signals to provide power drive capability for the load.

[0072] One possible implementation of the power converter provided in this application embodiment includes a half-bridge arm.

[0073] See Figure 9 This figure is a schematic diagram of a second type of power converter provided in an embodiment of this application.

[0074] Figure 9 In the power converter provided in the embodiment, the first end of the half-bridge arm is used to connect to the positive DC source DC+, and the second end of the half-bridge arm is used to connect to the load. Figure 9 In this embodiment, the half-bridge arm acts as a high-side switch, used to control the on / off state of the power supply circuit from the DC source to the load. When the switch in the half-bridge arm is turned on, the positive terminal DC+ of the DC source provides power to the load through the half-bridge arm; when the switch in the half-bridge arm is turned off, the power supply path of the positive terminal DC+ of the DC source is cut off, and the load no longer draws power from the positive terminal DC+ of the DC source.

[0075] This half-bridge arm can be used as both a high-side switch and a low-side switch.

[0076] See Figure 10 This figure is a schematic diagram of a third type of power converter provided in an embodiment of this application.

[0077] Figure 10 In the power converter provided in the embodiment, the first end of the half-bridge arm is used to connect to the load, and the second end of the half-bridge arm is used to ground. Figure 10 In this embodiment, the half-bridge arm acts as a low-side switch, used to switch the load-to-ground circuit on and off. When the switch in the half-bridge arm is turned on, the load is grounded, forming a circuit; when the switch in the half-bridge arm is turned off, the load-to-ground circuit is broken, and the load current cannot flow back to ground.

[0078] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0079] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving circuit, characterized in that, Includes a driver chip, a first common-mode inductor, and a second common-mode inductor; The first terminal of the first common-mode inductor is connected to the first terminal of the driver chip, the second terminal of the first common-mode inductor is used to connect to the gate of the first switching transistor, the third terminal of the first common-mode inductor is connected to the second terminal of the driver chip, and the fourth terminal of the first common-mode inductor is used to connect to the Kelvin source of the first switching transistor; the first terminal and the third terminal of the first common-mode inductor are terminals with the same name. The first terminal of the second common-mode inductor is connected to the first terminal of the driver chip, the second terminal of the second common-mode inductor is used to connect to the gate of the second switch, the third terminal of the second common-mode inductor is connected to the second terminal of the driver chip, and the fourth terminal of the second common-mode inductor is used to connect to the Kelvin source of the second switch; the first terminal and the third terminal of the second common-mode inductor are terminals with the same name. The drain of the first switching transistor is connected to the drain of the second switching transistor, and the source of the first switching transistor is connected to the source of the second switching transistor.

2. The driving circuit according to claim 1, characterized in that, Also includes: First source resistor and second source resistor; The first source resistor is located between the Kelvin source of the first switch and the driver chip; The second source resistor is located between the Kelvin source of the second switch and the driver chip.

3. The driving circuit according to claim 2, characterized in that, Also includes: First gate resistor and second gate resistor; The first gate resistor is located between the gate of the first switch and the driver chip; the second gate resistor is located between the gate of the second switch and the driver chip.

4. The driving circuit according to claim 1, characterized in that, The first common-mode inductor and the second common-mode inductor have the same number of winding turns.

5. The driving circuit according to claim 4, characterized in that, The core material of both the first common-mode inductor and the second common-mode inductor is ferrite.

6. The driving circuit according to any one of claims 1-5, characterized in that, Also includes: Controller; The controller is used to control the output of differential drive voltage at the first terminal and the second terminal of the driver chip.

7. A power converter, characterized in that, The driving circuit according to any one of claims 1-6 further includes at least one half-bridge arm, the half-bridge arm including: a first switching transistor and a second switching transistor; The drain of the first switching transistor serves as the first end of the half-bridge arm, and the source of the first switching transistor serves as the second end of the half-bridge arm.

8. The power converter according to claim 7, characterized in that, It includes two half-bridge arms, which are an upper bridge arm and a lower bridge arm, respectively; The first end of the upper bridge arm is used to connect to the positive terminal of the DC source, the second end of the upper bridge arm is connected to the first end of the lower bridge arm, and the second end of the lower bridge arm is used to connect to the negative terminal of the DC source; the switching transistors of the upper bridge arm and the lower bridge arm are not turned on at the same time.

9. The power converter according to claim 7, characterized in that, Includes one half-bridge arm; The first end of the half-bridge arm is used to connect to the positive terminal of the DC source, and the second end of the half-bridge arm is used to connect to the load.

10. The power converter according to claim 7, characterized in that, Includes one half-bridge arm; The first end of the half-bridge arm is used to connect the load, and the second end of the half-bridge arm is used to ground.

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