A dynamic clamp circuit for a boost converter loop and a boost converter

Abstract

The present application relates to the technical field of DC-DC switching power supply, particularly relates to a dynamic clamping circuit for a boost converter loop, the dynamic clamping circuit comprises a clamping voltage generation module and a clamping execution module; the clamping voltage generation module is configured to receive the current signal output by the current limiting protection circuit, and after superposition, the first clamping voltage is generated through the conversion of the first resistance network; the clamping execution module is configured to apply the first clamping voltage to the output end of the error amplifier to limit the upper limit of the error amplifier output voltage. In the present application, the defect that the fixed clamping cannot adapt to all working conditions is solved, the over-response problem of the error amplifier during load jump and output voltage adjustment can be effectively inhibited, the loop recovery time is shortened, and the clamping threshold can be adaptively adjusted according to the output target voltage and the load working condition, so that the alternate triggering of amplitude limiting and current limiting protection during heavy load boosting is avoided to form a metastable state, and the working reliability of the output side device is improved.

Description

Technical Field

[0001] This invention relates to the field of DC-DC switching power supply technology, and in particular to a dynamic clamping circuit for a boost converter loop and a boost converter. Background Technology

[0002] This section is intended to provide background or context for embodiments of the present invention. The description herein is not intended to imply that it is prior art simply because it is included in this section.

[0003] Boost converters, a type of DC-DC converter, are widely used in consumer electronics, industrial power supplies, dynamic boost audio amplifiers, and other applications. Peak current mode control has become the mainstream control architecture for Boost converters due to its advantages such as good loop stability, convenient current limiting protection, and fast transient response.

[0004] The loop bandwidth of a peak current-mode Boost converter is limited by the zero point in the right half-plane. The higher the boost ratio and the heavier the load, the lower the frequency of the zero point in the right half-plane, and the smaller the loop bandwidth. Under light load conditions, the output impedance increases, and the output poles shift towards zero, which also limits the loop bandwidth. Therefore, the Boost loop cannot achieve fast response under all operating conditions. When the load changes abruptly or the output voltage is dynamically adjusted, the error amplifier (EA) is prone to overresponse, resulting in severe overshoot / undershoot in the output voltage and inductor current, prolonging the loop recovery time.

[0005] To suppress overresponse in error amplifiers, existing solutions often employ fixed-voltage clamping circuits to limit the amplifier's output range. However, fixed clamping values ​​cannot adapt to different input / output voltages and load conditions. A clamping value that is too high fails to effectively suppress overresponse, while a clamping value that is too low compresses the loop's dynamic range, thus worsening transient response performance. Especially in applications with dynamically adjustable output voltage (such as audio amplifiers with dynamic boost control), under heavy-load boost conditions, output ripple easily triggers limiting protection, while the boost operation itself triggers current-limiting protection. The interaction between these two factors causes the loop to enter a metastable state. The average output voltage is lower than the reference voltage, but the transient peak just triggers limiting protection. The main loop loses control over the inductor current, causing the inductor current to jump dramatically between the current-limiting peak and zero, resulting in increased output ripple, deteriorated electromagnetic interference (EMI) performance, and reduced reliability of output-side devices. Extending the debouncing time of the limiting protection to suppress this problem leads to an excessively slow limiting protection response, failing to effectively suppress transient voltage overshoot. Summary of the Invention

[0006] Based on this, it is necessary to address the technical problems of the aforementioned Boost loop, such as poor transient response, easy occurrence of metastability due to the interaction between amplitude limiting and current limiting, EMI deterioration, and the inability of fixed clamping to adapt to all operating conditions. A dynamic clamping circuit and a boost converter are needed to adapt to all input / output and load conditions, suppress loop over-response, and eliminate loop metastability.

[0007] In a first aspect, the present invention provides a dynamic clamping circuit for a boost converter loop.

[0008] The dynamic clamping circuit includes a clamping voltage generation module and a clamping execution module; The clamping voltage generation module is configured to: receive the current limiting reference current signal output by the current limiting protection circuit, the slope compensation current signal output by the slope compensation circuit, and the differential voltage compensation current signal related to the input-output voltage difference of the boost converter; and superimpose the current limiting reference current signal, the slope compensation current signal, the differential voltage compensation current signal, and the bias current with the bias current, and then convert them through the first resistor network to generate the first clamping voltage. The clamping execution module is configured to apply the first clamping voltage to the output of the error amplifier to limit the upper limit of the output voltage of the error amplifier.

[0009] Optionally, the clamping execution module includes a first PMOS transistor, the source of which is connected to the output of the error amplifier, the gate of which receives the first clamping voltage, and the drain of which is grounded through a second resistor. When the output voltage of the error amplifier exceeds the sum of the absolute values ​​of the first clamping voltage and the gate-source voltage of the first PMOS transistor, the first PMOS transistor is turned on, clamping the output voltage of the error amplifier to the target upper limit value.

[0010] Optionally, the clamping execution module includes a first operational amplifier and a first NMOS transistor; The non-inverting input of the first operational amplifier is connected to the output of the error amplifier, the inverting input is connected to the first clamping voltage, and the output is connected to the gate of the first NMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the error amplifier, and the source is grounded; The first operational amplifier and the first NMOS transistor form a negative feedback loop. When the output voltage of the error amplifier exceeds the first clamping voltage, the first operational amplifier outputs a high level to drive the first NMOS transistor to turn on, thereby pulling the output voltage of the error amplifier down to the first clamping voltage.

[0011] Optionally, the clamping voltage generation module includes a fifth resistor, a fourth resistor, a first bias current source, a first current-limiting reference current source, a first slope compensation current source, and a first differential voltage compensation current source. The first end of the fifth resistor is connected to the first node, and the second end is connected to the second node; The first end of the fourth resistor is connected to the second node, and the second end is grounded. The output of the first bias current source is connected to the second node; The outputs of the first current-limiting reference current source, the first slope compensation current source, and the first differential pressure compensation current source are all connected to the first node; The first clamping voltage is determined by the voltage division effect of the fourth and fifth resistors on the superimposed current.

[0012] Optionally, the error amplifier output voltage is clamped to the target upper limit value in accordance with the calculation formula: V clamp_max =R4I bias0 +(R4+R5)(I limit_max +I cmpst0 +I diffV )+∣V gs0 | In the formula, V clamp_max R4 is the target upper limit value for the output voltage clamping of the error amplifier, R5 is the resistance value of the fourth resistor, and I is the resistance value of the fifth resistor. bias0 I is the output current of the first bias current source. limit_max I is the output current of the first current-limiting reference current source. cmpst0 I is the output current of the first slope compensation current source. diffV The output current of the first differential pressure compensation current source is |V gs0 | represents the absolute value of the gate-source voltage of the first PMOS transistor.

[0013] Optionally, the dynamic clamping circuit further includes a dynamic compensation branch, which includes a second clamping voltage generation module and a second clamping execution module. The second clamping voltage generation module is configured to: receive the second current-limiting reference current signal, the second slope compensation current signal, and the differential voltage compensation current signal that are dynamically adjusted with the boost converter's slope compensation, and generate the second clamping voltage through the second resistor network; The second clamping execution module is a PMOS transistor direct drive structure or an operational amplifier and NMOS transistor negative feedback structure. It applies the second clamping voltage to the output of the error amplifier and synchronously adjusts the upper limit clamping value when the boost converter adopts dynamic slope compensation.

[0014] Optionally, the second resistor network includes a seventh resistor and a sixth resistor, wherein a first end of the seventh resistor is connected to a third node and a second end is connected to a fourth node; The first end of the sixth resistor is connected to the fourth node, and the second end is grounded. When the second clamping execution module is a PMOS transistor direct-drive structure, the second clamping voltage satisfies the formula: V clamp_dr =R6I bias1 +(R6+R7)(I limit_dr +I cmpst1 +I diffV )+∣V gs1 | When the second clamping execution module is a negative feedback structure of an operational amplifier and an NMOS transistor, the second clamping voltage satisfies the formula: V clamp_dr =R6I bias1 +(R6+R7)(I limit_dr +I cmpst1 +I diffV ) In the formula, V clamp_dr This is the second clamping voltage, R6 is the resistance of the sixth resistor, R7 is the resistance of the seventh resistor, and I... bias1 I is the output current of the second bias current source. limit_dr I is the second current-limiting reference current. cmpst1 For the second slope compensation current, I diffV For differential pressure compensation current, |V gs1 | is the second PMOS transistor M p1 The absolute value of the gate-source voltage.

[0015] Optionally, the dynamic clamping circuit further includes a lower clamping circuit configured to limit the lower limit of the error amplifier output voltage; The lower clamping circuit includes a lower clamping voltage generation module and a lower clamping execution module; The lower clamping voltage generation module and the clamping voltage generation module have a symmetrical topology. The current limiting reference current signal is replaced with a reference current signal corresponding to the lowest static power consumption, and the resistor network is adjusted accordingly to generate the lower clamping voltage.

[0016] Optionally, the differential voltage compensation current signal is proportional to the output voltage of the boost converter, so that the first clamping voltage increases as the output voltage increases, in order to match the variation of the peak inductor current with the output voltage and adapt to the clamping requirements under different boost ratio conditions.

[0017] Secondly, the present invention also provides a boost converter. It includes an error amplifier, a power stage main circuit, a current limiting protection circuit, and a slope compensation circuit, as well as the aforementioned dynamic clamping circuit for the boost converter loop; The dynamic clamping circuit is connected in parallel to the output of the error amplifier to dynamically limit the upper limit of the output voltage of the error amplifier and suppress loop over-response when the boost converter load jumps and the output voltage is dynamically adjusted.

[0018] The aforementioned dynamic clamping circuit and boost converter used in the boost converter loop dynamically generate a clamping voltage by combining current-limiting reference current, ramp compensation current, and differential voltage compensation current. The clamping value can adaptively adjust according to the input-output voltage difference and load conditions, solving the defect of fixed clamping that cannot adapt to all operating conditions. It can effectively suppress the over-response problem of the error amplifier during load jumps and output voltage adjustments, shorten the loop recovery time, and optimize the loop transient performance under all operating conditions. Dynamic clamping can limit the output of the error amplifier to a reasonable range, avoid the loop metastability problem caused by the interaction of limiting protection and current limiting protection, enable the main loop to intervene in control in advance, effectively reduce output voltage ripple, suppress large jumps in inductor current, improve circuit EMI performance, and enhance the operating reliability of output-side devices.

[0019] Furthermore, this invention provides two clamping execution architectures: a MOSFET direct-drive type and an op-amp negative feedback type, respectively adapted to cost-sensitive and high-precision application scenarios. The accompanying dynamic compensation branch can be adapted to Boost converters with dynamic slope compensation, and the symmetrically arranged lower clamping circuit can simultaneously limit the lower limit of the error amplifier output, further improving the loop protection range and adapting to different circuit design requirements. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention, but do not constitute an undue limitation of the invention.

[0021] Figure 1 This is a schematic diagram of a PMOS transistor direct-drive dynamic clamping circuit in one embodiment; Figure 2 This is a schematic diagram of an NMOS transistor direct-drive lower clamping circuit in one embodiment; Figure 3 This is a schematic diagram of an operational amplifier negative feedback type dynamic clamping circuit in one embodiment; Figure 4 This is a schematic diagram of an operational amplifier negative feedback type lower clamping circuit in one embodiment. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0023] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0024] The dynamic clamping circuit for the boost converter loop provided in this embodiment of the invention can be applied to various peak current-mode DC-DC boost converters, especially suitable for scenarios with large dynamic load changes and adjustable output voltage, such as audio power amplifiers with dynamic boost control, industrial-grade wide-input power supplies, and consumer electronics fast-charging power supplies. The boost converter basic architecture of this embodiment includes modules such as error amplifier EA, power stage main circuit, current limiting protection circuit, slope compensation circuit, and output sampling circuit. Figure 1 As shown in the attached figure, this figure focuses on the dynamic clamping circuit and the error amplifier EA. The current limiting protection circuit, slope compensation circuit, output sampling circuit, and power stage main circuit are conventional components of boost converters in this field and are omitted from the figure. The inverting input of the error amplifier EA receives the output feedback voltage V. fb The non-inverting input receives the reference voltage V. ref2 The output terminal is grounded through an RC compensation network (R1, C1, and C2), forming the core controller of the voltage loop. In this embodiment, the dynamic clamping circuit is connected in parallel to the output terminal of the error amplifier EA to dynamically limit the upper and lower limits of the output voltage of the error amplifier EA, suppress loop over-response, and eliminate loop metastability caused by the coupling of amplitude limiting and current limiting.

[0025] Example 1

[0026] like Figure 1 As shown, this embodiment provides a dynamic clamping circuit for a boost converter loop, the dynamic clamping circuit including a clamping voltage generation module 2 and a clamping execution module 1.

[0027] The clamping voltage generation module 2 is configured to receive a current-limiting reference current signal, a slope compensation current signal, a differential voltage compensation current signal, and a bias current, and then convert them through a first resistor network to generate a first clamping voltage.

[0028] Specifically, the current-limiting reference current signal is the reference current corresponding to the converter's current-limiting threshold, which determines the basic lower limit of the clamping voltage. The slope compensation current signal is the current corresponding to the current-mode loop slope compensation, used to match the loop compensation characteristics. The differential voltage compensation current signal dynamically changes with the converter's input-output differential voltage, used to adapt to different boost ratio operating conditions. After the three operating condition-related currents are superimposed with the fixed bias current, the current-to-voltage conversion is completed through the first resistor network, generating a clamping reference voltage that dynamically adjusts with the operating conditions, which is different from the traditional fixed-value clamping scheme.

[0029] The clamping execution module 1 is configured to apply the first clamping voltage to the output terminal of the error amplifier EA to limit the upper limit of the output voltage of the error amplifier EA.

[0030] It is understandable that when the load jump or the output voltage is dynamically adjusted, causing the output of the error amplifier EA to rise too quickly and over-response, the clamping execution module is triggered to conduct, clamping the output voltage of the error amplifier EA at the dynamically calculated upper limit value, avoiding excessive saturation of the error amplifier EA output, shortening the loop recovery time, and preventing the main loop from completely losing control and entering the metastable state of current limiting and amplitude limiting coupling.

[0031] In one example, the clamping voltage generation module 2 includes a first resistor network and a first bias current source I. bias0 First current-limiting reference current source I limit_max First slope compensation current source I cmpst0 and the first differential pressure compensation current source I diffV The first resistor network is composed of the fifth resistor R5 and the fourth resistor R4 connected in series.

[0032] Specifically, such as Figure 1 As shown, the first node N1 is M. p0 The connection point between the gate of resistor R5 and the first terminal of resistor R5, i.e., the upper end of resistor R5 in the diagram, is the converging node for the three input currents. The terms "upper end" and "lower end" used below refer to the upper and lower ends shown in the diagram, for ease of understanding of this scheme. The second node N2 is the common connection point between the second terminal of resistor R5 (i.e., the lower end in the diagram) and the first terminal (upper end) of resistor R4, and is the bias current I. bias0The access node is connected to the second node N2. The second (lower) end of the fourth resistor R4 is grounded. The output of the first bias current source is connected to the second node N2 to provide a basic bias for the resistor network, ensuring that the clamping circuit still has a basic operating voltage under zero input current. The outputs of the first current-limiting reference current source, the first slope compensation current source, and the first differential voltage compensation current source are all connected to the first node N1. After the three currents are superimposed at the first node N1, they flow through the fifth resistor R5 and the fourth resistor R4. The superimposed current flows through the fourth resistor R4 and the fifth resistor R5 connected in series, generating the first clamping voltage through the voltage drop across the resistors.

[0033] The first clamping voltage is determined by the voltage division effect of the fourth resistor R4 and the fifth resistor R5 on the superimposed total current. By adjusting the resistance ratio of the fourth resistor R4 and the fifth resistor R5, the gain coefficient of the first clamping voltage can be flexibly adjusted to adapt to different specifications of Boost converter loops.

[0034] In one example, the target upper limit of the error amplifier output satisfies the formula: V clamp_max =R4I bias0 +(R4+R5)(I limit_max +I cmpst0 +I diffV )+∣V gs0 | In the formula, V clamp_max This is the target upper limit for clamping the output voltage of the error amplifier, i.e., the highest output voltage of the error amplifier EA after final clamping.

[0035] I bias0 The output current of the first bias current source provides the basic bias for the clamping circuit.

[0036] I limit_max The output current of the first current-limiting reference current source corresponds to the peak current-limiting threshold of the converter.

[0037] I cmpst0 This is the output current of the first slope-compensated current source, corresponding to the slope compensation amount of the current mode loop.

[0038] I diffV This is the output current of the first differential pressure compensation current source, which is the differential pressure compensation current related to the input-output differential pressure.

[0039] |V gs0 | represents the absolute value of the gate-source voltage of the first PMOS transistor.

[0040] Because the first PMOS transistor M p0When turned on, the source voltage must be higher than the gate voltage by one gate-source voltage drop. Therefore, the final clamping upper limit must be based on the gate voltage generated by the resistor network, plus the magnitude of the gate-source voltage. The formula uses absolute values ​​to avoid numerical logic ambiguity caused by the negative gate-source voltage of the PMOS.

[0041] In one example, the clamping execution module 1 adopts a PMOS transistor direct drive structure, including a first PMOS transistor M p0 And the second resistor R2. The M p0 The source is connected to the output of the error amplifier EA, the gate receives the first clamping voltage, and the drain is grounded through the second resistor R2.

[0042] Wherein, when the output voltage of the error amplifier EA exceeds the first clamping voltage and M p0 When the absolute values ​​of the gate-source voltages are summed, the M... p0 The source-gate voltage satisfies the conduction condition, M p0 When the circuit is turned on, the charge at the output terminal of the error amplifier EA is discharged to ground through the second resistor R2, thereby clamping the output voltage of the error amplifier to the target upper limit value.

[0043] The second resistor R2 is a current-limiting resistor used to control M. p0 The slope of the discharge current during conduction is adjusted to prevent excessive clamping action that could cause loop oscillation. The resistance value can be adjusted according to the loop bandwidth requirements.

[0044] In one example, such as Figure 1 As shown, the dynamic clamping circuit further includes a dynamic compensation branch, which includes a second clamping voltage generation module 4 and a second clamping execution module 3.

[0045] The second clamping voltage generation module 4 is configured to receive the second current-limiting reference current signal, the second slope compensation current signal, and the differential pressure compensation current signal, which are dynamically adjusted according to the boost converter's slope compensation, and generate the second clamping voltage through the second resistor network.

[0046] Specifically, when the Boost converter adopts a dynamic slope compensation scheme (such as dynamically adjusting the slope compensation amount according to the load and switching frequency), the current limiting threshold and the slope compensation amount will be dynamically adjusted synchronously. The second clamping voltage generation module synchronously collects the corresponding current after dynamic adjustment and generates a second clamping voltage that matches the current operating condition, ensuring that the clamping threshold always matches the loop parameters during the dynamic compensation process. The second clamping execution module 3 is configured to apply the second clamping voltage to the output terminal of the error amplifier EA, so as to synchronously adjust the upper limit clamping value of the error amplifier output voltage when the boost converter adopts dynamic slope compensation, avoiding the loop performance degradation caused by the mismatch between fixed clamping and dynamic slope compensation.

[0047] In one example, the second clamping execution module 3 adopts a PMOS transistor direct drive structure, including a second PMOS transistor M. p1 And the third resistor R3.

[0048] The second PMOS transistor M p1 The source is connected to the output of the error amplifier EA, the gate receives the second clamping voltage output by the second clamping voltage generation module 4, and the drain is grounded through the third resistor R3.

[0049] Its working principle is the same as that of the main branch clamping execution module. When the output voltage of the error amplifier EA exceeds the second clamping voltage and M... p1 When the absolute values ​​of the gate-source voltages are summed, M p1 The circuit is turned on to discharge the charge at the output of the error amplifier EA, achieving upper limit clamping under dynamic slope compensation conditions. The main branch and the dynamic branch work in parallel, always taking effect with a lower clamping threshold, jointly covering all steady-state and dynamic slope compensation conditions.

[0050] In one example, the second clamping voltage generation module 4 includes a second resistor network and a second bias current source I. bias1 Second current-limiting reference current source I limit_dr Second slope compensation current source I cmpst1 and differential pressure compensation current source I diffV The second resistor network consists of a seventh resistor R7 and a sixth resistor R6 connected in series.

[0051] Specifically, such as Figure 1 As shown, the third node N3 is M. p1 The connection point between the gate of the first resistor and the first end of the seventh resistor R7, i.e., the upper end of the seventh resistor R7 shown in the figure, is the converging node for the three input currents of the dynamic branch. The fourth node N4 is the common connection node between the second end (lower end) of the seventh resistor R7 and the first end (upper end) of the sixth resistor R6, and is the access node for the bias current of the dynamic branch. The second end (lower end) of the sixth resistor R6 is grounded. The output terminal of the second bias current source is connected to the fourth node N4. The output terminals of the second current-limiting reference current source, the second slope compensation current source, and the differential voltage compensation current source are all connected to the third node N3.

[0052] The second clamping voltage satisfies the calculation formula: V clamp_dr =R6I bias1 +(R6+R7)(I limit_dr +I cmpst1 +I diffV )+∣V gs1 | In the formula, V clamp_dr This is the second clamping voltage of the dynamic branch.

[0053] I bias1 This is the output current of the second bias current source.

[0054] I limit_dr The output current of the second current-limiting reference current source corresponds to the dynamically adjusted current-limiting threshold.

[0055] I cmpst1 This is the output current of the second slope compensation current source, corresponding to the dynamically adjusted slope compensation amount.

[0056] I diffV The output current of the differential pressure compensation current source shares the same differential pressure compensation signal with the main branch to ensure the consistency of the entire circuit's operating conditions.

[0057] |V gs1 | is the second PMOS transistor M p1 The absolute value of the gate-source voltage.

[0058] In one example, such as Figure 2 As shown, the dynamic clamping circuit also includes a lower clamping circuit, which is configured to limit the lower limit of the output voltage of the error amplifier.

[0059] The lower clamping circuit includes a lower clamping voltage generation module 6 and a lower clamping execution module 5.

[0060] The lower clamping voltage generation module 6 and the clamping voltage generation module 2 are symmetrically topologically arranged, wherein the current limiting reference current signal is replaced by a reference current signal I corresponding to the lowest static power consumption. q_shrink The resistor network is adjusted accordingly to generate the lower limit clamping voltage V. clamp_min .

[0061] It should be noted that the symmetrical topology can refer to the symmetrical current superposition method and the symmetrical resistor network topology, with the actuator type and connection method adapted according to the clamping direction. The actuator types and connection methods of the upper and lower branches are adapted differently according to the clamping direction. The lower clamping actuator uses an NMOS transistor M. nd0 The drain of the NMOS transistor is connected to the tenth resistor R. 10 Connect the chip's positive power supply V DD The source is connected to the output of the error amplifier EA, and the gate receives the lower limit clamping voltage V. clamp_min When the output voltage of the error amplifier EA is lower than the lower limit clamping voltage V... clamp_min When the difference between the gate-source voltage and the on-state voltage of the NMOS transistor is reached, the NMOS transistor turns on, and V... DD Injecting charge into the output of error amplifier EA raises the output voltage of EA, thereby achieving lower limit voltage clamping.

[0062] In one example, the differential voltage compensation current signal is proportional to the output voltage of the boost converter, so that the first clamping voltage increases as the output voltage increases, in order to match the variation of the peak inductor current with the output voltage, thereby adapting to the clamping requirements under different boost ratio conditions.

[0063] Specifically, for a Boost converter in Continuous Conduction Mode (CCM), under the same load conditions, a higher output voltage and a larger boost ratio result in a higher peak inductor current, and consequently, a higher steady-state value of the error amplifier EA. If a fixed clamping voltage is used, a low clamping value under high boost ratio conditions will compress the loop dynamic range and limit transient response, while a high clamping value under low boost ratio conditions will fail to effectively suppress overshoot. In this embodiment, the differential voltage compensation current is proportional to the output voltage; the higher the output voltage, the larger the superimposed compensation current, and the higher the generated clamping voltage. This ensures that the clamping threshold always matches the peak inductor current under the current boost ratio, achieving adaptive clamping across the entire boost ratio range, balancing transient suppression and loop dynamic range.

[0064] In one example, the complete working process of the dynamic clamping circuit is divided into three categories: steady-state condition, transient overshoot condition, and dynamic slope compensation condition.

[0065] 1. Steady-state operation: The Boost converter operates normally, and the output voltage of the error amplifier EA stabilizes at the closed-loop operating point, which is lower than the sum of the absolute values ​​of the first clamping voltage and the gate-source voltage of the first PMOS transistor. p0 When in the off state, the clamping circuit does not participate in the loop operation and does not affect the steady-state gain and stability of the main loop.

[0066] 2. Transient overshoot condition: When the load changes abruptly or the output voltage adjusts stepwise, the error amplifier EA output rises rapidly, exhibiting overresponse. When the output voltage of the error amplifier EA exceeds the sum of the absolute values ​​of the first clamping voltage and the gate-source voltage of the first PMOS transistor, M... p0 When the circuit is turned on, the excess charge at the output of the error amplifier EA is discharged to ground through the second resistor R2, forcing the upper limit of the output voltage of the error amplifier EA to be maintained at the target clamping value, preventing the error amplifier EA from entering the deep saturation region, and greatly shortening the loop recovery time.

[0067] 3. Dynamic Slope Compensation Operation: When the Boost converter enables dynamic slope compensation, the current limiting threshold and slope compensation amount are adjusted synchronously with the load and switching frequency, and the dynamic compensation branch synchronously generates a second clamping voltage. If the second clamping voltage is lower than the first clamping voltage of the main branch under dynamic operation, then the second PMOS transistor M... p1Prioritize triggering conduction to ensure that the clamping threshold always matches the current loop compensation parameters, avoiding false triggering of current limiting caused by mismatch between clamping value and loop parameters.

[0068] Furthermore, the adjustment range of the clamping voltage can be flexibly configured through three types of parameters.

[0069] First, by adjusting the resistance ratio of the fourth resistor R4 and the fifth resistor R5, the gain coefficient of the clamping voltage on the input current can be adjusted, thus adapting to converters with different error amplifier EA output voltage swings.

[0070] Secondly, by adjusting the output current of the first bias current source, the base value of the clamping voltage can be adjusted to adapt to the static operating point of different loops.

[0071] Third, by adjusting the gain coefficient of the differential voltage compensation current, it can be adapted to Boost converters with different input and output voltage ranges, meeting the needs of different scenarios such as wide-input industrial power supplies and fixed-output consumer power supplies.

[0072] This embodiment uses only a single PMOS transistor as the clamping actuator, eliminating the need for additional operational amplifiers. This results in fewer circuit components and a smaller chip footprint, making it suitable for cost-sensitive mass production applications such as consumer power supplies. By generating a dynamic clamping value through the linkage of current limiting, slope compensation, and differential voltage current, it overcomes the shortcomings of traditional fixed clamping, which cannot adapt to different boost ratios and load conditions. It effectively suppresses over-response of the error amplifier during load jumps and dynamic voltage regulation without compressing the normal dynamic range of the loop. Dynamic clamping avoids loop metastability triggered by the coupling of limiting and current limiting protection, reduces output voltage ripple, suppresses large jumps in inductor current, improves EMI performance, and enhances the operational reliability of output-side devices.

[0073] Example 2

[0074] like Figure 3 As shown, this embodiment provides a dynamic clamping circuit for a boost converter loop. The core difference lies in the execution unit of the clamping execution module and the dynamic compensation branch, which is replaced by a negative feedback architecture composed of an operational amplifier (OPA) and an NMOS transistor. This eliminates the clamping error caused by the gate-source voltage deviation of the MOS transistor, achieving high-precision clamping at the mV level. The other parts are completely consistent with Embodiment 1.

[0075] In one example, the dynamic clamping circuit for the boost converter loop, the clamping execution module 7 includes a first operational amplifier OPA0 and a first NMOS transistor M. n0 .

[0076] The non-inverting input of the first operational amplifier OPA0 is connected to the output of the error amplifier EA, the inverting input is connected to the first clamping voltage output by the clamping voltage generation module 8, and the output is connected to the first NMOS transistor M. n0 The gate of the first NMOS transistor M. n0 The drain of the amplifier is connected to the output of the error amplifier EA, and the source is grounded.

[0077] Among them, the first operational amplifier OPA0 and the first NMOS transistor M n0 A deep negative feedback loop is formed, and the virtual short characteristic of the operational amplifier OPA0 is used to force the voltage at the non-inverting input to be equal to the voltage at the inverting input. That is, the output voltage of the error amplifier EA is equal to the first clamping voltage, which completely cancels the influence of the deviation of the gate-source voltage of the MOS transistor.

[0078] In a specific example, the operation of the clamping execution module 7 is as follows: When the output voltage of the error amplifier EA is lower than the first clamping voltage, the voltage at the non-inverting input of the operational amplifier OPA0 is lower than the voltage at the inverting input, the op-amp outputs a low level, and the first NMOS transistor M... n0 When the clamping circuit is cut off, it does not participate in the main loop operation. When the output voltage of the error amplifier EA rises and exceeds the first clamping voltage, the voltage at the non-inverting input of the operational amplifier OPA0 is higher than that at the inverting input, the op-amp output voltage rises, and drives M... n0 When the circuit is turned on, the charge at the output terminal of the error amplifier EA is discharged, pulling down the output voltage of the error amplifier EA. Through negative feedback closed-loop regulation, the final output voltage of the error amplifier EA will stabilize at a value exactly equal to the first clamping voltage, achieving precise clamping.

[0079] The clamping error of this architecture originates only from the input offset voltage of the operational amplifier and the device mismatch. Under conventional processes, it can be controlled at the mV level, which is far superior to the gate-source voltage deviation of hundreds of mV in the PMOS direct drive solution. It is suitable for high-precision power supply scenarios with high clamping accuracy requirements and strict loop parameter matching.

[0080] In one example, under the op-amp architecture, the upper limit of the precision clamping of the error amplifier EA output satisfies the calculation formula: V clamp_max =R4I bias0 +(R4+R5)(I limit_max +I cmpst0 +I diffV ) In the formula, V clamp_max R4 is the upper limit of the precise clamping value output by the error amplifier, which is exactly equal to the first clamping voltage generated by the resistor network. R5 is the resistance value of the fourth resistor, and I is the resistance value of the fifth resistor. bias0 I is the output current of the first bias current source.limit_max I is the output current of the first current-limiting reference current source. cmpst0 I is the output current of the first slope compensation current source. diffV This is the output current of the first differential pressure compensation current source.

[0081] Compared with the PMOS scheme in Example 1, this example uses an operational amplifier OPA0 and an NMOS transistor to form a negative feedback loop. The clamping voltage is no longer affected by the drift of the gate-source voltage of the field-effect transistor with process, voltage, and temperature (PVT). It is determined only by the resistor network and the input current, thus having higher clamping accuracy and stability over the entire PVT range.

[0082] In one example, the second clamping execution module 9 of the dynamic compensation branch also adopts an operational amplifier negative feedback architecture, including a second operational amplifier OPA1 and a second NMOS transistor M. n1 The non-inverting input of the second operational amplifier OPA1 is connected to the output of the error amplifier EA, the inverting input is connected to the second clamping voltage output by the second clamping voltage generation module 10, and the output is connected to the second NMOS transistor M. n1 The gate of the second NMOS transistor M. n1 The drain of the circuit is connected to the output of the error amplifier EA, and the source is grounded.

[0083] Correspondingly, the formula for calculating the second clamping voltage is: V clamp_dr =R6I bias1 +(R6+R7)(I limit_dr +I cmpst1 +I diffV ) The main branch and the dynamic branch work in parallel, always taking effect with a lower clamping threshold, and maintaining high-precision clamping characteristics under all working conditions of dynamic slope compensation.

[0084] In another example, such as Figure 4 As shown, a high-precision lower clamping circuit can be constructed using a single operational amplifier OPAD to provide a lower limit clamp for the output voltage of the error amplifier EA.

[0085] Specifically, this example uses an operational amplifier OPAD in conjunction with a PMOS transistor M pd0 This constitutes the lower clamping execution unit. The lower clamping voltage generation module, composed of the eighth resistor R8, the ninth resistor R9, and multiple current sources, generates the lower limit clamping voltage V. clamp_minThe inverting input of the OPAD is connected to the inverting input, and the non-inverting input of the OPAD is connected to the output of the error amplifier EA for real-time sampling of the clamped voltage. The output of the OPAD is connected to the gate of the PMOS transistor Mpd0, and the source of Mpd0 is connected to the chip's positive power supply V. DD The drain is connected to the output of the error amplifier EA.

[0086] This scheme reuses the operational amplifier deep negative feedback architecture, and its working mechanism is consistent with the aforementioned OPA0 closed-loop upper clamping scheme. It relies on the virtual short characteristic of the operational amplifier to force the output voltage of the error amplifier EA to be equal to the lower limit clamping reference V. clamp_min This completely eliminates the clamping error caused by the gate-source voltage drift of the PMOS transistor, and the closed-loop regulation process will not be repeated here.

[0087] When the output voltage of error amplifier EA is lower than the set lower threshold V clamp_min When the OPAD output voltage decreases, the conduction level of the driving PMOS transistor Mpd0 increases, and V... DD Injecting current into the output node of error amplifier EA raises the output voltage of EA, eventually stabilizing at V. clamp_min This architecture achieves high-precision lower limit voltage clamping. Its advantages include: mV-level precision lower limit clamping can be achieved using only a single operational amplifier, resulting in higher clamping accuracy compared to NMOS direct-drive lower clamping circuits; better threshold consistency under full PVT conditions; and the lower clamping voltage generation logic and multi-path adaptive current principle in this implementation are consistent with the lower clamping scheme in Example 1.

[0088] The dynamic clamping circuit for the boost converter loop provided in this embodiment cancels the gate-source voltage deviation of the MOS transistor through deep negative feedback of the operational amplifier. The clamping error only comes from operational amplifier offset and device mismatch. Under conventional processes, it can be controlled at the mV level, which is far superior to the clamping accuracy of the PMOS direct drive solution. It is suitable for high-precision industrial power supplies, high-end audio power amplifiers and other scenarios with strict clamping threshold requirements.

[0089] The clamping voltage is determined solely by the resistance and input current, and is not affected by temperature or process deviations in the gate-source voltage of the MOSFET. It exhibits superior consistency in clamping threshold under all process, voltage, and temperature conditions, resulting in more stable loop performance.

[0090] Example 3

[0091] Based on the same inventive concept, this embodiment provides a boost converter. The boost converter includes a power stage main circuit, an error amplifier EA, a current limiting protection circuit, a slope compensation circuit, and the dynamic clamping circuit described in any of the preceding embodiments. The dynamic clamping circuit is connected in parallel to the output node of the error amplifier EA and is arranged in parallel with the RC compensation network (R1, C1, C2) on the output side of the error amplifier EA.

[0092] The main circuit of the power stage is a peak current-mode Boost power topology, containing conventional power devices such as inductors, output capacitors, and power switches, used to complete the boost conversion from the input voltage to the target output voltage. The current limiting protection circuit is used to collect the peak inductor current in real time and output a current limiting reference current signal; the slope compensation circuit generates the slope compensation current signal required for loop stability, and the current signals output by both are sent to the clamping voltage generation module inside the dynamic clamping circuit.

[0093] The dynamic clamping circuit acquires the current-limiting reference current, ramp compensation current, and differential voltage compensation current related to the input-output voltage difference through an internal clamping voltage generation module. After superimposing the bias current, it is converted by a resistor network to generate a clamping reference voltage that dynamically adapts to the operating conditions. The clamping execution module then limits the upper limit of the output voltage of the error amplifier EA in real time. At the same time, the boost converter can be equipped with a lower clamping circuit to synchronously limit the lower limit of the EA output voltage.

[0094] When the converter experiences heavy load, light load transition, or dynamic output voltage boost adjustment, the dynamic clamping circuit can adaptively adjust the clamping threshold of the EA output voltage to avoid deep over-response of the error amplifier, shorten the loop dynamic recovery time, eliminate the loop metastability caused by the mutual coupling of the limiting protection and the current limiting protection, reduce output voltage ripple, and improve the overall EMI performance.

[0095] This boost converter can be equipped with two clamping execution architectures: one is a PMOS transistor direct-drive clamping execution module, which has a simple circuit structure, small chip footprint, and is suitable for cost-sensitive consumer electronics power supplies.

[0096] The second is an operational amplifier negative feedback clamping execution module, which can achieve clamping accuracy at the mV level and is not affected by the PVT drift of the MOSFET gate-source voltage. It is suitable for applications with stringent transient performance requirements, such as high-precision industrial power supplies and dynamic boost audio amplifiers.

[0097] Example 4

[0098] This embodiment is implemented using the hardware circuit described in Embodiments 1 and 2, and is based on the same inventive concept as the product circuit scheme.

[0099] This embodiment provides a dynamic clamping method for a boost converter loop, applied to a peak current-mode boost converter, including the following steps: S1. Acquire the operating current signal of the boost converter, including the current-limiting reference current, the ramp compensation current, and the differential pressure compensation current related to the input-output voltage difference of the boost converter.

[0100] Specifically, the acquisition of the boost converter's operating current signal includes obtaining a current-limiting reference current from the converter's current-limiting protection module. This current corresponds to the peak inductor current limiting threshold of the converter, determining the basic lower limit of the clamping voltage. A slope compensation current is obtained from the slope compensation module. This current changes synchronously with the loop slope compensation amount to ensure that the clamping threshold matches the current-mode loop compensation characteristics. A differential voltage compensation current is obtained from the input / output sampling module. This current is proportional to the converter's output voltage and inversely proportional to the input voltage, dynamically adjusted according to the boost ratio.

[0101] It should be noted that all current signals are analog current domain signals, which can be directly obtained by mirroring the current through a current mirror without the need for additional analog-to-digital conversion circuits, thus meeting the integration requirements of analog power supply chips.

[0102] S2. The current-limiting reference current, slope compensation current, differential voltage compensation current and bias current are superimposed and then converted to voltage through a resistor network to generate a dynamic upper limit clamping voltage.

[0103] Specifically, voltage conversion includes: The bias current is connected to the lower node of the series resistor network, and the three operating currents are connected to the upper node of the series resistor network. All currents are superimposed in the resistor network, and current-to-voltage conversion is completed by Ohm's law. The gain coefficient of the clamping voltage to the input current can be adjusted by adjusting the resistance ratio of the two resistors in the series resistor network. The basic operating point of the clamping voltage can be adjusted by adjusting the magnitude of the bias current. The generated dynamic clamping voltage changes in real time with the current limiting threshold, slope compensation, and input-output voltage difference, always matching the current operating conditions of the Boost converter.

[0104] S3. Apply the dynamic upper limit clamping voltage to the output terminal of the error amplifier of the boost converter to limit the upper limit of the output voltage of the error amplifier and suppress the over-response of the main loop.

[0105] This method generates a dynamic clamping threshold by linking multiple operating currents, which is different from the traditional fixed clamping scheme. It can be adapted to all operating scenarios with different inputs and outputs and different loads, effectively suppressing transient overshoot without compressing the normal dynamic range of the loop.

[0106] Specifically, it includes two clamping execution methods. First, the direct-drive method using a switching transistor. The dynamic clamping voltage is applied to the gate of a PMOS transistor, and the source of the PMOS transistor is connected to the output of an error amplifier. When the output voltage of the error amplifier EA exceeds the sum of the clamping voltage and the gate-source voltage drop of the PMOS transistor, the PMOS transistor conducts to discharge charge, achieving clamping. This method has a simple circuit and low cost. Second, the operational amplifier negative feedback method. The dynamic clamping voltage is applied to the inverting input of an operational amplifier, and the non-inverting input of the operational amplifier is connected to the output of the error amplifier EA, driving an NMOS transistor. Through a negative feedback closed loop, the output voltage of the error amplifier EA is forced to equal the clamping voltage, achieving high-precision clamping. This method has high accuracy and small deviation.

[0107] Both execution methods are based on the same dynamic voltage generation logic, and can be flexibly selected according to the accuracy and cost requirements of the application scenario.

[0108] In one example, the method further includes a synchronous clamping adjustment step for dynamic slope compensation conditions: When the boost converter is in dynamic slope compensation mode, it collects the dynamically adjusted second current limiting reference current and second slope compensation current, and after superimposing them with the differential voltage compensation current, it generates the second clamping voltage through the second set of resistor networks, and synchronously adjusts the upper limit clamping value of the error amplifier. The main clamping branch and the dynamic clamping branch work in parallel, always taking effect with a lower clamping threshold, ensuring that the clamping value and loop parameters are always matched during dynamic adjustment, and avoiding current limiting false triggering or over-suppression problems.

[0109] In one example, the method further includes a symmetric output lower limit clamping step: Using the same current superposition-voltage conversion logic as the upper limit clamp, the current limiting reference current is replaced with the lowest static power consumption reference current to generate the lower limit clamp voltage, which limits the lower limit of the error amplifier output voltage; When the load changes from light load to heavy load and the error amplifier EA output undershoots, the lower limit clamp is triggered to prevent the error amplifier EA from entering the negative saturation region, shorten the recovery time of the heavy load transient, and at the same time ensure that the minimum static power consumption of the converter meets the requirements.

[0110] In one example, the differential voltage compensation current in the method is proportional to the output voltage of the boost converter, so that the generated clamping voltage increases synchronously with the increase of the output voltage, matching the variation of the peak value of the matching inductor current with the output voltage.

[0111] It should be noted that the higher the output voltage and the larger the boost ratio, the higher the peak inductor current, and the higher the steady-state output value of the error amplifier EA. The synchronously increasing clamping voltage can ensure that the loop has sufficient dynamic range and will not limit the transient response capability due to the clamping value being too low.

[0112] The lower the output voltage and the smaller the boost ratio, the lower the clamping voltage will be, ensuring effective suppression of overshoot and achieving adaptive optimal clamping effect across the entire boost ratio range.

[0113] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by instruction-related hardware, and the instructions can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, and optical disk, etc.

[0114] In summary, the dynamic clamping method for a boost converter loop provided in this embodiment is not limited to specific hardware structures such as PMOS direct drive and operational amplifier negative feedback. It can be adapted to various clamping execution architectures and can also be extended to clamping schemes implemented with digital control and software algorithms, thus covering a wider range. It can be directly mapped to the control logic of analog power supply chips and can also be ported to the control algorithms of digital power supplies, demonstrating strong adaptability for implementation.

[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A dynamic clamping circuit for a boost converter loop, characterized in that, The dynamic clamping circuit includes a clamping voltage generation module and a clamping execution module; The clamping voltage generation module is configured to: receive the current limiting reference current signal output by the current limiting protection circuit, the slope compensation current signal output by the slope compensation circuit, and the differential voltage compensation current signal related to the input-output voltage difference of the boost converter; and superimpose the current limiting reference current signal, the slope compensation current signal, the differential voltage compensation current signal, and the bias current with the bias current, and then convert them through the first resistor network to generate the first clamping voltage. The clamping execution module is configured to apply the first clamping voltage to the output of the error amplifier to limit the upper limit of the output voltage of the error amplifier.

2. The dynamic clamping circuit according to claim 1, characterized in that, The clamping execution module includes a first PMOS transistor, the source of which is connected to the output of the error amplifier, the gate of which receives the first clamping voltage, and the drain of which is grounded through a second resistor. When the output voltage of the error amplifier exceeds the sum of the absolute values ​​of the first clamping voltage and the gate-source voltage of the first PMOS transistor, the first PMOS transistor is turned on, clamping the output voltage of the error amplifier to the target upper limit value.

3. The dynamic clamping circuit according to claim 1, characterized in that, The clamping execution module includes a first operational amplifier and a first NMOS transistor; The non-inverting input of the first operational amplifier is connected to the output of the error amplifier, the inverting input is connected to the first clamping voltage, and the output is connected to the gate of the first NMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the error amplifier, and the source is grounded; The first operational amplifier and the first NMOS transistor form a negative feedback loop. When the output voltage of the error amplifier exceeds the first clamping voltage, the first operational amplifier outputs a high level to drive the first NMOS transistor to turn on, thereby pulling the output voltage of the error amplifier down to the first clamping voltage.

4. The dynamic clamping circuit according to claim 1, characterized in that, The clamping voltage generation module includes a fifth resistor, a fourth resistor, a first bias current source, a first current-limiting reference current source, a first slope compensation current source, and a first differential voltage compensation current source. The first end of the fifth resistor is connected to the first node, and the second end is connected to the second node; The first end of the fourth resistor is connected to the second node, and the second end is grounded. The output of the first bias current source is connected to the second node; The outputs of the first current-limiting reference current source, the first slope compensation current source, and the first differential pressure compensation current source are all connected to the first node; The first clamping voltage is determined by the voltage division effect of the fourth and fifth resistors on the superimposed current.

5. The dynamic clamping circuit according to claim 2, characterized in that, The error amplifier output voltage is clamped to the target upper limit value in accordance with the calculation formula: V clamp_max =R4I bias0 +(R4+R5)(I limit_max +I cmpst0 +I diffV )+∣V gs0 ∣ In the formula, V clamp_max R4 is the target upper limit value for the output voltage clamping of the error amplifier, R5 is the resistance value of the fourth resistor, and I is the resistance value of the fifth resistor. bias0 I is the output current of the first bias current source. limit_max I is the output current of the first current-limiting reference current source. cmpst0 I is the output current of the first slope compensation current source. diffV The output current of the first differential pressure compensation current source is |V gs0 | represents the absolute value of the gate-source voltage of the first PMOS transistor.

6. The dynamic clamping circuit according to claim 1, characterized in that, It also includes a dynamic compensation branch, which includes a second clamping voltage generation module and a second clamping execution module; The second clamping voltage generation module is configured to: receive the second current-limiting reference current signal, the second slope compensation current signal, and the differential voltage compensation current signal that are dynamically adjusted with the boost converter's slope compensation, and generate the second clamping voltage through the second resistor network; The second clamping execution module is a PMOS transistor direct drive structure or an operational amplifier and NMOS transistor negative feedback structure. It applies the second clamping voltage to the output of the error amplifier and synchronously adjusts the upper limit clamping value when the boost converter adopts dynamic slope compensation.

7. The dynamic clamping circuit according to claim 6, characterized in that, The second resistor network includes a seventh resistor and a sixth resistor, wherein the first end of the seventh resistor is connected to the third node and the second end is connected to the fourth node; The first end of the sixth resistor is connected to the fourth node, and the second end is grounded. When the second clamping execution module is a PMOS transistor direct-drive structure, the second clamping voltage satisfies the formula: V clamp_dr =R6I bias1 +(R6+R7)(I limit_dr +I cmpst1 +I diffV )+∣V gs1 ∣ When the second clamping execution module is a negative feedback structure of an operational amplifier and an NMOS transistor, the second clamping voltage satisfies the formula: V clamp_dr =R6I bias1 +(R6+R7)(I limit_dr +I cmpst1 +I diffV ) In the formula, V clamp_dr This is the second clamping voltage, R6 is the resistance of the sixth resistor, R7 is the resistance of the seventh resistor, and I... bias1 I is the output current of the second bias current source. limit_dr I is the second current-limiting reference current. cmpst1 For the second slope compensation current, I diffV For differential pressure compensation current, |V gs1 | is the second PMOS transistor M p1 The absolute value of the gate-source voltage.

8. The dynamic clamping circuit according to claim 1, characterized in that, It also includes a lower clamping circuit configured to limit the lower limit of the error amplifier output voltage; The lower clamping circuit includes a lower clamping voltage generation module and a lower clamping execution module; The lower clamping voltage generation module and the clamping voltage generation module have a symmetrical topology. The current limiting reference current signal is replaced with a reference current signal corresponding to the lowest static power consumption, and the resistor network is adjusted accordingly to generate the lower clamping voltage.

9. The dynamic clamping circuit according to claim 1, characterized in that, The differential voltage compensation current signal is proportional to the output voltage of the boost converter, so that the first clamping voltage increases as the output voltage increases, in order to match the variation of the peak inductor current with the output voltage and adapt to the clamping requirements under different boost ratio conditions.

10. A boost converter, characterized in that, It includes an error amplifier, a power stage main circuit, a current limiting protection circuit, and a slope compensation circuit, as well as a dynamic clamping circuit for a boost converter loop as described in any one of claims 1 to 9. The dynamic clamping circuit is connected in parallel to the output of the error amplifier to dynamically limit the upper limit of the output voltage of the error amplifier and suppress loop over-response when the boost converter load jumps and the output voltage is dynamically adjusted.

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