A short circuit protection circuit and method applied to a direct current step-down switching power supply

Abstract

The application relates to the technical field of power management chips, in particular to a short-circuit protection circuit and method applied to a direct-current step-down switching power supply. N The circuit comprises an overcurrent comparator, a logic drive module, a latch, an M-bit counter, an N-bit counter and an N-2 N bit counter. The overcurrent detection signal is synchronized with the clock signal by introducing the latch and the M-bit counter, and the Hiccup mode is triggered only when the overcurrent signal of M continuous periods is detected. Meanwhile, the N-bit counter, the N-2 N bit counter and the VDAC make the overcurrent reference level start to be stepped up period by period from the lowest value when the Hiccup mode is exited, the inductance current is limited period by period, abnormal current spikes are avoided, smooth transition when entering and exiting the Hiccup mode is realized, and the safety of power switch tubes and other components is protected.

Description

Technical Field

[0001] This invention belongs to the field of power management chip technology, specifically a short-circuit protection circuit and method for DC buck switching power supplies. Background Technology

[0002] With the rapid development of modern industrial electronics technology, high-performance applications are becoming increasingly widespread, covering areas such as server arrays, data storage systems, telecommunications base stations, and embedded computing. These applications generate significant demand for switching power supply chips with high switching frequencies, high voltages, and high load currents, while the requirements for output stability of these chips are also increasing. To meet short-circuit protection requirements, switching power supply chips typically employ Hiccup mode as their core protection mechanism. This mode enables the chip to enter a periodic restart state when an output short circuit or overcurrent is detected, effectively limiting power loss and protecting downstream loads.

[0003] The control structure of existing DC buck switching power supplies is as follows: Figure 1 As shown, the main components include an error amplifier EA, a PWM comparator CMP1, an overcurrent comparator CMP2, a reset comparator CMP3, a current sensing module CS, a clock oscillation module OSC, a logic driver module CLD, and core components such as the upper power transistor Mhpwr and the lower power transistor Mlpwr. The current sensing module CS outputs a detection signal IL*Rsns, which also serves as the input to both the PWM comparator CMP1 and the overcurrent comparator CMP2. The feedback voltage from the DC-DC buck switching power supply is compared and amplified with the reference level Vref_fb via the FB pin to generate an error level Vc. This error level Vc is supplied to the PWM comparator CMP1 to generate a PWM signal Vpwm, which is then output to the logic driver module CLD. The clock signal generated by the clock oscillation module OSC synchronously controls the output of the logic driver module CLD, thereby controlling the on / off state of the upper power transistor Mhpwr and the lower power transistor Mlpwr, respectively.

[0004] For overcurrent protection, a fixed overcurrent reference level Vref_oc serves as the inverting input of the overcurrent comparator CMP2, generating an overcurrent shutdown signal Voc. When the inductor current IL exceeds the limit, Voc generates a high-level signal asynchronous with CLK, causing the Hiccup signal Vhic to flip from low to high and output to the logic driver module CLD. This puts the DC-DC buck switching power supply into Hiccup mode, simultaneously turning off the upper power transistor Mhpwr and the lower power transistor Mlpwr, and the output voltage VOUT begins to drop. When the output voltage VOUT drops below the reset reference level Vref_rst, the reset comparator CMP3 outputs Vrst high, causing the Hiccup signal of the SR latch to flip low, and the DC-DC buck switching power supply exits Hiccup mode and returns to normal operation.

[0005] However, as Figure 2 As shown in the waveform timing diagram, traditional short-circuit protection methods have significant technical flaws. Under the existing protection mechanism, the system will immediately enter Hiccup mode upon the occurrence of a single overcurrent, and the generation of the overcurrent signal is independent of the clock signal. This asynchronous triggering mechanism makes the system highly susceptible to disturbances when entering and exiting Hiccup mode. More seriously, abnormally high inductor current spikes are easily generated when exiting Hiccup mode. These spike currents may damage the power switch and other components, while also causing abnormal fluctuations and oscillations in the output voltage. This severely affects the stable operation of the system, reduces the reliability of the chip, and poses a significant risk of downtime and damage to downstream load circuits.

[0006] Therefore, there is an urgent need for a low-cost, high-reliability short-circuit protection method and circuit that can ensure stable and safe operation when entering and exiting Hiccup mode. Summary of the Invention

[0007] The purpose of this invention is to address the problems of single overcurrent false triggering and current spikes and voltage oscillations when exiting Hiccup mode in the prior art, and to propose a short-circuit protection method and circuit for DC buck switching power supplies.

[0008] The technical solution of this invention is: In a first aspect, the present invention provides a short-circuit protection circuit for a DC buck switching power supply, comprising a main power circuit, a PWM control and overcurrent protection circuit, a continuous overcurrent counting and Hiccup mode control circuit, and a stepped soft recovery exit circuit; wherein... The main power circuit includes an input voltage terminal VIN, an upper power transistor Mhpwr, a lower power transistor Mlpwr, an inductor IL, and an output capacitor COUT. The source of the upper power transistor Mhpwr is connected to the input voltage terminal VIN of the DC-DC buck switching power supply, and the source of the lower power transistor Mlpwr is connected to the reference ground PGND of the DC-DC buck switching power supply. The drains of the upper power transistor Mhpwr and the lower power transistor Mlpwr are connected together as the output of the short-circuit protection circuit, which is connected to the inductor IL as the output voltage VOUT of the DC-DC buck switching power supply. The inductor IL is connected in series with the capacitor COUT and then connected to the reference ground PGND. The two ends of the capacitor COUT are connected in parallel with series sampling resistors RFB1 and RFB2. The connection point of the sampling resistors RFB1 and RFB2 serves as the feedback voltage FB of the DC-DC buck switching power supply. The PWM control and overcurrent protection circuit includes a current detection module CS, an error amplifier EA, a PWM comparator CMP1, an overcurrent comparator CMP2, a clock oscillation module OSC, and a logic driver module CLD. The signal input terminal of the current detection module CS is connected to the inductor IL to acquire the current detection signal IL*Rsns, and simultaneously outputs it to the non-inverting input terminals of the PWM comparator CMP1 and the overcurrent comparator CMP2. The non-inverting input terminal of the error amplifier EA receives the reference level Vref_fb, the inverting input terminal receives the feedback voltage FB, and outputs the error voltage Vc to the inverting input terminal of the PWM comparator CMP1. At the phase input terminal, the PWM comparator CMP1 outputs a PWM signal Vpwm to the logic driver module CLD; the inverting input terminal of the overcurrent comparator CMP2 is connected to the output terminal of the voltage output type digital-to-analog converter VDAC, receiving a variable overcurrent reference level Vref_oc, and the non-inverting input terminal receives the current detection signal IL*Rsns, outputting an overcurrent detection signal Voc_in synchronized to the latch and the logic driver module CLD; the clock signal CLK generated by the clock oscillation module OSC is synchronously output to the logic driver module CLD, the M-bit counter, and the N-bit counter; The continuous overcurrent counting and Hiccup mode control loop includes a latch, an M-bit counter, and an SR latch. The clock input terminal CK of the latch receives the clock signal CLK processed by the delay module. The output terminal Q of the latch is connected to the M-bit counter. The M-bit counter outputs an overcurrent shutdown signal Voc synchronized with the system clock signal CLK to the set terminal S of the SR latch, flipping the Hiccup signal Vhic output by the SR latch from low to high and outputting it to the logic driver module CLD, thus enabling the DC buck switching power supply to enter Hiccup mode. The reset terminal R of the SR latch is connected to the output of the stepped soft recovery exit loop, i.e., the reset signal Vrst, causing the Hiccup signal Vhic output by the SR latch to flip from high to low, thus enabling the DC buck switching power supply to exit Hiccup mode. The stepped soft recovery exit loop includes reset comparators CMP3 and N-2. N The system includes a decoder, an N-bit counter, and a voltage-output digital-to-analog converter (VDAC). The inverting input of the reset comparator CMP3 receives the feedback voltage FB and the reset reference level Vref_rst, outputting a reset signal Vrst to the reset terminal R of the SR latch. Simultaneously, the reset signal Vrst is connected to the reset terminal R of the N-bit counter, resetting its count value to the initial value of 0. The digital output of the N-bit counter is connected to N-2. N The input terminal of the decoder, the N-2N The decoder's output is connected to the input of the voltage-output digital-to-analog converter VDAC, namely N-2. N The decoder converts the count value of an N-bit counter into a switching control signal for the internal resistor network of a voltage-output digital-to-analog converter (VDAC). The VDAC includes a fixed-level voltage Vref_oc_in and a resistor network, wherein the fixed-level voltage Vref_oc_in is based on the N-2... N The decoder outputs a switch control signal, which outputs a variable overcurrent reference level Vref_oc to the inverting input of the overcurrent comparator CMP2. The logic drive module CLD receives the PWM signal Vpwm, the clock signal CLK, and the Hiccup signal Vhic output by the SR latch, and outputs drive signals to control the on and off of the upper power transistor Mhpwr and the lower power transistor Mlpwr, respectively.

[0009] Furthermore, the M-bit counter has M built-in counting stages, each corresponding to M consecutive overcurrent detection cycles; whenever the rising edge of the clock signal CLK arrives and the output of the latch is high, the counter value increments; only when an overcurrent signal of M consecutive cycles is detected will a valid high-level overcurrent shutdown signal Voc be output.

[0010] Furthermore, for the reset comparator CMP3, when the output voltage VOUT drops below the reset reference level Vref_rst, the output reset signal Vrst of the reset comparator CMP3 becomes high.

[0011] Furthermore, the N-2 N The decoder uses a binary decoder structure to decode the N-bit binary count value of the N-bit counter into 2. N Each of the two independent control signals controls the internal resistor network of the VDAC. N A simulated switch.

[0012] Furthermore, in the voltage output type digital-to-analog converter VDAC, the resistor network adopts a resistor series voltage divider structure, consisting of 2... N It consists of a series of equal-value resistors, with each voltage divider node on the resistor series connected in series with a switch and then connected to the output of the VDAC. The N-2 N Decoder output 2 N An independent control signal is used to select the switches of different voltage divider nodes in the resistor series, and output overcurrent reference levels Vref_oc of different amplitudes.

[0013] Secondly, the present invention provides a short-circuit protection method for DC buck switching power supplies, comprising the following steps: S1. Current detection and PWM modulation steps: The inductor current of the DC buck switching power supply is detected by the current detection module CS to obtain the current detection signal IL·Rsns; the feedback voltage FB is compared and amplified with the reference level Vref_fb by the error amplifier EA to generate the error voltage Vc; the PWM comparator CMP1 generates the PWM signal Vpwm based on the error voltage Vc and the current detection signal IL·Rsns to control the conduction and cutoff of the upper power transistor Mhpwr and the lower power transistor Mlpwr. S2. Overcurrent detection step: The current detection signal IL·Rsns is compared with the variable overcurrent reference level Vref_oc by the overcurrent comparator CMP2 to generate the overcurrent detection signal Voc_in; S3. Steps for entering Hiccup mode via continuous overcurrent counting: Input the overcurrent detection signal Voc_in into the latch and sample and latch it under the synchronization of the clock signal CLK; perform continuous periodic counting on the latched overcurrent signal, and when the continuous overcurrent period reaches a preset M, generate a high-level overcurrent shutdown signal Voc synchronized with the clock signal CLK; generate a high-level Hiccup signal Vhic based on the overcurrent shutdown signal Voc, and control the upper power transistor and the lower power transistor to turn off simultaneously, so that the DC buck switching power supply enters Hiccup mode; S4. Steps to exit Hiccup mode: Monitor whether the output voltage VOUT is lower than the reset reference level Vref_rst by resetting comparator CMP3. If it is, turn the Hiccup signal Vhic low to make the DC buck switching power supply exit Hiccup mode and return to normal working mode.

[0014] Furthermore, upon exiting Hiccup mode, the count value of the N-bit counter is reset to the initial value of 0, causing the variable overcurrent reference level Vref_oc output by VDAC to be instantly pulled down to the lowest value; Then, the N-bit counter increments from its initial value of 0 cycle by cycle under the drive of the clock signal CLK. The voltage output type digital-to-analog converter VDAC raises the variable overcurrent reference level Vref_oc from its lowest value in a stepwise manner cycle by cycle. After N cycles, it recovers to the highest value during normal operation, which is equal to the highest value of the fixed level Vref_oc_in.

[0015] Furthermore, during the step recovery process of the overcurrent reference level Vref_oc, the peak value of the inductor current IL is limited to achieve cycle-by-cycle current limiting and avoid current spikes.

[0016] The beneficial effects of this invention are: This invention introduces a latch and an M-bit counter to synchronize the overcurrent detection signal with the clock signal CLK. The system is only triggered to enter Hiccup mode when an overcurrent signal is detected for M consecutive cycles, which effectively avoids false triggering caused by a single disturbance and improves the system's anti-interference capability and stability.

[0017] This invention introduces an N-bit counter and N-2... N The decoder and voltage output digital-to-analog converter VDAC, when exiting Hiccup mode, raises the overcurrent reference level Vref_oc from its lowest value in a step-by-cycle manner to limit the inductor current IL cycle by cycle, avoiding abnormal current spikes caused by excessively high error voltage Vc. The step-by-step soft recovery mechanism effectively prevents overcharging and oscillation of the output voltage VOUT, achieving a smooth transition when entering and exiting Hiccup mode, protecting the power switch and other components, and improving the reliability of the chip and the stability of the system.

[0018] This invention achieves a low-cost, high-reliability short-circuit protection scheme without significantly increasing circuit complexity, and has wide applicability.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0021] Figure 1 A schematic diagram of the control structure of an existing DC buck switching power supply is shown.

[0022] Figure 2 The waveform timing diagram of the control structure of an existing DC buck switching power supply is shown.

[0023] Figure 3 A schematic diagram of the control structure of the DC buck switching power supply of the present invention is shown.

[0024] Figure 4 The waveform timing diagram of the control structure of the DC buck switching power supply of the present invention is shown.

[0025] Figure 2In the diagram, position A1 represents the asynchronous overcurrent shutdown signal Voc and the Hiccup signal Vhic; position B1 indicates that the Hiccup mode is entered after a single overcurrent, making it susceptible to false disturbances; position C1 indicates that after exiting Hiccup mode, there is a large IL current spike, and the output voltage VOUT is prone to overcharging and oscillation.

[0026] Figure 4 In the diagram, position A2 indicates the overcurrent shutdown signal Voc and the Hiccup signal Vhic, which are synchronized with the clock signal CLK; position B2 indicates that Hiccup mode is entered only after M consecutive overcurrent events to avoid false disturbances; position C1 indicates that after exiting Hiccup mode, the overcurrent reference level Vref_oc has N steps to avoid overcharging of the output voltage VOUT. Detailed Implementation

[0027] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0028] like Figure 3 As shown, the short-circuit protection circuit and method for DC buck switching power supplies provided by this invention mainly includes four core parts: main power circuit, PWM control and overcurrent protection circuit, continuous overcurrent counting and Hiccup mode control circuit, and stepped soft recovery exit circuit.

[0029] The first part, the main power circuit, consists of the input voltage terminal VIN, the upper power transistor Mhpwr, the lower power transistor Mlpwr, the inductor IL, and the output capacitor COUT. The input voltage terminal VIN is connected to the source of the upper power transistor Mhpwr. The drain of the upper power transistor Mhpwr is connected to one end of the inductor IL and the drain of the lower power transistor Mlpwr. The source of the lower power transistor Mlpwr is connected to the reference ground PGND. The other end of the inductor IL serves as the output voltage terminal VOUT of the DC buck switching power supply and is also connected to the positive terminal of the output capacitor COUT. The negative terminal of the output capacitor COUT is connected to the reference ground PGND. This main power circuit constitutes a typical buck switching power supply topology. When the upper power transistor Mhpwr is turned on, the input voltage VIN charges the inductor IL through Mhpwr and provides energy to the output terminal, while simultaneously charging the output capacitor COUT. When the upper power transistor Mhpwr is turned off and the lower power transistor Mlpwr is turned on, the inductor IL releases energy through Mlpwr, maintaining a stable output voltage. The output capacitor COUT is connected in parallel with two series-connected sampling resistors RFB1 and RFB2. The connection point of sampling resistors RFB1 and RFB2 generates a feedback voltage FB, which is connected to the inverting input of the error amplifier EA.

[0030] The second part, the PWM control and overcurrent protection circuit, consists of a current detection module CS, an error amplifier EA, a PWM comparator CMP1, an overcurrent comparator CMP2, a clock oscillation module OSC, and a logic driver module CLD. The signal input of the current detection module CS is connected to the inductor IL, used to detect the inductor current IL and generate a current detection signal IL*Rsns. This current detection signal is simultaneously output to the non-inverting input of both the PWM comparator CMP1 and the overcurrent comparator CMP2. The non-inverting input of the error amplifier EA receives the reference level Vref_fb, and the inverting input receives the feedback voltage FB. The output of the error amplifier EA generates an error voltage Vc and outputs it to the inverting input of the PWM comparator CMP1.

[0031] The clock signal CLK generated by the clock oscillation module OSC is synchronously output to the logic drive module CLD, the M-bit counter, and the N-bit counter. The frequency of the clock signal CLK determines the operating frequency of the switching power supply.

[0032] The PWM comparator CMP1 compares the current detection signal IL*Rsns with the error voltage Vc and outputs the PWM signal Vpwm to the logic driver module CLD. The logic driver module CLD receives the PWM signal Vpwm, the clock signal CLK, and the Hiccup signal Vhic (described later), and outputs drive signals to control the on and off of the upper power transistor Mhpwr and the lower power transistor Mlpwr, respectively, to achieve closed-loop control in peak current mode.

[0033] The inverting input of the overcurrent comparator CMP2 receives a variable overcurrent reference level Vref_oc, and the non-inverting input receives a current detection signal IL*Rsns. When the current detection signal is higher than the overcurrent reference level, the overcurrent comparator CMP2 outputs an overcurrent detection signal Voc_in to the input D of the latch and the logic driver module CLD.

[0034] The third part, the continuous overcurrent counting and Hiccup mode control loop, consists of a latch, an M-bit counter, and an SR latch, which is one of the core innovative parts of this invention.

[0035] The latch's clock input CK receives the clock signal CLK processed by the delay module, the latch's input D receives the overcurrent detection signal Voc_in, and the latch's output Q is connected to the enable terminal of the M-bit counter.

[0036] The M-bit counter has M built-in counting stages, each corresponding to one of the M consecutive overcurrent detection cycles. The counter increments whenever the rising edge of the clock signal CLK arrives and the output Q of the latch is high. When the overcurrent signal is interrupted (i.e., the output Q of the latch goes low), the counter is reset and starts counting again. Only when an overcurrent signal is detected for M consecutive cycles, i.e., when the counter value reaches M, does the M-bit counter output a valid high-level overcurrent shutdown signal Voc to the set terminal S of the SR latch.

[0037] The output terminal Q of the SR latch outputs the Hiccup signal Vhic to the logic driver module CLD. When the overcurrent shutdown signal Voc sets the SR latch, the Hiccup signal Vhic flips from low level to high level. After receiving the high-level Hiccup signal Vhic, the logic driver module CLD controls the upper power transistor Mhpwr and the lower power transistor Mlpwr to turn off simultaneously, and the DC buck switching power supply enters Hiccup mode.

[0038] This invention synchronizes the overcurrent detection signal with the clock signal CLK by introducing a latch and an M-bit counter. Furthermore, it triggers the Hiccup mode only when an overcurrent signal is detected for M consecutive cycles, effectively avoiding false triggering caused by a single disturbance and improving the system's anti-interference capability and stability. The specific value of M can be set according to the anti-interference requirements of the actual application scenario. For example, a larger M value can be set in industrial power supply applications with strong interference to improve reliability, while a smaller M value can be set in consumer electronics applications with less interference to improve response speed.

[0039] Part Four, the stepped soft recovery exit loop consists of the reset comparator CMP3, the N-bit counter, and N-2. N The decoder and voltage-output digital-to-analog converter VDAC constitute the core innovation of this invention. The inverting input of the reset comparator CMP3 receives the feedback voltage FB, and the non-inverting input receives the reset reference level Vref_rst. When the output voltage VOUT drops below the reset reference level Vref_rst, i.e., when the feedback voltage FB is lower than Vref_rst, the output reset signal Vrst of the reset comparator CMP3 becomes high. The reset signal Vrst is connected to the reset terminal R of the SR latch, causing the Hiccup signal Vhic output by the SR latch to flip from high to low, thus exiting the Hiccup mode and resuming normal operation.

[0040] Simultaneously, the reset signal Vrst is connected to the reset terminal R of the N-bit counter, resetting the counter's count value to its initial value of 0. The digital output terminal of the N-bit counter is connected to N-2. NThe input terminal of the decoder, N-2 N The decoder's output is connected to the input of a voltage-output digital-to-analog converter (VDAC). N-2 N The decoder uses a binary decoder structure to decode the N-bit binary count value of the N-bit counter into 2. N Each of the two independent control signals controls the internal resistor network of the VDAC. N A simulated switch.

[0041] The voltage-output digital-to-analog converter (VDAC) consists of a fixed-level resistor (Vref_oc_in) and a resistor network. The resistor network employs a resistor series voltage divider structure, consisting of 2... N The system consists of several equal-value resistors connected in series. A switch is connected in series at each of the different voltage divider nodes on the resistor string, and then connected to the output of the VDAC. N-2 N The decoder output 2 N Each independent control signal selects a switch with different voltage divider nodes connected in series with a resistor, thereby outputting an overcurrent reference level Vref_oc of different amplitudes to the inverting input of the overcurrent comparator CMP2. The overcurrent reference level Vref_oc output by VDAC is compared with the count value of the N-bit counter. n Satisfying the relation:

[0042] in, n The value range is 1 to 2. N ,when When Vref_oc outputs the lowest value; when When Vref_oc outputs its highest value, that is, the fixed level Vref_oc_in.

[0043] Upon exiting Hiccup mode, the reset signal Vrst resets the N-bit counter to its initial value of 0, causing the variable overcurrent reference level Vref_oc output by the VDAC to momentarily drop to its lowest value. Then, driven by the clock signal CLK, the N-bit counter increments cycle by cycle from its initial value of 0. The voltage output digital-to-analog converter VDAC raises the variable overcurrent reference level Vref_oc from its lowest value in a step-like manner cycle by cycle, restoring it to its highest value during normal operation after N cycles, which is equal to the highest value of the fixed level Vref_oc_in.

[0044] During the stepped recovery process of the overcurrent reference level Vref_oc, the overcurrent comparator CMP2 compares the current sensing signal IL*Rsns with the progressively raised overcurrent reference level Vref_oc, thereby limiting the inductor current IL cycle by cycle and avoiding current spikes. This stepped soft recovery mechanism effectively prevents overcharging and oscillation of the output voltage VOUT, achieving a smooth transition when entering and exiting Hiccup mode.

[0045] Under the short-circuit protection circuit of this invention, when entering Hiccup mode, the continuous M-cycle counting of the M-bit counter filters out single disturbance signals, significantly enhancing the system's anti-interference capability and eliminating the frequent entry into Hiccup mode due to single overcurrent false triggering found in traditional technologies. When exiting Hiccup mode, the overcurrent reference level Vref_oc rises stepwise from its lowest value, and the inductor current IL is limited to the corresponding overcurrent threshold range within each step cycle, preventing abnormal current spikes caused by excessively high error voltage Vc found in traditional technologies. The output voltage VOUT exhibits a smooth recovery process without severe fluctuations or oscillations. This smooth transition into and out of Hiccup mode effectively protects key electronic components such as power switches and output capacitors from overcurrent impacts, extending the lifespan of the chip and the entire power supply system. It also reduces interference and damage risks to downstream load circuits, improving the overall system's operational stability.

[0046] N-bit counter and N-2 N The decoder combination implements digital control of the overcurrent reference level. In this embodiment, the value of N can be optimized according to the accuracy requirements and response speed of the overcurrent protection. A longer counter bit width can achieve finer step resolution, but requires more recovery cycles; a shorter counter bit width has a faster recovery speed but coarser step size. Preferably, N is an integer between 4 and 8, which achieves a good balance between recovery speed and resolution.

[0047] The method of the present invention specifically includes the following steps: S1. Current detection and PWM modulation steps: The inductor current of the DC buck switching power supply is detected by the current detection module CS to obtain the current detection signal IL·Rsns; the feedback voltage FB is compared and amplified with the reference level Vref_fb by the error amplifier EA to generate the error voltage Vc; the PWM comparator CMP1 generates the PWM signal Vpwm based on the error voltage Vc and the current detection signal IL·Rsns to control the conduction and cutoff of the upper power transistor Mhpwr and the lower power transistor Mlpwr. S2. Overcurrent detection step: The current detection signal IL·Rsns is compared with the variable overcurrent reference level Vref_oc by the overcurrent comparator CMP2 to generate the overcurrent detection signal Voc_in; S3. Steps for entering Hiccup mode via continuous overcurrent counting: Input the overcurrent detection signal Voc_in into the latch and sample and latch it under the synchronization of the clock signal CLK; perform continuous periodic counting on the latched overcurrent signal, and when the continuous overcurrent period reaches a preset M, generate a high-level overcurrent shutdown signal Voc synchronized with the clock signal CLK; generate a high-level Hiccup signal Vhic based on the overcurrent shutdown signal Voc, and control the upper power transistor and the lower power transistor to turn off simultaneously, so that the DC buck switching power supply enters Hiccup mode; S4. Steps to exit Hiccup mode: Monitor whether the output voltage VOUT is lower than the reset reference level Vref_rst by resetting comparator CMP3. If it is, turn the Hiccup signal Vhic low to make the DC buck switching power supply exit Hiccup mode and return to normal working mode.

[0048] Upon exiting Hiccup mode, the N-bit counter is reset to its initial value of 0, causing the variable overcurrent reference level Vref_oc output by the VDAC to momentarily drop to its lowest value. Then, driven by the clock signal CLK, the N-bit counter increments cycle by cycle from its initial value of 0. The voltage output digital-to-analog converter VDAC raises the variable overcurrent reference level Vref_oc from its lowest value in a step-like manner, recovering to its highest value during normal operation after N cycles. During the step-like recovery process of the overcurrent reference level Vref_oc, the peak value of the inductor current IL is limited, achieving cycle-by-cycle current limiting and preventing current spikes.

[0049] like Figure 4 The waveform timing diagram of the present invention is shown below: The fixed-level Vref_oc_in is output via VDAC, and the variable overcurrent reference level Vref_oc is used as the inverting input of CMP2 to generate the signal Voc_in. In normal operating mode, Vref_oc is at its highest value and equals Vref_oc_in.

[0050] If an inductor current IL overcurrent occurs, Voc_in jumps from low to high, inputting to the latch and M-bit counter. Only when continuous overcurrent exceeds M cycles is a high-level overcurrent shutdown signal Voc, synchronized with CLK, generated. This causes the Hiccup signal Vhic to jump from low to high and output to CLD, putting the DC buck power supply into Hiccup mode. The upper power transistor Mhpwr and the lower power transistor Mlpwr are simultaneously turned off, and the output voltage VOUT begins to decrease. The system enters Hiccup mode synchronously with CLK after M overcurrent cycles, avoiding false triggering caused by disturbances and preventing system oscillations and safety hazards.

[0051] When VOUT drops below the reset reference level Vref_rst, the output Vrst of the reset comparator CMP3 goes high, and Vhic flips from high to low, causing the DC buck power supply to exit Hiccup mode and return to normal operation. At this time, the output of the N-bit counter is also reset to 0 by Vrst, making the Vref_oc output by VDAC the lowest value. Then, Vref_oc will be raised cycle by cycle through the N-bit counter and VDAC, thereby limiting the inductor current IL cycle by cycle. This prevents abnormally high IL spikes due to excessively high Vc levels when exiting Hiccup mode, preventing abnormal fluctuations in the output voltage VOUT, ensuring smooth mode switching, protecting component safety and system stability.

[0052] As the process continues, Vref_oc rises back to its highest value Vref_oc_in after N cycles, thus bringing the overcurrent threshold back to the normal operating range, preventing subsequent impact on the normal operation of the system and improving its versatility.

[0053] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A short-circuit protection circuit for a DC step-down switching power supply, characterized in that, This includes the main power circuit, PWM control and overcurrent protection circuit, continuous overcurrent counting and Hiccup mode control circuit, and stepped soft recovery exit circuit; among which, The main power circuit includes an input voltage terminal VIN, an upper power transistor Mhpwr, a lower power transistor Mlpwr, an inductor IL, and an output capacitor COUT. The source of the upper power transistor Mhpwr is connected to the input voltage terminal VIN of the DC-DC buck switching power supply, and the source of the lower power transistor Mlpwr is connected to the reference ground PGND of the DC-DC buck switching power supply. The drains of the upper power transistor Mhpwr and the lower power transistor Mlpwr are connected together as the output of the short-circuit protection circuit, which is connected to the inductor IL as the output voltage VOUT of the DC-DC buck switching power supply. The inductor IL is connected in series with the capacitor COUT and then connected to the reference ground PGND. The two ends of the capacitor COUT are connected in parallel with series sampling resistors RFB1 and RFB2. The connection point of the sampling resistors RFB1 and RFB2 serves as the feedback voltage FB of the DC-DC buck switching power supply. The PWM control and overcurrent protection circuit includes a current detection module CS, an error amplifier EA, a PWM comparator CMP1, an overcurrent comparator CMP2, a clock oscillation module OSC, and a logic driver module CLD. The signal input terminal of the current detection module CS is connected to the inductor IL to acquire the current detection signal IL*Rsns, and simultaneously outputs it to the non-inverting input terminals of the PWM comparator CMP1 and the overcurrent comparator CMP2. The non-inverting input terminal of the error amplifier EA receives the reference level Vref_fb, the inverting input terminal receives the feedback voltage FB, and outputs the error voltage Vc to the inverting input terminal of the PWM comparator CMP1. At the phase input terminal, the PWM comparator CMP1 outputs a PWM signal Vpwm to the logic driver module CLD; the inverting input terminal of the overcurrent comparator CMP2 is connected to the output terminal of the voltage output type digital-to-analog converter VDAC, receiving a variable overcurrent reference level Vref_oc, and the non-inverting input terminal receives the current detection signal IL*Rsns, outputting an overcurrent detection signal Voc_in synchronized to the latch and the logic driver module CLD; the clock signal CLK generated by the clock oscillation module OSC is synchronously output to the logic driver module CLD, the M-bit counter, and the N-bit counter; The continuous overcurrent counting and Hiccup mode control loop includes a latch, an M-bit counter, and an SR latch. The clock input terminal CK of the latch receives the clock signal CLK processed by the delay module. The output terminal Q of the latch is connected to the M-bit counter. The M-bit counter outputs an overcurrent shutdown signal Voc synchronized with the system clock signal CLK to the set terminal S of the SR latch, flipping the Hiccup signal Vhic output by the SR latch from low to high and outputting it to the logic driver module CLD, thus enabling the DC buck switching power supply to enter Hiccup mode. The reset terminal R of the SR latch is connected to the output of the stepped soft recovery exit loop, i.e., the reset signal Vrst, causing the Hiccup signal Vhic output by the SR latch to flip from high to low, thus enabling the DC buck switching power supply to exit Hiccup mode. The stepped soft recovery exit loop includes reset comparators CMP3 and N-2. N The system includes a decoder, an N-bit counter, and a voltage-output digital-to-analog converter (VDAC). The inverting input of the reset comparator CMP3 receives the feedback voltage FB and the reset reference level Vref_rst, outputting a reset signal Vrst to the reset terminal R of the SR latch. Simultaneously, the reset signal Vrst is connected to the reset terminal R of the N-bit counter, resetting its count value to the initial value of 0. The digital output of the N-bit counter is connected to N-2. N The input terminal of the decoder, the N-2 N The decoder's output is connected to the input of the voltage-output digital-to-analog converter VDAC, namely N-2. N The decoder converts the count value of an N-bit counter into a switching control signal for the internal resistor network of a voltage-output digital-to-analog converter (VDAC). The VDAC includes a fixed-level voltage Vref_oc_in and a resistor network, wherein the fixed-level voltage Vref_oc_in is based on the N-2... N The decoder outputs a switch control signal, which outputs a variable overcurrent reference level Vref_oc to the inverting input of the overcurrent comparator CMP2. The logic drive module CLD receives the PWM signal Vpwm, the clock signal CLK, and the Hiccup signal Vhic output by the SR latch, and outputs drive signals to control the on and off of the upper power transistor Mhpwr and the lower power transistor Mlpwr, respectively.

2. The short-circuit protection circuit for a DC step-down switching power supply as described in claim 1, characterized in that, The M-bit counter has M built-in counting stages, each corresponding to M consecutive overcurrent detection cycles. The counter value increments whenever the rising edge of the clock signal CLK arrives and the output of the latch is high. Only when an overcurrent signal is detected for M consecutive cycles will a valid high-level overcurrent shutdown signal Voc be output.

3. The short-circuit protection circuit for a DC step-down switching power supply as described in claim 1, characterized in that, For the reset comparator CMP3, when the output voltage VOUT drops below the reset reference level Vref_rst, the output reset signal Vrst of the reset comparator CMP3 becomes high.

4. The short-circuit protection circuit for a DC buck switching power supply as described in claim 1, characterized in that, The N-2 N The decoder uses a binary decoder structure to decode the N-bit binary count value of the N-bit counter into 2. N Each of the two independent control signals controls the internal resistor network of the VDAC. N A simulated switch.

5. The short-circuit protection circuit for a DC buck switching power supply as described in claim 4, characterized in that, In the voltage output type digital-to-analog converter VDAC, the resistor network adopts a resistor series voltage divider structure, consisting of 2 N It consists of a series of equal-value resistors, with each voltage divider node on the resistor series connected in series with a switch and then connected to the output of the VDAC. The N-2 N Decoder output 2 N An independent control signal is used to select the switches of different voltage divider nodes in the resistor series, and output overcurrent reference levels Vref_oc of different amplitudes.

6. A short-circuit protection method applied to a DC step-down switching power supply, characterized in that, Includes the following steps: S1. Current detection and PWM modulation steps: The inductor current of the DC buck switching power supply is detected by the current detection module CS to obtain the current detection signal IL·Rsns; the feedback voltage FB is compared and amplified with the reference level Vref_fb by the error amplifier EA to generate the error voltage Vc; the PWM comparator CMP1 generates the PWM signal Vpwm based on the error voltage Vc and the current detection signal IL·Rsns to control the conduction and cutoff of the upper power transistor Mhpwr and the lower power transistor Mlpwr. S2. Overcurrent detection step: The current detection signal IL·Rsns is compared with the variable overcurrent reference level Vref_oc by the overcurrent comparator CMP2 to generate the overcurrent detection signal Voc_in; S3. Steps for entering Hiccup mode via continuous overcurrent counting: Input the overcurrent detection signal Voc_in into the latch and sample and latch it under the synchronization of the clock signal CLK; perform continuous periodic counting on the latched overcurrent signal, and when the continuous overcurrent period reaches a preset M, generate a high-level overcurrent shutdown signal Voc synchronized with the clock signal CLK; generate a high-level Hiccup signal Vhic based on the overcurrent shutdown signal Voc, and control the upper power transistor and the lower power transistor to turn off simultaneously, so that the DC buck switching power supply enters Hiccup mode; S4. Steps to exit Hiccup mode: Monitor whether the output voltage VOUT is lower than the reset reference level Vref_rst by resetting comparator CMP3. If it is, turn the Hiccup signal Vhic low to make the DC buck switching power supply exit Hiccup mode and return to normal working mode.

7. The short-circuit protection method for DC buck switching power supplies according to claim 6, characterized in that... ； When exiting Hiccup mode, the count value of the N-bit counter is reset to the initial value of 0, causing the variable overcurrent reference level Vref_oc of the VDAC output to be pulled down to the lowest value instantly; Then, the N-bit counter increments from its initial value of 0 cycle by cycle under the drive of the clock signal CLK. The voltage output type digital-to-analog converter VDAC raises the variable overcurrent reference level Vref_oc from its lowest value in a stepwise manner cycle by cycle. After N cycles, it recovers to the highest value during normal operation, which is equal to the highest value of the fixed level Vref_oc_in.

8. The short-circuit protection method for DC buck switching power supplies according to claim 6, characterized in that, During the step recovery process of the overcurrent reference level Vref_oc, the peak value of the inductor current IL is limited to achieve cycle-by-cycle current limiting and avoid current spikes.

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