A PWM control-based compatible resistive and capacitive load driving circuit

Abstract

The application relates to the technical field of electronic circuits, and provides a compatible resistance and capacitance load driving circuit based on PWM control, which comprises the following steps: when identifying the load type, a processor judges the load type according to the change trend of the load voltage under the action of a tentative PWM pulse sequence; when judging that the load is a capacitance load, the processor controls the conduction or shutdown of a power loop according to the comparison result of the load voltage value collected by a load voltage collection unit and a preset load voltage threshold value; and when judging that the load is a resistance load, the processor controls the conduction or shutdown of the power loop according to the comparison result of a current detection signal and a preset load current threshold value. The compatibility problem of the high-power loop capacitance load and resistance load during switching is solved, the load can be normally driven when the load is a resistance load light load or a capacitance load, and the load can be timely shut down for protection when the load is a resistance load overload.

Description

Technical Field

[0001] This invention relates to the technical field of electronic circuits, and more particularly to a PWM-based drive circuit compatible with resistive and capacitive loads. Background Technology

[0002] In high-power electronic equipment applications (such as DC power supplies and current distributors), the type of load connected to the output circuit is not fixed and often needs to be switched or used in a compatible manner between resistive and capacitive loads. However, the physical and electrical characteristics of the two types of loads are fundamentally different: at startup, capacitive loads, because the voltage across the capacitor cannot change abruptly, behave almost like a short circuit, generating an inrush current much higher than the steady-state operating value; while resistive loads, when overloaded, exhibit a steady-state operating current that continuously exceeds the rated range, causing the circuit to overheat. Traditional drive protection circuits are usually designed for only a single type of load, making it difficult to accommodate the different needs of both types of loads in multiple stages such as startup, operation, and fault protection. This can easily lead to situations where a capacitive load, during normal startup, causes a sudden large current to trigger the overcurrent protection, preventing the equipment from starting normally; or when a resistive load experiences an overload, the protection response is not timely, causing the power switching devices to operate under extreme conditions for extended periods, resulting in excessive temperature rise and ultimately permanent damage to the devices. Therefore, how to design a circuit scheme that can intelligently identify load types and provide differentiated driving and protection strategies according to different types has become a key technical problem that urgently needs to be solved in this field.

[0003] To address the aforementioned capacitive load driving and control issues, numerous existing technical solutions have been proposed, but each of these solutions has its own inherent drawbacks.

[0004] For example, in comparison, Reference 1 (CN103918181A) discloses a capacitive load driving circuit. Its core technology involves constructing a relatively complex switching waveform to slowly charge the load capacitor during the switching process, thereby suppressing the current spike at startup and achieving smooth driving of the capacitive load. However, this scheme has several shortcomings: First, the generation of its switching waveform relies on a relatively complex auxiliary control circuit, resulting in a cumbersome overall circuit structure that is not conducive to integration and cost control. Second, this circuit cannot effectively identify the load type; regardless of whether a resistive or capacitive load is connected, the same slow switching strategy is used. This not only leads to a slower switching speed and increased switching losses during normal operation of the resistive load, but also causes the switching transistor to operate in a non-ideal switching state for extended periods, significantly reducing its efficiency. In high-power applications, power loss is dissipated in large quantities as heat, causing serious heat dissipation problems and threatening system reliability and lifespan.

[0005] For example, reference 2 (CN101610041B) discloses a simplified capacitive load drive circuit, which uses PWM-controlled switching elements to drive the capacitive load and connects the load capacitor and inductor in parallel in the main circuit. Its working principle is as follows: during the switching transistor's conduction period, the power supply charges the parallel inductor; during the switching transistor's turn-off period, the inductor discharges the load capacitor through a freewheeling circuit, thereby achieving energy transfer and capacitor charging. While this topology simplifies the circuit to some extent, its core energy transfer path is highly dependent on the inductor's periodic charging and discharging process. The inductor itself has core losses and winding copper losses, resulting in relatively low energy conversion efficiency, and the heat generation problem remains prominent in high-power applications. More importantly, this circuit topology is essentially optimized for capacitive loads; when a resistive load is connected, its driving characteristics cannot match it, thus completely lacking the ability to drive resistive loads.

[0006] For example, in comparison, reference 3 (CN1536546A) discloses a capacitive load driving circuit and a plasma display device with the circuit. This scheme uses multiple PWM control signals to drive multiple power switches connected in series in the main circuit, and the switching timing is staggered through delay processing between the PWM control signals to reduce abnormal current spikes and electromagnetic noise caused by the load capacitor turning on. While this multi-stage delay control strategy is beneficial for improving the smoothness of capacitive load startup, its drawbacks are also significant: First, this scheme cannot distinguish between resistive and capacitive loads, and is still a dedicated design for capacitive loads; second, the introduction of multiple series switches in the main circuit, each requiring a corresponding delay circuit and driving circuit, results in an extremely complex overall circuit structure, a large number of components, and a decrease in system reliability and consistency. In addition, the simultaneous participation of multiple switches in high-frequency switching significantly increases the total switching loss. Under high-power operating conditions, the junction temperature of the devices rises rapidly, making heat dissipation design difficult and severely limiting its application in industrial high-power applications.

[0007] Based on the above analysis, the existing technologies have the following common problems in driving resistive and capacitive loads: (1) The circuit topology is complex and the number of components is large, which is not conducive to engineering implementation and cost control; (2) It is impossible to effectively identify the specific type of connected load, resulting in a single control strategy and the inability to make targeted adjustments according to the load characteristics; (3) The compatibility with resistive loads is generally poor, making it difficult to achieve efficient driving of two types of loads in the same circuit; (4) The overall system efficiency is low, and the heat generation is serious under high power conditions, which puts forward high requirements for thermal management design and limits the improvement of power density of the equipment.

[0008] Therefore, there is an urgent need to provide a drive circuit with a simple circuit structure that can automatically identify resistive and capacitive load types and set normal conduction conditions and overload protection thresholds for different load types. This will ensure smooth start-up of capacitive loads and efficient conduction of resistive loads, while achieving rapid shutdown protection during resistive overloads, thus comprehensively improving the safety, reliability, and adaptability of driving multiple types of loads in high-power circuits. Summary of the Invention

[0009] To address the aforementioned problems, the present invention aims to provide a PWM-based drive circuit compatible with both resistive and capacitive loads. This solves the compatibility issue when switching between capacitive and resistive loads in high-power circuits, enabling normal driving when the load is a lightly loaded resistive or capacitive load, and timely shutdown protection when the load is an overloaded resistive load.

[0010] The above-mentioned objective of this invention is achieved through the following technical solutions: A PWM-controlled, resistive-capacitive load drive circuit includes: Power circuit, used to provide electrical energy to the load; A load current acquisition unit, coupled to the power circuit, is used to acquire the load current and output a current detection signal; A load voltage acquisition unit is connected in parallel across the load to acquire the load voltage and output a voltage detection signal. A PWM drive unit, connected in the power circuit, is used to control the on / off state of the power circuit according to the PWM drive signal; and The processor is connected to the load current acquisition unit, the load voltage acquisition unit and the PWM drive unit respectively, and is used to output a tentative PWM pulse sequence, identify the load type as resistive load or capacitive load according to the current detection signal and the voltage detection signal, and control the PWM drive signal and the on / off of the power circuit according to the identification result; When identifying the load type, the processor acquires the rising edge response waveform of the load voltage during the operation of the trial PWM pulse sequence. When the load voltage shows a positive voltage overshoot at the rising edge and then exhibits an exponential decay trend, it is determined to be a capacitive load; when the load voltage shows a step rise at the rising edge without overshoot, it is determined to be a resistive load. The processor is further configured to: under the capacitive load condition, control the power circuit to be turned on or off based on the comparison result between the load voltage value collected by the load voltage acquisition unit and a preset load voltage threshold; and under the resistive load condition, control the power circuit to be turned on or off based on the comparison result between the current detection signal and a preset load current threshold to achieve overcurrent protection.

[0011] Furthermore, the PWM drive unit includes a switching transistor, a drive resistor R2, and a push-pull circuit; The input terminal of the push-pull circuit is connected to the processor to receive the PWM drive signal, and the output terminal of the push-pull circuit is connected to the gate of the switching transistor via the drive resistor R2. The drain of the switching transistor is connected to the current input terminal of the power circuit, and the source of the switching transistor is connected to one end of the load.

[0012] Furthermore, the push-pull circuit includes an NPN transistor Q1, a PNP transistor Q2, and a current-limiting resistor R3; The system power supply is connected to the collector of the NPN transistor Q1 and the emitter of the PNP transistor Q2 via the current-limiting resistor R3. The base of the NPN transistor Q1 is connected to the base of the PNP transistor Q2 and together they serve as the input terminal of the push-pull circuit. The emitter of the NPN transistor Q1 is connected to the collector of the PNP transistor Q2, and together they serve as the output terminal of the push-pull circuit.

[0013] Furthermore, the method for the processor to identify the load type includes: Output multiple tentative PWM pulses with increasing duration, and collect the voltage across the load Load at the end of each tentative PWM pulse; If the voltage across the load Load increases sequentially at each end time, then the load Load is determined to be a capacitive load. If the voltage across the load at each end time does not show a sequentially increasing relationship, then the load is determined to be a resistive load.

[0014] Furthermore, when the processor determines that the load is a capacitive load, it compares the collected load voltage with a preset load voltage threshold: If the load voltage is greater than the load voltage threshold, it is determined that the load capacitance value of the load is within the acceptable range, the processor controls the switching transistor to remain on, and the power circuit operates normally; If the load voltage is less than or equal to the load voltage threshold, it is determined that the load capacitance value of the load Load exceeds the acceptable range, the processor controls the switch to turn off, and the power circuit performs a protection shutdown.

[0015] Furthermore, when the processor determines that the load is a resistive load, it compares the current detection signal with a preset load current threshold: If the current detection signal is less than the load current threshold, the load is determined to be in a light load or rated operating state, the processor controls the switching transistor to remain on, and the power circuit operates normally. If the current detection signal is greater than the load current threshold, the load is determined to be in an overload state, the processor controls the switching transistor to turn off, and the power circuit performs a protection shutdown.

[0016] Furthermore, the logic for the processor to determine the load type and control the power circuit includes: when the voltage detection sequence shows an increasing trend and the load voltage is greater than the load voltage threshold, it is determined to be a capacitive load and the load capacitance is less than the load capacitance that can be tolerated. The processor controls the switching transistor to remain on, and the power circuit is normally on. When the voltage detection sequence shows an increasing trend and the load voltage is less than or equal to the load voltage threshold, it is determined to be a capacitive load with a load capacitance greater than the tolerable load capacitance. The processor controls the switching transistor to turn off, and the power circuit protection is turned off. When the voltage detection sequence does not show an increasing trend and the current detection signal is less than the load current threshold, it is determined to be a resistive load and the load current is less than the load current that can be tolerated. The processor controls the switching transistor to continue to conduct, and the power circuit conducts normally. When the voltage detection sequence does not show an increasing trend and the current detection signal is greater than the load current threshold, it is determined to be a resistive load and the load current is greater than the load current that can be tolerated. The processor controls the switching transistor to turn off and the power circuit protection to turn off.

[0017] Furthermore, the power circuit includes a power input terminal, a switching transistor, a sampling resistor R1, and a load Load. The power input terminal, the sampling resistor, the switching transistor, and the load are connected in series. One end of the sampling resistor R1 is connected to the positive terminal of the power supply of the power circuit, and the other end is connected to the drain of the switching transistor. The load is connected between the source of the switching transistor and the negative terminal of the power supply of the power circuit.

[0018] Furthermore, the load current acquisition unit includes the sampling resistor R1 and the load current acquisition circuit; The first end of the sampling resistor R1 is connected to the positive terminal of the power supply of the power circuit, and the second end is connected to the input terminal of the switching transistor of the PWM drive unit. The two ends of the sampling resistor R1 respectively output differential voltage signals to the load current acquisition circuit. The output of the load current acquisition circuit is connected to the processor, and outputs an analog signal representing the load current to the processor.

[0019] Furthermore, the load voltage acquisition unit includes a first voltage divider resistor R4, a second voltage divider resistor R5, and the processor; One end of the first voltage divider resistor R4 is connected to the output terminal of the switching transistor in the power circuit, and the other end is connected to one end of the second voltage divider resistor R5 and the processor, respectively. The other end of the second voltage divider resistor R5 is connected to the negative terminal of the power supply of the power circuit, and the processor receives the load voltage sampling signal after being divided by the first voltage divider resistor R4 and the second voltage divider resistor R5.

[0020] Compared with the prior art, the present invention has at least one of the following beneficial effects: (1) This invention identifies the load type by combining load current acquisition and load voltage acquisition, which can accurately distinguish between resistive loads and capacitive loads, thus making it suitable for driving the two different types of loads, resistive and capacitive. Regardless of the type of load, normal driving can be achieved through the same circuit, effectively solving the technical problem of single control strategy and poor compatibility caused by the inability to identify the load type in the prior art.

[0021] (2) The present invention sets different normal conduction and protection shutdown conditions for different load types. When the load is identified as a capacitive load, the power circuit is controlled to conduct or shut down according to the comparison result of the load voltage and the preset voltage threshold. When the load is identified as a resistive load, the power circuit is controlled to conduct or shut down according to the comparison result of the load current and the preset current threshold. This effectively prevents false shutdown caused by different load types. It ensures that the capacitive load will not be mistakenly judged as overload shutdown due to instantaneous surge current when it starts up, and ensures that the resistive load can be protected and shut down in a timely and reliable manner when it is truly overloaded. This significantly improves the protection accuracy and reliability of the circuit.

[0022] (3) The present invention can flexibly set the load capacitance of the capacitive load and the load current of the resistive load to protect the turn-off of the capacitive load. Users or designers can set the corresponding voltage threshold and current threshold respectively through the processor according to the load capacitance value and load current value required in the actual application scenario, so as to flexibly adapt to capacitive loads of different specifications and resistive loads of different power levels, greatly expanding the application range and adaptability of the circuit.

[0023] (4) The circuit structure of the present invention is simple. No inductor is used in the circuit, which avoids the inherent magnetic core loss and winding copper loss during the charging and discharging of the inductor. The energy conversion efficiency is high and the power loss is low, which is suitable for high power applications. At the same time, only a single N-channel MOS transistor is needed as a switching element in the main circuit. There is no need for multiple series switching transistors and complex delay circuits. The number of components is small, which helps to reduce production costs, improve system reliability and consistency, and facilitate engineering implementation and mass promotion. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the PWM-controlled compatible resistive and capacitive load drive circuit of the present invention. Figure 2 This is a waveform diagram of the resistive load (light load) PWM drive and load current sampling signal of the present invention; Figure 3 This is a waveform diagram of the resistive load (light load) PWM drive and load voltage signal of the present invention; Figure 4 This is a waveform diagram of the resistive load (overload) PWM drive and load current sampling signal of the present invention; Figure 5 This is a waveform diagram of the resistive load (overload) PWM drive and load voltage sampling signal of the present invention; Figure 6 This is a waveform diagram of the capacitive load PWM drive and load current sampling signal of the present invention; Figure 7 This is a waveform diagram of the capacitive load PWM drive and the load voltage sampling signal of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] The technical solution of this invention can be widely applied to power electronic devices such as DC power supplies and current distributors. To facilitate understanding of the embodiments of this invention, some terms used in the text are explained as follows: PWM (Pulse Width Modulation) is a modulation technique that controls the on and off times of power switching devices by adjusting the duty cycle of a pulse signal; push-pull circuit is a power amplifier circuit composed of complementary transistors, whose function is to improve the load-carrying capacity of the drive signal and ensure reliable operation of the subsequent switching transistors.

[0028] This invention employs a PWM pulse drive method, collecting load circuit current and load voltage to achieve timely overload protection, while allowing normal operation under light load conditions. By identifying the load type, it avoids false shutdown caused by excessive inrush current when the load is capacitive, ensuring normal equipment startup. It also provides timely shutdown protection after overload when the load is resistive, preventing the load circuit from remaining in an overload conducting state for an extended period, which could lead to excessive load current, overheating, and equipment damage.

[0029] The technical solution of the present invention will be described in detail below through specific embodiments: First Embodiment like Figure 1 As shown, this embodiment provides a PWM-controlled compatible resistive and capacitive load drive circuit, including: Power circuit, used to provide electrical energy to the load; A load current acquisition unit, coupled to the power circuit, is used to acquire the load current and output a current detection signal; a load voltage acquisition unit, connected in parallel across the load, is used to acquire the load voltage and output a voltage detection signal; a PWM drive unit, connected to the power circuit, is used to control the on / off state of the power circuit according to the PWM drive signal; and a processor, connected to the load current acquisition unit, the load voltage acquisition unit, and the PWM drive unit respectively, is used to output a tentative PWM pulse sequence, identify the load type as resistive or capacitive based on the current detection signal and the voltage detection signal, and control the PWM drive signal and the on / off state of the power circuit according to the identification result; wherein, when identifying the load type, the processor acquires the rising edge response waveform of the load voltage during the action of the tentative PWM pulse sequence. When the load voltage shows a positive voltage overshoot at the rising edge and then exhibits an exponential decay trend, it is determined to be a capacitive load; when the load voltage shows a step rise at the rising edge without overshoot, it is determined to be a resistive load; The processor is further configured to: under the capacitive load condition, control the power circuit to be turned on or off based on the comparison result between the load voltage value collected by the load voltage acquisition unit and a preset load voltage threshold; and under the resistive load condition, control the power circuit to be turned on or off based on the comparison result between the current detection signal and a preset load current threshold to achieve overcurrent protection.

[0030] Based on the above technical solution, the working principle of the present invention can be briefly explained as follows: The core of this embodiment lies in the processor actively outputting a series of tentative PWM pulse sequences to apply a series of PWM drive signals with increasing durations to the load, while simultaneously acquiring the response information of the load current and load voltage. Since the electrical response characteristics of resistive and capacitive loads under PWM drive are fundamentally different—the terminal voltage of a resistive load quickly stabilizes during the PWM high-level period and does not change significantly with the extension of the conduction time; while the terminal voltage of a capacitive load, due to the charging effect of the capacitor, gradually increases with the extension of the PWM high-level duration, exhibiting a specific exponential upward trend—the processor can accurately determine the type of load currently connected by analyzing the change pattern of the load voltage under the action of the tentative pulses. After identifying the load type, the processor employs differentiated protection and control strategies for capacitive and resistive loads respectively: When a capacitive load is identified, the processor focuses on whether the load capacitance exceeds the acceptable range. By comparing the sampled load voltage value with a preset voltage threshold, the processor determines the capacitance and controls the circuit's on / off state. When a resistive load is identified, the processor focuses on whether the load current is overloaded. By comparing the detected current value with a preset current threshold, the processor determines whether an overload has occurred and executes the corresponding protection action. This "identify type first, then differentiate control" mechanism allows the power circuit to effectively avoid false overcurrent protection triggering due to excessive inrush current when a capacitive load starts up, ensuring normal equipment startup. Simultaneously, it can promptly shut down the protection when a resistive load is truly overloaded, preventing the circuit from being in an overload state for an extended period and causing overheating and damage. This approach ensures safe and efficient driving for both types of loads.

[0031] In this embodiment, the power circuit includes a power input terminal, a switching transistor, a sampling resistor R1, and a load Load. The power input terminal, the sampling resistor R1, the switching transistor, and the load Load are connected in series. One end of the sampling resistor R1 is connected to the positive terminal of the power supply of the power circuit, and the other end is connected to the drain of the switching transistor. The load is connected between the source of the switching transistor and the negative terminal of the power supply of the power circuit. In this embodiment, the power input terminal is the positive terminal PWR of the power circuit, the switching transistor is an N-channel MOSFET M1, and the negative terminal of the power supply of the power circuit is the negative terminal GND of the power circuit.

[0032] Specifically, the power circuit in this embodiment consists of the positive terminal PWR of the power circuit power supply, the sampling resistor R1, the load Load, and the negative terminal GND of the power circuit power supply connected in series. In this embodiment, the power circuit constitutes the main power transmission channel of the entire drive circuit. It is formed by connecting the positive terminal PWR of the power circuit power supply, the sampling resistor R1, the load Load, and the negative terminal GND of the power circuit power supply in series, creating a complete current loop. The positive terminal PWR and the negative terminal GND of the power circuit power supply together provide the necessary power source for the load. The sampling resistor R1, connected in series in the loop, converts the load current into a voltage signal that can be acquired. The load Load is the actual connected electrical equipment, which can be either a resistive or capacitive load. This series structure has the advantages of a simple loop topology and consistent current across all components, ensuring that the current flowing through the sampling resistor R1 is always equal to the current flowing through the load Load under any operating condition. This provides accurate current detection data for the load current acquisition unit and lays the foundation for subsequent load type identification and overload protection control.

[0033] In this embodiment, the load current acquisition unit includes a sampling resistor R1, a load current acquisition circuit, and the processor; the first end of the sampling resistor R1 is connected to the positive terminal of the power supply of the power circuit, and the second end is connected to the input terminal of the switching transistor of the PWM drive unit. The two ends of the sampling resistor R1 respectively output differential voltage signals to the load current acquisition circuit; the output terminal of the load current acquisition circuit is connected to the processor and outputs an analog signal characterizing the load current to the processor.

[0034] Specifically, in this embodiment, one end of the sampling resistor R1 is connected to the positive terminal PWR of the power circuit power supply, and the other end is connected to the drain of the N-channel MOSFET M1. The two ends of the sampling resistor R1 output the high-side voltage signal V+ and the low-side voltage signal V- to the load current acquisition circuit, respectively. The output terminal of the load current acquisition circuit is connected to the processor and outputs the load current acquisition signal I_ADC to the processor.

[0035] The load current acquisition unit in this embodiment is responsible for real-time monitoring of the load current in the power circuit. It consists of three parts: a sampling resistor R1, a load current acquisition circuit, and a processor. The sampling resistor R1 is a high-precision alloy resistor, connected in series on the high-voltage side of the power circuit. That is, one end of it is connected to the positive terminal PWR of the power supply of the power circuit, and the other end is connected to the drain of the N-channel MOSFET M1. This connection method is often referred to as a high-side current sampling structure. Its advantage is that it is not affected by the load grounding method and can obtain a more stable and accurate current signal. The high-side voltage signal V+ and the low-side voltage signal V- of the sampling resistor are respectively led out from the two ends of the sampling resistor R1 to the load current acquisition circuit. V+ reflects the potential of the sampling resistor near the positive terminal of the power supply, and V- reflects the potential of the sampling resistor near the drain of M1. The difference between the two is the voltage drop across the sampling resistor. This voltage drop is proportional to the current flowing through the sampling resistor (following Ohm's law). After receiving V+ and V-, the load current acquisition circuit performs differential amplification, filtering, and analog-to-digital conversion on them, converting them into a load current acquisition signal I_ADC that the processor can recognize, and then outputs it to the processor. Through this signal link, the processor can obtain the load current value in the current power circuit in real time, providing accurate data support for subsequent resistive load overload detection.

[0036] In this embodiment, the load voltage acquisition unit includes a first voltage divider resistor R4, a second voltage divider resistor R5, and the processor; one end of the first voltage divider resistor R4 is connected to the output terminal of the switching transistor in the power circuit, and the other end is connected to one end of the second voltage divider resistor R5 and the processor respectively; the other end of the second voltage divider resistor R5 is connected to the negative terminal of the power supply of the power circuit, and the processor receives the load voltage sampling signal after being divided by the first voltage divider resistor R4 and the second voltage divider resistor R5.

[0037] Specifically, the load voltage acquisition unit in this embodiment includes a first voltage divider resistor R4, a second voltage divider resistor R5, a filter capacitor C1, a Zener diode D1, and the processor; One end of the first voltage divider resistor R4 is connected to the source of the N-channel MOSFET M1, and the other end is connected to one end of the second voltage divider resistor R5, one end of the filter capacitor C1, the cathode of the Zener diode D1, and the processor, respectively. The other end of the second voltage divider resistor R5, the other end of the filter capacitor C1, and the anode of the Zener diode D1 are all connected to the negative terminal GND of the power circuit power supply, and the processor receives the load voltage acquisition signal LV_ADC.

[0038] The load voltage acquisition unit in this embodiment is used to monitor the voltage across the load in real time, thereby providing crucial data support for capacitive load identification and voltage threshold comparison. It consists of a first voltage divider resistor R4, a second voltage divider resistor R5, a filter capacitor C1, a Zener diode D1, and a processor. One end of the first voltage divider resistor R4 is connected to the source of the N-channel MOSFET M1; this node represents the potential at the upper end of the load (Load). The lower end of the load (Load) is connected to the negative terminal of the power supply (GND) in the power circuit. Therefore, the potential difference between this node and GND is essentially the voltage across the load. Since this voltage may be higher than the withstand voltage of the processor's ADC port, a resistor divider network is formed by the voltage divider resistors R4 and R5 to reduce the load voltage to a range acceptable to the processor according to a preset ratio. The voltage signal after voltage division is filtered by the filter capacitor C1 to remove high-frequency switching noise and interference, making the voltage signal sent to the processor smoother and more stable. Zener diode D1 is connected between the processor input and GND, acting as a clamping protection. When an abnormal situation causes the voltage after voltage division to exceed the breakdown voltage of the Zener diode, Zener diode D1 conducts and clamps the voltage within a safe range, effectively preventing overvoltage damage to the processor port. The signal after voltage division, filtering, and clamping protection is sent to the processor as the load voltage acquisition signal LV_ADC. The processor can use this signal to determine the current voltage across the load. Furthermore, considering the exponential increase in voltage over time during capacitive load charging, the processor identifies the load type and executes corresponding on / off control logic based on the comparison with a preset voltage threshold.

[0039] In this embodiment, the PWM drive unit includes a switching transistor, a drive resistor R2, and a push-pull circuit; the input terminal of the push-pull circuit is connected to the processor to receive the PWM drive signal, and the output terminal of the push-pull circuit is connected to the gate of the switching transistor via the drive resistor R2; the drain of the switching transistor is connected to the current input terminal of the power circuit, and the source of the switching transistor is connected to one end of the load.

[0040] The push-pull circuit includes an NPN transistor Q1, a PNP transistor Q2, and a current-limiting resistor R3. The system power supply is connected to the collector of the NPN transistor Q1 and the emitter of the PNP transistor Q2 via the current-limiting resistor R3. The base of the NPN transistor Q1 and the base of the PNP transistor Q2 are connected together and serve as the input terminal of the push-pull circuit. The emitter of the NPN transistor Q1 and the collector of the PNP transistor Q2 are connected together and serve as the output terminal of the push-pull circuit.

[0041] Specifically, in this embodiment, the PWM driving unit includes an N-channel MOSFET M1 (i.e., a switching transistor), a driving resistor R2, a push-pull circuit, and the processor. The PWM drive signal PWM_MCU output terminal of the processor is connected to the input terminal of the push-pull circuit. The output terminal of the push-pull circuit is connected to the gate of the N-channel MOSFET M1 through the drive resistor R2. The drain of the N-channel MOSFET M1 is connected to the other end of the sampling resistor R1. The source of the N-channel MOSFET M1 is connected to one end of the load Load. The other end of the load Load is connected to the negative terminal GND of the power supply of the power circuit. The push-pull circuit consists of an NPN transistor Q1, a PNP transistor Q2, and a current-limiting resistor R3. The system power supply VCC is connected to the collector of the NPN transistor Q1 and the emitter of the PNP transistor Q2 via the current-limiting resistor R3. The bases of the NPN transistor Q1 and the PNP transistor Q2 are connected together and connected to the PWM drive signal PWM_MCU output terminal of the processor. The emitter of the NPN transistor Q1 and the collector of the PNP transistor Q2 are connected together and serve as the output terminal of the push-pull circuit.

[0042] In this embodiment, the PWM drive unit is the core execution component for controlling the on / off state of the power loop. It consists of an N-channel MOSFET M1, a drive resistor R2, a push-pull circuit, and a processor. The PWM drive signal PWM_MCU generated by the processor is first amplified by the push-pull circuit. This push-pull circuit is composed of NPN transistor Q1 and PNP transistor Q2 connected in a complementary symmetrical manner. The bases of Q1 and Q2 are shorted together to receive the PWM_MCU signal output by the processor. The system power supply VCC is supplied to the collector of Q1 and the emitter of Q2 through a current-limiting resistor R3. When PWM_MCU is high, NPN transistor Q1 is turned on, and the output of the push-pull circuit is pulled high to near VCC level; when PWM_MCU is low, PNP transistor Q2 is turned on, and the output of the push-pull circuit is pulled low to near GND level. This push-pull structure provides strong current drive capability, ensuring rapid charging and discharging of the MOSFET input capacitor. The output of the push-pull circuit is connected to the gate of the N-channel MOSFET M1 via a drive resistor R2. The drive resistor R2 limits the gate drive current, preventing excessive gate oscillations and voltage spikes during high-frequency switching, thus protecting the MOSFET gate from damage. The N-channel MOSFET M1 serves as the main switch in the power circuit. Its drain is connected to the other end of the sampling resistor R1, and its source is connected to one end of the load. When the processor output PWM_MCU is high, after being driven by the push-pull circuit and drive resistor R2, the gate voltage of M1 is higher than its turn-on threshold voltage, causing M1 to conduct, closing the power circuit, and supplying power to the load. When PWM_MCU is low, the gate voltage of M1 is pulled low, turning off M1, disconnecting the power circuit, and isolating the load from the power supply. By changing the duty cycle of PWM_MCU, the processor can precisely control the on-time of M1, thereby adjusting the load charging time or power supply energy, providing a flexible hardware basis for exploratory pulse identification and capacitive load charging control.

[0043] In this embodiment, the method for the processor to identify the load type includes: Output multiple tentative PWM pulses with increasing durations, and collect the voltage across the load at the end of each tentative PWM pulse. If the voltage across the load increases sequentially at each end of the pulse, the load is determined to be a capacitive load. If the voltage across the load does not increase sequentially at each end of the pulse, the load is determined to be a resistive load.

[0044] The specific comparison is as follows: Output at least three tentative PWM pulses, the durations of which are respectively... , , ,and < < When the PWM drive signal is high, the load sampling voltage is constant; when the PWM drive signal is low, the load sampling voltage is 0. During the conduction process, a first pulse is output tentatively, with a duration of [duration missing]. At this time, the data collected on the load... The voltage at time is Then, tentatively output a second pulse, with a duration of [duration missing]. At this time, the data collected on the load... The voltage at time is Then, tentatively output a third pulse, with a duration of [duration missing]. At this time, the data collected on the load... The voltage at time is .

[0045] The voltage across the load (Load) is collected at the end of each trial PWM pulse, and the corresponding values ​​are obtained. , , ; When satisfied < < When this occurs, the load is determined to be a capacitive load; When not satisfied < < When this occurs, the load is determined to be a resistive load.

[0046] The processor's load type identification method in this embodiment is based on the core design idea of ​​utilizing the unique voltage response characteristics of resistive and capacitive loads under PWM pulse drive. Accurate load type identification is achieved by actively applying tentative excitation and analyzing the response waveform. Specifically, the processor first outputs at least three tentative PWM pulses with sequentially increasing durations. The durations of these three pulses are as follows: , , And satisfy < < During the conduction period of each trial pulse, the processor captures the load terminal voltage at the instant the pulse ends in real time through the load voltage acquisition unit, and records it as follows: , , .

[0047] From a physical mechanism perspective, for resistive loads, the terminal voltage and current follow a linear relationship according to Ohm's law. When a fixed amplitude PWM voltage is applied, the loop current reaches its steady-state value at the instant of conduction, and the load terminal voltage remains constant throughout the pulse duration. Therefore, under pulses of different durations, the collected voltage... , , They are essentially equal and do not show an increasing trend with the extension of pulse duration, therefore they do not satisfy the condition. < < The conditions are as follows. For capacitive loads, their terminal voltage is dominated by the capacitor charging effect; the voltage across the capacitor gradually increases with the extension of the charging time. The longer the pulse duration, the higher the voltage value reached by the capacitor after charging. Therefore, the collected voltage... , , Must be satisfied < < The increasing relationship.

[0048] Through the aforementioned discrimination logic, the processor can quickly and accurately determine the load type using only three incremental pulses. This identification method eliminates the need for complex frequency scanning or impedance measurement, offering advantages such as low computational complexity, rapid response, and ease of engineering implementation. It provides a reliable basis for subsequent implementation of differentiated protection and control strategies for different load types, thus fundamentally solving the fundamental problem of traditional solutions' inability to distinguish load types, resulting in a single control strategy.

[0049] In this embodiment, when the processor determines that the load is a capacitive load, it compares the collected load voltage with a preset load voltage threshold. If the load voltage is greater than the load voltage threshold, it is determined that the load capacitance value of the load is within the acceptable range, and the processor controls the switch to remain on, and the power circuit operates normally. If the load voltage is less than or equal to the load voltage threshold, it is determined that the load capacitance value of the load exceeds the acceptable range, and the processor controls the switch to turn off, and the power circuit performs a protection shutdown.

[0050] Specifically, in this embodiment, when the processor determines that the load is a capacitive load, the load circuit is closed when the PWM drive signal is high. Since the voltage across the capacitor cannot change abruptly, the capacitor is approximately short-circuited, causing an instantaneous overload in the load circuit current, and the capacitor is in a charging state. When the PWM drive signal is low, the load circuit is open, the capacitor is in a discharging state, and the load current decreases. Adjusting the PWM drive pulse duty cycle, with the duty cycle increasing sequentially (i.e., extending the PWM high-level time, extending the capacitor charging time, and shortening the PWM low-level time, shortening the capacitor discharging time), results in a gradual increase in the voltage across the capacitor at the end of each drive pulse, i.e., a gradual increase in the load sampling voltage. (See also...) Figure 6 and Figure 7 As shown, Figure 6 This is a waveform diagram of the capacitive load PWM drive and load current sampling signal of the present invention. Figure 7 This is a waveform diagram of the capacitive load PWM drive and the load voltage sampling signal of the present invention.

[0051] Calculate the load capacitance value using the capacitor charging formula: (1- ) in for Constant load voltage, The initial voltage, This is the power supply voltage for the power circuit. For the charging circuit resistance, This is the load capacitance value. This refers to charging time; In this embodiment, Approximately 0V, R is the charging circuit resistance; in this system, it includes the current sampling resistor R1 and the internal resistance of the switching transistor M1. During the above process, because... The initial voltage in this system is approximately 0V. The power supply voltage in this system is the PWR system voltage, approximately 24V. R is the charging circuit resistance, and the voltage at time t is the inherent characteristic of the sampling resistor R1 and the switching transistor M1. It is only related to the load capacitance value C.

[0052] The processor sets the load voltage threshold based on the load capacitance value to be handled. ; when > At this time, the processor controls the PWM drive signal PWM_MCU to be high, the N-channel MOSFET M1 is continuously turned on, the power circuit is normally turned on, and the load capacitance is less than the load-bearing capacitance. when ≤ When the processor controls the PWM drive signal PWM_MCU to be low, the N-channel MOSFET M1 is turned off, the power circuit protection is turned off, and the load capacitance is greater than the load-carrying capacitance.

[0053] This embodiment provides a specific control strategy for cases where the processor determines the load to be capacitive. When a capacitive load is connected to the power circuit, since the voltage across the capacitor cannot change abruptly, the capacitor exhibits near-short-circuit characteristics at the instant the PWM drive signal becomes high and the MOSFET turns on. A surge current much larger than the steady-state value will appear in the circuit, causing the capacitor to enter a charging state, and the load current gradually decreases. When the PWM drive signal becomes low and the MOSFET turns off, the power circuit is disconnected, and the capacitor enters a discharging state through its own discharge circuit, reducing the load current to zero. Based on this, the processor further adjusts the duty cycle of the output PWM drive pulse, gradually increasing the duty cycle sequentially. Specifically, the high-level on-time is progressively extended, and the low-level off-time is progressively shortened. As a result, the charging time and discharging time of the capacitor in each pulse cycle become longer and shorter, thus the voltage across the capacitor gradually increases at the end of each drive pulse, and the corresponding load voltage sampling signal also gradually increases.

[0054] Based on this physical law, and according to the correspondence between voltage and capacitance in capacitor charging characteristics, combined with the fixed power supply voltage and loop resistance in the system, the processor can calculate the load capacitance from the load voltage measured at a specific moment. Internally, the processor pre-sets a corresponding load voltage threshold based on the load capacitance value that the system design requires to withstand. In actual operation, the processor will collect the load voltage. With preset voltage threshold Comparison: When Greater than When the current load capacitance is less than the maximum capacitance the system can withstand, the load is within the allowable range, the processor controls the PWM drive signal to remain high, the N-channel MOSFET remains on, and the power circuit operates normally; conversely, when the current load capacitance is less than the maximum capacitance the system can withstand, the load is within the allowable range, the processor controls the PWM drive signal to remain high, the N-channel MOSFET remains on, and the power circuit operates normally; Less than or equal to When the current load capacitance exceeds the system's maximum withstand capacitance, continued conduction could lead to excessive inrush current or overheating of the circuit. The processor immediately pulls the PWM drive signal low, turns off the N-channel MOSFET, and performs a protective shutdown of the power circuit. Through this mechanism, the present invention achieves intelligent identification and precise protection of capacitive loads, ensuring normal startup and operation of small capacitive loads while promptly cutting off the circuit when large capacitive loads are connected, preventing equipment damage due to overcurrent surges.

[0055] In this embodiment, when the processor determines that the load is a resistive load: The current detection signal is compared with a preset load current threshold: if the current detection signal is less than the load current threshold, the load is determined to be in a light load or rated operating state, the processor controls the switching transistor to remain on, and the power circuit operates normally; if the current detection signal is greater than the load current threshold, the load is determined to be in an overload state, the processor controls the switching transistor to turn off, and the power circuit performs a protection shutdown.

[0056] For resistive light-load conditions, please refer to Figure 2 and Figure 3 As shown, Figure 2 This is a waveform diagram of the resistive load (light load) PWM drive and load current sampling signal of the present invention. Figure 3 This is a waveform diagram of the resistive load (light load) PWM drive and load voltage signal of the present invention. Figure 2 and Figure 3 As shown, when the PWM drive signal is high, the load sampling voltage is a constant value and the load current is a steady-state light load current; when the PWM drive signal is low, the load sampling voltage is 0 and the load current is 0.

[0057] For resistive overload conditions, please refer to Figure 4 and Figure 5 As shown, Figure 4 This is a waveform diagram of the resistive load (overload) PWM drive and load current sampling signal of the present invention. Figure 5 This is a waveform diagram of the resistive load (overload) PWM drive and load voltage sampling signal of the present invention. Figure 4 and Figure 5 As shown, when the PWM drive signal is high, the load sampling voltage is constant and the load current exceeds the overload threshold; when the PWM drive signal is low, the load sampling voltage is 0 and the load current is 0.

[0058] The processor sets a load current threshold based on the load current it needs to withstand. ; When the load current acquisition signal I_ADC < When the processor controls the PWM drive signal PWM_MCU to be high, the N-channel MOSFET M1 is continuously turned on, and the power circuit is normally turned on. When the load current acquisition signal I_ADC> When the processor controls the PWM drive signal PWM_MCU to be low, the N-channel MOSFET M1 is turned off, and the power circuit protection is turned off.

[0059] This embodiment provides a specific control strategy for cases where the processor determines the load to be resistive. The key difference between a resistive load and a capacitive load is that its resistance value is relatively fixed. When a fixed amplitude power supply voltage is applied, the loop current quickly reaches a steady-state value at the moment of conduction, and the terminal voltage does not change with the extension of the conduction time. Therefore, the judgment of whether it is in a safe operating state mainly depends on the magnitude of the load current.

[0060] Based on the above characteristics, the processor pre-sets a corresponding load current threshold according to the maximum load current required by the system design. During the actual operation of the power circuit, the processor continuously receives the load current acquisition signal I_ADC from the load current acquisition unit and compares this real-time current value with a preset current threshold. Compare these values ​​and make an on / off decision accordingly. When I_ADC is less than... When I_ADC is greater than 1, it indicates that the current load current is within the system's safe operating range, the load is under light load or rated load, the power circuit can operate safely and continuously, the processor controls the PWM drive signal PWM_MCU to remain high, the N-channel MOSFET M1 remains on, and the power circuit is normally supplying power to the load. When the current exceeds the maximum capacity set by the system, the load is in an overload state. If the circuit continues to conduct at this time, the excessive current will flow through the circuit for a long time, causing the power switching devices and circuits to overheat, which may lead to equipment damage or even safety accidents. The processor immediately pulls the PWM drive signal PWM_MCU low to a low level, the N-channel MOSFET M1 is quickly turned off, and the power circuit performs a protection shutdown action to isolate the load from the power supply.

[0061] Through the above mechanism, this invention achieves real-time monitoring and precise overload protection of the operating status of resistive loads. In practical applications, the load current threshold... It can be flexibly configured according to different application scenarios and equipment specifications, which can ensure that the load operates stably within the normal operating current range and respond and protect in time when overload occurs, effectively preventing the equipment from overheating and being damaged due to prolonged overload conduction, and significantly improving the safety and reliability of the system.

[0062] In this embodiment, the logic for the processor to determine the load type and control the power loop includes: When the voltage detection sequence shows an increasing trend and the load voltage is greater than the load voltage threshold, it is determined to be a capacitive load and the load capacitance is less than the load capacitance that can be withstood. The processor controls the switching transistor to continue to be turned on, and the power circuit is normally turned on. When the voltage detection sequence shows an increasing trend and the load voltage is less than or equal to the load voltage threshold, it is determined to be a capacitive load with a load capacitance greater than the tolerable load capacitance. The processor controls the switching transistor to turn off, and the power circuit protection is turned off. When the voltage detection sequence does not show an increasing trend and the current detection signal is less than the load current threshold, it is determined to be a resistive load and the load current is less than the load current that can be tolerated. The processor controls the switching transistor to continue to conduct, and the power circuit conducts normally. When the voltage detection sequence does not show an increasing trend and the current detection signal is greater than the load current threshold, it is determined to be a resistive load and the load current is greater than the load current that can be tolerated. The processor controls the switching transistor to turn off and the power circuit protection to turn off.

[0063] The specific comparison is as follows: When the PWM drive signal is high, the N-channel MOSFET is turned on, and the load circuit is closed; when the PWM drive signal is low, the N-channel MOSFET is turned off, and the load circuit is disconnected, depending on the following conditions: When the following conditions are met... < < and > When the load is determined to be capacitive and the load capacitance is less than the load capacitance that can be withstood, the N-channel MOSFET M1 remains on, and the power circuit conducts normally; when the conditions are met... < < and ≤ When the load is determined to be capacitive and the load capacitance is greater than the load capacity that can be handled, the N-channel MOSFET M1 is turned off, and the power circuit protection is turned off; when the conditions are not met... < < And I_ADC< When the load is determined to be resistive and the load current is less than the tolerable load current, the N-channel MOSFET M1 remains on, and the power circuit conducts normally; when the condition is not met... < < And I_ADC> When the load is determined to be resistive and the load current is greater than the load current that can be tolerated, the N-channel MOSFET M1 is turned off, and the power circuit protection is turned off.

[0064] In this embodiment, the duty cycle of the tentative PWM pulses output by the processor increases sequentially, that is, the high-level time of the PWM is extended sequentially and the low-level time is shortened sequentially. For capacitive loads, the voltage across the load gradually increases at the end of each trial PWM pulse. The processor determines whether the load capacitance exceeds the acceptable range based on the voltage change at the end of adjacent pulses. When the voltage increase across the load approaches zero under the action of multiple consecutive trial PWM pulses, the processor determines that the load has been charged to near the power supply voltage, and the power circuit maintains normal conduction.

[0065] The above description is merely a preferred embodiment of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should also be considered within the scope of protection of the present invention.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A PWM-controlled drive circuit compatible with resistive and capacitive loads, characterized in that, include: Power circuit, used to provide electrical energy to the load; A load current acquisition unit, coupled to the power circuit, is used to acquire the load current and output a current detection signal; A load voltage acquisition unit is connected in parallel across the load to acquire the load voltage and output a voltage detection signal. A PWM drive unit is connected in the power circuit and is used to control the on / off state of the power circuit according to the PWM drive signal. as well as The processor is connected to the load current acquisition unit, the load voltage acquisition unit and the PWM drive unit respectively, and is used to output a tentative PWM pulse sequence, identify the load type as resistive load or capacitive load according to the current detection signal and the voltage detection signal, and control the PWM drive signal and the on / off of the power circuit according to the identification result; When identifying the load type, the processor acquires the rising edge response waveform of the load voltage during the operation of the trial PWM pulse sequence. When the load voltage shows a positive voltage overshoot at the rising edge and then exhibits an exponential decay trend, it is determined to be a capacitive load; when the load voltage shows a step rise at the rising edge without overshoot, it is determined to be a resistive load. The processor is further configured to: under the capacitive load condition, control the power circuit to be turned on or off based on the comparison result between the load voltage value collected by the load voltage acquisition unit and a preset load voltage threshold; and under the resistive load condition, control the power circuit to be turned on or off based on the comparison result between the current detection signal and a preset load current threshold to achieve overcurrent protection.

2. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 1, characterized in that, The PWM drive unit includes a switching transistor, a drive resistor R2, and a push-pull circuit. The input terminal of the push-pull circuit is connected to the processor to receive the PWM drive signal, and the output terminal of the push-pull circuit is connected to the gate of the switching transistor via the drive resistor R2. The drain of the switching transistor is connected to the current input terminal of the power circuit, and the source of the switching transistor is connected to one end of the load.

3. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 2, characterized in that, The push-pull circuit includes an NPN transistor Q1, a PNP transistor Q2, and a current-limiting resistor R3; The system power supply is connected to the collector of the NPN transistor Q1 and the emitter of the PNP transistor Q2 via the current-limiting resistor R3. The base of the NPN transistor Q1 is connected to the base of the PNP transistor Q2 and together they serve as the input terminal of the push-pull circuit. The emitter of the NPN transistor Q1 is connected to the collector of the PNP transistor Q2, and together they serve as the output terminal of the push-pull circuit.

4. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 1, characterized in that, The method for the processor to identify the load type includes: Output multiple tentative PWM pulses with increasing duration, and collect the voltage across the load Load at the end of each tentative PWM pulse; If the voltage across the load Load increases sequentially at each end time, then the load Load is determined to be a capacitive load. If the voltage across the load at each end time does not show a sequentially increasing relationship, then the load is determined to be a resistive load.

5. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 4, characterized in that, When the processor determines that the load is a capacitive load, it compares the collected load voltage with a preset load voltage threshold. If the load voltage is greater than the load voltage threshold, it is determined that the load capacitance value of the load is within the acceptable range, the processor controls the switching transistor to remain on, and the power circuit operates normally; If the load voltage is less than or equal to the load voltage threshold, it is determined that the load capacitance value of the load Load exceeds the acceptable range, the processor controls the switch to turn off, and the power circuit performs a protection shutdown.

6. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 4, characterized in that, When the processor determines that the load is a resistive load, it compares the current detection signal with a preset load current threshold. If the current detection signal is less than the load current threshold, the load is determined to be in a light load or rated operating state, the processor controls the switching transistor to remain on, and the power circuit operates normally. If the current detection signal is greater than the load current threshold, the load is determined to be in an overload state, the processor controls the switching transistor to turn off, and the power circuit performs a protection shutdown.

7. The PWM-based compatible resistive and capacitive load drive circuit according to claim 5 or 6, characterized in that, The logic of the processor to determine the load type and control the power circuit includes: when the voltage detection sequence shows an increasing trend and the load voltage is greater than the load voltage threshold, it is determined to be a capacitive load and the load capacitance is less than the load capacitance that can be tolerated. The processor controls the switching transistor to continue to be turned on, and the power circuit is normally turned on. When the voltage detection sequence shows an increasing trend and the load voltage is less than or equal to the load voltage threshold, it is determined to be a capacitive load with a load capacitance greater than the tolerable load capacitance. The processor controls the switching transistor to turn off, and the power circuit protection is turned off. When the voltage detection sequence does not show an increasing trend and the current detection signal is less than the load current threshold, it is determined to be a resistive load and the load current is less than the load current that can be tolerated. The processor controls the switching transistor to continue to conduct, and the power circuit conducts normally. When the voltage detection sequence does not show an increasing trend and the current detection signal is greater than the load current threshold, it is determined to be a resistive load and the load current is greater than the load current that can be tolerated. The processor controls the switching transistor to turn off and the power circuit protection to turn off.

8. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 1, characterized in that, The power circuit includes a power input terminal, a switching transistor, a sampling resistor R1, and a load Load. The power input terminal, the sampling resistor, the switching transistor, and the load are connected in series. One end of the sampling resistor R1 is connected to the positive terminal of the power supply of the power circuit, and the other end is connected to the drain of the switching transistor. The load is connected between the source of the switching transistor and the negative terminal of the power supply of the power circuit.

9. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 1, characterized in that, The load current acquisition unit includes the sampling resistor R1 and the load current acquisition circuit; The first end of the sampling resistor R1 is connected to the positive terminal of the power supply of the power circuit, and the second end is connected to the input terminal of the switching transistor of the PWM drive unit. The two ends of the sampling resistor R1 respectively output differential voltage signals to the load current acquisition circuit. The output of the load current acquisition circuit is connected to the processor, and outputs an analog signal representing the load current to the processor.

10. The PWM-controlled compatible resistive and capacitive load drive circuit according to claim 9, characterized in that, The load voltage acquisition unit includes a first voltage divider resistor R4, a second voltage divider resistor R5, and the processor; One end of the first voltage divider resistor R4 is connected to the output terminal of the switching transistor in the power circuit, and the other end is connected to one end of the second voltage divider resistor R5 and the processor, respectively. The other end of the second voltage divider resistor R5 is connected to the negative terminal of the power supply of the power circuit, and the processor receives the load voltage sampling signal after being divided by the first voltage divider resistor R4 and the second voltage divider resistor R5.

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