A control method and device of a converter, an electronic device, and a storage medium

Abstract

The application discloses a kind of transformer control method, device, electronic equipment and storage medium, determine the duty cycle upper limit and the duty cycle lower limit of current period, obtain the inductance current of inductance of current period, according to the inductance current of inductance of current period, determine the current error of current period, then according to the current error of current period, determine the next period current error prediction value, finally according to the current error of current period and the next period current error prediction value, between the duty cycle upper limit and the duty cycle lower limit of current period, determine target duty cycle.It is determined that the next period current error prediction value is determined by the current error of current period, and according to the current error of current period and the next period current error prediction value, dynamically determine the target duty cycle between the upper limit and the lower limit of duty cycle, realize the continuous adjustment of duty cycle, to avoid the high-frequency harmonic component and electromagnetic interference problem caused by the step mutation of duty cycle between maximum value and minimum value.

Description

Technical Field

[0001] This invention belongs to the field of power electronics, and specifically relates to a control method, device, electronic equipment, and storage medium for a converter. Background Technology

[0002] In power electronic converters, the traditional pulse width modulation (PWM) control method relies on a fixed frequency of switching operations with a continuously changing duty cycle, which can achieve smooth adjustment. However, when the load or input voltage changes rapidly, the duty cycle can only be adjusted once per switching cycle, resulting in slow system response and poor dynamic performance.

[0003] To improve dynamic response speed, a pulse sequence control method has been proposed in related technologies. This method presets a maximum duty cycle and a minimum duty cycle, and directly selects one of them as the output based on the sign of the current error. However, the duty cycle only changes abruptly between the maximum and minimum values, which can easily generate high-frequency harmonic components and cause electromagnetic interference and other problems. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a control method, apparatus, electronic device and storage medium for a converter that overcomes or at least partially solves the above problems.

[0005] In a first aspect, embodiments of the present invention provide a control method for a converter, the converter including a power factor correction main circuit, the power factor correction main circuit including an inductor, the method comprising: Determine the upper and lower limits of the duty cycle for the current period; Obtain the inductor current of the inductor in the current cycle; The current error for the current cycle is determined based on the inductor current of the inductor in the current cycle. Based on the current error of the current cycle, determine the predicted current error value for the next cycle; Based on the current error of the current cycle and the predicted current error of the next cycle, a target duty cycle is determined between the upper limit and the lower limit of the duty cycle of the current cycle.

[0006] Optionally, the converter further includes a rectifier bridge, and determining the upper and lower limits of the duty cycle for the current cycle includes: Obtain the output voltage of the rectifier bridge; The effective value of the output voltage of the rectifier bridge is determined based on the output voltage of the rectifier bridge. Based on the effective value, determine the upper and lower limits of the duty cycle for the current period.

[0007] Optionally, determining the upper and lower limits of the duty cycle for the current period based on the effective value includes: Based on the effective value, determine the peak value of the output voltage of the rectifier bridge; Obtain the inductance value of the inductor and the output current of the power factor correction main circuit for the current cycle; The upper limit of the duty cycle is determined based on the peak value of the output voltage of the rectifier bridge, the inductance value of the inductor, and the output current of the power factor correction main circuit in the current cycle. Obtain the output voltage of the power factor correction main circuit for the current cycle; The lower limit of the duty cycle is determined based on the peak value of the output voltage of the rectifier bridge, the inductance value of the inductor, the output current of the power factor correction main circuit in the current cycle, and the output voltage of the power factor correction main circuit in the current cycle.

[0008] Optionally, determining the current error for the current period based on the inductor current of the inductor in the current period includes: The inductor current reference value is determined based on the peak value of the rectifier bridge output voltage, the output voltage of the rectifier bridge in the current cycle, the output current of the power factor correction main circuit in the current cycle, and the preset output voltage of the power factor correction main circuit. The difference between the inductor current reference value and the inductor current of the current cycle is determined as the current error of the current cycle.

[0009] Optionally, determining the predicted current error value for the next cycle based on the current error of the current cycle includes: Based on the polarity of the current error in the current cycle, select the upper limit of the duty cycle or the lower limit of the duty cycle as the reference duty cycle; The inductor current prediction value for the next cycle is determined based on the reference duty cycle, the output voltage of the rectifier bridge in the current cycle, the output voltage of the power factor correction main circuit in the current cycle, and the inductance value of the inductor. Based on the predicted inductor current value for the next cycle, determine the predicted current error value for the next cycle.

[0010] Optionally, determining the target duty cycle between the upper and lower limits of the duty cycle in the current cycle based on the current error of the current cycle and the predicted current error of the next cycle includes: Determine whether the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and whether the absolute value of the predicted current error in the next cycle is greater than a preset threshold. If the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and the absolute value of the predicted current error in the next cycle is greater than a preset threshold, then a target duty cycle is determined between the upper limit and the lower limit of the duty cycle in the current cycle.

[0011] Optionally, determining the target duty cycle between the upper and lower limits of the current duty cycle includes: The braking weight factor is determined based on the absolute value of the predicted current error for the next cycle and the preset threshold. The driving weighting factor is determined based on the absolute value of the current current error; The target duty cycle is determined based on the driving weight factor, the braking weight factor, the upper limit of the duty cycle for the current cycle, and the lower limit of the duty cycle.

[0012] Secondly, embodiments of the present invention provide a control device for a converter, the converter including a power factor correction main circuit, the power factor correction main circuit including an inductor, and the device comprising: The duty cycle upper and lower limit determination module is used to determine the upper and lower limits of the duty cycle for the current period. An inductor current acquisition module is used to acquire the inductor current of the inductor in the current cycle; The current error determination module is used to determine the current error of the current cycle based on the inductor current of the inductor in the current cycle. The current error prediction value determination module is used to determine the current error prediction value for the next cycle based on the current error of the current cycle. The target duty cycle determination module is used to determine the target duty cycle between the upper limit and the lower limit of the duty cycle in the current cycle based on the current error of the current cycle and the predicted current error of the next cycle.

[0013] Optionally, the converter further includes a rectifier bridge, and the duty cycle upper and lower limit determination module includes: The rectifier bridge output voltage acquisition submodule is used to acquire the output voltage of the rectifier bridge; The effective value determination submodule is used to determine the effective value of the output voltage of the rectifier bridge based on the output voltage of the rectifier bridge. The duty cycle upper and lower limit determination submodule is used to determine the upper and lower limits of the duty cycle for the current period based on the effective value.

[0014] Optional, the duty cycle upper and lower limit determination submodule includes: A peak value determination unit is used to determine the peak value of the output voltage of the rectifier bridge based on the effective value. An inductance value acquisition unit is used to acquire the inductance value of the inductor and the output current of the power factor correction main circuit in the current cycle; The duty cycle upper limit determination unit is used to determine the upper limit of the duty cycle based on the peak value of the output voltage of the rectifier bridge, the inductance value of the inductor, and the output current of the power factor correction main circuit in the current cycle. The output voltage acquisition unit is used to acquire the output voltage of the power factor correction main circuit in the current cycle; The duty cycle lower limit determination unit is used to determine the duty cycle lower limit based on the peak value of the output voltage of the rectifier bridge, the inductance value of the inductor, the output current of the power factor correction main circuit in the current cycle, and the output voltage of the power factor correction main circuit in the current cycle.

[0015] Optionally, the current error determination module includes: The inductor current reference value determination submodule is used to determine the inductor current reference value based on the peak value of the output voltage of the rectifier bridge, the output voltage of the rectifier bridge in the current cycle, the output current of the power factor correction main circuit in the current cycle, and the preset output voltage of the power factor correction main circuit. The current error determination submodule is used to determine the difference between the inductor current reference value and the inductor current of the inductor in the current cycle as the current error of the current cycle.

[0016] Optionally, the current error prediction value determination module includes: The reference duty cycle determination submodule is used to select the upper limit of the duty cycle or the lower limit of the duty cycle as the reference duty cycle based on the polarity of the current error in the current cycle. The inductor current prediction value determination submodule is used to determine the inductor current prediction value for the next cycle based on the reference duty cycle, the output voltage of the rectifier bridge in the current cycle, the output voltage of the power factor correction main circuit in the current cycle, and the inductance value of the inductor. The current error prediction value determination submodule is used to determine the current error prediction value for the next cycle based on the inductor current prediction value for the next cycle.

[0017] Optionally, the target duty cycle determination module includes: The judgment submodule is used to determine whether the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and whether the absolute value of the predicted current error in the next cycle is greater than a preset threshold. The target duty cycle determination submodule is used to determine a target duty cycle between the upper and lower limits of the duty cycle in the current cycle if the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and the absolute value of the predicted current error in the next cycle is greater than a preset threshold.

[0018] Optional, the target duty cycle determination submodule includes: The braking weight factor determination unit is used to determine the braking weight factor based on the absolute value of the predicted value of the current error in the next cycle and the preset threshold. A drive weighting factor determination unit is used to determine a drive weighting factor based on the absolute value of the current current error. The target duty cycle determination unit is used to determine the target duty cycle based on the driving weight factor, the braking weight factor, the upper limit of the duty cycle of the current cycle, and the lower limit of the duty cycle.

[0019] Thirdly, embodiments of the present invention provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0020] Fourthly, embodiments of the present invention provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0021] This invention discloses a control method for a converter. The converter includes a power factor correction (PFC) main circuit, which includes an inductor. The method involves determining the upper and lower limits of the duty cycle for the current cycle, acquiring the inductor current for the current cycle, determining the current error for the current cycle based on the current current, determining the predicted current error for the next cycle based on the current error, and finally determining the target duty cycle between the upper and lower limits based on the current error and the predicted current error for the next cycle. By determining the predicted current error for the next cycle based on the current error of the current cycle, and dynamically determining the target duty cycle between the upper and lower limits based on the current error and the predicted current error for the next cycle, continuous adjustment of the duty cycle is achieved. This avoids the high-frequency harmonic components and electromagnetic interference problems caused by abrupt changes in the duty cycle only between its maximum and minimum values. Attached Figure Description

[0022] Figure 1 This is a flowchart illustrating the steps of a converter control method according to an embodiment of the present invention; Figure 2This is a schematic diagram of the structure of a converter control device according to an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In power electronic converters, traditional pulse width modulation control methods rely on fixed-frequency switching operations with a continuously changing duty cycle, which can achieve smooth adjustment. However, when the load or input voltage changes rapidly, the duty cycle can only be adjusted once per switching cycle, resulting in slow system response and poor dynamic performance.

[0025] To improve dynamic response speed, a pulse sequence control method has been proposed in related technologies. This method presets a maximum duty cycle and a minimum duty cycle, and directly selects one of them as the output based on the sign of the current error. However, the duty cycle only changes abruptly between the maximum and minimum values, which can easily generate high-frequency harmonic components and cause electromagnetic interference and other problems.

[0026] The core concept of this invention is to determine the predicted value of the current error in the next cycle by using the current error in the current cycle, and to dynamically determine the target duty cycle between the upper and lower limits of the duty cycle based on the current error in the current cycle and the predicted value of the current error in the next cycle. This achieves continuous adjustment of the duty cycle, thereby avoiding the high-frequency harmonic components and electromagnetic interference problems caused by the step change of the duty cycle between the maximum and minimum values.

[0027] Reference Figure 1 The diagram illustrates a flowchart of a control method for a converter according to an embodiment of the present invention. The converter includes a power factor correction main circuit, which includes an inductor, and specifically includes the following steps: Step 101: Determine the upper and lower limits of the duty cycle for the current period.

[0028] This invention provides a control method for a converter, applicable to power factor correction (PFC) converters. In a PFC converter, power factor correction is achieved by controlling the on and off states of a switching transistor to make the input current follow the input voltage waveform. However, traditional pulse width modulation (PWM) control methods have slow response times, while pulse sequence control methods, although fast, suffer from abrupt changes in duty cycle between maximum and minimum values, which can easily generate high-frequency harmonic components and electromagnetic interference.

[0029] Determine the upper and lower limits of the duty cycle for the current cycle. The upper limit represents the maximum allowable duty cycle under the current operating conditions, and the lower limit represents the minimum allowable duty cycle under the current operating conditions. These two boundary values ​​provide a limiting range for subsequent duty cycle adjustments.

[0030] Step 102: Obtain the inductor current of the inductor in the current cycle.

[0031] The power factor correction main circuit (PFC main circuit) refers to the converter circuit used to make the input current follow the input voltage waveform and improve the power factor. The inductor is the core energy storage element in the PFC main circuit. It is used to store energy when the switch is turned on and release energy when it is turned off. It works with the switching on and off of the switch to shape the input current and regulate the output voltage.

[0032] Inductor current is the current flowing through the inductor in the power factor correction main circuit, which can be obtained in real time by sampling with a current sensor.

[0033] Step 103: Determine the current error of the current cycle based on the inductor current of the current cycle.

[0034] Current error refers to the difference between the inductor current reference value and the actual sampled inductor current. It reflects the degree of deviation between the current and the target current. The sign of the current error indicates the direction of the current deviation: a positive current error indicates that the actual current is too small and the duty cycle needs to be increased; a negative current error indicates that the actual current is too large and the duty cycle needs to be decreased.

[0035] Step 104: Determine the predicted value of the current error for the next cycle based on the current error of the current cycle.

[0036] After determining the current error for the current cycle, the predicted current error for the next cycle is determined based on the current error for the current cycle. The predicted value is used to characterize the degree of current deviation that may occur in the next cycle under the current error conditions. Step 105: Based on the current error of the current cycle and the predicted current error of the next cycle, determine the target duty cycle between the upper limit and the lower limit of the duty cycle of the current cycle.

[0037] When a potential oscillation risk or control instability trend is identified based on the current error and the predicted error, the duty cycle can be continuously adjusted between the upper and lower limits based on the current error of the current cycle and the predicted current error of the next cycle, so as to output a smooth target duty cycle and avoid abrupt changes in the duty cycle.

[0038] When it is determined that there is no risk of oscillation or a tendency to lose control, the upper or lower limit of the duty cycle can be directly selected as the target duty cycle based on the sign of the current current error, in order to maintain a fast response.

[0039] By introducing a current error prediction mechanism, the system can determine whether there is a potential risk of oscillation or a tendency for control instability based on the current error of the current cycle and the predicted current error of the next cycle. When a risk exists, the system continuously adjusts the duty cycle between the upper and lower limits, avoiding the high-frequency harmonic components and electromagnetic interference problems caused by abrupt duty cycle changes in traditional pulse sequence control. When there is no risk, the system maintains extreme output, balancing fast dynamic response and steady-state control accuracy. Furthermore, it effectively reduces inductor current ripple, improves the sinusoidal nature of the input current waveform, and enhances the system's power quality and electromagnetic compatibility.

[0040] This invention discloses a control method for a converter. The converter includes a power factor correction (PFC) main circuit, which includes an inductor. The method involves determining the upper and lower limits of the duty cycle for the current cycle, acquiring the inductor current for the current cycle, determining the current error for the current cycle based on the current current, determining the predicted current error for the next cycle based on the current error, and finally determining the target duty cycle between the upper and lower limits based on the current error and the predicted current error for the next cycle. By determining the predicted current error for the next cycle based on the current error of the current cycle, and dynamically determining the target duty cycle between the upper and lower limits based on the current error and the predicted current error for the next cycle, continuous adjustment of the duty cycle is achieved. This avoids the high-frequency harmonic components and electromagnetic interference problems caused by abrupt changes in the duty cycle only between its maximum and minimum values.

[0041] In this embodiment of the invention, the converter further includes a rectifier bridge. Step 101, determining the upper limit and lower limit of the duty cycle for the current cycle, may specifically include the following sub-steps: Sub-step S11: Obtain the output voltage of the rectifier bridge.

[0042] A rectifier bridge is a rectifier circuit composed of four diodes. The input terminal of the rectifier bridge is connected to the AC power supply, and the output terminal of the rectifier bridge is connected to the input terminal of the PFC main circuit. The rectifier bridge is responsible for converting the AC input voltage into a pulsating DC voltage to provide input power to the PFC main circuit. The PFC main circuit is responsible for shaping the pulsating DC voltage so that the input current follows the voltage waveform, thereby achieving a high power factor.

[0043] Obtain the output voltage of the rectifier bridge. The output voltage of the rectifier bridge is a full-wave rectified waveform with a frequency twice that of the AC input frequency. The voltage value changes periodically between zero and peak value over time.

[0044] Sub-step S12: Determine the effective value of the output voltage of the rectifier bridge based on the output voltage of the rectifier bridge.

[0045] The RMS value is the square root of the average square of the voltage over a period of time. It reflects the overall magnitude of the AC voltage. The RMS value of the rectifier bridge output voltage can be obtained by sampling the voltage over a complete waveform cycle and calculating the root mean square of the sampled values. The RMS value of the rectifier bridge output voltage is numerically equal to the RMS value of the AC input voltage. In practical control, the RMS value calculated by sampling the rectifier bridge output voltage can be directly used as the RMS value of the input voltage.

[0046] rectifier bridge output voltage This is a full-wave rectified waveform, which is the waveform obtained by taking the absolute value of an AC sine wave. Taking a 50Hz AC input as an example, the frequency of the rectifier bridge output voltage is 100Hz, and a complete waveform period is 10ms. Unlike the original sine wave, each complete waveform period of the rectifier bridge output voltage has only two zero-crossing points (start and end points). The interval between adjacent zero-crossing points corresponds to half a rectified waveform period (i.e., 5ms), while a complete measurement period should be the interval between two adjacent zero-crossing points in the same direction (i.e., from one zero-crossing point to the next, corresponding to 10ms).

[0047] It can detect the zero-crossing point of the rectifier bridge output voltage and determine the effective value of the rectifier bridge output voltage based on multiple rectifier bridge output voltages between adjacent zero-crossing points. For example, to detect the zero-crossing point, a measurement cycle is started, and the zero-crossing point of the rectifier bridge output voltage is detected in real time. When a zero-crossing point is detected, a new measurement cycle is started, and the sampling counter is activated. Set to 1, and sum the squares of the voltages. Reset to zero; continuous sampling and accumulation within the period. During the measurement period, the output voltage of the rectifier bridge is sampled at each sampling moment to obtain the instantaneous voltage value at the current moment. Each time a sample is taken, the sampling counter is incremented by 1. ), and add the square of the current sampled value to the summation ( This process continues until the next zero-crossing occurs; when another zero-crossing is detected, the current measurement cycle ends, and the sampling counter... This records the total number of samples within the current period, plus the cumulative sum. This records the sum of squares of all sampled values ​​within the current period. These two data points constitute the statistical information for a complete measurement period; based on the above data, the effective value of the rectifier bridge output voltage is calculated using the following formula:

[0048] in, It is the sum of the squares of the voltages. The number of samples.

[0049] Sub-step S13: Based on the valid values, determine the upper limit and lower limit of the duty cycle for the current period.

[0050] Duty cycle limit and duty cycle lower limit The duty cycle adjustment range is limited to ensure that the output duty cycle does not exceed the physical limit, and it also adaptively adjusts according to changes in input voltage to ensure stable operation of the system under various operating conditions.

[0051] By acquiring the rectifier bridge output voltage and calculating its effective value, and then determining the upper and lower limits of the duty cycle based on the effective value, the duty cycle boundary is adaptively adjusted according to the input voltage. When the input voltage increases, the amplitude of the rectifier bridge output voltage increases, the calculated effective value increases, and the upper and lower limits of the duty cycle decrease accordingly; when the input voltage decreases, the upper and lower limits of the duty cycle increase accordingly. In this way, the adjustment range of the duty cycle can adaptively follow the changes in the input voltage, providing accurate limiting boundaries for subsequent continuous adjustment and avoiding control failure or performance degradation caused by fixed boundaries.

[0052] In this embodiment of the invention, sub-step S13, which determines the upper limit and lower limit of the duty cycle for the current period based on the valid values, may specifically include the following sub-steps: Sub-step S131: Determine the peak value of the output voltage of the rectifier bridge based on the effective value.

[0053] Peak value of rectifier bridge output voltage With effective value The relationship between them is:

[0054] Based on this conversion relationship and the effective value, the peak value of the rectifier bridge's output voltage is determined. The peak value of the rectifier bridge's output voltage is the same as the peak value of the input voltage, which refers to the AC input voltage. This peak value reflects the maximum amplitude of the input voltage.

[0055] Sub-step S132: Obtain the inductance value of the inductor and the output current of the power factor correction main circuit for the current cycle.

[0056] The inductance value is an inherent parameter of the power factor correction main circuit. The output current of the power factor correction main circuit can be obtained in real time through a current sensor, reflecting the current load magnitude. The load magnitude is reflected in the output current. The heavier the load, the greater the output current.

[0057] Sub-step S133: Determine the upper limit of the duty cycle based on the peak value of the rectifier bridge output voltage, the inductance value of the inductor, and the power factor correction of the current cycle to adjust the output current of the main circuit.

[0058] Based on the peak value of the rectifier bridge's output voltage Inductance value of an inductor and the output current of the power factor correction main circuit in the current cycle Determine the upper limit of the duty cycle. .

[0059] The formula for calculating the upper limit of the duty cycle is:

[0060] in, The angular frequency of the input voltage ( , (This refers to the mains frequency, such as 50Hz or 60Hz). This formula reflects the maximum duty cycle required during the current rise phase. The upper limit of the duty cycle increases accordingly when the output current or inductance is large; conversely, it decreases accordingly when the input voltage peak is high.

[0061] Sub-step S134: Obtain the output voltage of the power factor correction main circuit for the current cycle.

[0062] The output voltage is the DC bus voltage at the output terminal of the PFC main circuit. It can be obtained in real time by sampling through a voltage sensor and is an important feedback quantity for maintaining output stability.

[0063] Sub-step S135: Determine the lower limit of the duty cycle based on the peak value of the rectifier bridge output voltage, the inductance value of the inductor, the output current of the power factor correction main circuit in the current cycle, and the output voltage of the power factor correction main circuit in the current cycle.

[0064] Based on the peak value of the rectifier bridge's output voltage Inductance value of an inductor The output current of the power factor correction main circuit in the current cycle. and the output voltage of the power factor correction main circuit in the current cycle Determine the lower limit of the duty cycle. .

[0065] The formula for calculating the lower limit of the duty cycle is:

[0066] This formula reflects the minimum duty cycle required during the current descent phase. When the input voltage peak is high... As the term increases, the lower limit of the duty cycle decreases; when the output current is large or the inductance value is large... As the term increases, the lower limit of the duty cycle decreases further. In practical applications, the lower limit of the duty cycle can be adjusted to ensure that it is not less than 0.

[0067] Duty cycle limit and duty cycle lower limit It is the boundary value obtained by taking the extreme values ​​of the sine and cosine terms in the ideal duty cycle formula under a given input voltage. The upper limit of the duty cycle corresponds to... , The ideal duty cycle; the lower limit of the duty cycle corresponds to , The ideal duty cycle is defined by these two boundary values. These two boundary values ​​constitute the safe adjustment range of the duty cycle under the current operating condition. The target duty cycle in subsequent control will be determined within this range, thereby ensuring stable system operation. The formula for the ideal duty cycle is the instantaneous value that changes with time:

[0068] This formula describes the instantaneous duty cycle required to achieve ideal current tracking within each switching cycle. Because... and Over time, It changes continuously within a rectification cycle.

[0069] Determine the upper limit of duty cycle and duty cycle lower limit Afterwards, upper and lower limit ratio coefficients can be calculated to further adjust the duty cycle boundaries.

[0070] The first term of the ideal duty cycle formula is:

[0071] This item represents the slow-changing part of the duty cycle (voltage control part). The maximum value of the first item is 1, and the minimum value is... .

[0072] Upper and lower limit scaling factors are used to map the theoretical duty cycle range to the actual usable duty cycle boundaries:

[0073]

[0074] in, This is the upper limit proportional coefficient, used to dynamically adjust the upper limit of the duty cycle to adapt to changes in the input voltage; This is the lower limit proportional coefficient, used to dynamically adjust the lower limit of the duty cycle to adapt to changes in input and output voltage. By scaling the theoretical duty cycle range proportionally, it ensures that the actual duty cycle upper and lower limits always encompass the ideal duty cycle, thus providing a suitable limiting range for duty cycle adjustment while maintaining system stability.

[0075] Compared to schemes that use fixed duty cycle boundaries, the upper and lower limits of the duty cycle in this embodiment can be adaptively adjusted according to changes in operating conditions such as input voltage and load current. This ensures that the adjustment range of the duty cycle is always reasonable under different operating conditions, avoids control failure or performance degradation caused by improper boundaries, and provides accurate limiting boundaries for subsequent continuous adjustment of the duty cycle.

[0076] In this embodiment of the invention, step 103, determining the current error of the current cycle based on the inductor current of the current cycle, may specifically include the following sub-steps: Sub-step S21: Determine the reference value of the inductor current based on the peak value of the rectifier bridge output voltage, the output voltage of the rectifier bridge in the current cycle, the output current of the power factor correction main circuit in the current cycle, and the preset output voltage of the power factor correction main circuit.

[0077] Based on the peak value of the rectifier bridge's output voltage The output voltage of the rectifier bridge in the current cycle The output current of the power factor correction main circuit in the current cycle. and the preset output voltage of the power factor correction main circuit Determine the reference value of inductor current. The formula for calculating the inductor current reference value is as follows:

[0078] The physical meaning of this formula is: the reference value of the inductor current should be related to the output voltage of the rectifier bridge. In phase (both waveforms are identical), its amplitude is determined by the output power. and peak input voltage This is determined jointly. Based on the power balance principle, input power equals output power, thus deriving an expression for the inductor current reference value. The current reference value generated in this way allows the input current to follow the input voltage waveform, thereby achieving power factor correction.

[0079] Sub-step S22: The difference between the inductor current reference value and the inductor current of the current cycle is determined as the current error of the current cycle.

[0080] Inductor current reference value and the inductor current of the current cycle The difference is determined as the current error for the current cycle. :

[0081] By constructing an inductor current reference value based on the peak input voltage, the instantaneous value of the rectifier bridge output voltage, the output current, and the preset output voltage, the reference current waveform is made consistent with the rectifier bridge output voltage waveform. This ensures that the input current and input voltage are in phase, achieving the core objective of power factor correction. Simultaneously, by subtracting the inductor current reference value from the actual sampled current, quantified current error information is obtained, providing an accurate input for subsequent predictive control and duty cycle adjustment. This current error includes not only the magnitude of the deviation but also its direction (positive or negative), facilitating the determination of whether to increase or decrease the duty cycle.

[0082] In this embodiment of the invention, step 104, determining the predicted value of the current error for the next cycle based on the current error of the current cycle, may specifically include the following sub-steps: Sub-step S31: Select the upper or lower limit of the duty cycle as the reference duty cycle based on the polarity of the current error in the current cycle.

[0083] Because the actual control frequency is much higher than the power frequency (e.g., the switching frequency is tens to hundreds of kilohertz, while the power frequency is 50Hz or 60Hz), the inductor current in adjacent control cycles is not equal. In order to accurately predict the current state of the next cycle, this embodiment of the invention establishes a prediction mechanism based on a state-space model.

[0084] If the current current error (If the actual current is too low, the duty cycle needs to be increased), then select the upper limit of the duty cycle. As a reference duty cycle; if the current current error (If the actual current is too high, the duty cycle needs to be reduced), then select the lower limit of the duty cycle. Used as a reference duty cycle.

[0085] Sub-step S32: Based on the reference duty cycle, the output voltage of the rectifier bridge in the current cycle, the output voltage of the power factor correction main circuit in the current cycle, and the inductance value of the inductor, determine the predicted value of the inductor current for the next cycle.

[0086] Based on the reference duty cycle The output voltage of the rectifier bridge in the current cycle The output voltage of the power factor correction main circuit in the current cycle. and the inductance value of the inductor Determine the predicted inductor current value for the next cycle. The formula for calculating the predicted inductor current is as follows:

[0087] in, For the switching cycle, Input voltage for the current cycle, For reference duty cycle, This represents the inductor current during the current cycle. This formula describes the variation of the inductor current over one switching cycle under a given reference duty cycle. The first term... The second term represents the increase in inductor current during the conduction period of the switching transistor. This represents the decrease in inductor current during the turn-off period of the switching transistor; together, these two factors determine the net change in inductor current.

[0088] Sub-step S33: Determine the predicted current error value for the next cycle based on the predicted inductor current value for the next cycle.

[0089] The formula for calculating the predicted current error is:

[0090] in, This is a reference value for the inductor current. This predicted value reflects the degree of current deviation that may occur in the next cycle.

[0091] The inductor current for the next cycle is predicted using a state-space model, thus obtaining the predicted current error for that cycle. This prediction mechanism can anticipate potential current deviations in the next cycle that might result from current control decisions, providing a basis for subsequent judgments and adaptive adjustments. Compared to traditional control methods that rely solely on current errors, introducing predictive information allows for earlier identification of oscillation risks, enabling proactive smoothing adjustments to prevent the system from entering an oscillating state.

[0092] In this embodiment of the invention, step 105, determining the target duty cycle between the upper and lower limits of the duty cycle in the current cycle based on the current error of the current cycle and the predicted current error of the next cycle, may specifically include the following sub-steps: Sub-step S41: Determine whether the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and whether the absolute value of the predicted current error in the next cycle is greater than a preset threshold.

[0093] The embodiments of the present invention provide a current hysteresis buffer band, which is an error tolerance range that allows the current error to change in the opposite direction within a certain range without triggering control action.

[0094] A positive number can be preset. ( This serves as a reference width for the hysteresis buffer band. Based on the polarity of the current error, the current error in the next cycle is allowed to vary within the following range: when... When the current is too low, the allowable current error range for the next cycle is... That is, it allows the current to overshoot from the smaller direction to the larger direction; when When the current is too high, the allowable current error range for the next cycle is... This means that the current is allowed to surge from a higher value direction to a lower value direction. Among these, and Different values ​​can be set, meaning the buffer band widths of the positive and negative halves can be asymmetrical.

[0095] The buffer band width can be flexibly set according to different operating conditions, load variation range, and control accuracy requirements. For example, under conditions of drastic load changes, the buffer band width can be appropriately increased to improve disturbance rejection capability; under steady-state conditions requiring high-precision control, the buffer band width can be appropriately decreased to improve control accuracy. The buffer band parameters can be preset through offline calibration or adaptively adjusted online according to the system operating status using a preset control algorithm.

[0096] Based on the current error of the current cycle and the predicted current error for the next cycle, determine whether there is a potential risk of oscillation or a trend of control instability. The judgment condition is: the current error of the current cycle. Error prediction value of current in the next cycle The polarities are opposite, and the absolute value of the predicted current error for the next cycle is... It is greater than the buffer band threshold corresponding to the current direction (i.e., it exceeds the hysteresis buffer band range).

[0097] Reversed polarity indicates that the current control decision may cause the current to overshoot in the next cycle. Exceeding the buffer band threshold indicates that the overshoot amplitude exceeds the allowable tolerance range in the current direction. When the above conditions are met at the same time, it indicates that the current control strategy may lead to oscillation risk or control instability trend, and smoothing adjustment is required.

[0098] Sub-step S42: If the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and the absolute value of the predicted current error in the next cycle is greater than a preset threshold, then the target duty cycle is determined between the upper limit and the lower limit of the duty cycle in the current cycle.

[0099] If the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and the absolute value of the predicted current error in the next cycle is greater than the preset threshold, then there is a risk of oscillation or a tendency for control to become unstable. Therefore, it is necessary to continuously adjust (interpolate) between the upper and lower limits of the duty cycle to output a smooth target duty cycle and avoid abrupt changes.

[0100] When there is no risk of oscillation or a tendency for control to become unstable, the upper or lower limit of the duty cycle can be directly selected as the target duty cycle based on the sign of the current current error, so as to maintain the fast response advantage of pulse sequence control.

[0101] By introducing a directional memory-enabled and flexibly adjustable current hysteresis buffer band, the current error can change in the opposite direction within a certain range without triggering control action, effectively filtering out false triggers caused by measurement noise or minor disturbances. The buffer band parameters can be adjusted online according to operating conditions, and the positive and negative half-zones can be set asymmetrically, enabling the system to adapt to the differentiated needs of various application scenarios. Simultaneously, by determining whether the prediction error exceeds the buffer band range, potential oscillation risks can be identified in advance, and the system can switch to continuous adjustment mode when such risks exist. This maintains the advantages of rapid response from pulse sequence control while avoiding electromagnetic interference and current ripple problems caused by frequent switching, significantly improving the system's anti-disturbance capability and stability margin under complex operating conditions.

[0102] In this embodiment of the invention, sub-step S42 includes: Sub-step S421: Determine the braking weight factor based on the absolute value of the predicted current error for the next cycle and a preset threshold.

[0103] Sub-step S422: Determine the driving weighting factor based on the absolute value of the current current error.

[0104] Sub-step S423: Determine the target duty cycle based on the driving weight factor, braking weight factor, and the upper and lower limits of the duty cycle for the current cycle.

[0105] Duty cycle limit and duty cycle lower limit The interval formed by these two boundary values ​​contains all possible values ​​of the ideal duty cycle. Between the upper and lower limits of the duty cycle, there exists an unknown ideal duty cycle. Theoretically, applying this ideal duty cycle can maintain the current error at zero. However, due to factors such as system parameter drift, load changes, and measurement noise, this ideal duty cycle is difficult to calculate directly and accurately. This invention presents a method based on current error... and predicted current error control law Through nonlinear interpolation and Choose the optimal duty cycle from among them.

[0106] Control Law The design follows these principles: Output duty cycle range positioning: when... When the current is too high, the duty cycle needs to be reduced. Output duty cycle Located at the theoretical optimal value Duty cycle upper limit Between, that is ;when When the current is too low, the duty cycle needs to be increased, the output duty cycle... Located at the lower limit of duty cycle Compared with the theoretical optimal value Between, that is The impact of error magnitude on output: The larger the absolute value of the current error, the closer the output duty cycle is to the boundary value (driven dominance); the larger the absolute value of the predicted current error in the next cycle, the closer the output duty cycle is to the theoretical optimal value. (Brake-dominated); Boundary continuity: when and At that time, the output duty cycle is equal to ,when and At that time, the output duty cycle is equal to This condition ensures the continuity of the control law at the boundary.

[0107] in, The weights correspond to the driving terms of the duty cycle (the larger the current error, the stronger the driving force is needed). The weights correspond to the braking terms of the duty cycle (the larger the prediction overshoot, the earlier convergence is needed).

[0108] Based on the absolute value of the predicted current error for the next cycle and the preset threshold (Half-width of the hysteresis buffer band), calculate the braking weighting factor :

[0109] in, The preset braking weight adjustment factor ( Braking weighting factor This means that when the prediction error is exactly at the boundary of the buffer zone, the braking weight is zero, and the system is entirely determined by the driving term; when the prediction error exceeds the boundary, the braking weight is positive, and the greater the deviation, the stronger the braking force, pushing the output duty cycle towards the theoretical optimal value. Directional callback.

[0110] Determine the driving weighting factor based on the absolute value of the current error. ,in The preset driving weight adjustment factor ( The driving weight factor reflects the influence of the current error on the duty cycle adjustment: the larger the current error, the stronger the driving demand, and the closer the output duty cycle should be to the boundary.

[0111] Control Law The calculation formula is:

[0112] in, For symbolic functions: when Time to take ,when Time to take The physical meaning of the formula is analyzed as follows: When When the current is too high, the output duty cycle changes from... Adjust downwards; the stronger the brake, the closer it gets. ;when When the current is too low, the output duty cycle changes from... Adjust upwards (this expression will produce) (It can be used for amplitude limiting).

[0113] Determine the target duty cycle The controller then writes the duty cycle value into the comparison register of the PWM (Pulse Width Modulation) module. The PWM module generates a corresponding pulse width modulation signal based on the written comparison value and the set period value, which is used to control the on and off of the switching transistors in the power factor correction main circuit.

[0114] By constructing a nonlinear interpolation control law based on driving and braking weights, continuous and smooth adjustment of the duty cycle between its upper and lower limits was achieved. Specifically, the current error drives the duty cycle closer to the boundary, ensuring rapid response even with large errors; the predicted current error, after being converted by the braking weight factor, pulls the duty cycle back towards the theoretical optimal value, effectively suppressing overshoot and oscillation risks. Driving weight adjustment factor Braking weight adjustment factor It can be adjusted according to system characteristics to flexibly adapt to the control requirements of different application scenarios. The control law automatically switches to continuous regulation when there is a risk of oscillation, and degenerates into extreme value control when there is no risk, thus balancing dynamic response speed and steady-state control accuracy.

[0115] The error amplitude-weighted duty cycle selection mechanism of this invention obtains the current error of the current cycle by sampling and obtains the predicted current error of the next cycle based on a state-space prediction model. Driving weight factors and braking weight factors are configured for both. Based on the weighted error magnitude, nonlinear interpolation is performed between the upper and lower limits of the duty cycle, making the output duty cycle continuously adjustable and avoiding the drawback of traditional pulse sequence control where the duty cycle only switches between maximum and minimum values ​​in a step manner. Furthermore, based on a dynamic weight factor mechanism, the driving weight factor is dynamically adjusted according to the magnitude of the current error, enabling the control law to adaptively match the nonlinear characteristics of the power factor correction main circuit. The larger the current error, the stronger the driving weight, and the closer the duty cycle is to the boundary for a fast response; the smaller the current error, the weaker the driving weight, and the more stable the duty cycle is near the theoretical optimal value to avoid overshoot.

[0116] This invention utilizes a dynamic weighting mechanism of error amplitude and prediction error, combined with a state-space model, to achieve continuous adjustment of the duty cycle. The current error amplitude determines the driving weight, propelling the duty cycle closer to the boundary; the prediction error amplitude determines the braking weight, pulling the duty cycle back towards the theoretical optimal value. The synergistic effect of these two factors achieves continuous, smooth, and non-linear interpolation output of the duty cycle between its upper and lower limits, fundamentally avoiding the abrupt changes caused by traditional binarization selection.

[0117] A dual-mechanism collaborative strategy of "error amplitude-driven dynamic weights + bidirectional hysteresis buffer" is proposed, enabling the control action to possess adaptive characteristics of "emphasizing regulation under large errors and stabilizing output under small errors." Under large errors, the driving weights dominate, and the duty cycle quickly approaches the boundary, achieving strong regulation; under small errors, the braking weights are relatively enhanced, and the duty cycle stabilizes near the theoretical optimal value, effectively avoiding frequent duty cycle switching and overshoot caused by small errors, and significantly improving the system's stability margin and robustness under disturbances.

[0118] Reference Figure 2 The diagram illustrates a control device for a converter according to an embodiment of the present invention. The converter includes a power factor correction main circuit, which includes an inductor and may specifically include the following structure: The duty cycle upper and lower limit determination module 201 is used to determine the upper limit and lower limit of the duty cycle for the current period. The inductor current acquisition module 202 is used to acquire the inductor current of the inductor in the current cycle; The current error determination module 203 is used to determine the current error of the current cycle based on the inductor current of the inductor in the current cycle. The current error prediction value determination module 204 is used to determine the current error prediction value for the next cycle based on the current error of the current cycle. The target duty cycle determination module 205 is used to determine the target duty cycle between the upper limit and the lower limit of the duty cycle in the current cycle based on the current error of the current cycle and the predicted current error of the next cycle.

[0119] This invention discloses a control device for a converter. The converter includes a power factor correction (PFCC) main circuit, which includes an inductor. The device determines the upper and lower limits of the duty cycle for the current cycle, acquires the inductor current for the current cycle, determines the current error for the current cycle based on the current current, determines the predicted current error for the next cycle based on the current error, and finally determines the target duty cycle between the upper and lower limits based on the current error and the predicted current error for the next cycle. By determining the predicted current error for the next cycle based on the current error of the current cycle and dynamically determining the target duty cycle between the upper and lower limits based on the current error and the predicted current error for the next cycle, continuous duty cycle adjustment is achieved. This avoids the high-frequency harmonic components and electromagnetic interference problems caused by abrupt changes in the duty cycle only between its maximum and minimum values.

[0120] In this embodiment of the invention, the converter further includes a rectifier bridge, and the duty cycle upper and lower limit determination module includes: The rectifier bridge output voltage acquisition submodule is used to acquire the output voltage of the rectifier bridge. The RMS value determination submodule is used to determine the RMS value of the rectifier bridge's output voltage based on the rectifier bridge's output voltage. The duty cycle upper and lower limit determination submodule is used to determine the upper and lower limits of the duty cycle for the current period based on the valid values.

[0121] In this embodiment of the invention, the duty cycle upper and lower limit determination submodule includes: The peak value determination unit is used to determine the peak value of the output voltage of the rectifier bridge based on the effective value. The inductance value acquisition unit is used to acquire the inductance value of the inductor and the output current of the power factor correction main circuit in the current cycle. The duty cycle upper limit determination unit is used to determine the upper limit of the duty cycle based on the peak value of the rectifier bridge output voltage, the inductance value of the inductor and the power factor correction of the current cycle to correct the output current of the main circuit. The output voltage acquisition unit is used to acquire the output voltage of the power factor correction main circuit in the current cycle. The duty cycle lower limit determination unit is used to determine the duty cycle lower limit based on the peak value of the rectifier bridge output voltage, the inductance value of the inductor, the output current of the power factor correction main circuit in the current cycle, and the output voltage of the power factor correction main circuit in the current cycle.

[0122] In this embodiment of the invention, the current error determination module includes: The inductor current reference value determination submodule is used to determine the inductor current reference value based on the peak value of the rectifier bridge output voltage, the rectifier bridge output voltage of the current cycle, the output current of the power factor correction main circuit of the current cycle, and the preset output voltage of the power factor correction main circuit. The current error determination submodule is used to determine the current error of the current cycle by the difference between the inductor current reference value and the inductor current of the current cycle.

[0123] In this embodiment of the invention, the current error prediction value determination module includes: The reference duty cycle determination submodule is used to select the upper or lower limit of the duty cycle as the reference duty cycle based on the polarity of the current error in the current cycle. The inductor current prediction value determination submodule is used to determine the inductor current prediction value for the next cycle based on the reference duty cycle, the output voltage of the rectifier bridge in the current cycle, the output voltage of the power factor correction main circuit in the current cycle, and the inductance value of the inductor. The current error prediction value determination submodule is used to determine the current error prediction value for the next cycle based on the inductor current prediction value for the next cycle.

[0124] In this embodiment of the invention, the target duty cycle determination module includes: The judgment submodule is used to determine whether the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and whether the absolute value of the predicted current error in the next cycle is greater than a preset threshold. The target duty cycle determination submodule is used to determine the target duty cycle between the upper and lower limits of the current cycle if the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and the absolute value of the predicted current error in the next cycle is greater than a preset threshold.

[0125] In this embodiment of the invention, the target duty cycle determination submodule includes: The braking weight factor determination unit is used to determine the braking weight factor based on the absolute value of the predicted current error value for the next cycle and a preset threshold. The driving weight factor determination unit is used to determine the driving weight factor based on the absolute value of the current current error. The target duty cycle determination unit is used to determine the target duty cycle based on the driving weight factor, the braking weight factor, the upper limit of the duty cycle and the lower limit of the duty cycle in the current cycle.

[0126] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0127] This invention also provides an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the various processes of the control method embodiments of the converter described above and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0128] It should be noted that the electronic devices in the embodiments of the present invention include the mobile electronic devices and non-mobile electronic devices described above.

[0129] This invention also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the control method embodiment of the converter described above and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0130] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0131] This invention also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the control method embodiment of the converter described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0132] It should be understood that the chip mentioned in the embodiments of the present invention may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0134] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0135] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A control method for a converter, characterized in that, The converter includes a power factor correction main circuit, the power factor correction main circuit includes an inductor, and the method includes: Determine the upper and lower limits of the duty cycle for the current period; Obtain the inductor current of the inductor in the current cycle; The current error for the current cycle is determined based on the inductor current of the inductor in the current cycle. Based on the current error of the current cycle, determine the predicted current error value for the next cycle; Based on the current error of the current cycle and the predicted current error of the next cycle, a target duty cycle is determined between the upper limit and the lower limit of the duty cycle of the current cycle.

2. The control method according to claim 1, characterized in that, The converter further includes a rectifier bridge, and determining the upper and lower limits of the duty cycle for the current cycle includes: Obtain the output voltage of the rectifier bridge; The effective value of the output voltage of the rectifier bridge is determined based on the output voltage of the rectifier bridge. Based on the effective value, determine the upper and lower limits of the duty cycle for the current period.

3. The control method according to claim 2, characterized in that, The step of determining the upper and lower limits of the duty cycle for the current period based on the effective value includes: Based on the effective value, determine the peak value of the output voltage of the rectifier bridge; Obtain the inductance value of the inductor and the output current of the power factor correction main circuit for the current cycle; The upper limit of the duty cycle is determined based on the peak value of the output voltage of the rectifier bridge, the inductance value of the inductor, and the output current of the power factor correction main circuit in the current cycle. Obtain the output voltage of the power factor correction main circuit for the current cycle; The lower limit of the duty cycle is determined based on the peak value of the output voltage of the rectifier bridge, the inductance value of the inductor, the output current of the power factor correction main circuit in the current cycle, and the output voltage of the power factor correction main circuit in the current cycle.

4. The control method according to claim 3, characterized in that, The step of determining the current error for the current period based on the inductor current of the inductor in the current period includes: The inductor current reference value is determined based on the peak value of the rectifier bridge output voltage, the output voltage of the rectifier bridge in the current cycle, the output current of the power factor correction main circuit in the current cycle, and the preset output voltage of the power factor correction main circuit. The difference between the inductor current reference value and the inductor current of the current cycle is determined as the current error of the current cycle.

5. The control method according to claim 3, characterized in that, The step of determining the predicted current error value for the next cycle based on the current error of the current cycle includes: Based on the polarity of the current error in the current cycle, select the upper limit of the duty cycle or the lower limit of the duty cycle as the reference duty cycle; The inductor current prediction value for the next cycle is determined based on the reference duty cycle, the output voltage of the rectifier bridge in the current cycle, the output voltage of the power factor correction main circuit in the current cycle, and the inductance value of the inductor. Based on the predicted inductor current value for the next cycle, determine the predicted current error value for the next cycle.

6. The control method according to claim 1, characterized in that, The step of determining a target duty cycle between the upper and lower limits of the duty cycle in the current cycle, based on the current error of the current cycle and the predicted current error of the next cycle, includes: Determine whether the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and whether the absolute value of the predicted current error in the next cycle is greater than a preset threshold. If the polarity of the current error in the current cycle is opposite to that of the predicted current error in the next cycle, and the absolute value of the predicted current error in the next cycle is greater than a preset threshold, then a target duty cycle is determined between the upper limit and the lower limit of the duty cycle in the current cycle.

7. The control method according to claim 6, characterized in that, Determining the target duty cycle between the upper and lower limits of the current duty cycle includes: The braking weight factor is determined based on the absolute value of the predicted current error for the next cycle and the preset threshold. The driving weighting factor is determined based on the absolute value of the current current error; The target duty cycle is determined based on the driving weight factor, the braking weight factor, the upper limit of the duty cycle for the current cycle, and the lower limit of the duty cycle.

8. A control device for a converter, characterized in that, The converter includes a power factor correction main circuit, the power factor correction main circuit includes an inductor, and the device includes: The duty cycle upper and lower limit determination module is used to determine the upper and lower limits of the duty cycle for the current period. An inductor current acquisition module is used to acquire the inductor current of the inductor in the current cycle; The current error determination module is used to determine the current error of the current cycle based on the inductor current of the inductor in the current cycle. The current error prediction value determination module is used to determine the current error prediction value for the next cycle based on the current error of the current cycle. The target duty cycle determination module is used to determine the target duty cycle between the upper limit and the lower limit of the duty cycle in the current cycle based on the current error of the current cycle and the predicted current error of the next cycle.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the control method for the converter as described in any one of claims 1-7.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the control method for the converter as described in any one of claims 1-7.

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