Power factor correction circuit and control method, control device and storage medium thereof

Abstract

Embodiments of the present application provide a power factor correction circuit and a control method, a control device and a storage medium thereof. The control method comprises: obtaining a zero-crossing off-maintaining time and a grid voltage; in response to the grid voltage satisfying a preset entering zero-crossing interval condition, turning off a first line frequency switch tube and a second line frequency switch tube; and in response to the off duration of the first line frequency switch tube and the second line frequency switch tube reaching the zero-crossing off-maintaining time, controlling the first line frequency switch tube and the second line frequency switch tube to work in a line frequency complementary conduction mode. By turning off the line frequency switch tube in the zero-crossing interval of the grid voltage and maintaining the zero-crossing off-maintaining time, the grid side is opened, and the Y capacitor is only powered by the bus capacitor to complete the pre-charging in the zero-crossing off-maintaining time. After the line frequency wave is resumed, the Y capacitor voltage no longer reverses and jumps greatly, thereby helping to weaken the grid side current peak, reduce the conducted EMI noise, improve the filter design pressure and product EMC pass rate.

Description

Technical Field

[0001] This application relates to the field of electronic power technology, and in particular to a power factor correction circuit and its control method, control device and storage medium. Background Technology

[0002] In the market for ultra-high efficiency switching power supplies, the totem-pole bridgeless power factor correction (PFC) topology has become one of the preferred solutions for various power supply products due to its theoretically high conversion efficiency. The core idea of ​​totem-pole bridgeless PFC is to eliminate the independent rectifier bridge and integrate the power frequency rectification function with the active switching function to reduce the number of devices and the on-state voltage drop in the conduction path.

[0003] However, the totem-pole waveform generation method has certain problems in practical applications. Near the zero-crossing point of the grid voltage, the instantaneous value of the input voltage is extremely low, and the signal-to-noise ratio of the current sampling signal in the PFC control loop drops sharply. At the same time, factors such as digital control delay and phase-locked loop (PLL) phase error work together to make it difficult for the controller to accurately generate a current command in phase with the grid voltage. At this time, the grid-side current will produce a spike distortion.

[0004] This current spike has abundant high-frequency spectral components, making it a relatively strong source of electromagnetic interference. It will significantly increase the high-frequency noise amplitude in conducted electromagnetic interference (EMI) tests, putting great pressure on filter design, increasing cost and size, and may even make it difficult for products to pass electromagnetic compatibility (EMC) certification. Summary of the Invention This application provides a power factor correction circuit and its control method, control device and storage medium, which can turn off the power frequency switching transistor in the zero-crossing range of the grid voltage, making the grid side open circuit, which helps to weaken the grid side current spikes and improve the conducted EMI performance.

[0005] In a first aspect, embodiments of this application provide a control method for a power factor correction circuit. The power factor correction circuit includes a low-frequency bridge arm branch, which includes a first power frequency switch and a second power frequency switch connected in series. The connection point between the first power frequency switch and the second power frequency switch is used to connect to a first end of the power grid. The control method includes: acquiring a zero-crossing turn-off duration and a power grid voltage; in response to the power grid voltage satisfying a preset zero-crossing interval condition, turning off the first power frequency switch and the second power frequency switch; and in response to the turn-off duration of the first power frequency switch and the second power frequency switch reaching the zero-crossing turn-off duration, controlling the first power frequency switch and the second power frequency switch to operate in a power frequency complementary conduction mode.

[0006] In one or more embodiments, the control method further includes: determining the actual grid phase angle at the current moment based on the grid voltage; obtaining the zero-point voltage phase angle, a preset zero-crossing phase angle margin, and the grid cycle; determining the zero-crossing turn-off phase angle range based on the zero-point voltage phase angle and the preset zero-crossing phase angle margin; determining that the grid voltage satisfies the preset zero-crossing interval condition if the actual grid phase angle is within the zero-crossing turn-off phase angle range; determining the zero-crossing end phase angle range based on the zero-point voltage phase angle, the preset zero-crossing phase angle margin, the grid cycle, and the zero-crossing turn-off duration; and determining that the turn-off duration of the first power frequency switch and the second power frequency switch reaches the zero-crossing turn-off duration if the actual grid phase angle is within the zero-crossing end phase angle range.

[0007] In one or more embodiments, the power factor correction circuit further includes a bus capacitor, a Y capacitor CY1, a filter inductor, and a high-frequency bridge arm branch. The high-frequency bridge arm branch includes a first high-frequency switch and a second high-frequency switch connected in series. The high-frequency bridge arm branch, the low-frequency bridge arm branch, and the bus capacitor are connected in parallel to the DC bus. The connection point of the first high-frequency switch and the second high-frequency switch is connected to the first terminal of the filter inductor. The second terminal of the filter inductor is connected to one terminal of the Y capacitor CY1 and the second terminal of the power grid. The other terminal of the Y capacitor CY1 is connected to the bus capacitor. An equivalent charging loop is formed between the bus capacitor and the Y capacitor CY1. Obtaining the zero-crossing turn-off sustaining time includes: obtaining a control delay, the equivalent resistance of the equivalent charging loop, and the capacitance value of the Y capacitor CY1; determining the zero-crossing turn-off sustaining time based on the control delay, the equivalent resistance, and the capacitance value, wherein the zero-crossing turn-off sustaining time satisfies the following relationship: Toff≥T_delay+3RC cy1 ; Toff is the zero-crossing turn-off duration, T_delay is the control delay, R is the equivalent resistance, and C...cy1 Let CY1 be the capacitance value of the Y capacitor.

[0008] In one or more embodiments, obtaining the zero-crossing shutdown duration includes: setting an initial zero-crossing shutdown duration and using the initial zero-crossing shutdown duration as the current zero-crossing shutdown duration; under preset load conditions, based on the current zero-crossing shutdown duration, running the power factor correction circuit and detecting the grid current waveform; if the grid current waveform has a current spike at the zero-crossing moment, increasing the current zero-crossing shutdown duration according to a first adjustment rule, and re-running the power factor correction circuit and detecting the grid current waveform until the grid current waveform does not have a current spike at the zero-crossing moment; if the grid current waveform does not have a current spike at the zero-crossing moment, decreasing the current zero-crossing shutdown duration according to a second adjustment rule, and running the power factor correction circuit and detecting the grid current waveform until the grid current waveform has a current spike at the zero-crossing moment, and determining the current zero-crossing shutdown duration corresponding to the previous detection before the current spike appears as the zero-crossing shutdown duration.

[0009] In one or more embodiments, the power factor correction circuit further includes a high-frequency bridge arm branch, the high-frequency bridge arm branch including a first high-frequency switch and a second high-frequency switch connected in series, and the control method further includes: in response to the grid voltage meeting a preset zero-crossing interval condition, controlling the first high-frequency switch and the second high-frequency switch to perform a duty cycle soft switching action during the zero-crossing shutdown maintenance time.

[0010] In one or more embodiments, the power factor correction circuit further includes a filter inductor. Controlling the first high-frequency switch and the second high-frequency switch to perform a duty cycle soft-switching action includes: before the grid voltage crosses zero, gradually reducing the duty cycle of the first current main control switch by a first preset step size, and controlling the duty cycle of the first current synchronous rectifier according to a preset waveform rule, until the current of the filter inductor decreases to a preset target current value, and then turning off the first current main control switch. Specifically, before the grid voltage crosses zero, if the grid voltage is in the positive half-cycle, the first current main control switch is the second high-frequency switch, and the first current synchronous rectifier is the first high-frequency switch; if the grid voltage is in the negative half-cycle, the first current main control switch is the second high-frequency switch, and the first current synchronous rectifier is the first high-frequency switch. The first high-frequency switch is the first main control switch, and the second high-frequency switch is the first current synchronous rectifier. After the grid voltage crosses zero, the duty cycle of the second current main control switch is gradually increased according to a second preset step size, and the duty cycle of the second current synchronous rectifier is controlled according to a preset waveform rule until the duty cycle of the second current main control switch reaches the target duty cycle. Specifically, after the grid voltage crosses zero, if the grid voltage is in the positive half-cycle, the second current main control switch is the second high-frequency switch, and the second current synchronous rectifier is the first high-frequency switch; if the grid voltage is in the negative half-cycle, the second current main control switch is the first high-frequency switch, and the second current synchronous rectifier is the second high-frequency switch.

[0011] In one or more embodiments, the method for determining the second preset step size includes: acquiring the inductance of the filter inductor, the switching period, the current bus voltage, and the target current; and determining the second preset step size based on the inductance of the filter inductor, the switching period, the current bus voltage, and the target current, wherein the second preset step size satisfies the following relationship: ΔD≤(L×I_target) / (Vbus×T_s) Where I_target is the target current, L is the inductance of the filter inductor, Vbus is the current bus voltage, and T_s is the switching cycle.

[0012] In a second aspect, embodiments of this application provide a control device, including: a processor, and a memory communicatively connected to the processor; the memory stores computer program instructions executable by the processor, which, when executed by the processor, cause the control device to perform the control method as described in any of the first aspects.

[0013] Thirdly, embodiments of this application provide a power factor correction circuit, including: a low-frequency bridge arm branch, a high-frequency bridge arm branch, a bus capacitor, a filter inductor, and a control device as described in the second aspect; the low-frequency bridge arm branch includes a first power frequency switch and a second power frequency switch connected in series, the connection point of the first power frequency switch and the second power frequency switch being used to connect to a first end of the power grid; the high-frequency bridge arm branch includes a first high-frequency switch and a second high-frequency switch connected in series, the high-frequency bridge arm branch, the low-frequency bridge arm branch, and the bus capacitor being connected in parallel to a DC bus, the connection point of the first high-frequency switch and the second high-frequency switch being used to connect to a second end of the power grid via the filter inductor; the control device is connected to the control terminal of the low-frequency bridge arm branch and the control terminal of the high-frequency bridge arm branch.

[0014] Fourthly, embodiments of this application provide a computer storage medium storing instructions or programs that, when executed by at least one processor, cause the at least one processor to perform the method described in any of the first aspects above.

[0015] Fifthly, embodiments of this application also provide a computer program product, the computer program product including a computer program stored on a computer-readable storage medium, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the method described in the first aspect above.

[0016] The beneficial effects of this application are as follows: This application provides a power factor correction circuit and its control method, control device, and storage medium. The control method includes: acquiring the zero-crossing turn-off duration and the grid voltage; in response to the grid voltage meeting a preset zero-crossing interval condition, turning off the first and second power frequency switches; in response to the turn-off duration of the first and second power frequency switches reaching the zero-crossing turn-off duration, controlling the first and second power frequency switches to operate in a power frequency complementary conduction mode. By turning off the power frequency switches within the grid voltage zero-crossing interval and maintaining the zero-crossing turn-off duration, the grid side is open-circuited. During the zero-crossing turn-off duration, the Y capacitor is pre-charged only by the bus capacitor. After the power frequency transmission resumes, the Y capacitor voltage no longer experiences a large reverse jump, thereby helping to weaken grid-side current spikes, reduce conducted EMI noise, and improve filter design pressure and product EMC pass rate. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not intended to limit the embodiments, and elements having the same reference numerals in the drawings are designated as similar elements.

[0018] Figure 1This is a schematic diagram of the topology of the power factor correction circuit provided in the embodiments of this application; Figure 2 This is a schematic diagram showing the relationship between the driving waveforms of the first high-frequency switch to the second power frequency switch and the grid voltage provided in the embodiments of this application; Figure 3 yes Figure 2 A magnified view of the driving waveform near the zero crossing point; Figure 4 This is a schematic diagram of the grid voltage near the zero crossing point, the voltage of Y capacitor CY1, and the current waveforms of each branch provided in the embodiments of this application; Figure 5 yes Figure 4 A magnified schematic diagram of a portion of the current spike; Figure 6 This is a schematic diagram of the driving waveform at the moment of switching from the positive half-cycle to the negative half-cycle provided in the embodiments of this application; Figure 7 This is a schematic diagram of the charging circuit of the bus capacitor to Y capacitor CY1 after commutation provided in the embodiments of this application; Figure 8 This is a schematic diagram of the circuit formed by the power grid after commutation, provided in an embodiment of this application. Figure 9 This is a schematic diagram of an equivalent circuit provided in an embodiment of this application; Figure 10 This is a schematic diagram of the equivalent RC charging circuit provided in the embodiment of this application, in which the Y capacitor CY1 is powered only by the bus capacitor after the power frequency switch is turned off at zero crossing. Figure 11 This is a schematic diagram of the current and voltage waveforms after the power frequency switch is turned off at zero crossing, as provided in the embodiments of this application. Figure 12 yes Figure 11 A magnified view of a portion of the image; Figure 13 This is a schematic diagram of the control device provided in the embodiments of this application; Figure 14 This is a schematic flowchart of the power factor correction circuit control method provided in the embodiments of this application; Figure 15 This is a waveform diagram of the zero-crossing shutdown sustaining time setting process provided in the embodiments of this application; Figure 16 This is a timing diagram showing the zero-crossing turn-off sustaining time, the driving of the power frequency switch, and the grid voltage and current, provided in the embodiments of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described clearly and in detail below with reference to the accompanying drawings. Obviously, the embodiments in this application are only some embodiments, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0020] It should be noted that when an element is described as "connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements between them.

[0021] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0022] To facilitate understanding of the methods provided in the embodiments of this application, the power factor correction circuit provided in the embodiments of this application will be described first.

[0023] Please see Figure 1 , Figure 1 The diagram schematically illustrates the topology of a power factor correction (PFC) circuit according to this application. This power factor correction circuit can employ a totem-pole bridgeless PFC, integrating the power frequency rectification function and the high-frequency chopping function into the same bridge arm structure, which helps to reduce the number of power devices in the conduction path, reduce the on-state voltage drop, and improve the overall conversion efficiency.

[0024] In some of these embodiments, see Figure 1 The power factor correction circuit includes a low-frequency bridge arm branch 10, a high-frequency bridge arm branch 20, a bus capacitor C1, a filter inductor L1, a filter capacitor C2, a Y capacitor CY1, a Y capacitor CY2, and a control device.

[0025] The bus capacitor C1 refers to the energy storage capacitor connected between the positive and negative terminals of the DC bus. One end of the bus capacitor C1 is connected to the positive terminal of the DC bus, and the other end is connected to the negative terminal of the DC bus. The voltage across the bus capacitor C1 is denoted as the bus voltage Vbus. The bus capacitor C1 serves two purposes: firstly, it supports the DC bus voltage and smooths out power fluctuations in the downstream load; secondly, during the zero-crossing blocking period of this application, the bus capacitor C1 acts as a pre-charging energy source for the Y capacitor, providing charging current to the Y capacitor. By using the bus capacitor as a pre-charging power source, no additional charging branch is needed, which helps simplify the circuit structure and control hardware costs.

[0026] The high-frequency bridge arm branch 20 refers to a bridge arm operating in a high-frequency switching state for implementing PFC chopper control. The high-frequency bridge arm branch 20 includes a first high-frequency switch Q1 and a second high-frequency switch Q2 connected in series. One end of the first high-frequency switch Q1 is connected to the positive terminal of the DC bus, and the other end of the first high-frequency switch Q1 is connected to one end of the second high-frequency switch Q2 at a first common connection point. The other end of the second high-frequency switch Q2 is connected to the negative terminal of the DC bus, and the first common connection point is connected to the first terminal of the filter inductor L1. The switching frequency of the high-frequency bridge arm branch 20 is higher than the power frequency, for example, 20kHz. The high-frequency bridge arm branch 20 controls the charging and discharging of the filter inductor L1 through pulse width modulation, making the input current follow the grid voltage waveform to achieve power factor correction.

[0027] The low-frequency bridge arm branch 10 refers to a bridge arm operating at the power frequency and used to implement power frequency rectification. The low-frequency bridge arm branch 10 includes a first power frequency switch Q3 and a second power frequency switch Q4 connected in series. One end of the first power frequency switch Q3 is connected to the positive terminal of the DC bus, and the other end of the first power frequency switch Q3 and one end of the second power frequency switch Q4 are connected to a second common connection point. The other end of the second power frequency switch Q4 is connected to the negative terminal of the DC bus. The second common connection point is used to connect to the first terminal of the power grid, such as the neutral terminal of an AC power grid. The operating frequency of the low-frequency bridge arm branch 10 is the same as the power grid frequency, for example, 50Hz. During the positive half-cycle of the power grid voltage, the second power frequency switch Q4 remains normally on, and the first power frequency switch Q3 remains normally off, with current flowing through Q4. During the negative half-cycle of the power grid voltage, the first power frequency switch Q3 remains normally on, and the second power frequency switch Q4 remains normally off, with current flowing through the first power frequency switch Q3. Delegating the rectification function to the low-frequency bridge arm to perform power frequency switching helps reduce switching losses and improve overall efficiency.

[0028] The high-frequency bridge arm branch 20, the low-frequency bridge arm branch 10, and the bus capacitor C1 are connected in parallel to the DC bus. That is, the two ends of the high-frequency bridge arm branch 20, the two ends of the low-frequency bridge arm branch 10, and the two ends of the bus capacitor C1 are connected across the positive and negative ends of the DC bus. This parallel structure allows the high-frequency chopper and the power frequency rectifier to share the same DC bus, which facilitates the transfer of energy between the AC and DC sides.

[0029] The filter inductor L1 is an energy storage inductor connected in series between the first point of common coupling (PCC) and the second terminal of the power grid. The first terminal of filter inductor L1 is connected to the PCC. The second terminal of filter inductor L1 is connected to one end of filter capacitor C2, one end of Y capacitor CY1, and the second terminal of the power grid, such as the live wire of an AC power grid. Filter inductor L1 stores energy when the high-frequency switching transistor is turned on and releases the energy to the bus capacitor and load when the high-frequency switching transistor is turned off. It is the core energy storage component of PFC chopper. The current flowing through filter inductor L1 is denoted as Iinv.

[0030] Filter capacitor C2 is the filter capacitor connected between the second terminal of filter inductor L1 and the second common connection point. One end of filter capacitor C2 is connected to the second terminal of filter inductor L1, and the other end of filter capacitor C2 is connected to the second common connection point. Filter capacitor C2 and filter inductor L1 together form an LC filter network, used to suppress high-frequency switching ripple and improve the quality of grid-connected current waveform. The current flowing through filter capacitor C2 is denoted as Ic.

[0031] Y-capacitors CY1 and CY2 are safety capacitors used to suppress common-mode interference. The AC power grid consists of a live wire (L) and a neutral wire (N). In a common grounding method, the center point between the live wire (L) and neutral wire (N) of the AC power grid is used as the grounding reference point for common-mode analysis. One end of Y-capacitor CY1 is connected to the second terminal of the filter inductor L1 (i.e., one side of the second terminal of the AC power grid), and the other end of Y-capacitor CY1 is connected to the negative terminal of the DC bus. One end of Y-capacitor CY2 is connected to the first terminal of the AC power grid, and the other end of Y-capacitor CY2 is connected to the negative terminal of the DC bus. Y-capacitors CY1 and CY2 provide a low-impedance discharge path for common-mode noise, helping to reduce conducted EMI. The current flowing through Y-capacitor CY1 is denoted as Icy1, the current flowing through Y-capacitor CY2 is denoted as Icy2, and the current on the AC power grid side is denoted as Igrid.

[0032] It should be noted that during zero-crossing commutation, the voltage across the Y capacitor CY1 may experience a rapid reverse jump. Based on the relationship between capacitor current and voltage change rate, this jump will generate a displacement current spike on the Y capacitor. This spike is reflected as a grid-side current spike through the grid-side circuit, which is one of the important sources of conducted EMI. This application addresses this phenomenon by turning off the power frequency switch during the zero-crossing interval, thus opening the grid side and allowing the bus capacitor C1 to pre-charge the Y capacitor CY1, thereby reducing the voltage jump amplitude after recovery ripple generation.

[0033] The first high-frequency switch Q1, the second high-frequency switch Q2, the first power frequency switch Q3, and the second power frequency switch Q4 can all be metal-oxide-semiconductor field-effect transistors (MOSFETs), or insulated-gate bipolar transistors (IGBTs) or other controllable switching devices; no limitation is made here. Each switch can utilize its own body diode or be connected to an external freewheeling diode to provide a current freewheeling path.

[0034] The control device is connected to the control terminal of the low-frequency bridge arm branch 10 and the control terminal of the high-frequency bridge arm branch 20. Specifically, the drive output terminal of the control device is connected to the gate (or gate electrode) of the first high-frequency switch Q1, the second high-frequency switch Q2, the first power frequency switch Q3, and the second power frequency switch Q4, respectively. The control device controls the turn-on and turn-off sequence of each switch by outputting drive signals, thereby executing the control method provided in the embodiments of this application. The control device can also be connected to a grid voltage sampling circuit, an inductor current sampling circuit, etc., to obtain feedback quantities such as grid voltage and inductor current.

[0035] In this embodiment, the power factor correction circuit adopts a totem-pole bridgeless structure, with clear division of labor between the high-frequency and low-frequency bridge arms: the high-frequency bridge arm is responsible for chopping and current regulation, while the low-frequency bridge arm is responsible for power frequency commutation. The bus capacitor C1 supports the bus voltage during normal operation and also serves as a pre-charge power supply for the Y capacitor during zero-crossing suppression. While the Y capacitor is used for common-mode suppression, its voltage behavior at zero-crossing is also a focus of the control strategy in this application. The above circuit structure provides the hardware foundation for the subsequent control method of turning off the power frequency transistor at zero crossing.

[0036] In some embodiments, the waveform generation method of each switch in the power factor correction circuit is as follows. Please refer to... Figure 2 and Figure 3 , Figure 2 The diagram shows the correspondence between the driving waveforms of the first high-frequency switch Q1 to the second power frequency switch Q4 and the mains voltage Vgrid. Figure 3 This is a magnified view of the driving waveform near the zero crossing point.

[0037] When the AC input voltage is in the positive half-cycle (i.e., the grid voltage Vgrid > 0), the second power frequency switch Q4 remains normally on, and the first power frequency switch Q3 remains normally off, with current flowing through Q4 to form a path. When the AC input voltage is in the negative half-cycle (grid voltage Vgrid < 0), the first power frequency switch Q3 remains normally on, and the second power frequency switch Q4 remains normally off, with current flowing through Q3 to form a path. Figure 3 As shown in the second section, Q4 is turned on before 0.03s, corresponding to the positive half-cycle of the mains voltage; Q3 is turned on after 0.03s, corresponding to the negative half-cycle of the mains voltage. The power frequency transistor maintains a constant on / off state during the half-cycle, resulting in fewer switching cycles and helping to reduce switching losses.

[0038] The high-frequency bridge arm employs complementary conduction pulse width modulation control with a dead time to reduce the risk of shoot-through. During the positive half-cycle, the second high-frequency switch Q2 acts as the main control switch. When Q2 is on, the filter inductor L1 stores energy, and the inductor current increases. When Q2 is off, the first high-frequency switch Q1 acts as the synchronous rectifier, providing a freewheeling path for the inductor current and transferring energy to the bus capacitor and load. During the negative half-cycle, Q1 acts as the main control switch, and Q2 acts as the synchronous rectifier. Figure 3 As shown in the first section, before 0.03s, it is in the positive half-cycle, with the second high-frequency switch Q2 being the main control switch and the first high-frequency switch Q1 being the synchronous rectifier; after 0.03s, it is in the negative half-cycle, with the first high-frequency switch Q1 being the main control switch and the second high-frequency switch Q2 being the synchronous rectifier.

[0039] The master control switch is a high-frequency switch that controls the charging and discharging of the inductor by adjusting its duty cycle during the current half-cycle of the power frequency. The synchronous rectifier is a high-frequency switch that conducts during the turn-off period of the master control switch, providing a low-impedance freewheeling path for the inductor current. Dead time is the brief interval during which both the upper and lower transistors of the same bridge arm are turned off, used to prevent shoot-through.

[0040] In this embodiment, by configuring the power frequency rectification and high-frequency chopping on the low-frequency bridge arm and the high-frequency bridge arm respectively, the control logic is clear and easy to adjust independently. The high-frequency bridge arm interchanges the roles of main controller and synchronous rectification during the positive and negative half-cycles, which can continuously achieve PFC control throughout the entire power frequency cycle, helping to improve the sinusoidal nature of the input current and the power factor.

[0041] In some embodiments, combined Figures 4 to 9 The generation mechanism of the zero-crossing current spike is explained as follows.

[0042] Please see Figure 4 and Figure 5 , Figure 4 The waveforms of the grid voltage, Y capacitor voltage, and branch currents near the zero-crossing point are shown. Figure 5 This is a magnified view of a localized current spike. From Figure 4 It can be seen that the voltage of the Y capacitor reverses after the grid voltage crosses zero. According to the capacitor current formula: Icy1=C cy1 ×(dVcy1 / dt) C cy1 Let I be the capacitance of the Y capacitor. The Y capacitor current Icy1 is related to the rate of change of the Y capacitor voltage Vcy1, dVcy1 / dt. When the Y capacitor voltage rapidly reverses, dVcy1 / dt is large, resulting in a large displacement current spike on the Y capacitor. Figure 5As shown in the red circle, a current spike appears in Icy1, and the grid-side current Igrid also shows a spike with similar amplitude but opposite direction, while the inductor current Iinv is relatively smooth. This indicates that the grid-side current spike does not originate from a sudden change in the inductor current, but mainly from the coupling of the Y capacitor displacement current through the grid loop.

[0043] Please see Figure 6 , Figure 6 The driving waveform at the moment of switching from the positive half-cycle to the negative half-cycle is shown. At the zero-crossing point, the second power frequency switch Q4 switches from normally on to off, and the first power frequency switch Q3 switches from off to normally on. At the same time, the duty cycle of the first high-frequency switch Q1 reverses from a smaller value to a larger value.

[0044] At some point after commutation (e.g.) Figure 6 In the interval shown in T1, due to the large duty cycle of the first high-frequency switch Q1, the Y capacitor CY1 is clamped to near the bus voltage, meaning the instantaneous voltage of CY1 is approximately equal to the bus voltage Vbus. The corresponding current loop is as follows: Figure 7 As shown, the bus capacitor C1 charges the Y capacitor CY1 through the conducting switch. Since there is often a deviation between the actual control phase and the true phase of the power grid, the grid voltage may still be on the positive half-axis. The conduction of Q3 will also form another loop through the AC source, such as... Figure 8 As shown.

[0045] The two loops mentioned above are combined into an equivalent model, such as Figure 9 As shown. In the equivalent model, the bus capacitor C1, filter inductor L1, and Y capacitor CY1 are interconnected with the power grid AC. And: Icy1 = Iinv - Igird; Since the filter inductor L1 limits the sudden change in current, the current flowing through L1 is much smaller than the mains current and can be approximated as negligible. Therefore: Igrid≈ Icy1; The inventor of this application has reviewed... Figure 4 , Figure 5 The comparison and analysis of the measured waveforms shown above with the equivalent circuit revealed that the current spikes on the grid side and the current spikes passing through the Y capacitor are opposite in direction and approximately equal in amplitude, similar to Igrid≈ The derivation results of Icy1 are consistent. Therefore, it can be clearly stated that the grid-side current spike at the zero-crossing point is not primarily caused by a sudden change in inductor current, but rather by the coupling of the displacement current caused by the reverse voltage jump of the Y capacitor through the grid-side loop. If the transmission of this displacement current to the grid side cannot be limited from the loop, relying solely on phase alignment or fine-tuning of local switching timing will still be insufficient to reliably eliminate the zero-crossing current spike and the resulting conducted EMI problems.

[0046] Based on the above findings, this application adopts a control approach that simultaneously turns off the first and second power frequency switches in the zero-crossing interval, opens the grid side, and pre-charges the Y capacitor by the bus capacitor, so as to cut off the transmission path of the displacement current to the AC grid side from the circuit structure, thereby weakening the grid side current spike.

[0047] The control device shuts off the power frequency transistor drive before and after the zero-crossing point, turning off both the first power frequency switch Q3 and the second power frequency switch Q4, opening the grid side and making the grid current Igrid approximately zero. At this time, the Y capacitor CY1 is powered only by the bus capacitor C1 through the equivalent on-resistance, and the equivalent circuit is simplified to... Figure 10 The RC charging circuit is shown. During the zero-crossing turn-off sustaining time window, the Y capacitor voltage is gradually pre-charged to near the target level. When the power frequency transmission resumes, the Y capacitor voltage is at a suitable level, no longer experiencing large reverse jumps, dVcy1 / dt decreases, and the displacement current spike weakens accordingly.

[0048] Please see Figure 11 and Figure 12 , Figure 11 The waveforms of the grid current after wave blocking are shown. Figure 12 This is a magnified view of a portion of the circuit. It can be seen that at the moment of power frequency switching, there is no obvious spike in the grid-side current; only the current change caused by pre-charging exists on the Y capacitor, and this change is no longer significantly coupled to the grid side.

[0049] In this embodiment, the grid side is opened by the zero-crossing blocking wave, which restricts the charging path of the Y capacitor to the bus capacitor side. This cuts off the transmission path of displacement current to the grid side from the circuit structure, which helps to suppress zero-crossing current spikes without changing the main power topology.

[0050] Specifically, such as Figure 13 As shown, the control device 30 includes at least one processor 31 and a memory 32 connected in communication. Figure 13 Taking a bus system connection and a processor 31 as an example. Understandably, the various components in the control device 30 are coupled together through a bus system, which is used to achieve communication between the components. It is easy to understand that the bus system, in addition to the data bus, can also include a power bus, a control bus, and a status signal bus, etc. However, for clarity and brevity, in... Figure 13 The general refers to all buses as bus systems. This is understandable. Figure 13 The structures shown in the embodiments are merely illustrative and do not limit the structure of the control device 30 described above. For example, the control device 30 may also include components that are more... Figure 13 The structure shown has more or fewer components, or has the same as Figure 13 The diagram shows different configurations of the structure.

[0051] Specifically, the processor 31 provides computational and control capabilities to support the control device 30 in executing corresponding business logic. For example, it supports the control device 30 in executing the methods provided in the embodiments of this application, or in executing the steps in any possible implementation of the methods provided in the embodiments of this application. Those skilled in the art will understand that the processor 31 can be a general-purpose processor 31, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0052] The memory 32, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, instructions, and modules, such as the programs, instructions, and modules corresponding to the methods in the embodiments of this application. In some embodiments, the memory 32 may include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, and the data storage area may store data created according to the use of the processor 31. The processor 31 executes various functional applications and data processing of the control device 30 by running the non-transitory software programs, instructions, and modules stored in the memory 32 to implement the methods provided in the embodiments of this application, or to perform the steps in any possible implementation of the methods provided in the embodiments of this application. In some embodiments of this application, the memory 32 may include high-speed random access memory and may also include non-transitory memory. For example, at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 32 may also include memory remotely located relative to the processor 31, which may be connected to the processor 31 via a communication network. It is understood that examples of the above-mentioned communication networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0053] As can be understood from the foregoing, the implementing entity of any method provided in the embodiments of this application can be any suitable type of control device 30 with certain computing and control capabilities, such as the aforementioned control device 30. In some feasible implementations, any method provided in the embodiments of this application can be implemented by the processor 31 executing computer program instructions stored in the memory.

[0054] The control method provided in this application will be described in detail below with reference to exemplary applications and implementations of the control device provided in the embodiments of this application. This method is applied to a control device for a power factor correction circuit. Specifically, the execution subject of this method is one or at least two processors of the control device.

[0055] Please see Figure 14 The control method includes, but is not limited to, the following steps S100 to S300.

[0056] Step S100: Obtain the zero-crossing shutdown duration and grid voltage.

[0057] Zero-crossing turn-off duration refers to the target duration during which the first and second power frequency switches remain in the off state simultaneously within the zero-crossing range of the grid voltage, denoted as Toff.

[0058] The grid voltage refers to the instantaneous or sampled voltage value at the AC input port of the power factor correction circuit, denoted as Vgrid. The grid voltage can be obtained by sampling through a resistor divider network, or the existing voltage sampling signal in the PFC control loop can be directly reused to reduce hardware costs.

[0059] Step S200: In response to the grid voltage meeting the preset zero-crossing condition, turn off the first power frequency switch and the second power frequency switch.

[0060] The preset zero-crossing condition refers to the judgment rule used to determine whether the grid voltage has entered the region near zero crossing. When the grid voltage meets this condition, the control device simultaneously turns off the first power frequency switch Q3 and the second power frequency switch Q4, thus opening the grid side.

[0061] Step S300: In response to the turn-off duration of the first power frequency switch and the second power frequency switch reaching the zero-crossing turn-off maintenance time, control the first power frequency switch and the second power frequency switch to operate in the power frequency complementary conduction mode.

[0062] The power frequency complementary conduction mode refers to the normal operating mode in which the low-frequency bridge arm alternately turns on and off during the positive and negative half-cycles. Specifically: during the positive half-cycle, the second power frequency switch Q4 is normally on, and the first power frequency switch Q3 is normally off; during the negative half-cycle, the first power frequency switch Q3 is normally on, and the second power frequency switch Q4 is normally off. When the off-time reaches Toff, the control device resumes this normal waveform transmission mode.

[0063] In this embodiment, by turning off the power frequency switch during the zero-crossing interval, the grid side is opened, and the Y capacitor is pre-charged solely by the bus capacitor. Once the power frequency transmission resumes, the Y capacitor voltage no longer experiences a large reverse jump, thus helping to weaken grid-side current spikes and reduce conducted EMI noise. This scheme maintains normal power frequency complementary conduction outside the zero-crossing interval, minimizing the impact on normal PFC operation.

[0064] In some embodiments, the control method may also include, but is not limited to, the following steps S201 to S206.

[0065] Step S201: Determine the actual grid phase angle at the current moment based on the grid voltage.

[0066] The actual power grid phase angle refers to the phase angle of the fundamental voltage wave of the AC power grid at the current moment, denoted as θ.

[0067] Specifically, the preprocessed grid voltage can be input into a generalized second-order integrator (SOGI). The transfer function of the SOGI can be expressed as: , ; Where ω is the grid angular frequency, satisfying ω=2πf, f is the grid frequency, and k is the damping coefficient, used to determine the system bandwidth and dynamic response speed. For example, k can be taken as = ; The component that is in phase with the fundamental frequency of the power grid; The component orthogonal to the fundamental frequency of the power grid (relative) (Lag 90°).

[0068] Next, based on the orthogonal components of SOGI output and The real-time power grid phase angle θ is obtained through arctangent calculation: .

[0069] It should be noted that in actual implementation, it can also be combined with and The quadrant in which the phase angle is located is extended to θ to obtain a continuous phase angle in the range of 0° to 360°.

[0070] In this embodiment, SOGI can extract quadrature components from noisy grid voltages, providing a certain degree of suppression for harmonics and noise. The real-time phase angle is obtained by combining the arctangent, and then zero-crossing control is achieved using a phase angle window. The logic is clear and easy to implement in embedded systems.

[0071] Step S202: Obtain the zero-point voltage phase angle, the preset zero-crossing phase angle margin, and the grid cycle.

[0072] The zero-point voltage phase angle θ_zero refers to the phase angle corresponding to the moment when the AC grid voltage crosses zero, including 0° and 180°. The preset zero-crossing phase angle margin refers to the angular allowance reserved on both sides of the zero-point voltage phase angle, denoted as θ_th; in one example, θ_th can be 2°. The grid cycle refers to the duration of one complete power frequency cycle of the AC grid voltage, denoted as T_grid.

[0073] A preset zero-crossing phase angle margin θ_th is used to form a zero-crossing judgment window on both sides of the zero-point voltage phase angle. This allows the dual-frequency switching transistors to enter the turn-off interval earlier when the grid voltage is close to zero, reducing the risk that the actual grid may have entered the zero-crossing neighborhood before the frequency switching transistors are turned off due to factors such as phase-locked loop errors, sampling errors, and control delays. Based on a 50Hz power frequency, 2° corresponds to a phase angle time width on the order of 111μs. This width is sufficient to cover zero-crossing judgment deviations caused by phase-locked loop or phase angle calculation errors, sampling and control cycles, etc., which helps ensure that the first and second frequency switching transistors are turned off before zero crossing. Furthermore, it represents a very small percentage of half a power frequency cycle, helping to avoid a significant shortening of the effective conduction angle due to an excessively large zero-crossing phase angle margin, thereby mitigating the adverse effects on power factor and current harmonics. It should be noted that 2° is only an example and not a limitation on θ_th; it can be set as needed in actual applications.

[0074] Step S203: Determine the zero-crossing turn-off phase angle range based on the zero-point voltage phase angle and the preset zero-crossing phase angle margin; Step S204: If the actual grid phase angle is within the zero-crossing turn-off phase angle range, then determine that the grid voltage meets the preset conditions for entering the zero-crossing interval. The zero-crossing turn-off phase angle range refers to the set of phase angles that determine whether the grid has entered the zero-crossing interval. For example, the zero-crossing turn-off phase angle range can be taken as the range in which the absolute value of the phase angle is less than or equal to the sum of the zero-point voltage phase angle and the preset zero-crossing phase angle margin. That is, when |θ|≤θ_zero+θ_th, the grid is determined to have entered the zero-crossing interval, and a power frequency tube turn-off signal is generated.

[0075] Step S205: Determine the zero-crossing end phase angle range based on the zero-point voltage phase angle, the preset zero-crossing phase angle margin, the power grid cycle, and the zero-crossing turn-off maintenance time; Step S206: If the actual power grid phase angle is within the zero-crossing end phase angle range, then determine that the turn-off duration of the first power frequency switch and the second power frequency switch reaches the zero-crossing turn-off maintenance time.

[0076] The zero-crossing termination phase angle range refers to the set of phase angles used to determine the end of the zero-crossing interval and the resumption of power frequency transmission. For example, the zero-crossing termination phase angle range can be taken as the range of the sum of the phase angle greater than or equal to the zero-point voltage phase angle, the preset zero-crossing phase angle margin, and the phase angle increment corresponding to the zero-crossing turn-off duration. That is, when θ ≥ θ_zero + θ_th + (Toff / T_grid) × 360°, the zero-crossing interval is determined to have ended, and the power frequency tube resumes normal transmission.

[0077] In this embodiment, the entry and exit of the zero-crossing interval are determined by the phase angle range, and the time window Toff is mapped to the phase angle window, which is convenient to implement in the digital controller and is adaptive to the power grid frequency, which helps to maintain a relatively accurate timing of wave blocking even when the frequency fluctuates.

[0078] In some embodiments, the power factor correction circuit further includes a bus capacitor, a Y capacitor CY1, a filter inductor, and a high-frequency bridge arm branch. An equivalent charging loop is formed between the bus capacitor and the Y capacitor CY1. Obtaining the zero-crossing turn-off sustaining time includes, but is not limited to, the following steps S211 to S212. Step S211: Obtain the control delay, the equivalent resistance of the equivalent charging loop, and the capacitance value of the Y capacitor CY1; Step S212: Determine the zero-crossing turn-off sustaining time based on the control delay, the equivalent resistance, and the capacitance value.

[0079] Control delay refers to the total time required for the control system to complete the actual turn-off action of the power frequency switch from determining that it has entered the zero-crossing interval. It is denoted as T_delay. Control delay can include at least one of the following: phase-locked loop (PLL) phase detection delay, pulse-width modulation (PWM) drive delay, and switch-on delay. PLL phase detection delay refers to the time difference between the moment the grid voltage actually reaches zero (or just enters the set zero-crossing interval) and the moment the control system outputs "determined to have entered the zero-crossing interval" based on the PLL output. PWM drive delay refers to the time elapsed from when the control device issues the digital command to "turn off the power frequency switch" (PWM output is 0) until the drive circuit actually establishes a valid turn-off level at the switch control electrode. Switch-on delay (mainly referring to turn-off delay) refers to the time elapsed from when the switch control electrode reaches the turn-off condition until the switch actually exits conduction, the current drops to a negligible level, and the port is in a turn-off state.

[0080] The equivalent resistance, denoted as R, refers to the equivalent on-resistance of the charging process from the bus capacitor C1 to the Y capacitor CY1. The equivalent resistance can include at least one of the following: the on-resistance of the switching transistor, the circuit board trace resistance, and the loop connection resistance. The on-resistance of the switching transistor refers to the resistance across its power path when the switching transistor is in the on-state. The circuit board trace resistance refers to the resistance of the copper traces on the printed circuit board. In the charging circuit, in addition to the switching transistor body and the copper traces on the printed circuit board, there are contact resistances and additional series resistances introduced by the connection links. Specifically, the equivalent resistance includes the circuit board trace resistance between the bus capacitor C1 and the switching transistor Q1, the on-resistance of the switching transistor Q1, the circuit board trace resistance between the switching transistor Q1 and the filter inductor L1, the circuit board trace resistance between the filter inductor L1 and the Y capacitor CY1, and the circuit board trace resistance between the Y capacitor CY1 and the bus capacitor C1.

[0081] By turning off the first power frequency switch Q3 and the second power frequency switch Q4 during the zero-crossing interval, the grid side is open-circuited (Igrid≈0). At this time, the Y capacitor CY1 is powered only by the bus capacitor C1, and the equivalent circuit is as follows: Figure 10 The RC charging circuit shown is illustrated. The capacitance value of capacitor Y, CY1, is denoted as C. cy1 The charging current equation is: i_cy1(t)=(Vbus / R)×e^( t / (RC cy1 )); t is the charging time, based on the step response of a first-order RC circuit: u(t) = u(∞) + [u(0)] u(∞)]×e^( t / (RC)); Where u(0) represents the starting voltage of charging Y capacitor CY1, and u(∞) represents the ending voltage of charging Y capacitor CY1.

[0082] In one example, the precharge target can be set to make the voltage of the Y capacitor approach the voltage at the midpoint of the bus from the current starting voltage, i.e., u(∞) = V_bus / 2.

[0083] The time constant of a first-order RC circuit is τ = RC cy1 The relationship between charging time t and the degree of approximation to the final value is given by the exponential term e^( The value of t / τ determines that the larger t is, the closer u(t) is to u(∞), and the residual deviation decreases exponentially. However, when the charging time is taken as three times the time constant, t is set to 3RC. cy1 Substituting into the above step response expression, we get: u(3τ)=Vbus / 2+[u(0) Vbus / 2] ×e^( 3); Since the natural logarithm e ≈ 2.718, we can calculate e^( 3)≈0.0498≈5%.

[0084] Therefore, we can conclude that: u(3RC)≈Vbus / 2+5%×[u(0) Vbus / 2]; In other words, when the charging time reaches three times the time constant, the deviation between the voltage of Y capacitor CY1 and the target value V_bus / 2 has converged to about 5% of the initial deviation. This approximation is usually sufficient for suppressing the reverse voltage jump and displacement current after zero-crossing recovery. If the factor is increased further, the pre-charging benefit is limited, but it will prolong the time when the dual power frequency switches are simultaneously turned off, occupying more effective conduction angles, which is detrimental to the power factor and current harmonics. If it is significantly less than three times the time constant, the residual voltage deviation is large, and Vcy1 may still show a significant reverse jump after power frequency recovery, resulting in a worse zero-crossing current spike suppression effect. Therefore, in this embodiment, 3RC cy1 The preferred value for the charging time required for the Y capacitor CY1 to complete effective pre-charging is used to achieve a balance between the pre-charging effect and the zero-crossing shutdown maintenance time.

[0085] Considering the delays in detection and driving within the actual control link, the shutdown action described in this paper needs to be completed before the Y capacitor CY1 begins to receive effective pre-charge. Therefore, the zero-crossing shutdown duration Toff needs to cover the control delay T_delay, meaning the shutdown window value must satisfy the following: Toff≥T_delay+3RC cy1 ; In one example, to minimize the blocking window while ensuring the pre-charge effect, the following can be considered: Toff = T_delay + 3RC cy1 ; It should be noted that setting t to 3RC cy1 This is not the only limitation; in other embodiments, the coefficients can be adjusted to meet acceptable precharge error requirements, i.e., the minimum value of T_off can be taken as T_delay + kRC. cy1 (k is a positive real number). In addition, the above quantitative relationship can be adaptively adjusted when the equivalent charging circuit model, pre-charge target voltage, or circuit parameters are different.

[0086] In this embodiment, by equating the pre-charging process of the Y capacitor within the zero-crossing interval to an RC charging process, a quantitative relationship is established between the zero-crossing turn-off sustaining time and the control delay, equivalent resistance, and the capacitance value of the Y capacitor CY1. This allows for direct estimation of the theoretical lower limit of Toff during the scheme design phase. This approach links the waveform blocking window setting to circuit parameters, which is beneficial for pre-charging the Y capacitor voltage to near the target level before resuming power frequency transmission. This reduces the reverse jump amplitude and displacement current of the Y capacitor voltage after resuming transmission, and reduces the workload of repeatedly testing and adjusting parameters.

[0087] In some embodiments, obtaining the zero-crossing shutdown duration includes, but is not limited to, the following steps S213 to S216.

[0088] Step S213: Set the initial zero-crossing shutdown duration and use the initial zero-crossing shutdown duration as the current zero-crossing shutdown duration.

[0089] The zero-crossing turn-off duration refers to the time window during which the first and second power frequency switching transistors are kept off when the AC grid voltage crosses zero.

[0090] The initial zero-crossing shutdown duration refers to the initial value of the zero-crossing shutdown duration adopted at the start of iterative tuning. The current zero-crossing shutdown duration refers to the actual zero-crossing shutdown duration value issued and maintained in this round of testing.

[0091] In practice, the initial zero-crossing turn-off duration can be set based on the theoretical estimate given by the aforementioned RC pre-charge model. Alternatively, it can be set as a certain proportion of the power frequency cycle. For example, 0.01 times the power frequency cycle can be used as the starting point. After this initial value is written into the control parameters, it will be used as the current zero-crossing turn-off duration for subsequent operation and observation.

[0092] Step S214: Under preset load conditions, based on the current zero-crossing turn-off duration, run the power factor correction circuit and detect the grid current waveform.

[0093] The preset load conditions refer to typical load conditions used to set the zero-crossing turn-off duration. The grid current waveform refers to the waveform of the AC input current changing over time, and the section near the zero-crossing moment should be observed closely.

[0094] A current spike refers to a transient current surge that occurs near the zero-crossing point and is significantly higher than the normal sinusoidal trend. In practical implementation, preset load conditions can include full-load and light-load conditions. Several typical operating points can also be covered according to product specifications. Full-load conditions refer to the operating condition where the output load power of the power factor correction circuit is close to or reaches the rated output power; light-load conditions refer to the operating condition where the output load power is significantly lower than the rated output power, such as 10% or 20% of the rated power. Under each load condition, the power frequency switch is kept off in the zero-crossing interval according to the current zero-crossing turn-off duration. After stable operation, the grid current is collected to determine whether a current spike exists at the zero-crossing point. Observing under full-load and light-load conditions separately helps to consider the spike suppression effect under different operating conditions.

[0095] Step S215: If there is a current spike in the grid current waveform at the zero crossing moment, increase the current zero crossing turn-off duration according to the first adjustment rule, and re-run the power factor correction circuit and detect the grid current waveform until there is no current spike in the grid current waveform at the zero crossing moment.

[0096] The first adjustment rule refers to the method of increasing the zero-crossing turn-off duration when a zero-crossing current spike still exists. In practice, the first adjustment rule can be to increase Toff by a fixed step size or by a proportional increase. During adjustment, the turn-off window before and after the zero-crossing can be symmetrically widened to ensure consistent processing near the zero-crossing in both the positive and negative half-cycles. After each adjustment, the circuit is re-run with the new current zero-crossing turn-off duration, and the grid current is monitored. If the spike still exists, the duration is increased further until the current spike essentially disappears at the zero-crossing moment. Figure 15 As shown. The purpose of this step is to first find the available interval of zero-crossing shutdown duration that can suppress spikes.

[0097] Step S216: If there is no current spike in the grid current waveform at the zero crossing moment, the current zero crossing turn-off duration is reduced according to the second adjustment rule, and the power factor correction circuit and grid current waveform are run until a current spike appears in the grid current waveform at the zero crossing moment. The current zero crossing turn-off duration corresponding to the previous detection before the current spike appears is determined as the zero crossing turn-off duration.

[0098] The second adjustment rule refers to the method used to reduce the zero-crossing turn-off duration when the zero-crossing current spike has been suppressed. In practice, the second adjustment rule can be to reduce the zero-crossing turn-off duration by a fixed step size or by a proportional reduction. The window before and after the zero-crossing can also be symmetrically narrowed during adjustment. After each reduction, the process is restarted and the zero-crossing current is observed. If the spike still does not appear, the reduction can continue; once a zero-crossing current spike reappears, the zero-crossing turn-off duration is reverted to the value used before the spike appeared, and this value is used as the adjusted zero-crossing turn-off duration.

[0099] In practical applications, after a current spike occurs, the zero-crossing turn-off duration can be shortened further with smaller steps based on the current zero-crossing turn-off duration corresponding to the previous detection before the current spike occurred. The power factor correction circuit is run again and the grid current waveform is detected. If no current spike still occurs, the duration is shortened further with smaller steps. Once a current spike occurs again, the zero-crossing turn-off duration corresponding to the previous detection before the current spike occurs is determined as the zero-crossing turn-off duration. That is, after approaching the critical point, the duration is shortened finely with smaller steps to determine the zero-crossing turn-off duration.

[0100] This embodiment employs a tuning approach of "increasing first, then decreasing, using measured spikes as the criterion." However, factors such as control delay, parasitic parameters of printed circuit boards, and device variability make it difficult to accurately incorporate these factors into the analytical formula. Using the disappearance of grid current spikes as the criterion allows for direct absorption of these factors in the actual system. Furthermore... Figure 7 The circuit formed by the bus capacitor after the power frequency tube is turned off is shown. When the zero-crossing turn-off duration is too short, the Y capacitor is not pre-charged enough, and a current spike is easily generated after the waveform is restored. This embodiment does not rely on precise resistor and capacitor values, but approximates a more suitable window width through waveform feedback. In this embodiment, the zero-crossing turn-off duration is first increased to eliminate the spike, and then decreased to find a shorter usable value. This helps to shorten the turn-off window as much as possible while suppressing the spike, and reduces the impact on normal PFC modulation and current continuity. Moreover, the criterion is intuitive and suitable for quickly obtaining a usable zero-crossing turn-off duration during prototype debugging or production line calibration, reducing the blindness of simply relying on repeated trial and error. In some embodiments, if the zero-crossing turn-off duration has been obtained in step S212, it can be used as an initial value to perform the steps in this embodiment for verification and fine-tuning; if the theoretical parameters are incomplete, the tuning can also be completed directly from the empirical initial value.

[0101] In some embodiments, to reduce the impact of the high-frequency transistor reversal on the inductor, the control method may further include step S400: in response to the grid voltage meeting the preset zero-crossing interval condition, during the zero-crossing turn-off maintenance time, the first high-frequency switch and the second high-frequency switch are controlled to perform a duty cycle soft switching action.

[0102] The grid voltage refers to the input voltage on the AC grid side. The zero-crossing interval refers to a time window near the zero-crossing point of the grid voltage, used to execute zero-crossing turn-off control of the power frequency switching transistor. The preset zero-crossing interval entry condition refers to the judgment condition used to determine whether the current window has been entered, thereby initiating duty cycle soft switching. In specific implementation, this condition can be set based on the comparison result of the grid voltage amplitude and the preset threshold, or it can be set based on the voltage zero-crossing detection signal, phase-locked loop phase information, or equivalent electrical angle range.

[0103] Zero-crossing turn-off duration refers to the time during which the power frequency switch remains off near a zero-crossing point. During this time, the power frequency bridge arm can pause its normal half-cycle conduction to complete the zero-crossing related processing. The first and second high-frequency switches refer to the bridge arm switches operating at higher switching frequencies in the power factor correction circuit, used to cooperate with the power frequency switch to complete AC side current modulation and energy conversion.

[0104] Soft duty cycle switching refers to gradually decreasing or increasing the duty cycle of the main control switch of the high-frequency bridge arm before and after zero-crossing commutation, rather than switching to the target duty cycle instantaneously, in order to reduce sudden changes in inductor current.

[0105] In practice, after entering the zero-crossing interval and maintaining the zero-crossing turn-off time, the duty cycle of the current master high-frequency switch is gradually reduced according to a preset rule. This reduction can be done by decreasing the duty cycle in fixed steps, periodically, or according to a preset curve or a preset ratio. After the duty cycle reaches a low level, the high-frequency bridge arm master control relationship is switched according to changes in grid voltage polarity. Subsequently, the duty cycle of the new master high-frequency switch is gradually increased according to a preset rule, transitioning to the target duty cycle required for normal modulation. This increase can be done by increasing the duty cycle in fixed steps, periodically, or according to a preset curve or a preset ratio.

[0106] Through the aforementioned process of gradually decreasing and gradually increasing the duty cycle, the change in duty cycle during the zero-crossing commutation phase becomes smoother. This helps reduce voltage and current surges on the filter inductor, improves the current waveform near the zero crossing, and facilitates coordinated execution with the zero-crossing turn-off control of the power frequency switch within the same time window. The step size, duration, and start and end times of the duty cycle soft switching can be adjusted according to the inductance, switching frequency, bus voltage, and load conditions to achieve a balance between suppressing surges and maintaining control response.

[0107] In some embodiments, the first high-frequency switch and the second high-frequency switch are controlled to perform a duty cycle soft switching action, including but not limited to the following steps S410 to S420.

[0108] Step S410: Before the grid voltage crosses zero, gradually reduce the duty cycle of the first current main control switch according to the first preset step size, and control the duty cycle of the first current synchronous rectifier according to the preset waveform generation rule until the current of the filter inductor decreases to the preset target current value, and then turn off the first current main control switch. Specifically, before the grid voltage crosses zero, if the grid voltage is in the positive half-cycle, the first current main control switch is the second high-frequency switch Q2, and the first current synchronous rectifier is the first high-frequency switch Q1; if the grid voltage is in the negative half-cycle, the first current main control switch is the first high-frequency switch Q1, and the first current synchronous rectifier is the second high-frequency switch Q2.

[0109] Before the grid voltage crosses zero, it refers to the period of time after the grid voltage meets the preset conditions for entering the zero-crossing interval, when the grid voltage is about to change polarity but has not yet crossed the zero point. This stage can overlap with the first part of the zero-crossing shutdown maintenance time.

[0110] The first current master control switch refers to the high-frequency switch that primarily undertakes modulation tasks during the first half-cycle of the zero-crossing interval after the grid voltage meets the preset zero-crossing condition. The first current synchronous rectifier refers to another high-frequency switch that works in conjunction with the first current master control switch to achieve synchronous rectification. Their roles interchange as the grid voltage polarity changes.

[0111] The first preset step size refers to the adjustment amount used when the duty cycle of the main control switch is reduced cycle by cycle before the grid voltage reaches the zero-crossing interval after the grid voltage meets the preset zero-crossing condition. This step size can be a fixed value or set according to a certain proportion of the current duty cycle. For example, the current duty cycle can be set to half of the previous duty cycle, or it can be set according to other decreasing rules.

[0112] The preset waveform generation rule refers to the method by which the duty cycle of the synchronous rectifier is generated. One possible method is to make the duty cycle of the synchronous rectifier complementary to that of the main control switch, while retaining the dead time. For example, the duty cycle of the synchronous rectifier can be calculated using the following formula: D_syn=(1 D_main D_dead)×Ts; Where D_main is the duty cycle of the first current master switch, D_syn is the duty cycle of the first current synchronous rectifier, D_dead is the duty cycle corresponding to the dead time, and Ts is the switching cycle.

[0113] The current in the filter inductor refers to the instantaneous current flowing through it. The preset target current value refers to the minimum current level to which the inductor current is expected to fall before crossing zero; this target value is usually set to zero.

[0114] Specifically, based on the sampled inductor current, it can be determined whether to further reduce the main control duty cycle. The ideal duty cycle value D_ref can be calculated using the following formula: D_ref=(Vbus |V_grid|) / Vbus; Where Vbus is the bus voltage and |V_grid| is the absolute value of the grid voltage. The initial duty cycle for the soft switching before zero crossing can be D_init = D_ref / 2, or it can be any other initial value smaller than the current normal modulation duty cycle. Subsequently, the duty cycle of the first current master control switch can be reduced cycle by cycle according to the first preset step size, so that the inductor current gradually decreases. When the current decreases to the preset target current value, the first current master control switch is turned off. The synchronous rectifier can continue to operate according to the preset waveform rules to maintain the consistency of the bridge arm drive relationship.

[0115] Taking the transition of the grid voltage from the positive half-cycle to the negative half-cycle as an example, the stage before zero crossing can be further explained as follows. When the actual phase angle corresponding to the grid voltage satisfies: θ_zero+θ_th<θ≤θ_zero, The duty cycle of the main control switch Q2 can be gradually reduced. Here, θ is the actual phase angle, θ_zero is the zero-point voltage phase angle, and θ_th is the preset zero-crossing phase angle margin. The initial duty cycle can be D_init = D_ref / 2. Subsequent duty cycles can be updated according to D_now = D_last / 2, or according to other decreasing methods. D_last is the main control duty cycle of the previous control cycle, and D_now is the main control duty cycle of the current control cycle. When the inductor current decreases to the preset target current value, the main control switch Q2 is turned off, and the synchronous rectifier Q1 is then updated according to D_syn = (1 D_main The relationship between D_dead)Ts maintains wave generation.

[0116] Step S420: After the grid voltage crosses zero, the duty cycle of the second current master control switch is gradually increased according to the second preset step size, and the duty cycle of the second current synchronous rectifier is controlled according to the preset waveform generation rule until the duty cycle of the second current master control switch reaches the target duty cycle. Specifically, after the grid voltage crosses zero, if the grid voltage is in the positive half-cycle, the second current master control switch is the second high-frequency switch Q2, and the second current synchronous rectifier is the first high-frequency switch Q1; if the grid voltage is in the negative half-cycle, the second current master control switch is the first high-frequency switch Q1, and the second current synchronous rectifier is the second high-frequency switch Q2.

[0117] After the grid voltage crosses zero, it refers to the period of time after the grid voltage has crossed the zero point and entered a new half-cycle. This period overlaps with the latter part of the zero-crossing shutdown maintenance time.

[0118] The second current master control switch refers to the high-frequency switch that primarily undertakes modulation tasks during the new half-cycle after the grid voltage crosses zero, once the preset zero-crossing condition is met. The second current synchronous rectifier refers to another high-frequency switch that works in conjunction with the second current master control switch to achieve synchronous rectification. Compared to before the zero-crossing, the roles of the master control switch and the synchronous rectifier are reversed.

[0119] The second preset step size refers to the adjustment amount used when the duty cycle of the new main control switch is increased cycle by cycle after the grid voltage crosses zero following the preset zero-crossing condition. This step size can be denoted as ΔD. ΔD can be a fixed value or adjusted according to the operating conditions.

[0120] The target duty cycle refers to the desired duty cycle level of the second currently controlled switch under normal modulation of the new half-cycle. One option is to set the target duty cycle to be close to the value of D_ref, for example, D_ref... ΔD can also be directly taken as D_ref. The specific value can be determined by considering the control accuracy and the current establishment speed after zero crossing.

[0121] In practice, after commutation, a small initial duty cycle can be given to the second current master control switch, and then gradually increased according to the second preset step size. One optional update method is: D_main = D_Last + ΔD; Where D_Last is the master control duty cycle of the previous control cycle, and D_main is the master control duty cycle of the current control cycle. When D_main increases to the target duty cycle, the soft handover can end and normal modulation can begin. The synchronous rectifier can still generate the duty cycle according to the preset waveform generation rules, for example, by continuing to use the complementary plus dead-time method.

[0122] Taking the transition of the grid voltage from the positive half-cycle to the negative half-cycle as an example, the post-zero crossing stage can be further explained as follows: when the phase satisfies: θ_zero<θ≤θ_zero+θ_th+(Toff / T_grid)×360°, After commutation, the main control switch becomes Q1. Here, Toff is the zero-crossing turn-off duration, and T_grid is the grid cycle. The duty cycle of the main control switch Q1 can be increased using a soft-start method, for example, by gradually updating it according to D_main = D_Last + ΔD, and gradually approaching D_ref. ΔD or D_ref. The synchronous rectifier tube Q2 can be matched with the output according to the preset waveform rules.

[0123] In this embodiment, before zero crossing, the duty cycle of the first current master switch is gradually reduced, allowing the filter inductor current to smoothly return to the preset target current value. After zero crossing, the duty cycle of the second current master switch is gradually increased, allowing the filter inductor current to smoothly re-establish itself. This process can be coordinated with the turn-off arrangement of the power frequency switch during the zero-crossing turn-off maintenance time, so that the role switching on the high-frequency side occurs during the stage when the inductor current is low. This helps to reduce the current impact on the inductor when the high-frequency switch role switches switch, and improves the current waveform quality near zero crossing.

[0124] In some embodiments, the method for determining the second preset step size includes, but is not limited to, steps S411 to S412. Step S411: Obtain the inductance of the filter inductor, the switching period, the current bus voltage, and the target current; Step S412: Determine the second preset step size based on the inductance of the filter inductor, the switching period, the current bus voltage, and the target current.

[0125] The principle for determining the second preset step size is further explained below. The rate of change of the voltage v(t) and the current i(t) of the filter inductor satisfy the following differential relationship: v(t) = L × di(t) / dt; Where L is the inductance of the filter inductor.

[0126] Within one switching cycle, the time increment corresponding to the duty cycle increment can be expressed as: dt=ΔD×T_s, Where ΔD is the second preset step size, and T_s is the switching period. Specifically, the switching period is the switching period of the high-frequency switching transistor. Combining the above relationship, the second preset step size can be constrained as follows: ΔD≤(L×I_target) / (Vbus×T_s) Wherein, the target current I_target = I_ref × sin(θ) is used to characterize the instantaneous grid-side current command under the current phase. I_ref is the set reference current used to characterize the command amplitude of the grid-side current. For example, when a PFC grid-side (AC input) current of 1A is required, I_ref = 1A. θ is the phase angle of the power grid.

[0127] That is, the second preset step size range can be calculated using the inductance of the filter inductor, the switching cycle, the current bus voltage and the target current, and the second preset step size can be determined from the second preset step size range.

[0128] In this embodiment, the soft start time is related to the inductance, bus voltage, switching cycle, and target current, so that the duty cycle rise rate matches the inductor current change capability, which helps to obtain a more stable soft start effect under different operating conditions.

[0129] As another aspect of the embodiments of this application, the embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions for causing an electronic device to perform the methods provided in the embodiments of this application.

[0130] In some embodiments, the storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0131] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0132] As an example, executable instructions may, but do not necessarily, correspond to files in the file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0133] As an example, executable instructions can be deployed to execute on a single computing device (including devices such as smart terminals and servers), or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0134] As another aspect of the embodiments of this application, the embodiments of this application also provide a computer program product, the computer program product including a computer program stored on a computer-readable storage medium, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the method as described in the foregoing embodiments.

[0135] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0136] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general-purpose hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for at least one computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A control method for a power factor correction circuit, characterized in that, The power factor correction circuit includes a low-frequency bridge arm branch, which includes a first power frequency switch and a second power frequency switch connected in series. The connection point between the first power frequency switch and the second power frequency switch is used to connect to a first terminal of the power grid. The control method includes: Obtain the zero-crossing turn-off duration and grid voltage; In response to the grid voltage meeting the preset zero-crossing interval condition, the first power frequency switch and the second power frequency switch are turned off. In response to the turn-off duration of the first power frequency switch and the second power frequency switch reaching the zero-crossing turn-off maintenance time, the first power frequency switch and the second power frequency switch are controlled to operate in a power frequency complementary conduction mode.

2. The control method according to claim 1, characterized in that, The control method further includes: Based on the grid voltage, determine the actual grid phase angle at the current moment; Obtain the zero-point voltage phase angle, preset zero-crossing phase angle margin, and grid cycle; Based on the zero-point voltage phase angle and the preset zero-crossing phase angle margin, the range of zero-crossing turn-off phase angle is determined; If the actual grid phase angle is within the range of the zero-crossing turn-off phase angle, then the grid voltage is determined to meet the preset condition for entering the zero-crossing interval. Based on the zero-point voltage phase angle, the preset zero-crossing phase angle margin, the power grid cycle, and the zero-crossing turn-off duration, the range of the zero-crossing end phase angle is determined. If the actual power grid phase angle is within the zero-crossing end phase angle range, then the turn-off duration of the first power frequency switch and the second power frequency switch is determined to reach the zero-crossing turn-off maintenance time.

3. The control method according to claim 2, characterized in that, The power factor correction circuit further includes a bus capacitor, a Y capacitor CY1, a filter inductor, and a high-frequency bridge arm branch. The high-frequency bridge arm branch includes a first high-frequency switch and a second high-frequency switch connected in series. The high-frequency bridge arm branch, the low-frequency bridge arm branch, and the bus capacitor are connected in parallel to the DC bus. The connection point of the first high-frequency switch and the second high-frequency switch is connected to the first terminal of the filter inductor. The second terminal of the filter inductor is connected to one terminal of the Y capacitor CY1 and the second terminal of the power grid. The other terminal of the Y capacitor CY1 is connected to the bus capacitor. An equivalent charging circuit is formed between the bus capacitor and the Y capacitor CY1. Obtaining the zero-crossing turn-off sustaining time includes: Obtain the control delay, the equivalent resistance of the equivalent charging circuit, and the capacitance value of the Y capacitor CY1; Based on the control delay, the equivalent resistance, and the capacitance value, the zero-crossing turn-off duration is determined, wherein the zero-crossing turn-off duration satisfies the following relationship: Toff≥T_delay+3RC cy1 ; Toff is the zero-crossing turn-off duration, T_delay is the control delay, R is the equivalent resistance, and C... cy1 Let CY1 be the capacitance value of the Y capacitor.

4. The control method according to claim 2, characterized in that, The acquisition of the zero-crossing shutdown duration includes: Set an initial zero-crossing shutdown duration and use the initial zero-crossing shutdown duration as the current zero-crossing shutdown duration; Under preset load conditions, based on the current zero-crossing shutdown duration, the power factor correction circuit is run and the grid current waveform is detected; If the grid current waveform has a current spike at the zero crossing moment, the current zero crossing shutdown duration is increased according to the first adjustment rule, and the power factor correction circuit and the grid current waveform are re-run until the grid current waveform does not have a current spike at the zero crossing moment. If the grid current waveform does not have a current spike at the zero-crossing moment, the current zero-crossing shutdown duration is reduced according to the second adjustment rule, and the power factor correction circuit is run and the grid current waveform is detected until a current spike appears at the zero-crossing moment. The current zero-crossing shutdown duration corresponding to the previous detection before the current spike appears is determined as the zero-crossing shutdown duration.

5. The control method according to any one of claims 1-4, characterized in that, The power factor correction circuit further includes a high-frequency bridge arm branch, which includes a first high-frequency switch and a second high-frequency switch connected in series. The control method further includes: In response to the grid voltage meeting the preset zero-crossing interval condition, during the zero-crossing shutdown maintenance time, the first high-frequency switch and the second high-frequency switch are controlled to perform a duty cycle soft switching action.

6. The control method according to claim 5, characterized in that, The power factor correction circuit further includes a filter inductor, and the step of controlling the first high-frequency switch and the second high-frequency switch to perform a duty cycle soft switching action includes: Before the grid voltage crosses zero, the duty cycle of the first current main control switch is gradually reduced according to a first preset step size, and the duty cycle of the first current synchronous rectifier is controlled according to a preset waveform rule until the current of the filter inductor is reduced to a preset target current value, at which point the first current main control switch is turned off. Specifically, before the grid voltage crosses zero, if the grid voltage is in the positive half-cycle, the first current main control switch is the second high-frequency switch, and the first current synchronous rectifier is the first high-frequency switch; if the grid voltage is in the negative half-cycle, the first current main control switch is the first high-frequency switch, and the first current synchronous rectifier is the second high-frequency switch. After the grid voltage crosses zero, the duty cycle of the second current master control switch is gradually increased according to a second preset step size, and the duty cycle of the second current synchronous rectifier is controlled according to a preset waveform generation rule until the duty cycle of the second current master control switch reaches the target duty cycle. Wherein, after the grid voltage crosses zero, if the grid voltage is in the positive half-cycle, the second current master control switch is the second high-frequency switch and the second current synchronous rectifier is the first high-frequency switch; if the grid voltage is in the negative half-cycle, the second current master control switch is the first high-frequency switch and the second current synchronous rectifier is the second high-frequency switch.

7. The control method according to claim 6, characterized in that, The method for determining the second preset step size includes: Obtain the inductance, switching period, current bus voltage, and target current of the filter inductor; Based on the inductance of the filter inductor, the switching period, the current bus voltage, and the target current, the second preset step size is determined, and the second preset step size satisfies the following relationship: ΔD≤(L×I_target) / (Vbus×T_s) Where I_target is the target current, L is the inductance of the filter inductor, Vbus is the current bus voltage, and T_s is the switching cycle.

8. A control device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer program instructions executable by the processor, which, when executed by the processor, cause the control device to perform the control method as described in any one of claims 1 to 7.

9. A power factor correction circuit, characterized in that, include: Low-frequency bridge arm branch, high-frequency bridge arm branch, bus capacitor, filter inductor, and control device as described in claim 8; The low-frequency bridge arm branch includes a first power frequency switch and a second power frequency switch connected in series. The connection point between the first power frequency switch and the second power frequency switch is used to connect to the first end of the power grid. The high-frequency bridge arm branch includes a first high-frequency switch and a second high-frequency switch connected in series. The high-frequency bridge arm branch, the low-frequency bridge arm branch, and the bus capacitor are connected in parallel to the DC bus. The connection point between the first high-frequency switch and the second high-frequency switch is used to connect to the second end of the power grid via the filter inductor. The control device is connected to the control terminal of the low-frequency bridge arm branch and the control terminal of the high-frequency bridge arm branch.

10. A computer storage medium, characterized in that, The computer storage medium stores instructions or programs that, when executed by at least one processor, cause the at least one processor to perform the steps of the control method as described in any one of claims 1 to 7.

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