High-side nmos floating ground generation circuit

Abstract

The application relates to the technical field of integrated circuits, and discloses a high-side NMOS floating ground generating circuit, which comprises a floating ground node, a voltage sampling module, a pull-down control module and a floating ground generating module; the input end of the voltage sampling module is coupled to a power supply, the voltage sampling module is used for detecting the voltage amplitude of the power supply and generating a corresponding sampling signal; the pull-down control module is connected between the floating ground node and a reference ground, the control end of the pull-down control module is coupled to the output end of the voltage sampling module, and the pull-down control module selectively pulls down the floating ground node to the reference ground in response to the sampling signal; the floating ground generating module is used for generating a floating ground voltage with a fixed amplitude relative to the power supply; when the voltage amplitude of the power supply is lower than a preset threshold, the voltage sampling module controls the pull-down control module to be turned on, so as to increase the voltage difference between the floating ground node and the power supply; when the voltage amplitude of the power supply is higher than the preset threshold, the voltage sampling module controls the pull-down control module to be turned off, so as to stop the pull-down of the floating ground node. Dynamic self-adaptive adjustment of the floating ground voltage amplitude with the change of the power supply voltage is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-side NMOS floating ground generation circuit. Background Technology

[0002] In high-voltage half-bridge or bridge circuit designs, N-type LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) and GaN power transistors are often used as high-side power switches due to their excellent on-resistance and breakdown voltage characteristics. However, the source potential of the high-side switch is not fixed at ground level, but floats between the supply voltage and ground voltage depending on the switching action. This presents a driving challenge—for an N-type LDMOS to be fully turned on, its gate-source voltage (VGS) must be higher than the threshold voltage, meaning the gate potential must be significantly higher than the floating source potential by a sufficient driving voltage amplitude. This implies that when the high-side transistor needs to be turned on, its gate potential must be one VGS higher than its floating source potential, and this source potential may be close to or even equal to the supply voltage. While traditional bootstrap circuits can solve this driving problem, when the supply voltage VBB varies over a wide range (e.g., 5V~30V), existing floating ground generation circuits often use fixed bias or open-loop structures, resulting in insufficient floating ground amplitude at low voltages and excessive stress on devices at high voltages. This makes it impossible to adaptively compensate, and in severe cases, it can lead to increased on-resistance of high-side power transistors, or even cause thermal runaway of the system.

[0003] Chinese invention patent CN115622548B proposes a high-side NMOS floating ground drive circuit, which generates a floating ground voltage by forming a fixed bias structure with multiple PMOS transistors and a current source. However, this scheme relies on open-loop current mirror matching, and its floating ground voltage is fixed by the circuit structure, making it unable to respond to real-time changes in the supply voltage. When the supply voltage decreases, the generated floating ground voltage difference decreases accordingly, which can easily lead to insufficient drive of the subsequent bootstrap switching transistors, resulting in significant voltage drop and conduction losses, thus limiting its application in wide-voltage input scenarios.

[0004] In summary, there is an urgent need for an improved high-side NMOS floating ground generation circuit, which aims to solve the problem of insufficient driving capability of existing fixed-bias floating ground circuits over a wide supply voltage range. Summary of the Invention

[0005] The technical problem to be solved by this invention is that the existing high-side NMOS floating ground generation circuit adopts a fixed bias open-loop structure, which cannot adaptively generate a sufficient and stable floating ground amplitude across the entire supply voltage range, resulting in insufficient drive of the bootstrap switch and high conduction loss at low voltage.

[0006] To address the aforementioned technical problems, this invention provides a high-side NMOS floating ground generation circuit, comprising: The floating ground node serves as the lowest potential reference node for the charge pump. A voltage sampling module, whose input terminal is coupled to a power supply, is used to detect the voltage amplitude of the power supply and generate a corresponding sampling signal; A pull-down control module, connected between the floating ground node and the reference ground, has its control terminal coupled to the output terminal of the voltage sampling module, and selectively pulls the floating ground node towards the reference ground in response to the sampling signal; and A floating ground generation module, connected between the power supply and the floating ground node, is used to generate a floating ground voltage with a fixed amplitude relative to the power supply; wherein: (a) When the voltage amplitude of the power supply is lower than a preset threshold, the voltage sampling module controls the pull-down control module to turn on, so as to increase the voltage difference between the floating ground node and the power supply; (b) When the voltage amplitude of the power supply is higher than a preset threshold, the voltage sampling module controls the pull-down control module to shut down, so as to stop the pull-down of the floating ground node.

[0007] Furthermore, the voltage sampling module includes: The sampling transistor has its control terminal coupled to the voltage divider node of the power supply, its first conducting terminal coupled to the power supply, and its second conducting terminal coupled to the sampling output node. A load element is connected between the second conducting terminal of the sampling transistor and the reference ground; The feedback unit has its input terminal coupled to the sampling output node and its output terminal coupled to the control terminal of the sampling transistor, which is used to form positive feedback.

[0008] Furthermore, the feedback unit includes: A buffer, the input of which is coupled to the sampling output node; The feedback transistor has its control terminal coupled to the output terminal of the buffer, its first conducting terminal coupled to the control terminal of the sampling transistor, and its second conducting terminal coupled to the reference ground.

[0009] Furthermore, the pull-down control module includes a pull-down transistor, the control terminal of which is coupled to the sampling output node, its first conducting terminal is coupled to the floating ground node, and its second conducting terminal is coupled to the reference ground.

[0010] Furthermore, both the sampling transistor and the feedback transistor are NMOS transistors, and the load element is a resistor.

[0011] Furthermore, the voltage sampling module also includes a high-voltage isolation transistor, which is connected in series between the voltage divider node of the power supply and the control terminal of the sampling transistor, and is used to protect the low-voltage devices in the voltage sampling module when the voltage amplitude of the power supply is high.

[0012] Furthermore, the high-voltage isolation transistor is an NMOS transistor, with its control terminal coupled to an internal low-voltage power supply, its first conducting terminal coupled to the control terminal of the sampling transistor, and its second conducting terminal coupled to the voltage divider node of the power supply.

[0013] Furthermore, the floating ground generation module includes: A first resistor, the first end of which is coupled to the power supply; A floating ground output transistor, the control terminal of which is coupled to the second terminal of the first resistor, the first conducting terminal of which is coupled to the power supply, and the second conducting terminal of which provides the floating ground voltage; A first clamping element is coupled between the control terminal of the floating ground output transistor and the floating ground node, and is used to clamp the voltage between the control terminal of the floating ground output transistor and the floating ground node to a clamping voltage value. A current mirror transistor has its control terminal coupled to the control terminal of the floating ground output transistor, its first conducting terminal coupled to the power supply, and its second conducting terminal coupled to the floating ground node; the current mirror transistor and the floating ground output transistor form a current mirror structure to provide current to the floating ground node.

[0014] Furthermore, the floating ground generation module also includes a second clamping element coupled between the floating ground node and the reference ground to limit the maximum magnitude by which the floating ground node is pulled down.

[0015] Furthermore, both the first clamping element and the second clamping element are Zener diodes; wherein: The cathode of the first clamping element is coupled to the control terminal of the floating ground output transistor, and the anode is coupled to the floating ground node; The cathode of the second clamping element is coupled to the floating ground node, and the anode is coupled to the reference ground.

[0016] Furthermore, the floating ground generation module also includes: A first capacitor element is coupled between the power supply and the control terminal of the floating ground output transistor to stabilize the control terminal voltage of the floating ground output transistor. A second capacitor element is coupled between the power supply and the floating ground node to stabilize the floating ground voltage.

[0017] Furthermore, it also includes an amplitude detection module, the input of which is coupled to the floating ground node, for detecting whether the voltage difference between the floating ground node and the power supply reaches a preset value, and outputting an enable signal for use by subsequent circuits when the preset value is reached.

[0018] Furthermore, the amplitude detection module includes: A voltage divider network, coupled between the power supply and the floating ground node, is used to sample the voltage difference. A comparator transistor, whose control terminal is coupled to the output terminal of the voltage divider network, is used to compare the voltage divider sample with its threshold voltage and output the comparison result; An output stage, coupled to the output terminal of the comparator transistor, is used to output the enable signal based on the comparison result; A hysteresis feedback branch is coupled between the output terminal of the output stage and the output terminal of the voltage divider network to provide hysteresis characteristics for the amplitude detection module.

[0019] Furthermore, it also includes a subsequent charge pump circuit with the floating ground node as the lowest potential reference node, the charge pump circuit comprising: A non-overlapping clock generation circuit is used to generate a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal are phase-complementary. First energy storage capacitor and second energy storage capacitor; The first charging switch and the second charging switch are controlled by the first clock signal and the second clock signal, respectively, to alternately charge and discharge the first energy storage capacitor and the second energy storage capacitor, so as to superimpose the fixed amplitude on the power supply to generate a control signal for driving the high-side bootstrap switch.

[0020] Furthermore, it also includes a current bias module that provides bias current to the floating ground generation circuit, the current bias module including a bandgap reference current source and a current mirror circuit.

[0021] Compared with the prior art, the present invention has at least the following beneficial effects: This invention uses a voltage sampling module to detect the voltage amplitude of the power supply in real time, and adaptively controls the pull-down control module to selectively pull down the floating ground node accordingly. When the supply voltage is too low, the floating ground node is actively pulled to the reference ground to increase the floating ground voltage amplitude ΔV1, ensuring that the subsequent bootstrap switch can obtain sufficient gate drive voltage and conduct fully across the entire voltage range, effectively reducing conduction losses and system temperature rise.

[0022] When the supply voltage is too high, the pull-down control module is automatically shut down to avoid floating ground amplitude overshoot and prevent the device from being subjected to excessive voltage stress.

[0023] In other words, this invention achieves dynamic adaptive adjustment of the floating ground voltage amplitude as the supply voltage changes, and can generate a sufficient and stable floating ground voltage across the entire voltage range, thereby improving the driving capability, reliability and system efficiency of the high-side NMOS drive circuit in wide voltage input scenarios. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the overall circuit of the high-side NMOS floating ground generation circuit disclosed in an embodiment of the present invention.

[0026] Figure 2 As disclosed in the embodiments of the present invention Figure 1 Circuit schematic diagram of medium voltage sampling module, pull-down control module, floating ground generation module and amplitude detection module.

[0027] Figure 3 As disclosed in the embodiments of the present invention Figure 2 Simulation waveforms of key nodes when the supply voltage is relatively high.

[0028] Figure 4 As disclosed in the embodiments of the present invention Figure 2 Simulation waveforms of key nodes when the supply voltage is relatively low.

[0029] Figure 5 When the drop-down control module is not set in the embodiments of the present invention Figure 2 Simulation waveforms of key nodes when the supply voltage is relatively low.

[0030] In the diagram: 100, voltage sampling module; 200, pull-down control module; 300, floating ground generation module; 400, post-stage charge pump circuit; 500, amplitude detection module. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] In this embodiment, the high-side NMOS floating ground generation circuit provided by the present invention includes a floating ground node HS_GND, a voltage sampling module 100, a pull-down control module 200, a floating ground generation module 300, and a subsequent charge pump circuit 400.

[0033] Specifically: The floating ground node HS_GND serves as the lowest potential reference node for the charge pump.

[0034] The input terminal of the voltage sampling module 100 is coupled to the power supply VBB to detect the voltage amplitude of the power supply VBB and generate a corresponding sampling signal. The voltage sampling module 100 detects the voltage amplitude of the power supply VBB in real time. When the voltage amplitude of the power supply VBB is lower than a preset threshold, the voltage sampling module 100 controls the pull-down control module 200 to turn on, pulling the floating ground node HS_GND down to the reference ground GND, thereby increasing the voltage difference between the floating ground node HS_GND and the power supply VBB, that is, increasing the fixed amplitude ΔV1 relative to the power supply VBB. When the voltage amplitude of the power supply VBB is higher than the preset threshold, the voltage sampling module 100 controls the pull-down control module 200 to turn off, stopping the pull-down of the floating ground node HS_GND, to avoid excessive voltage stress on the device due to excessive floating ground amplitude.

[0035] The pull-down control module 200 is connected between the floating ground node HS_GND and the reference ground GND. Its control terminal is coupled to the output terminal of the voltage sampling module 100, and in response to the sampling signal, it selectively pulls the floating ground node HS_GND down to the reference ground GND.

[0036] The floating ground generation module 300 is connected between the power supply VBB and the floating ground node HS_GND to generate a floating ground voltage with a fixed amplitude relative to the power supply VBB.

[0037] The subsequent charge pump circuit 400 uses the floating ground node HS_GND as the lowest potential reference node. Please refer to [link / reference]. Figure 1 The subsequent charge pump circuit 400 includes a non-overlapping clock generation circuit, a first energy storage capacitor C1, a second energy storage capacitor C2, a first charging switch NM10, a second charging switch NM11, a bootstrap switch NM12, a first charge pump capacitor CP1, a second charge pump capacitor CP2, a third switch PM13, a fourth switch PM14, a fifth switch NM13, a sixth switch NM14, and multiple inverters inv2 to inv8, NOR gates nor1 and nor2.

[0038] The non-overlapping clock generation circuit consists of NOR gates nor1 and nor2, and inverters inv2, inv3, inv4, inv5, and inv6. This circuit generates a first clock signal and a second clock signal, which are complementary in phase, alternately charging and discharging the first energy storage capacitor C1 and the second energy storage capacitor C2. Specifically, NOR gates nor1 and nor2 are cross-coupled, and inverters inv2 to inv6 shape and delay the clock signals to ensure sufficient dead time between the first and second clock signals, preventing the first charging switch NM10 and the second charging switch NM11 from conducting simultaneously.

[0039] The gate of the first charging switch NM10 receives a first clock signal, its first conducting terminal is coupled to the power supply VBB, and its second conducting terminal is coupled to the first terminal of the first energy storage capacitor C1. The second terminal of the first energy storage capacitor C1 is coupled to the floating ground node HS_GND. The gate of the second charging switch NM11 receives a second clock signal, its first conducting terminal is coupled to the power supply VBB, and its second conducting terminal is coupled to the first terminal of the second energy storage capacitor C2. The second terminal of the second energy storage capacitor C2 is coupled to the floating ground node HS_GND.

[0040] The first charging switch NM10 and the second charging switch NM11 are controlled by the first clock signal and the second clock signal, respectively, and alternately charge and discharge the first energy storage capacitor C1 and the second energy storage capacitor C2. Specifically, when the first clock signal is high, the first charging switch NM10 is turned on, and the power supply VBB charges the first energy storage capacitor C1, causing the voltage of the gate NM12_G of the bootstrap switch NM12 to rise to VBB + ΔV1, where ΔV1 is a fixed amplitude relative to the power supply VBB. When the second clock signal is high, the second charging switch NM11 is turned on, and the power supply VBB charges the second energy storage capacitor C2. Through the alternating charging and discharging of the first energy storage capacitor C1 and the second energy storage capacitor C2, the gate NM12_G of the bootstrap switch NM12 maintains a sufficient driving voltage, allowing the bootstrap switch NM12 to be fully turned on.

[0041] The first conducting terminal of the bootstrap switch NM12 is coupled to the power supply VBB, and its second conducting terminal is coupled to the first terminal of the first charge pump capacitor CP1. When the bootstrap switch NM12 is turned on, the power supply VBB charges the first charge pump capacitor CP1 through the bootstrap switch NM12.

[0042] The second terminal of the first charge pump capacitor CP1 is coupled to the first terminal of the second charge pump capacitor CP2. The second terminal of the second charge pump capacitor CP2 is coupled to the first conducting terminal of the third switch PM13 and the second conducting terminal of the fourth switch PM14. The control terminal of the third switch PM13 is coupled to the gate NM12_G of the bootstrap switch NM12, and its second conducting terminal outputs the drive voltage VCP.

[0043] The control terminal PM14_G of the fourth switch PM14 is coupled to the output of a three-stage inverter consisting of inverters inv7 and inv8, the sixth switch NM14, and the seventh switch PM15. The input of this three-stage inverter receives the clock signal CLK. When the control terminal PM14_G of the fourth switch PM14 is low, the fourth switch PM14 is turned on, pulling the first terminal of the second charge pump capacitor CP2 high to the voltage of the power supply VBB. Due to the principle that the voltage across a capacitor cannot change abruptly, the voltage of the first charge pump capacitor CP1 becomes VBB + ΔV2, where ΔV2 is the charging amplitude of the second charge pump capacitor CP2. At this time, when the gate NM12_G of the bootstrap switch NM12 is low, the third switch PM13 is turned on, transmitting the voltage VBB + ΔV2 to the drive voltage VCP to drive the high-side power transistor.

[0044] The control terminal of the fifth switch NM13 is coupled to the control circuit. Its first conducting terminal is coupled to the second terminal of the first charge pump capacitor CP1, and its second conducting terminal is coupled to the floating ground node HS_GND through the seventh resistor R7. The fifth switch NM13, the seventh resistor R7, and the control circuit work together to determine the charging amplitude of the second charge pump capacitor CP2.

[0045] Please see Figure 2 In this embodiment, the high-side NMOS floating ground generation circuit mainly includes a low-voltage control section, a high-side floating ground generation section, and a floating ground generation amplitude detection section. These three sections are described in detail below: First, the low-voltage control section.

[0046] The low-voltage control section includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a first resistor R1, a second resistor R2, a third resistor R3, a buffer buffer1, and an inverter inv9.

[0047] The first PMOS transistor PM1, the second PMOS transistor PM2, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6 together form a current mirror structure. The source of the first PMOS transistor PM1 is coupled to the power supply VBB, and its gate is connected to its drain and then coupled to the gate of the second PMOS transistor PM2. The source of the second PMOS transistor PM2 is coupled to the power supply VBB, and its drain is coupled to the drain of the first NMOS transistor NM1. The source of the fifth PMOS transistor PM5 is coupled to the power supply VBB, its gate is coupled to the gate of the first PMOS transistor PM1, and its drain is coupled to the source of the sixth PMOS transistor PM6. The gate of the sixth PMOS transistor PM6 is coupled to its drain, and its drain is coupled to the drain of the second NMOS transistor NM2.

[0048] The first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 form a current mirror circuit to provide bias current for the circuit. The gate and drain of the first NMOS transistor NM1 are connected and coupled to the gates of the second NMOS transistor NM2 and the third NMOS transistor NM3, and its source is coupled to reference ground GND. The drain of the second NMOS transistor NM2 is coupled to the drain of the sixth PMOS transistor PM6, and its source is coupled to reference ground GND. The drain of the third NMOS transistor NM3 is coupled to the drain of the second PMOS transistor PM2, and its source is coupled to reference ground GND.

[0049] The third PMOS transistor, PM3, is connected to the gate and source of the eighth NMOS transistor, NM8, forming a discharge path to the reference ground (GND) to prevent malfunctions when the gate voltage of the fourth NMOS transistor, NM4, is too high. Specifically, the source of the third PMOS transistor, PM3, is coupled to the source of the eighth NMOS transistor, NM8, and its drain is coupled to the gate of the eighth NMOS transistor, which is then coupled to the reference ground (GND). When the gate voltage of the eighth NMOS transistor, NM8, is too high, the third PMOS transistor, PM3, turns on, discharging excess charge to the reference ground (GND) and protecting subsequent devices.

[0050] The fourth PMOS transistor PM4 and the sixth NMOS transistor NM6 form a switch, turning off the circuit when it is not enabled. The source of the fourth PMOS transistor PM4 is coupled to the power supply VBB, its gate receives the inverted enable signal output from inverter inv9, and its drain is coupled to the gate of the fifth PMOS transistor PM5. The drain of the sixth NMOS transistor NM6 is coupled to the gate of the fourth NMOS transistor NM4, its gate receives the inverted enable signal output from inverter inv9, and its source is coupled to reference ground GND.

[0051] The inverter inv9 receives an external enable signal EN at its input and outputs an inverted enable signal to the gates of the fourth PMOS transistor PM4 and the sixth NMOS transistor NM6. When the external enable signal EN is high, inverter inv9 outputs a low level, turning on the fourth PMOS transistor PM4 and turning off the sixth NMOS transistor NM6, thus putting the circuit into operation. When the external enable signal EN is low, inverter inv9 outputs a high level, turning off the fourth PMOS transistor PM4 and turning on the sixth NMOS transistor NM6, thus turning the circuit off.

[0052] The first terminal of the first resistor R1 is coupled to the power supply VBB, and its second terminal is coupled to the drain of the eighth NMOS transistor NM8 and the gate of the fourth NMOS transistor NM4. The source of the eighth NMOS transistor NM8 is coupled to the drain of the fourth NMOS transistor NM4, and its gate is coupled to the internal low-voltage power supply VDD. The function of the eighth NMOS transistor NM8 is to isolate high voltage. When the voltage amplitude of the power supply VBB is high, the drain potential of the eighth NMOS transistor NM8 is lower than the power supply VBB by a Zener clamp voltage, which is quite high. Without the eighth NMOS transistor NM8, this high voltage would damage the fourth NMOS transistor NM4 and the devices below it. By using the eighth NMOS transistor NM8, the high voltage is isolated on the drain side of the eighth NMOS transistor NM8, protecting the low-voltage devices.

[0053] The first end of the third resistor R3 is coupled to the source of the fourth NMOS transistor NM4, and the second end is coupled to the reference ground GND. The function of the third resistor R3 is to generate a voltage at the source of the fourth NMOS transistor NM4, so as to turn off the device when the gate voltage of the fourth NMOS transistor NM4 is low.

[0054] The gate of the fourth NMOS transistor NM4 serves as the sampling input terminal, coupled to the voltage divider node of the power supply VBB through the eighth NMOS transistor NM8. Its drain is coupled to the internal low-voltage power supply VDD, and its source is coupled to the sampling output node VBB_SENSE and the first terminal of the third resistor R3. The fourth NMOS transistor NM4 constitutes a sampling transistor, used to control its conduction level according to the voltage amplitude of the power supply VBB.

[0055] The third resistor R3 serves as a load element, connected between the source of the fourth NMOS transistor NM4 and the reference ground GND, and is used to convert the current of the fourth NMOS transistor NM4 into a sampling signal.

[0056] The ninth NMOS transistor NM9 and buffer1 constitute a feedback unit to form positive feedback and enhance the anti-interference capability of the sampling signal. The input of buffer1 is coupled to the sampling output node VBB_SENSE, and its output is coupled to the gate of the ninth NMOS transistor NM9. The drain of the ninth NMOS transistor NM9 is coupled to the gate of the fourth NMOS transistor NM4, and its source is coupled to the reference ground GND.

[0057] When the voltage of the sampling output node VBB_SENSE is high, this high level is buffered by buffer1 and applied to the gate of the ninth NMOS transistor NM9. NM9 turns on, pulling the gate of the fourth NMOS transistor NM4 low to the reference ground GND. After the gate of NM4 is pulled low, NM4 is further turned off, causing the voltage of the sampling output node VBB_SENSE to rise further. This positive feedback process enhances the circuit's anti-interference capability and prevents the sampling signal from jittering due to noise near the preset threshold.

[0058] The fifth NMOS transistor, NM5, forms a pull-down transistor. Its gate is coupled to the sampling output node VBB_SENSE, its drain is coupled to the floating ground node HS_GND, and its source is coupled to the reference ground GND through the second resistor R2. The fifth NMOS transistor, NM5, forms the core device of the pull-down control module 200. Its control terminal is coupled to the output terminal of the voltage sampling module 100, and in response to the sampling signal, it selectively pulls the floating ground node HS_GND down to the reference ground GND.

[0059] The second resistor R2 is connected between the source of the fifth NMOS transistor NM5 and the reference ground GND. It is used to limit the magnitude of the branch current when the fifth NMOS transistor NM5 is turned on, and to prevent excessive current from damaging the device.

[0060] The fourth NMOS transistor NM4, the third resistor R3, the ninth NMOS transistor NM9, the buffer 1, and the fifth NMOS transistor NM5 together constitute the voltage sampling module 100 and the pull-down control module 200. Among them, the fourth NMOS transistor NM4 serves as the sampling transistor, the third resistor R3 serves as the load element, the ninth NMOS transistor NM9 and the buffer 1 constitute the feedback unit, and the fifth NMOS transistor NM5 serves as the pull-down transistor.

[0061] Second, the high-side floating ground is generated in part.

[0062] The high-side floating ground generation section includes a first resistor R1, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a twelfth PMOS transistor PM12, a thirteenth PMOS transistor PM13, a first Zener diode Z1, and a second Zener diode Z2.

[0063] In this configuration, the first terminal of the first resistor R1 is coupled to the power supply VBB, and its second terminal is coupled to the gate of the eighth PMOS transistor PM8. The source of the eighth PMOS transistor PM8 is coupled to the power supply VBB, and its drain is coupled to the floating ground node HS_GND. The eighth PMOS transistor PM8 constitutes a floating ground output transistor, with its control terminal coupled to the power supply VBB through the first resistor R1, its first on terminal coupled to the power supply VBB, and its second on terminal providing the floating ground voltage.

[0064] The gate of the seventh PMOS transistor PM7 is coupled to the gate of the eighth PMOS transistor PM8, its source is coupled to the power supply VBB, and its drain is coupled to the floating ground node HS_GND. The seventh PMOS transistor PM7 forms a current mirror transistor; its control terminal is coupled to the control terminal of the eighth PMOS transistor PM8, its first on-terminal is coupled to the power supply VBB, and its second on-terminal is coupled to the floating ground node HS_GND. The seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 form a current mirror structure to provide current to the floating ground node HS_GND.

[0065] The gate of the twelfth PMOS transistor PM12 is connected to its drain and coupled to the power supply VBB, while its source is coupled to the gate of the eighth PMOS transistor PM8. The twelfth PMOS transistor PM12 is used as a MOS capacitor, with its gate and drain connected to form the first terminal of the capacitor and its source forming the second terminal, used to stabilize the gate voltage of the eighth PMOS transistor PM8.

[0066] The gate and drain of the thirteenth PMOS transistor PM13 are connected and coupled to the power supply VBB, while its source is coupled to the floating ground node HS_GND. The thirteenth PMOS transistor PM13 also functions as a MOS capacitor to stabilize the voltage of the floating ground node HS_GND.

[0067] The cathode of the first Zener diode Z1 is coupled to the gate of the eighth PMOS transistor PM8, and its anode is coupled to the floating ground node HS_GND. The first Zener diode Z1 constitutes the first clamping element, coupled between the control terminal of the eighth PMOS transistor PM8 and the floating ground node HS_GND, and is used to clamp the voltage between the control terminal of the eighth PMOS transistor PM8 and the floating ground node HS_GND to the clamping voltage value.

[0068] The current in the branch containing the first resistor R1 is determined by the second NMOS transistor NM2. When the voltage amplitude of the power supply VBB exceeds the preset value, the voltage across the first resistor R1 is high, which may cause the gate-source voltage VGS of the eighth PMOS transistor PM8 to become too large and be damaged. At this time, the first Zener diode Z1 breaks down, clamping the voltage across the first resistor R1 to a fixed voltage value, thus protecting the eighth PMOS transistor PM8.

[0069] The potential of the floating ground node HS_GND is lower than the gate voltage of the eighth PMOS transistor PM8 by one PMOS threshold voltage. Through the clamping effect of the first Zener diode Z1, the voltage difference ΔV1 between the floating ground node HS_GND and the power supply VBB is stabilized at a fixed amplitude. The function of the seventh PMOS transistor PM7 is to protect the gate-source voltage VGS of the eighth PMOS transistor PM8, preventing it from becoming excessive.

[0070] The cathode of the second Zener diode Z2 is coupled to the floating ground node HS_GND, and its anode is coupled to the reference ground GND. The second Zener diode Z2 constitutes a second clamping element, coupled between the floating ground node HS_GND and the reference ground GND, used to limit the maximum pull-down amplitude of the floating ground node HS_GND. When the fifth NMOS transistor NM5 is turned on and pulls the floating ground node HS_GND down, the second Zener diode Z2 prevents the floating ground node HS_GND from being pulled down excessively, thus avoiding an excessively large ΔV1.

[0071] Third, the amplitude detection part generated by floating ground.

[0072] The amplitude detection section includes the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the seventh NMOS transistor NM7, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the Schmitt trigger smit1, and the inverter inv1.

[0073] Specifically, the first terminal of the fourth resistor R4 is coupled to the power supply VBB, and its second terminal is coupled to the source of the ninth PMOS transistor PM9 and the source of the tenth PMOS transistor PM10. The gate of the ninth PMOS transistor PM9 is coupled to the gate and drain of the eleventh PMOS transistor PM11, and its drain is coupled to the input of the Schmitt trigger smit1. The gate of the tenth PMOS transistor PM10 is coupled to its drain, and its drain is coupled to the drain of the seventh NMOS transistor NM7. The gate of the seventh NMOS transistor NM7 is coupled to the common node of the fifth resistor R5 and the sixth resistor R6, and its source is coupled to the floating ground node HS_GND. The source of the eleventh PMOS transistor PM11 is coupled to the power supply VBB, and its drain is coupled to its gate.

[0074] The first terminal of the fifth resistor R5 is coupled to the power supply VBB, and its second terminal is coupled to the first terminal of the sixth resistor R6 and the gate of the seventh NMOS transistor NM7. The second terminal of the sixth resistor R6 is coupled to the floating ground node HS_GND.

[0075] The input of Schmitt trigger smit1 is coupled to the drain of the ninth PMOS transistor PM9, and its output is coupled to the input of inverter inv1. The output of inverter inv1 outputs a detection completion signal.

[0076] The fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 form a voltage divider network, which is coupled between the power supply VBB and the floating ground node HS_GND. It is used to sample the voltage difference ΔV1 between the floating ground node HS_GND and the power supply VBB.

[0077] The seventh NMOS transistor NM7 forms a comparator transistor. Its control terminal is coupled to the common node of the fifth resistor R5 and the sixth resistor R6, which is the output terminal of the voltage divider network. It is used to compare the voltage divider sample with the threshold voltage of the seventh NMOS transistor NM7 and output the comparison result.

[0078] The ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the Schmitt trigger smit1, and the inverter inv1 constitute the output stage, which is coupled to the output terminal of the seventh NMOS transistor NM7 and is used to output an enable signal based on the comparison result.

[0079] The ninth PMOS transistor, PM9, forms a hysteresis feedback branch, coupled between the output of the output stage and the output of the voltage divider network, providing hysteresis characteristics for the amplitude detection module. Specifically, when the output of the Schmitt trigger smit1 is low, the gate potential of the ninth PMOS transistor PM9 is pulled low, and PM9 turns on, pulling the output of the voltage divider network (i.e., the common node of the fifth resistor R5 and the sixth resistor R6) high, further turning on the seventh NMOS transistor NM7. This positive feedback mechanism provides hysteresis characteristics for the amplitude detection module, preventing the enable signal from erroneously flipping near the preset value.

[0080] The working principle of the amplitude detection module 500 is as follows: When the voltage amplitude of the power supply VBB is high, the voltage difference ΔV1 between the floating ground node HS_GND and the power supply VBB is large enough. The voltage division sampling value of the fifth resistor R5 and the sixth resistor R6 exceeds the threshold voltage of the seventh NMOS transistor NM7. The seventh NMOS transistor NM7 is turned on, the input of Schmitt trigger smit1 is pulled low, and the inverter inv1 outputs a high-level detection completion signal.

[0081] When the voltage amplitude of the power supply VBB is low, ΔV1 is small, the voltage divider sampling value is lower than the threshold voltage of the seventh NMOS transistor NM7, the seventh NMOS transistor NM7 is turned off, the input of Schmitt trigger smit1 is pulled high, and the inverter inv1 outputs a low level, indicating that the floating ground amplitude has not yet reached the preset value.

[0082] The following is combined with Figures 3 to 5 The working principle of the circuit of the present invention will be explained in detail.

[0083] (1) The working principle of the circuit provided by this invention when the power supply VBB is at a relatively high voltage (e.g., 30V) is as follows: When the external enable signal EN is low, the circuit is in an disabled state. At this time, the voltage of the floating ground node HS_GND is the same as the voltage of the power supply VBB, and this potential cannot enable the subsequent circuits to work properly.

[0084] When the external enable signal EN goes high, the inverter inv9 outputs a low level, the fourth PMOS transistor PM4 turns on, and the sixth NMOS transistor NM6 turns off, and the circuit enters the working state. The bias current generated by the bandgap reference is mirrored through the current mirror to the branches of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the branches of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6.

[0085] When the voltage amplitude of the power supply VBB is high, the current in the branch containing the first resistor R1 is generated and mirrored by the bandgap reference, and is a fixed current. Because the power supply VBB is high, the voltage across the first resistor R1 is large enough to exceed the breakdown voltage of the first Zener diode Z1, causing the first Zener diode Z1 to break down and clamp the voltage across the first resistor R1 to a fixed value. This clamping voltage serves as the gate-source voltage VGS of the eighth PMOS transistor PM8, causing PM8 to conduct. At this time, the potential of the floating ground node HS_GND is lower than the gate voltage of the eighth PMOS transistor PM8 by one PMOS threshold voltage, i.e., ΔV1 equals the clamping voltage of the first Zener diode Z1 minus the threshold voltage of the eighth PMOS transistor PM8.

[0086] Simultaneously, due to the high power supply VBB, the gate potential of the fourth NMOS transistor NM4 is pulled up. Its potential is the internal low-voltage power supply VDD minus the gate-source voltage VGS of the eighth NMOS transistor NM8, which is sufficient to turn on the fourth NMOS transistor NM4. After the fourth NMOS transistor NM4 turns on, the sampling output node VBB_SENSE is pulled low. This low-level sampling signal is applied to the gate of the fifth NMOS transistor NM5, turning off the fifth NMOS transistor NM5 and stopping the pull-down of the floating ground node HS_GND. At this time, the floating ground node HS_GND is only generated by the floating ground generation module 300 and does not require additional pull-down.

[0087] When the voltage amplitude of the power supply VBB is high, the second Zener diode Z2 does not operate because the fifth NMOS transistor NM5 is turned off. The function of the seventh PMOS transistor PM7 is to protect the gate-source voltage VGS of the eighth PMOS transistor PM8 from excessive voltage.

[0088] (1) The working principle of the circuit provided by this invention when the power supply VBB is at a low voltage (such as 5V) is as follows: When the external enable signal EN is low, the circuit is in an disabled state, and the voltage of the floating ground node HS_GND is the same as the voltage of the power supply VBB.

[0089] When the external enable signal EN goes high, the circuit enters the working state. When the voltage amplitude of the power supply VBB is low, the voltage across the first resistor R1 is insufficient to break down the first Zener diode Z1. At this time, the gate voltage of the eighth PMOS transistor PM8 is determined by the current in the branch containing the first resistor R1 and the second NMOS transistor NM2. Because the power supply VBB is low, the gate-source voltage VGS of the eighth PMOS transistor PM8 is insufficient to fully turn on the eighth PMOS transistor PM8, resulting in an insufficient amplitude of ΔV1.

[0090] Meanwhile, due to the low power supply VBB, the gate voltage of the fourth NMOS transistor NM4 is insufficient to fully turn it on, resulting in NM4 being either turned off or only weakly turned on. The sampling output node VBB_SENSE is pulled up to the internal low-voltage power supply VDD through the third resistor R3, becoming high.

[0091] The high-level sampling signal is applied to the gate of the fifth NMOS transistor NM5, which turns on and pulls the floating ground node HS_GND down to the reference ground GND. After the floating ground node HS_GND is pulled down, the voltage difference ΔV1 between it and the power supply VBB increases, ensuring that the value of ΔV1 is large enough when the supply voltage is low, so that the subsequent bootstrap switch NM12 can be fully turned on, reducing the voltage drop caused by the MOS transistor not being fully turned on.

[0092] Simultaneously, the high level of the sampling output node VBB_SENSE is buffered by buffer1 and applied to the gate of the ninth NMOS transistor NM9. NM9 turns on, pulling the gate of the fourth NMOS transistor NM4 low to the reference ground GND. After the gate of NM4 is pulled low, NM4 is further turned off, causing the voltage of the sampling output node VBB_SENSE to rise further. This positive feedback process ensures that the fifth NMOS transistor NM5 remains on, preventing jitter near the preset threshold.

[0093] The function of the second Zener diode Z2 is to protect the floating ground node HS_GND from being pulled down too much, so as to prevent ΔV1 from becoming too large. When the fifth NMOS transistor NM5 pulls down the floating ground node HS_GND to a level exceeding the safe range, the second Zener diode Z2 breaks down, clamping the potential of the floating ground node HS_GND at a safe value.

[0094] The amplitude detection module 500 performs real-time detection of the voltage difference ΔV1 between the floating ground node HS_GND and the power supply VBB. When ΔV1 reaches a preset value, i.e., when the voltage sampling value of the voltage divider between the fifth resistor R5 and the sixth resistor R6 exceeds the threshold voltage of the seventh NMOS transistor NM7, the seventh NMOS transistor NM7 is turned on, the input of the Schmitt trigger smit1 is pulled low, and the inverter inv1 outputs a high-level detection completion signal for use by the subsequent circuits. When ΔV1 does not reach the preset value, the detection completion signal is low, and the subsequent circuits wait for the floating ground voltage to be established.

[0095] Figure 3 The key waveforms are shown when the power supply VBB is at a higher voltage. From Figure 3 It can be seen that when the external enable signal EN is low (before 50µs), the voltage of the floating ground node HS_GND is consistent with the voltage of the power supply VBB. After the external enable signal EN goes high (at 50µs), due to the high power supply VBB, the voltage value of the sampling output node VBB_SENSE is low. This value is lower than the threshold voltage of the fifth NMOS transistor NM5, so the fifth NMOS transistor NM5 cannot be turned on, and the floating ground node HS_GND is not pulled down. The floating ground amplitude ΔV1 generated internally by the circuit is sufficient and no additional compensation is needed.

[0096] Figure 4 The key waveforms are shown when the power supply VBB is at a low voltage. From Figure 4 It can be seen that when the external enable signal EN is low, the voltage of the floating ground node HS_GND is the same as the voltage of the power supply VBB. After the external enable signal EN goes high, due to the low power supply VBB, the voltage value of the sampling output node VBB_SENSE is pulled high. This value turns on the fifth NMOS transistor NM5, further pulling the floating ground node HS_GND down towards the reference ground GND, increasing the voltage difference ΔV1 between the power supply VBB and the floating ground node HS_GND.

[0097] Figure 5 The key waveforms are shown when the fifth NMOS transistor NM5 is removed and the power supply VBB is at a lower voltage. From Figure 5 It can be seen that, in the absence of the fifth NMOS transistor NM5, even if the voltage value of the sampling output node VBB_SENSE is pulled high, due to the lack of the pull-down control module 200, the floating ground node HS_GND can only rely on the floating ground generation module 300 to generate the floating ground voltage. (Comparison) Figure 4 and Figure 5It can be seen that when the supply voltage is low, the ΔV1 generated after setting the fifth NMOS transistor NM5 is significantly larger than the ΔV1 without setting the fifth NMOS transistor NM5. This comparison fully demonstrates that the present invention, by setting the pull-down control module 200, can generate sufficient ΔV1 across the entire supply voltage range.

[0098] Through comparative analysis of the two operating conditions described above, it can be seen that in this embodiment, the voltage amplitude of the power supply VBB is sampled by the fourth NMOS transistor NM4. The sampling result controls the conduction and turn-off of the fifth NMOS transistor NM5 through the sampling output node VBB_SENSE, thereby selectively pulling down the floating ground node HS_GND to the reference ground GND. When the power supply VBB is low, the ΔV1 generated by the floating ground generation module 300 itself is insufficient to fully turn on the subsequent bootstrap switch NM12. At this time, the fifth NMOS transistor NM5 further pulls down the floating ground node HS_GND, increasing ΔV1. When the power supply VBB is high, the ΔV1 generated by the floating ground generation module 300 itself is sufficient. At this time, the fifth NMOS transistor NM5 is turned off, and the pull-down stops.

[0099] In this embodiment, the positive feedback loop formed by the ninth NMOS transistor NM9 and the buffer 1 further enhances the stability of the circuit. When the sampling output node VBB_SENSE is high, this high level, after passing through the buffer 1, turns on the ninth NMOS transistor NM9, pulling the gate of the fourth NMOS transistor NM4 low, thus further turning off the fourth NMOS transistor NM4. This ensures that the sampling output node VBB_SENSE remains high, and the fifth NMOS transistor NM5 remains on. This positive feedback mechanism effectively prevents the sampling signal from jittering near a preset threshold.

[0100] The eighth NMOS transistor, NM8, acts as a high-voltage isolation device, protecting the fourth NMOS transistor, NM4, and the low-voltage devices downstream of it when the power supply voltage VBB is high. When VBB is high, the drain potential of the eighth NMOS transistor, NM8, is lower than VBB by a Zener clamp voltage, which is still quite high. Through the isolation effect of the eighth NMOS transistor, the high voltage is blocked on the drain side of NM8, preventing low-voltage devices such as the fourth NMOS transistor, NM4, from experiencing high-voltage stress.

[0101] When the power supply voltage VBB is high, the first Zener diode Z1 clamps the voltage across the first resistor R1 to a fixed value, protecting the gate-source voltage VGS of the eighth PMOS transistor PM8 from becoming too high. The first resistor R1, in conjunction with the first Zener diode Z1, clamps the gate-source voltage of the eighth PMOS transistor PM8 within a safe range when the power supply voltage VBB is high.

[0102] The twelfth PMOS transistor PM12 and the thirteenth PMOS transistor PM13 are used as MOS capacitors to stabilize the gate voltage of the eighth PMOS transistor PM8 and the voltage of the floating ground node HS_GND, respectively. Because MOS capacitors have a high capacitance density, a large capacitance value can be achieved within a small chip area, which is beneficial for improving circuit integration.

[0103] The ninth PMOS transistor PM9 in the amplitude detection module 500 forms a hysteresis feedback branch, providing hysteresis characteristics for the amplitude detection module 500. When the detection completion signal flips, the conduction state of the ninth PMOS transistor PM9 changes, altering the voltage at the output of the voltage divider network, causing the flipping threshold to shift. This hysteresis characteristic effectively prevents the detection completion signal from frequently flipping near the preset threshold, improving the reliability of the detection.

[0104] The current bias module consists of a first PMOS transistor PM1, a second PMOS transistor PM2, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3, providing bias current for the entire circuit. A bandgap reference generates a stable bias current, which is mirrored to each branch through a current mirror, providing a stable operating current for the circuit and reducing its sensitivity to changes in the power supply VBB.

[0105] Based on the above structure, the high-side NMOS floating ground generation circuit provided by this invention can generate a sufficient floating ground amplitude ΔV1 across a wide supply voltage range of 5V to 30V. When the supply voltage is low, the additional pull-down action of the pull-down control module 200 ensures that ΔV1 is large enough to guarantee that the subsequent bootstrap switch NM12 is fully turned on. When the supply voltage is high, the pull-down control module 200 automatically turns off to prevent excessive ΔV1 from increasing device stress. This adaptive adjustment mechanism allows this invention to adapt to a wide range of supply voltage inputs, exhibiting excellent versatility and reliability.

[0106] The subsequent charge pump circuit 400, based on the principle that the voltage across a capacitor cannot change abruptly, superimposes a fixed amplitude ΔV2 onto the power supply VBB to generate a drive voltage VCP higher than the power supply VBB, used to drive the high-side power transistor. The complementary clock signal generated by the non-overlapping clock generation circuit ensures that the first charging switch NM10 and the second charging switch NM11 conduct alternately, avoiding the short-circuit risk caused by simultaneous conduction. The three-stage inverter structure provides sufficient drive capability for the fourth switch PM14, ensuring its rapid turn-on and turn-off.

[0107] The bootstrap switch NM12 is fully turned on when the voltage across its gate NM12_G reaches VBB+ΔV1. The power supply VBB charges the first charge pump capacitor CP1 through the bootstrap switch NM12. When the fourth switch PM14 is turned on, the first terminal of the second charge pump capacitor CP2 is pulled high to the power supply VBB. Since the voltage across the capacitor cannot change abruptly, the voltage across the first charge pump capacitor CP1 becomes VBB+ΔV2. At this time, the third switch PM13 is turned on, transmitting the voltage VBB+ΔV2 to the drive voltage VCP to drive the high-side power transistor.

[0108] The fifth switch NM13 and the seventh resistor R7 work together with the control circuit to determine the charging amplitude of the second charge pump capacitor CP2. By adjusting the on-time of the fifth switch NM13 and the resistance of the seventh resistor R7, the magnitude of ΔV2 can be precisely controlled to adapt to the driving requirements of different power transistors.

[0109] In summary, the high-side NMOS floating ground generation circuit provided by this invention uses a voltage sampling module 100 to detect the voltage amplitude of the power supply VBB in real time, and adaptively controls the pull-down control module 200 to selectively pull down the floating ground node HS_GND accordingly, achieving dynamic adaptive adjustment of the floating ground voltage amplitude as the supply voltage changes. This circuit can generate a sufficient and stable floating ground voltage across the entire supply voltage range, ensuring full conduction of the subsequent bootstrap switch, reducing conduction losses, and improving system efficiency. Simultaneously, the positive feedback loop enhances the circuit's anti-interference capability, the high-voltage isolation devices and clamping elements ensure the circuit's reliability under high-voltage conditions, and the amplitude detection module 500 ensures reliable indication after the floating ground voltage is established.

[0110] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-side NMOS floating ground generation circuit, characterized in that, include: The floating ground node serves as the lowest potential reference node for the charge pump. A voltage sampling module (100) has its input terminal coupled to a power supply for detecting the voltage amplitude of the power supply and generating a corresponding sampling signal; A pull-down control module (200) is connected between the floating ground node and the reference ground. Its control terminal is coupled to the output terminal of the voltage sampling module (100). In response to the sampling signal, it selectively pulls the floating ground node down to the reference ground. as well as A floating ground generation module (300) is connected between the power supply and the floating ground node, and is used to generate a floating ground voltage with a fixed amplitude relative to the power supply; wherein: (a) When the voltage amplitude of the power supply is lower than a preset threshold, the voltage sampling module (100) controls the pull-down control module (200) to turn on, so as to increase the voltage difference between the floating ground node and the power supply; (b) When the voltage amplitude of the power supply is higher than a preset threshold, the voltage sampling module (100) controls the pull-down control module (200) to shut down, so as to stop the pull-down of the floating ground node.

2. The high-side NMOS floating ground generation circuit according to claim 1, characterized in that, The voltage sampling module (100) includes: The sampling transistor has its control terminal coupled to the voltage divider node of the power supply, its first conducting terminal coupled to the power supply, and its second conducting terminal coupled to the sampling output node. A load element is connected between the second conducting terminal of the sampling transistor and the reference ground; The feedback unit has its input terminal coupled to the sampling output node and its output terminal coupled to the control terminal of the sampling transistor, which is used to form positive feedback.

3. The high-side NMOS floating ground generation circuit according to claim 2, characterized in that, The feedback unit includes: A buffer, the input of which is coupled to the sampling output node; The feedback transistor has its control terminal coupled to the output terminal of the buffer, its first conducting terminal coupled to the control terminal of the sampling transistor, and its second conducting terminal coupled to the reference ground.

4. The high-side NMOS floating ground generation circuit according to claim 2, characterized in that, The pull-down control module (200) includes a pull-down transistor, the control terminal of which is coupled to the sampling output node, the first conducting terminal of which is coupled to the floating ground node, and the second conducting terminal of which is coupled to the reference ground.

5. The high-side NMOS floating ground generation circuit according to claim 2, characterized in that, Both the sampling transistor and the feedback transistor are NMOS transistors, and the load element is a resistor.

6. The high-side NMOS floating ground generation circuit according to claim 2, characterized in that, The voltage sampling module (100) also includes a high-voltage isolation transistor, which is connected in series between the voltage divider node of the power supply and the control terminal of the sampling transistor, and is used to protect the low-voltage devices in the voltage sampling module (100) when the voltage amplitude of the power supply is high.

7. The high-side NMOS floating ground generation circuit according to claim 6, characterized in that, The high-voltage isolation transistor is an NMOS transistor, with its control terminal coupled to an internal low-voltage power supply, its first conducting terminal coupled to the control terminal of the sampling transistor, and its second conducting terminal coupled to the voltage divider node of the power supply.

8. The high-side NMOS floating ground generation circuit according to claim 1, characterized in that, The floating ground generation module (300) includes: A first resistor, the first end of which is coupled to the power supply; A floating ground output transistor, the control terminal of which is coupled to the second terminal of the first resistor, the first conducting terminal of which is coupled to the power supply, and the second conducting terminal of which provides the floating ground voltage; A first clamping element is coupled between the control terminal of the floating ground output transistor and the floating ground node, and is used to clamp the voltage between the control terminal of the floating ground output transistor and the floating ground node to a clamping voltage value. A current mirror transistor has its control terminal coupled to the control terminal of the floating ground output transistor, its first conducting terminal coupled to the power supply, and its second conducting terminal coupled to the floating ground node; the current mirror transistor and the floating ground output transistor form a current mirror structure to provide current to the floating ground node.

9. The high-side NMOS floating ground generation circuit according to claim 8, characterized in that, The floating ground generation module (300) also includes a second clamping element coupled between the floating ground node and the reference ground to limit the maximum magnitude by which the floating ground node can be pulled down.

10. The high-side NMOS floating ground generation circuit according to claim 9, characterized in that, Both the first clamping element and the second clamping element are Zener diodes; wherein: The cathode of the first clamping element is coupled to the control terminal of the floating ground output transistor, and the anode is coupled to the floating ground node; The cathode of the second clamping element is coupled to the floating ground node, and the anode is coupled to the reference ground.

11. The high-side NMOS floating ground generation circuit according to claim 8, characterized in that, The floating ground generation module (300) also includes: A first capacitor element is coupled between the power supply and the control terminal of the floating ground output transistor to stabilize the control terminal voltage of the floating ground output transistor. A second capacitor element is coupled between the power supply and the floating ground node to stabilize the floating ground voltage.

12. The high-side NMOS floating ground generation circuit according to claim 1, characterized in that, It also includes an amplitude detection module (500), the input terminal of which is coupled to the floating ground node, for detecting whether the voltage difference between the floating ground node and the power supply reaches a preset value, and outputting an enable signal for use by the subsequent circuit when the preset value is reached.

13. The high-side NMOS floating ground generation circuit according to claim 12, characterized in that, The amplitude detection module (500) includes: A voltage divider network, coupled between the power supply and the floating ground node, is used to sample the voltage difference. A comparator transistor, whose control terminal is coupled to the output terminal of the voltage divider network, is used to compare the voltage divider sample with its threshold voltage and output the comparison result; An output stage, coupled to the output terminal of the comparator transistor, is used to output the enable signal based on the comparison result; The hysteresis feedback branch is coupled between the output terminal of the output stage and the output terminal of the voltage divider network.

14. The high-side NMOS floating ground generation circuit according to claim 1, characterized in that, It also includes a downstream charge pump circuit (400) with the floating ground node as the lowest potential reference node, the downstream charge pump circuit (400) comprising: A non-overlapping clock generation circuit is used to generate a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal are phase-complementary. First energy storage capacitor and second energy storage capacitor; The first charging switch and the second charging switch are controlled by the first clock signal and the second clock signal, respectively, and alternately charge and discharge the first energy storage capacitor and the second energy storage capacitor to generate a control signal for driving the high-side bootstrap switch by superimposing the fixed amplitude on the power supply.

15. The high-side NMOS floating ground generation circuit according to claim 1, characterized in that, It also includes a current bias module that provides bias current to the floating ground generation circuit, the current bias module comprising a bandgap reference current source and a current mirror circuit.

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