A method for controlling time delay of front and back stages of power converter based on CPLD

Abstract

The application relates to a CPLD-based delay control circuit and belongs to the technical field of power electronic converters, which solves the problem of excessively high CPLD resource occupancy rate in the prior art for starting / shutting down delay time control of front-stage and rear-stage converters. The delay control circuit comprises a first delay circuit and a second delay circuit, and the input ends of the first delay circuit and the second delay circuit are connected. After receiving a starting signal, the input ends of the first delay circuit and the second delay circuit, the second delay circuit directly outputs a starting control signal without delay; the first delay circuit outputs a starting signal after a first delay time; after receiving a shutdown signal, the input ends of the first delay circuit and the second delay circuit, the first delay circuit directly outputs a shutdown control signal without delay; and the second delay circuit outputs a shutdown control signal after a second delay time. A simple and reliable CPLD-based delay control circuit is realized.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter technology, and in particular to a delay control circuit based on CPLD. Background Technology

[0002] Two-stage DC-DC converters based on Buck-LLC converters, combining the advantages of both pre- and post-converter stages, can meet more complex operating conditions and are increasingly being used in new energy fields such as photovoltaic systems, electric vehicle charging, and DC microgrids. To improve converter performance and ensure stable system operation, the power-on / off sequence control of the pre- and post-converter stages is crucial. Generally, during power-on, the post-converter LLC converter should start first, followed by the pre-converter Buck converter. This ensures a smooth start-up of the Buck converter under stable load conditions, reducing instability caused by sudden changes in the circuit. During power-off, the pre-converter Buck converter should turn off first, followed by the post-converter LLC converter. Discharging the bus voltage through the LLC converter avoids safety issues caused by the bus remaining energized after power-off.

[0003] Meanwhile, with the rapid development of electronic technology, large-scale programmable logic devices such as CPLDs and FPGAs have met the requirements of most applications in terms of integration, functionality, and performance. The emergence of programmable logic devices has shortened product development cycles, improved field flexibility, and reduced development risks. With the continuous development of processes, technologies, and markets, the application prospects of programmable logic devices will become increasingly broad.

[0004] To achieve delay control, a counter can be designed in the CPLD to count the clock signal and thus control the delay. For stable system operation, the power-on / power-off delay time of the upstream and downstream converters is in the millisecond range. However, the crystal clock signals in current CPLDs are generally in the megahertz range. Using clock signal counting to achieve delay consumes a significant amount of CPLD resources. Experimental testing revealed that, using a Xilinx XC9672Xl CPLD to obtain the delayed turn-on of the Buck converter's switching transistor and the delayed turn-off of the LLC converter's switching transistor, the macrocell occupancy rate increased from 55% to 83%. The CPLD compilation results showed excessively high resource occupancy, which may cause functional deficiencies or errors. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a CPLD-based delay control circuit to solve the problem of excessive CPLD resource occupancy in the power-on / off control signal delay control of existing two-stage DC-DC converters.

[0006] On one hand, embodiments of the present invention provide a delay control circuit based on a CPLD. The delay control circuit includes a first delay circuit and a second delay circuit, the input terminals of which are connected. After receiving a power-on signal, the second delay circuit directly outputs a power-on control signal without delay. The first delay circuit outputs a power-on signal after a first delay time. After receiving a power-off signal, the first delay circuit directly outputs a power-off control signal without delay. The second delay circuit outputs a power-off control signal after a second delay time.

[0007] Furthermore, the first delay circuit includes: a first D flip-flop inst1, a second D flip-flop inst5, a first NOT gate inst2, a second NOT gate inst4, and a first tri-state gate inst3. The CP pin of the first D flip-flop inst1 and the input of the second NOT gate inst4 are connected and used as the input of the first delay circuit to receive the power-on / off signal. The D terminal of the first D flip-flop inst1 is connected to VCC, and the Q terminal is connected to the input of the first NOT gate inst2. The output of the first NOT gate inst2 is connected to the enable terminal of the first tri-state gate inst3. The input of the first tri-state gate inst3 is grounded, and its output is connected to the CLR terminal of the first D flip-flop inst1. The output of the second NOT gate inst4 is connected to the CLR terminal of the second D flip-flop inst5. The CP terminal of the second D flip-flop inst5 is connected to the output of the first NOT gate inst2. The D terminal of the second D flip-flop inst5 is connected to the power supply VCC. The Q terminal of the second D flip-flop inst5 outputs the power-on or power-off control signal of the first delay circuit.

[0008] Furthermore, the first delay circuit also includes: a first RC circuit, which includes a capacitor C1 and a resistor R1. One end of R1 is connected to the power supply VCC, and the other end is connected to one end of the capacitor C1. The other end of the capacitor C1 is grounded, and the connection end of R1 and C1 is connected to the CLR terminal of the first D flip-flop inst1.

[0009] Furthermore, the first delay circuit also includes: I / O ports PORT3 and PORT2. One end of PORT3 is connected to the CLR terminal of the first D flip-flop inst1, and the other end is connected to the connection terminal of the first RC circuit R1 and C1. One end of PORT2 is connected to the Q terminal of the second D flip-flop inst5, and the other end serves as the output terminal of the first delay circuit.

[0010] Furthermore, the second delay circuit includes: a third D flip-flop inst7, a fourth D flip-flop inst10, a third NOT gate inst6, a fourth NOT gate inst8, and a second tri-state gate inst9; the power-on / off signal is connected to the input of the third NOT gate inst6, and the output of the third NOT gate inst6 is connected to the CP pin of the third D flip-flop inst7; the D terminal of the third D flip-flop inst7 is connected to VCC, the Q terminal is connected to the input of the fourth NOT gate inst8, the output of the fourth NOT gate inst8 is connected to the enable terminal of the second tri-state gate inst9, the input of the second tri-state gate inst9 is grounded, and the output of the second tri-state gate inst9 is connected to the CLR terminal of the third D flip-flop inst7; the power-on / off signal is connected to the SET terminal of the fourth D flip-flop inst10, the D terminal of the fourth D flip-flop inst10 is grounded, the CP terminal is connected to the output of the fourth NOT gate inst8, and the Q terminal of the fourth D flip-flop inst10 outputs the power-on or power-off control signal for the second delay circuit.

[0011] Furthermore, the second delay circuit also includes a second RC circuit, which includes a capacitor C2 and a resistor R2. One end of R2 is connected to the power supply VCC, and the other end is connected to one end of the capacitor C2. The other end of the capacitor C2 is grounded, and the connection end of R2 and C2 is connected to the CLR terminal of the third D flip-flop inst7.

[0012] Furthermore, the second delay circuit also includes: I / O ports PORT4 and PORT5, one end of PORT5 is connected to the CLR terminal of the third D flip-flop inst7, and the other end is connected to the connection terminal of the second RC circuit R2 and C2; one end of PORT4 is connected to the Q terminal of the fourth D flip-flop inst10, and the other end serves as the output terminal of the second delay circuit.

[0013] Furthermore, the delay control circuit also includes an I / O port PORT1. One end of PORT1 is connected to the input terminals of the first delay circuit and the second delay circuit, and the other end serves as the input terminal of the delay control circuit to receive power-on or power-off signals.

[0014] Furthermore, the first delay circuit and the second delay circuit are implemented using the hardware description language in the CPLD.

[0015] On the other hand, embodiments of the present invention provide a power converter with pre- and post-stage delay control, the power converter including a Buck pre-stage, an LLC post-stage, and a delay control circuit; the Buck pre-stage and the LLC post-stage are respectively equipped with power-on / off control ports; the power-on / off control signal output by the first delay circuit is input to the power-on / off control port of the Buck pre-stage; the power-on / off control signal output by the second delay circuit is input to the power-on / off control port of the LLC post-stage.

[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0017] 1. The delay control circuit of this invention includes a first delay circuit and a second delay circuit, with their input terminals connected. Upon receiving a power-on signal, the second delay circuit directly outputs a power-on control signal without delay. The first delay circuit outputs the power-on signal after a first delay time. Upon receiving a power-off signal, the first delay circuit directly outputs a power-off control signal without delay. The second delay circuit outputs the power-off control signal after a second delay time. A CPLD is used to implement the power-on / off delay control of the front and rear stages of a Buck-LLC two-stage converter. This delay control circuit is simple and easy to implement, has a short development cycle, and is simple in circuit design, while effectively improving the stability and safety of the converter.

[0018] 2. The delay control circuit of this invention consists of two parts: a CPLD and surrounding hardware RC circuitry. The CPLD logic is written in a hardware description language, including D flip-flops inst1, inst5, inst7, and inst10; NOT gates inst2, inst4, inst6, and inst8; tri-state gates inst3 and inst9; and I / O ports PORT1-PORT5. PORT1 is the input power-on / off signal, PORT2 is the Buck power-on / off control signal, PORT4 is the LLC power-on / off control signal, and PORT3 and PORT5 are each connected to a set of RC circuits, achieving a long delay. Traditionally, when using counters to obtain the delayed turn-on of the Buck converter and the delayed turn-off of the LLC converter, the macrocell occupancy rate in the CPLD increases from 55% to 83%. With the delay control circuit of this invention, the CPLD macrocell occupancy rate only increases from 55% to 64%, significantly saving CPLD resources.

[0019] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0020] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0021] Figure 1 This is a schematic diagram of a delay control circuit structure based on a CPLD according to the present invention;

[0022] Figure 2 This is a timing diagram of the signal changes in a CPLD-based delay control circuit according to the present invention. Detailed Implementation

[0023] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0024] A specific embodiment of the present invention discloses a delay control circuit based on a CPLD, such as... Figure 1 As shown. The delay control circuit includes a first delay circuit and a second delay circuit, and the input terminals of the first delay circuit and the second delay circuit are connected.

[0025] Upon receiving a power-on signal, the input terminals of the first and second delay circuits are respectively: the second delay circuit outputs a power-on control signal directly without delay; the first delay circuit outputs a power-on signal after a first delay time. Upon receiving a power-off signal, the input terminals of the first and second delay circuits are respectively: the first delay circuit outputs a power-off control signal directly without delay; the second delay circuit outputs a power-off control signal after a second delay time.

[0026] Specifically, the input terminals of the first delay circuit and the second delay circuit are connected to receive external power-on / off signals, and the first delay circuit and the second delay circuit output different delay control signals.

[0027] The first delay circuit includes: a first D flip-flop inst1, a second D flip-flop inst5, a first NOT gate inst2, a second NOT gate inst4, and a first tri-state gate inst3. The CP pin of the first D flip-flop inst1 and the input of the second NOT gate inst4 are connected and used as the input of the first delay circuit to receive the power-on / off signal. The D terminal of the first D flip-flop inst1 is connected to VCC, and the Q terminal is connected to the input of the first NOT gate inst2. The output of the first NOT gate inst2 is connected to the enable terminal of the first tri-state gate inst3. The input of the first tri-state gate inst3 is grounded, and its output is connected to the CLR terminal of the first D flip-flop inst1. The output of the second NOT gate inst4 is connected to the CLR terminal of the second D flip-flop inst5. The CP terminal of the second D flip-flop inst5 is connected to the output of the first NOT gate inst2. The D terminal of the second D flip-flop inst5 is connected to the power supply VCC. The Q terminal of the second D flip-flop inst5 outputs the power-on or power-off control signal of the first delay circuit.

[0028] The first delay circuit further includes: a first RC circuit, which includes a capacitor C1 and a resistor R1. One end of R1 is connected to the power supply VCC, and the other end is connected to one end of the capacitor C1. The other end of the capacitor C1 is grounded, and the connection end of R1 and C1 is connected to the CLR terminal of the first D flip-flop inst1.

[0029] Specifically, the first RC circuit extends the delay of the power-on control signal at the output of the first delay circuit. At time t1, under the action of the rising edge power-on signal from PORT1, inst1 outputs a high level at port Q, and inst2 is inverted to output a low level. This causes the enable terminal of the first tri-state gate inst3 to be low, resulting in a high-impedance output for inst3. At this time, the power supply VCC in the first RC circuit charges C1 through R1. When the voltage on C1 is greater than the voltage threshold of port PORT3, since the first tri-state gate inst3 is in a high-impedance state, C1 provides a high level to the CLR of inst1 through port PORT3. During this high-level maintenance, the output Q of inst1 outputs a low level, which is inverted by inst2 to generate a rising edge transition. Since the output of inst4 is low at this time, it does not clear inst5, so inst5 transitions. The presence of the first RC circuit extends the time for inst5 to generate the power-on control signal.

[0030] The first delay circuit also includes: I / O ports PORT3 and PORT2. One end of PORT3 is connected to the CLR terminal of the first D flip-flop inst1, and the other end is connected to the connection terminal of the first RC circuit R1 and C1. One end of PORT2 is connected to the Q terminal of the second D flip-flop inst5, and the other end serves as the output terminal of the first delay circuit.

[0031] The second delay circuit includes: a third D flip-flop inst7, a fourth D flip-flop inst10, a third NOT gate inst6, a fourth NOT gate inst8, and a second tri-state gate inst9; the power-on / off signal is connected to the input of the third NOT gate inst6, and the output of the third NOT gate inst6 is connected to the CP pin of the third D flip-flop inst7; the D terminal of the third D flip-flop inst7 is connected to VCC, the Q terminal is connected to the input of the fourth NOT gate inst8, the output of the fourth NOT gate inst8 is connected to the enable terminal of the second tri-state gate inst9, the input of the second tri-state gate inst9 is grounded, and the output of the second tri-state gate inst9 is connected to the CLR terminal of the third D flip-flop inst7; the power-on / off signal is connected to the SET terminal of the fourth D flip-flop inst10, the D terminal of the fourth D flip-flop inst10 is grounded, the CP terminal is connected to the output of the fourth NOT gate inst8, and the Q terminal of the fourth D flip-flop inst10 outputs the power-on or power-off control signal for the second delay circuit.

[0032] The second delay circuit also includes a second RC circuit, which includes a capacitor C2 and a resistor R2. One end of R2 is connected to the power supply VCC, and the other end is connected to one end of the capacitor C2. The other end of the capacitor C2 is grounded, and the connection end of R2 and C2 is connected to the CLR terminal of the third D flip-flop inst7.

[0033] Specifically, the second RC circuit extends the delay time of the power-off control signal at the output of the second delay circuit.

[0034] Between times t3 and t4, the enable pin of the second tri-state gate, inst9, is low, resulting in a high-impedance output. Power supply VCC charges capacitor C2 through resistor R2. When the voltage level on C2 exceeds the high-level threshold of the CPLD's I / O port, the reset signal for the third D flip-flop, inst7, is activated. The Q output of inst7 goes low, and after being inverted by inst8, it triggers the Q output of the fourth D flip-flop, inst10, to go low, thus obtaining the shutdown control signal for the second delay circuit (delayed shutdown control signal).

[0035] The second delay circuit also includes: I / O ports PORT4 and PORT5. One end of PORT5 is connected to the CLR terminal of the third D flip-flop inst7, and the other end is connected to the connection terminal of the second RC circuit R2 and C2. One end of PORT4 is connected to the Q terminal of the fourth D flip-flop inst10, and the other end serves as the output terminal of the second delay circuit.

[0036] Specifically, such as Figure 2 As shown, at time t1: the power-on signal goes high, the SET signal of the fourth D flip-flop inst10 is activated, and the Q output of inst10 goes high, obtaining the power-on control signal for the second delay circuit. Simultaneously, the CP port of the first D flip-flop inst1 is triggered, and the Q output of inst1 goes high. After being inverted by the first NOT gate inst2, the enable terminal of the first tri-state gate inst3 goes low, and the output of the first tri-state gate inst3 is in a high-impedance state. At this time, the power supply VCC charges C1 through R1. At time t2: the voltage level on C1 exceeds the high-level threshold of the CPLD's I / O port, the clear signal of the first D flip-flop inst1 is activated, and the Q output of inst1 goes low. After being inverted by the first NOT gate inst2, the second D flip-flop inst5 is triggered, and the Q output of the second D flip-flop inst5 goes high, obtaining the power-on control signal for the first delay circuit (the delayed power-on control signal). Simultaneously, the enable terminal of the first tri-state gate inst3 is activated, outputting a low level, and capacitor C1 completes its discharge, preparing for charging during the next power-on.

[0037] At time t3: The power-on signal goes low. After passing through the second NOT gate (inst4), the second D flip-flop (inst5) is cleared by the CLR signal, and the Q output of inst5 goes low, obtaining the power-off signal for the first delay circuit. Simultaneously, the input power-off signal passes through the third NOT gate (inst6), triggering the third D flip-flop (inst7) to output a high level. After being inverted by the fourth NOT gate (inst8), the enable pin of the second tri-state gate (inst9) goes low, resulting in a high-impedance output. Power supply VCC charges C2 through R2. At time t4: The voltage level on C2 exceeds the high-level threshold of the CPLD's I / O port. The clear signal of the third D flip-flop (inst7) is activated, and the Q output of inst7 goes low. After being inverted by inst8, the Q output of the fourth D flip-flop (inst10) goes low, obtaining the power-off control signal for the second delay circuit (delayed power-off control signal). Simultaneously, the enable pin of the tri-state gate (inst9) is activated, and inst9 outputs a low level, allowing capacitor C2 to discharge, ready to recharge for the next power-off.

[0038] The delay control circuit also includes an I / O port PORT1. One end of PORT1 is connected to the input of the first delay circuit and the second delay circuit, and the other end serves as the input of the delay control circuit to receive power-on or power-off signals.

[0039] The first and second delay circuits are implemented using the hardware description language in CPLD.

[0040] Another specific embodiment of the present invention discloses a pre- and post-stage delay control power converter, the power converter including a Buck pre-stage, an LLC post-stage, and a delay control circuit; the Buck pre-stage and the LLC post-stage are respectively equipped with power-on / off control ports; the power-on / off control signal output by the first delay circuit is input to the power-on / off control port of the Buck pre-stage; the power-on / off control signal output by the second delay circuit is input to the power-on / off control port of the LLC post-stage.

[0041] Specifically, a first delay circuit and a second delay circuit are constructed based on complex programmable logic devices and peripheral circuits. The input terminals of the first delay circuit and the second delay circuit are connected and receive power-on and power-off signals. The output terminals of the first delay circuit and the second delay circuit are respectively connected to the front and rear stage control terminals of the power converter to control the power-on and power-off times of the front and rear stages of the power converter, so that the front stage of the power converter powers on last and the rear stage powers on first; the front stage of the power converter powers off first and the rear stage powers off last.

[0042] Compared with existing technologies, the delay control circuit provided in this embodiment includes a first delay circuit and a second delay circuit, with their input terminals connected. Upon receiving a power-on signal, the second delay circuit directly outputs a power-on control signal without delay. The first delay circuit outputs a power-on signal after a first delay time. Similarly, upon receiving a power-off signal, the first delay circuit directly outputs a power-off control signal without delay. The second delay circuit outputs a power-off control signal after a second delay time. A CPLD is used to implement the power-on / off delay control of the front and rear stages of a Buck-LLC two-stage converter. This delay control circuit is simple and easy to implement, has a short development cycle, and is simple in circuit design, while effectively improving the stability and safety of the converter. The delay control circuit provided in this embodiment consists of a CPLD and surrounding hardware RC circuitry. The CPLD logic is written in a hardware description language, including D flip-flops inst1, inst5, inst7, and inst10; NOT gates inst2, inst4, inst6, and inst8; tri-state gates inst3 and inst9; and I / O ports PORT1-PORT5. PORT1 is the input power-on / off signal, PORT2 is the Buck power-on / off control signal, PORT4 is the LLC power-on / off control signal, and PORT3 and PORT5 are each connected to a set of RC circuits to achieve long delays. Traditionally, when using counters to obtain the delayed turn-on of the Buck converter and the delayed turn-off of the LLC converter, the macrocell occupancy rate in the CPLD increases from 55% to 83%. This invention's delay control circuit reduces the CPLD macrocell occupancy rate from 55% to 64%, significantly saving CPLD resources.

[0043] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0044] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A delay control circuit based on a CPLD, characterized in that, The delay control circuit includes a first delay circuit and a second delay circuit, and the input terminals of the first delay circuit and the second delay circuit are connected. Upon receiving a power-on signal, the input terminals of the first and second delay circuits are respectively: the second delay circuit outputs a power-on control signal directly without delay; the first delay circuit outputs a power-on signal after a first delay time. Upon receiving a power-off signal, the input terminals of the first and second delay circuits are respectively: the first delay circuit outputs a power-off control signal directly without delay; the second delay circuit outputs a power-off control signal after a second delay time.

2. The delay control circuit according to claim 1, characterized in that, The first delay circuit includes: a first D flip-flop inst1, a second D flip-flop inst5, a first NOT gate inst2, a second NOT gate inst4, and a first tri-state gate inst3. The CP pin of the first D flip-flop inst1 and the input of the second NOT gate inst4 are connected and used as the input of the first delay circuit to receive the power-on / off signal. The D terminal of the first D flip-flop inst1 is connected to VCC, and the Q terminal is connected to the input of the first NOT gate inst2. The output of the first NOT gate inst2 is connected to the enable terminal of the first tri-state gate inst3. The input of the first tri-state gate inst3 is grounded, and its output is connected to the CLR terminal of the first D flip-flop inst1. The output of the second NOT gate inst4 is connected to the CLR terminal of the second D flip-flop inst5. The CP terminal of the second D flip-flop inst5 is connected to the output of the first NOT gate inst2. The D terminal of the second D flip-flop inst5 is connected to the power supply VCC. The Q terminal of the second D flip-flop inst5 outputs the power-on or power-off control signal of the first delay circuit.

3. The delay control circuit according to claim 2, characterized in that, The first delay circuit further includes: a first RC circuit, which includes a capacitor C1 and a resistor R1. One end of R1 is connected to the power supply VCC, and the other end is connected to one end of the capacitor C1. The other end of the capacitor C1 is grounded, and the connection end of R1 and C1 is connected to the CLR terminal of the first D flip-flop inst1.

4. The delay control circuit according to claim 3, characterized in that, The first delay circuit also includes: I / O ports PORT3 and PORT2. One end of PORT3 is connected to the CLR terminal of the first D flip-flop inst1, and the other end is connected to the connection terminal of the first RC circuit R1 and C1. One end of PORT2 is connected to the Q terminal of the second D flip-flop inst5, and the other end serves as the output terminal of the first delay circuit.

5. The delay control circuit according to claim 1, characterized in that, The second delay circuit includes: a third D flip-flop inst7, a fourth D flip-flop inst10, a third NOT gate inst6, a fourth NOT gate inst8, and a second tri-state gate inst9; the power-on / off signal is connected to the input of the third NOT gate inst6, and the output of the third NOT gate inst6 is connected to the CP pin of the third D flip-flop inst7; the D terminal of the third D flip-flop inst7 is connected to VCC, the Q terminal is connected to the input of the fourth NOT gate inst8, the output of the fourth NOT gate inst8 is connected to the enable terminal of the second tri-state gate inst9, the input of the second tri-state gate inst9 is grounded, and the output of the second tri-state gate inst9 is connected to the CLR terminal of the third D flip-flop inst7; the power-on / off signal is connected to the SET terminal of the fourth D flip-flop inst10, the D terminal of the fourth D flip-flop inst10 is grounded, the CP terminal is connected to the output of the fourth NOT gate inst8, and the Q terminal of the fourth D flip-flop inst10 outputs the power-on or power-off control signal for the second delay circuit.

6. The delay control circuit according to claim 5, characterized in that, The second delay circuit also includes a second RC circuit, which includes a capacitor C2 and a resistor R2. One end of R2 is connected to the power supply VCC, and the other end is connected to one end of the capacitor C2. The other end of the capacitor C2 is grounded, and the connection end of R2 and C2 is connected to the CLR terminal of the third D flip-flop inst7.

7. The delay control circuit according to claim 6, characterized in that, The second delay circuit also includes: I / O ports PORT4 and PORT5. One end of PORT5 is connected to the CLR terminal of the third D flip-flop inst7, and the other end is connected to the connection terminal of the second RC circuit R2 and C2. One end of PORT4 is connected to the Q terminal of the fourth D flip-flop inst10, and the other end serves as the output terminal of the second delay circuit.

8. The delay control circuit according to any one of claims 1-7, characterized in that, The delay control circuit also includes an I / O port PORT1. One end of PORT1 is connected to the input of the first delay circuit and the second delay circuit, and the other end serves as the input of the delay control circuit to receive power-on or power-off signals.

9. The delay control circuit according to claim 2 or 5, characterized in that, The first and second delay circuits are implemented using the hardware description language in CPLD.

10. A pre- and post-stage delay control power converter based on the delay control circuit of any one of claims 1-9, characterized in that, The power converter includes a Buck preamplifier, an LLC power cascade stage, and a delay control circuit. The Buck preamplifier and the LLC power cascade stage each have a power-on / off control port. The power-on / off control signal output by the first delay circuit is input to the power-on / off control port of the Buck preamplifier. The power-on / off control signal output by the second delay circuit is input to the power-on / off control port of the LLC power cascade stage.

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