Multiphase power converter with current balancing

Abstract

A multi-phase power converter with current balancing. An apparatus (200) includes a voltage control circuit (210). A first current control circuit (220) has a first current control circuit input coupled to an output of the voltage control circuit, and has a second current control circuit input. A second current control circuit (222) has a third current control circuit input coupled to an output of the voltage control circuit, and has a fourth current control circuit input. A current balancing circuit (214) has a first current balancing circuit output and a second current balancing circuit output. The first current balancing circuit output is coupled to the second current control circuit input.

Description

Technical Field

[0001] This application relates to electronic devices, and more specifically, to a multiphase power converter with current balancing. Background Technology

[0002] Switching power converters (also known as switching converters) are used in a variety of applications. For example, one application using a switching converter is to power light-emitting diodes (LEDs) that are part of the backlight of a display system within a driver. Some systems that include switching converters are space-constrained, and therefore the space available for the integrated circuits and associated passive components is relatively small. In examples of display systems (e.g., automotive or industrial displays), a relatively small space separate from the display panel itself can be used for a printed circuit board containing integrated circuits and associated passive components that drive the display and the LED backlight. At least one of the integrated circuits (e.g., LED driver integrated circuits) used in the display system includes a switching converter to provide voltage to the LEDs.

[0003] Switching converters contain passive components such as inductors and capacitors. These passive components are located outside the LED driver integrated circuit. Due to space constraints, the size of the passive components in a switching converter can be relatively small. The switching frequency of a switching converter is inversely proportional to the inductance of its inductors. Smaller inductance values ​​(which can be advantageous for saving space because smaller inductors are required) allow the switching converter to operate at relatively high switching frequencies. A suitable choice for switching converters used for high switching frequency operation is an interleaved multiphase switching converter. Summary of the Invention

[0004] In one example, the display system includes a display panel and a plurality of light-emitting diodes (LEDs) arranged relative to the display panel to illuminate the display panel. A voltage control circuit has outputs. A first current control circuit has a first current control circuit input coupled to the output of the voltage control circuit, a second current control circuit input, and a first current control circuit output coupled to at least one of the LEDs. A second current control circuit has a third current control circuit input coupled to the output of the voltage control circuit, a fourth current control circuit input, and a second current control circuit output coupled to the at least one of the LEDs. A current balancing circuit has a first current balancing circuit output and a second current balancing circuit output. The first current balancing circuit output is coupled to the second current control circuit input, and the second current balancing circuit output is coupled to the fourth current control circuit input. The current balancing circuit is configured to generate a first current at the first current balancing circuit output and a second current at the second current balancing circuit output. The first current and the second current are based on the difference between a first average current of the first current control circuit and a second average current of the second current control circuit.

[0005] In another example, a device includes a voltage control circuit. A first current control circuit has a first current control circuit input coupled to the output of the voltage control circuit, and a second current control circuit input. A second current control circuit has a third current control circuit input coupled to the output of the voltage control circuit, and a fourth current control circuit input. A current balancing circuit has a first current balancing circuit output and a second current balancing circuit output. The first current balancing circuit output is coupled to the second current control circuit input. The second current balancing circuit output is coupled to the fourth current control circuit input. The current balancing circuit generates a first current and a second current. The first current and the second current are based on the difference between a first average current of the first current control circuit and a second average current of the second current control circuit.

[0006] In another example, a device includes a first current control circuit having a first transistor. The first current control circuit has a first clock input, a first error current input, a first current balancing input, and a first output. The first current control circuit is configured to combine a first error current from the first error current input with a first balancing current from the first current balancing input to generate a first reference current, and to change the state of the first transistor in response to a first current through the first transistor reaching the first reference current. A second current control circuit has a second transistor. The second current control circuit has a second clock input, a second error current input, a second current balancing input, and a second output. The second current control circuit is configured to combine a second error current from the second error current input with a second balancing current from the second current balancing input to generate a second reference current, and to change the state of the second transistor in response to a second current through the second transistor reaching the second reference current. The current balancing circuit has a first input, a second input, a first current output, and a second current output. The first input is coupled to the first output. The second input is coupled to the second output. The first current output is coupled to the first current balancing input, and the second current output is coupled to the second current balancing input. The current balancing circuit can be configured to generate a first balancing current at the first current output and a second balancing current at the second current output in response to the difference between the first current and the second current. Attached Figure Description

[0007] Figure 1 This is a system diagram of the display system in the example.

[0008] Figure 2 It is the example used for driving. Figure 1 A schematic diagram of a multiphase boost converter for LED backlighting in a display system.

[0009] Figure 3 In the example Figure 2 A schematic diagram of the current balancing circuit in a multiphase boost converter.

[0010] Figure 4 The waveforms show the operation of the current balancing circuit in the example at a duty cycle greater than 50%.

[0011] Figure 5 The waveforms show the operation of the current balancing circuit in the example at a duty cycle of less than 50%.

[0012] Figure 6 In the example Figure 2 A schematic diagram of the current control circuit inside a multiphase boost converter. Detailed Implementation

[0013] The same reference numerals or other reference indicators are used in the accompanying drawings to denote the same or similar features (by function and / or structure).

[0014] For a multiphase switching converter to operate correctly, power dissipation and thermal performance must be balanced between its phases. Some multiphase switching converters can be fine-tuned to account for process variations within the integrated circuit containing the converter. However, fine-tuning cannot account for variations in external components of the integrated circuit, such as external inductors. The examples described herein relate to multiphase switching converters that dynamically adjust the current through each phase such that the average current within each phase is approximately equal.

[0015] Figure 1 This is a diagram of an example display system 100. The display system 100 includes a display panel 110, a diffuser and light guide 115, a direct-lit backlight system 120a (or an edge-lit backlight system 120b), and a printed circuit board (PCB) 130. The display panel 110 includes one or more components, such as a front layer 110a with a contrast coating, a polarizing film 110b, a color filter 110c, a liquid crystal 110d, a thin-film transistor 110e, and a polarizing film 110f. The backlight system 120a (or 120b) includes one or more light-emitting diodes (LEDs) 122 arranged relative to the display panel 110, which provide backlighting for the display system. The PCB 130 includes one or more integrated circuits (ICs), such as a timing controller 131, a liquid crystal display (LCD) bias circuit 132, a gamma buffer 133, a level shifter 134, and an LED driver 135. Passive components such as inductors, resistors, and capacitors are also disposed on the PCB 130. PCB 130 can be set along the periphery of the display system, but it can provide very little space for the PCB.

[0016] LED driver 135 may include a switching converter, such as a boost switching converter, to supply voltage to LED 122. In one example, LED driver 135 can control the brightness level of light generated by LED 122 by controlling the average current through the LED. In one example, LED driver 135 responds to a PWM dimming signal (PWM_DIMMING, as described below) by turning on LED 122 when the PWM dimming signal is in a first logic state (e.g., logic high) and turning off LED 122 when the PWM dimming signal is in a second logic state (e.g., logic low). The frequency of the PWM dimming signal is faster than the frequency response of the human eye, and therefore no flicker is perceptible to humans. The intensity of light generated by the flickering LED 122 detected by the human eye is a function of the duty cycle of the PWM dimming signal.

[0017] As described above, the limited space available on PCB 130 allows for relatively small inductors on the PCB, resulting in relatively small inductance values. Due to the smaller inductance values, the switch converter on LED driver 135 can be configured to have a relatively high switching frequency. In some instances, the switch converter is a multiphase switch converter, such as a multiphase boost converter, a multiphase buck converter, or a multiphase buck-boost converter. Such a switch converter has two or more phases.

[0018] Figure 2 It is possible Figure 1 A circuit diagram of a multiphase boost converter 200 used in an LED driver 135 is shown. The multiphase boost converter 200 includes voltage control circuitry 210, current control circuitry 220 and 222, current balancing circuitry 214, resistors R1, R2, and R3, capacitor C1, inductors L1 and L2, and diodes D1 and D2. In one example, voltage control circuitry 210, current control circuitry 220 and 222, and current balancing circuitry 214 are disposed on integrated circuit 208, while resistors R1-R3, capacitor C1, inductors L1 and L2, and diodes D1 and D2 are disposed externally to integrated circuit 208. Integrated circuit 208 and resistors R1-R3, capacitor C1, inductors L1 and L2, and diodes D1 and D2 can be mounted on a printed circuit board or other suitable connection structure. Integrated circuit 208 has externally accessible terminals, such as switching terminals 208a and 208b, compensation terminal 208c, and feedback terminal 208d. The input voltage VIN is provided to the input voltage terminal 201 of the boost converter 200, and the output voltage VOUT is provided at the output voltage terminal 202 coupled to one or more series-connected LED strings 122. Resistors R1 and R2 are coupled in series between the output voltage terminal 202 and ground, and provide a voltage divider feedback voltage VFB.

[0019] Voltage control circuit 210 includes amplifier 212 (e.g., transconductance amplifier), voltage-to-current (V2I) converter 216, and clock and slope generator 218. Amplifier 212 has inputs 212a and 212b and an output 212c. A reference voltage (e.g., from a reference voltage generation circuit) is provided to input 212. A feedback voltage VFB is provided to input 212b via feedback terminal 208d of integrated circuit 208. Amplifier 212 generates an output error signal at its output 212c based on the difference between the reference voltage REF and the feedback voltage VFB. Output 212c of amplifier 212 is coupled to input 216a of V2I converter 216. Resistor R3 and capacitor C1 are coupled in series between compensation terminal 208c and ground. Output 212c of amplifier 212 is coupled to compensation terminal 208c. V2I converter 216 has an output 216b. V2I converter 216 converts the error signal from amplifier 212 into an error current.

[0020] exist Figure 2 In this example, the multiphase boost converter 200 is a two-phase boost converter and therefore has two current control circuits 220 and 222—one current control circuit for each phase. Current control circuit 220 has inputs 220a, 220b, 220c, and 220d and an output 220e. Similarly, control circuit 222 has inputs 222a, 222b, 222c, and 222d and an output 222e. Each current control circuit 220, 222 also receives a PWM_DIMMING signal, as described above. Current balancing circuit 214 has inputs 214a and 214b and outputs 214c and 214d. Clock and slope generator 218 has outputs 218a, 218b, 218c, and 218d. Inputs 214a and 214b of current balancing circuit 214 are coupled to switching terminals SW_P 208a and SW_S 208b, respectively. The outputs 214c and 214d of the current balancing circuit 214 are coupled to the inputs 220b and 222b of the current control circuits 220 and 222, respectively. The output 216b of the V2I converter 216 is coupled to the inputs 220a and 222a of the current control circuits 220 and 222, respectively. The outputs 218a and 218b of the clock and slope generator 218 are coupled to the inputs 220d and 222d of the current control circuits 220 and 222, respectively. The outputs 218c and 218d of the clock and slope generator 218 are coupled to the inputs 220c and 222c of the current control circuits 220 and 222, respectively.

[0021] The clock and slope generator 218 generates clock signals (clock) CLOCKP and CLOCKS for the corresponding current control circuits 220 and 222 at its outputs 218a and 218b. For a two-phase boost converter, as in... Figure 2In this example, CLOCKP and CLOCKS are approximately 180 degrees out of phase with respect to each other. The clock and slope generator 218 also generates slope compensation currents ISLOPE_P and ISLOPE_S at its outputs 218c and 218d for the corresponding current control circuits 220 and 222.

[0022] The error current from V2I converter 216 is provided as error currents IEA_P and IEA_S to inputs 220a and 222a of current control circuits 220 and 222, respectively. As described below, current balancing circuit 214 generates current balancing currents ICB_P and ICB_S for current control circuits 220 and 222 to help balance the average current through the current control circuits. Integrated circuit 208 has switching terminals SW_P 210a and SW_S 210b, which are externally accessible terminals of the integrated circuit. The output 220e of current control circuit 220 is coupled to switching terminal SW_P 208a, and the output 222e of current control circuit 222 is coupled to switching terminal SW_S 208b. One terminal of inductor L1 is coupled to input voltage terminal 201, and the other terminal of inductor L1 is coupled to the anode of diode D1 and to switching terminal SW_P 208a. One terminal of inductor L2 is also coupled to input voltage terminal 201, and the other terminal of inductor L2 is coupled to the anode of diode D2 and to switch terminal SW_S208b. The cathodes of diodes D1 and D2 are coupled together and to output voltage terminal 202.

[0023] Current control circuits 220 and 222 contain transistors (described below) Figure 6 As shown in the diagram, the transistors are turned on and off to regulate the current to a load (e.g., LED 122). In one example, the transistors of current control circuits 220 and 222 are turned on according to corresponding clocks CLOCK_P / CLOCK_S. For example, the rising edge of clock CLOCK_P turns on the transistor in current control circuit 220, and the rising edge of clock CLOCK_S turns on the transistor in current control circuit 222. In this example, the multiphase boost converter 200 is a peak current mode controlled boost converter. Each current control circuit 220, 222 includes circuitry (e.g., a comparator) for detecting when the current through the corresponding transistor reaches a peak reference current. When the current through the transistor reaches the peak reference current, the current control circuits 220, 222 turn off the transistor. Therefore, the transistors of each current control circuit 220, 222 are turned on in response to clocks CLOCK_P / CLOCK_S and turned off in response to the current through the transistor reaching the peak reference current.

[0024] Each current control circuit 220, 222 generates its peak reference current based at least in part on the charge balance current (ICB_P / ICB_S), the error current (IEA_P / IEA_S), and the slope compensation current (ISLOPE_P / ISLOPE_S). The charge balance circuit 214 senses the current passing through the transistors of the current control circuits 220 and 222 and determines the average value of these currents. Based on the difference between the average currents of the current control circuits 220 and 222, the charge balance circuit 214 generates charge balance currents ICB_P and ICB_S to iteratively adjust the peak reference currents of the current control circuits 220 and 222, thereby making the average transistor currents approximately equal.

[0025] Figure 3 This is a schematic diagram of an example charge balancing circuit 214. In this example, the charge balancing circuit 214 includes inverters 314 and 317, filters 315 and 325, amplifiers 316, 326, 330 and 340, a reference voltage circuit 344, logic circuit 350, and a power-on reset (POR) circuit 370, as well as switches SW22, SW32, SW41 and SW42 (e.g., transistors). Figure 3 In the examples, transistors 316, 326, 330, and 340 are transconductance amplifiers.

[0026] Input 214a is coupled to one terminal of switch SW21, and the other terminal of switch SW21 is coupled to terminal 315a of filter 315. The ground reference PGND_P for current control circuit 220 is coupled to terminal 315b of filter 315. The voltage difference between input 214a (SW_P) and PGND_P represents the current flowing through the transistor in current control circuit 220. Opposite terminals of switch SW22 are coupled to terminals 315a and 315b, respectively. Filter 315 includes resistors R21 and R22 forming a passive low-pass filter and capacitor C21. Opposite terminals of resistor R21 are coupled to terminals 315a and 315c of filter 315. Similarly, opposite terminals of resistor R22 are coupled to terminals 315b and 315d of filter 315. Opposite terminals of capacitor C21 are coupled to terminals 315c and 315d, respectively. Terminals 315c and 315d of filter 315 are coupled to the positive (+) and negative (-) inputs of amplifier 330, respectively.

[0027] Input 214b is coupled to one terminal of switch SW31, and the other terminal of switch SW31 is coupled to terminal 325a of filter 325. The ground reference PGND_S for current control circuit 222 is coupled to terminal 325b of filter 325. The voltage difference between input 214b (SW_S) and PGND_S represents the current flowing through the transistor of current control circuit 222 (e.g., proportional to the stated current). Opposite terminals of switch SW32 are coupled to terminals 325a and 325b, respectively. Filter 325 includes resistors R31 and R32 and capacitor C31, forming a passive low-pass filter. Opposite terminals of resistor R31 are coupled to terminals 325a and 325c of filter 325. Similarly, opposite terminals of resistor R32 are coupled to terminals 325b and 325d of filter 325. Opposite terminals of capacitor C31 are coupled to terminals 325c and 325d, respectively. Terminals 325c and 325d of filter 325 are coupled to the positive and negative inputs of amplifier 326, respectively.

[0028] The output of amplifier 330 is coupled to terminal SW41a of switch SW41, and the other terminal SW41b of switch SW41 is coupled to the positive input of amplifier 340, terminal of capacitor C41, and terminal SW42a of switch SW42. The other terminal of capacitor C41 is coupled to ground. Terminal SW42b of switch SW42 is coupled to the negative input of amplifier 340 and the output of reference voltage circuit 344. Reference voltage circuit 344 generates a reference voltage REF for the negative input of amplifier 340 at its output. When switch SW42 is closed, capacitor C41 is charged to the level of reference voltage REF. A POR circuit 370, which may include a single-trigger circuit, closes switch SW42 for a short period of time (e.g., one microsecond) during a power-on reset event, initially charging capacitor C41 to the reference voltage to help ensure a valid start-up condition for the multiphase boost converter. For the remainder of the multiphase boost converter 200's operation, switch SW42 is open. Amplifier 340 has both a negative and a positive output. The negative output is coupled to output 214c and provides current ICB_P. The positive output is coupled to output 214d and provides current ICB_S.

[0029] Logic circuit 350 includes output signals S0 and S1, which control the on / off states of switches SW21, SW22, SW31, and SW32. Signal S0 controls the on / off state of switch SW21 and, via inverter 314, controls the on / off state of switch SW22. Signal S1 controls the on / off state of switch SW31 and, via inverter 317, controls the on / off state of switch SW32. When signal S0 is in a first logic state (e.g., logic high), filter 315 is enabled, causing switch SW21 to close (conduct) and switch SW22 to open (off). When signal S0 is in a second logic state (e.g., logic low), filter 315 is disabled, causing switch SW21 to open (off) and switch SW22 to close (conduct). When signal S1 is in a first logic state (e.g., logic high), filter 325 is enabled, causing switch SW31 to close (conduct) and switch SW32 to open (off). When signal S1 is in the second logic state (e.g., logic low), filter 325 is disabled, causing switch SW31 to open (turn off) and switch SW32 to close (turn on).

[0030] When filter 315 is enabled, it performs a low-pass filter on its input signals SW_P_PGND_P at its output signal VCS_P_VGND_P. Due to the low-pass operation of filter 315, the output signal VCS_P_VGND_P represents the average value of the current flowing through the transistor in current control circuit 220. When filter 325 is enabled, it performs a low-pass filter on its input signals SW_S_PGND_S at its output signal VCS_S_VGND_S. Due to the low-pass operation of filter 325, the output signal VCS_S_VGND_S represents the average value of the current flowing through the transistor in current control circuit 222.

[0031] Amplifier 316 amplifies the difference between VCS_P and VGND_P into a single-ended signal V_AVGC_P. Amplifier 326 amplifies the difference between VCS_S and VGND_S into a single-ended signal V_AVGC_S. Amplifier 330 amplifies the difference between V_AVGC_P and V_AVGC_S. The difference between AVGC_P and V_AVGC_S represents an error signal indicating the difference in the average current flowing through current control circuits 220 and 222.

[0032] The PWM_DIMMING control switches SW41 to open / close. When SW41 is closed, the error signal from amplifier 330 is provided to the positive input of amplifier 330. Amplifier 330 amplifies the difference between the error signal and the reference voltage from reference voltage circuit 344. When the error signal becomes more positive than the reference voltage, the current ICB_S from amplifier 340 increases and the current ICB_P decreases. When the error signal becomes more negative than the reference voltage, the current ICB_P from amplifier 340 increases and the current ICB_S decreases. The currents ICB_P and ICB_S control the peak current references of current control circuits 220 and 222, as described below.

[0033] With switch SW42 open, capacitor C41 is charged to the error signal from amplifier 330 when switch SW41 is closed. Then, when PWM_DIMMING is logic low and switch SW41 is open, the voltage across capacitor C41 can be used as the positive input of amplifier 340. By maintaining the voltage to the positive input of amplifier 340 at the level of the error signal when PWM_DIMMING goes low, the multiphase boost converter 200 can re-establish regulation faster than if capacitor C41 were not present.

[0034] After the transistor in the current control circuit 220 turns on and off, voltage ringing may occur at the corresponding switch terminal 208a. This short period depends, for example, on the rate of increase of the current through the transistor. Similarly, after the transistor in the current control circuit 222 turns on and off, voltage ringing may occur at the corresponding switch terminal 208b. During the switching terminal ringing period, attempting to sense the current through the corresponding transistor may be inaccurate. Therefore, the logic circuit 350 implements a blanking period during such ringing periods, during which one or the other of filters 315 and 325 is disabled.

[0035] In this example, logic circuit 350 includes NOR gates 352 and 354, and AND gates 356 and 358. NOR gate 352 has inputs 352a, 352b, and 352c. Input 352a receives the signal ON_BLANK_P. Input 352b receives the signal ON_BLANK_S. Input 352c receives the signal OFF_BLANK_S. The following description... Figure 6Examples of how to generate signals ON_BLANK_P, ON_BLANK_S, and OFF_BLANK_S are provided. Signal ON_BLANK_P is a pulse (e.g., a positive pulse) that begins in response to the turn-on of a transistor in current control circuit 220 and lasts for a sufficiently long period (blank period) approximately equal to the duration of ringing at switch terminal 208a. Signal ON_BLANK_S is a pulse that begins in response to the turn-on of a transistor in current control circuit 222 and lasts for a blank period approximately equal to the duration of ringing at switch terminal 208b. Signal OFF_BLANK_S is a pulse that begins in response to the turn-off of a transistor in current control circuit 222 and lasts for a blank period approximately equal to the duration of ringing at switch terminal 208b. Therefore, the output signal from NOR gate 352 is logic high only when signals ON_BLANK_P, ON_BLANK_S, and OFF_BLANK_S are not logic high. In other words, if the blanking period does not occur when the transistor in the current control circuit 220 is turned on or when the transistor in the current control circuit 222 is turned on or off, the output signal from the NOR gate 352 is logic high.

[0036] NOR gate 354 has inputs 354a, 354b, and 354c. Input 354a receives the signal ON_BLANK_S. Input 354b receives the signal ON_BLANK_P. Input 354c receives the signal OFF_BLANK_P. The signal ON_BLANK_S is a pulse that begins in response to the turn-on of the transistor in current control circuit 222 and lasts for a blanking period approximately equal to the duration of ringing at switch terminal 208b. The signal ON_BLANK_P is a pulse that begins in response to the turn-on of the transistor in current control circuit 220 and lasts for a blanking period approximately equal to the duration of ringing at switch terminal 208a. The signal OFF_BLANK_P is a pulse that begins in response to the turn-off of the transistor in current control circuit 220 and lasts for a blanking period approximately equal to the duration of ringing at switch terminal 208a. Therefore, the output signal from NOR gate 354 is logic high only when none of the signals ON_BLANK_S, ON_BLANK_P, and OFF_BLANK_P are logic high. In other words, the output signal from NOR gate 354 is logic high if the blanking period does not occur when the transistor in current control circuit 222 is turned on or when the transistor in current control circuit 220 is turned on or off.

[0037] AND gate 356 has inputs 356a and 356b. Input 356a is coupled to the output of NOR gate 352. Input 356b receives the signal ISON_P, as described below. Figure 6As described, the signal is a signal that controls the on and off states of the transistor in the current control circuit 220. In one example, a logic high ISON_P signal turns the transistor on, and a logic low ISON_P signal turns the transistor off. The AND gate 356 performs a logical AND operation on the output signal from the NOR gate 352 and the signal ISON_P as signal S0, thereby enabling the filter 315 when the transistor in the current control circuit 220 is on and the aforementioned blanking period associated with the NOR gate 352 does not occur.

[0038] The AND gate 358 has inputs 358a and 358b. Input 358a is coupled to the output of the NOR gate 354. Input 358b receives the signal ISON_S, as described below. Figure 6 As described, the signal is a signal that controls the on and off states of the transistor in the current control circuit 222. In one example, a logic high ISON_S signal turns the transistor on, and a logic low ISON_S signal turns the transistor off. The AND gate 358 performs a logical AND operation on the output signal from the NOR gate 354 and the signal ISON_S, which is signal S1, thereby enabling the filter 325 when the transistor in the current control circuit 222 is on and the aforementioned blanking period associated with the NOR gate 354 does not occur.

[0039] Figure 4 This is a timing diagram illustrating an example of the operation of a current balancing circuit 214 with a duty cycle greater than 50% for a multiphase boost converter 200. Figure 4 The signals shown in the example include SW_P, ISON_P, ON_BLANK_P, OFF_BLANK_P, S0, SW_S, ISON_S, ON_BLANK_S, OFF_BLANK_S, and S1. Signals SW_P and SW_S represent the voltages on switch terminals 208a and 208b when the corresponding transistors within current control circuits 220 and 222 are turned on. Because the duty cycle is greater than 50% in this example, signals ISON_P and ISON_S overlap to some extent (e.g., both are logic high for a portion of each switching cycle). Signals ON_BLANK_P and OFF_BLANK_P remain high for a short period during the blanking period following the corresponding rising edge 420 and falling edge 423 of signal ISON_P (e.g., pulses 421 and 422). Signals ON_BLANK_S and OFF_BLANK_S also remain high for a short period of time during the blanking period following the corresponding rising and falling edges of signal ISON_S (e.g., pulses 431 and 432).

[0040] When signal ISON_P is logic high and the blanking periods defined by the pulses on signals ON_BLANK_P, ON_BLANK_S, and OFF_BLANK_S do not occur, signal S0 is logic high at 424. Similarly, when signal ISON_P is logic high and the blanking periods defined by the pulses on signals ON_BLANK_P, ON_BLANK_S, and OFF_BLANK_S do not occur, signal S1 is logic high at 434.

[0041] Figure 5 This is a timing diagram illustrating an example of the operation of a current balancing circuit 214 with a duty cycle of less than 50% for a multiphase boost converter 200. Figure 5 The same signals are shown in the example. Signals ISON_P and ISON_S do not overlap when the duty cycle is less than 50%. Therefore, when signal ISON_P is logic high, only one blanking period occurs, namely pulse 521 of signal ON_BLANK_P. Therefore, signal S0 becomes logic high in response to the falling edge 521a of pulse 521 and remains logic high until the subsequent falling edge 522 of signal ISON_P. Similarly, when signal ISON_S is logic high, only one blanking period occurs, namely pulse 531 of signal ON_BLANK_S. Therefore, signal S1 becomes logic high in response to the falling edge 531a of pulse 531 and remains logic high until the subsequent falling edge 532 of signal ISON_P.

[0042] Figure 6This is a circuit diagram illustrating an example of current control circuit 220. Current control circuit 222 can be implemented as a similar circuit. Current control circuit 220 includes a current adder 602, resistor RSNS, comparator 610, set (S)-reset (R) trigger 612, AND gate 614, single trigger circuits 620 and 622, and transistor M1. Transistor M1 (e.g., an n-channel field-effect transistor) is the transistor mentioned above regarding current control circuit 220. The drain of transistor M1 is coupled to switch terminal 208a, and the source is coupled to ground. Currents ICB_P, IEA_P, and ISLOPE_P are added together at current adder 602, and the added current IREF then flows through resistor RSNS. The voltage across resistor RSNS is proportional to the sum of currents ICB_P, IEA_P, and ISLOPE_P. One terminal of resistor RSNS is coupled to the negative input of comparator 610. Switch terminal 208a is coupled to the positive input of comparator 610. The SR flip-flop has an R input, an S input, and a Q output. The output of comparator 610 is coupled to the R input. CLOCK_P is provided to the S input. When the signal from comparator 610 is logic high, the SR flip-flop 612 is reset and its Q output becomes logic low. When CLOCK_P is logic high, the SR flip-flop 612 is set and its Q output becomes logic high. AND gate 614 has an input 614a coupled to the Q output of SR flip-flop 612 and an input 614b that receives the PWM_DIMMING signal. When both the PWM_DIMMING signal and the Q output are logic high, the AND gate generates its output signal ISON_P to a logic high state, thereby turning on transistor M1. When PWM_DIMMING is logic high, transistor M1 repeatedly turns on and off during each switching cycle of the multiphase boost converter 200. In response to the rising edge of CLOCK_P, the SR flip-flop is set, and the signal ISON_P goes high, turning on transistor M1. With transistor M1 on, the current I_M1 through it increases. Eventually, the current I_M1 reaches the level of IREF, at which point comparator 610 sets its output to high, resetting the SR flip-flop 612. In response to the SR flip-flop being reset, the output signal ISON_P from the AND gate 614 goes low, turning off transistor M1. This process is repeated when PWM_DIMMING is high. When PWM_DIMMING is low, transistor M1 is turned off.

[0043] The current IREF is partially proportional to the current ICB_P. The current IREF represents the peak current reference of the current control circuit 220. By adjusting the current IREF in the current control circuit 220 and the corresponding current IREF in the current control circuit 222, the peak current reference of the phase is iteratively adjusted to advantageously maintain the average current through transistor M1 in the current control circuit 220 approximately equal to the average current through the corresponding transistor in the current control circuit 222.

[0044] Single-trigger circuit 620 has an input coupled to the output of AND gate 614. Similarly, single-trigger circuit 622 has an input coupled to the output of AND gate 614. The input of single-trigger circuit 622 is inverted relative to the input of single-trigger circuit 620. Single-trigger circuit 620 generates a pulse as ON_BLANK_P in response to the rising edge of ISON_P. Single-trigger circuit 622 generates a pulse as OFF_BLANK_P in response to the falling edge of ISON_P. As described above, the duration of the single-trigger pulse is set long enough to approximately equal the ringing time at the corresponding switch terminal.

[0045] In this description, the term "coupled" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0046] Any switch described herein can be implemented as a transistor. Furthermore, in this specification, the phrase "based on" means "at least partially based on". Therefore, if X is based on Y, then X can depend on Y and any number of other factors.

[0047] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Such configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or through a combination thereof.

[0048] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0049] The circuits or devices described herein as containing certain components may be practically adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacturing, for example by an end user and / or a third party, to form the described structure.

[0050] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuit system. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0051] Reference may be made to the control input and current terminals of the transistor in the claims. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter. The gate, source, and drain of an FET, and the base, collector, and emitter of a BJT, are the terminals of a transistor.

[0052] In this document, the reference to "FET on" or "enabled" means that a conductive channel exists in the FET and drain current can flow through it. The reference to "FET off" or "disabled" means that no conductive channel exists, and therefore drain current does not flow through the FET. However, a "disabled" FET can have current flowing through the body diode of the transistor.

[0053] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, a component shown as a resistor generally represents one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0054] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as external to the integrated circuit may be contained within the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0055] The use of the phrase "ground" in the foregoing description includes chassis ground, earth, floating ground, virtual ground, digital ground, public ground, and / or any other form of ground connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0056] Within the scope of the claims, modifications may be made to the described examples, and other examples are also possible.

Claims

1. A display system comprising: Display panel; Multiple light-emitting diodes (LEDs) are arranged relative to the display panel to illuminate the display panel; as well as Voltage control circuit, which has an output; A first current control circuit has a first current control circuit input coupled to the output of the voltage control circuit, a second current control circuit input, and a first current control circuit output coupled to at least one of the LEDs. The second current control circuit has a third current control circuit input coupled to the output of the voltage control circuit, a fourth current control circuit input, and a second current control circuit output coupled to at least one of the LEDs. as well as A current balancing circuit having a first current balancing circuit output and a second current balancing circuit output, the first current balancing circuit output being coupled to a second current control circuit input, and the second current balancing circuit output being coupled to a fourth current control circuit input, the current balancing circuit being configurable to generate a first current at the first current balancing circuit output and a second current at the second current balancing circuit output, the first current and the second current being based on the difference between a first average current of the first current control circuit and a second average current of the second current control circuit.

2. The display system according to claim 1, wherein: The first current control circuit can be configured to adjust the first reference current based on the current from the output of the voltage control circuit and the first current; and The second current control circuit can be configured to adjust the second reference current based on the current from the output of the voltage control circuit and the second current.

3. The display system according to claim 2, wherein: The first current control circuit can be configured to generate the first reference current by summing the current from the output of the voltage control circuit and the first current; and The second current control circuit can be configured to generate the second reference current by summing the current from the output of the voltage control circuit and the second current.

4. The display system according to claim 1, wherein the current balancing circuit comprises: A first low-pass filter having a first low-pass filter output and configurable to low-pass filter a first current sensing signal to generate a first filtered signal at the first low-pass filter output. A second low-pass filter having a second low-pass filter output and configurable to low-pass filter a second current sensing signal to generate a second filtered signal at the output of the second low-pass filter. as well as A first amplifier has a first amplifier input coupled to the output of the first low-pass filter and a second amplifier input coupled to the output of the second low-pass filter.

5. The display system of claim 4, wherein the first current control circuit comprises a first transistor, the second current control circuit comprises a second transistor, and wherein: The first low-pass filter can be configured to be disabled during a first blanking period after the first transistor is turned on; and The second low-pass filter can be configured to be disabled during a third blanking period after the second transistor is turned on.

6. The display system of claim 4, wherein the first current control circuit comprises a first transistor, the second current control circuit comprises a second transistor, and wherein: The first low-pass filter can be configured to be disabled during a first blanking period after the first transistor is turned on, a second blanking period after the second transistor is turned off, and a third blanking period after the second transistor is turned on; and The second low-pass filter can be configured to be disabled during a fourth blanking period after the second transistor is turned on, a fifth blanking period after the first transistor is turned off, and a sixth blanking period after the first transistor is turned on.

7. The display system according to claim 4, wherein: The first low-pass filter includes a first resistor coupled to a first capacitor; and The second low-pass filter includes a second resistor coupled to the second capacitor.

8. The display system of claim 4, wherein the first amplifier has a first amplifier output, and the display system further comprises: A switch having a first switch terminal coupled to the output of the first amplifier and having a second switch terminal; The second amplifier has a second amplifier input coupled to the second switch terminal and a third amplifier input; A reference voltage circuit is coupled to the input of the third amplifier; as well as A capacitor having capacitor terminals coupled to the second switch terminal.

9. An apparatus comprising: Voltage control circuit, which has an output; A first current control circuit has a first current control circuit input coupled to the output of the voltage control circuit and a second current control circuit input; The second current control circuit has a third current control circuit input coupled to the output of the voltage control circuit and a fourth current control circuit input. as well as A current balancing circuit having a first current balancing circuit output and a second current balancing circuit output, the first current balancing circuit output being coupled to a second current control circuit input, and the second current balancing circuit output being coupled to a fourth current control circuit input, the current balancing circuit being configurable to generate a first current at the first current balancing circuit output and a second current at the second current balancing circuit output, the first current and the second current being based on the difference between a first average current of the first current control circuit and a second average current of the second current control circuit.

10. The device according to claim 9, wherein: The first current control circuit can be configured to adjust the first reference current based on the current from the output of the voltage control circuit and the first current; and The second current control circuit can be configured to adjust the second reference current based on the current from the output of the voltage control circuit and the second current.

11. The device according to claim 10, wherein: The first current control circuit can be configured to generate the first reference current by summing the current from the output of the voltage control circuit and the first current; and The second current control circuit can be configured to generate the second reference current by summing the current from the output of the voltage control circuit and the second current.

12. The device of claim 9, wherein the current balancing circuit comprises: A first low-pass filter having a first low-pass filter output and configurable to low-pass filter a first current sensing signal to generate a first filtered signal at the first low-pass filter output. A second low-pass filter having a second low-pass filter output and configurable to low-pass filter a second current sensing signal to generate a second filtered signal at the output of the second low-pass filter. as well as A first amplifier has a first amplifier input coupled to the output of the first low-pass filter and a second amplifier input coupled to the output of the second low-pass filter.

13. The device of claim 12, wherein the first current control circuit comprises a first transistor, the second current control circuit comprises a second transistor, and wherein: The first low-pass filter can be configured to be disabled during a first blanking period after the first transistor is turned on; and The second low-pass filter can be configured to be disabled during a third blanking period after the second transistor is turned on.

14. The device of claim 12, wherein the first current control circuit comprises a first transistor, the second current control circuit comprises a second transistor, and wherein: The first low-pass filter can be configured to be disabled during a first blanking period after the first transistor is turned on, a second blanking period after the second transistor is turned off, and a third blanking period after the second transistor is turned on; and The second low-pass filter can be configured to be disabled during a fourth blanking period after the second transistor is turned on, a fifth blanking period after the first transistor is turned off, and a sixth blanking period after the first transistor is turned on.

15. The device according to claim 12, wherein: The first low-pass filter includes a first resistor coupled to a first capacitor; and The second low-pass filter includes a second resistor coupled to the second capacitor.

16. The device of claim 12, wherein the first amplifier has a first amplifier output, and the device further comprises: A switch having a first switch terminal coupled to the output of the first amplifier and having a second switch terminal; The second amplifier has a second amplifier input coupled to the second switch terminal and a third amplifier input; A reference voltage circuit is coupled to the input of the third amplifier; as well as A capacitor having capacitor terminals coupled to the second switch terminal.

17. An apparatus comprising: A first current control circuit has a first transistor, a first clock input, a first error current input, a first current balance input, and a first output. The first current control circuit is configured to combine a first error current from the first error current input with a first balance current from the first current balance input to generate a first reference current, and to change the state of the first transistor in response to the first current through the first transistor reaching the first reference current. The second current control circuit has a second transistor, a second clock input, a second error current input, a second current balance input, and a second output. The second current control circuit is configured to combine a second error current from the second error current input with a second balance current from the second current balance input to generate a second reference current, and to change the state of the second transistor in response to the second current through the second transistor reaching the second reference current. as well as A current balancing circuit has a first input, a second input, a first current output, and a second current output, the first input being coupled to the first output, the second input being coupled to the second output, the first current output being coupled to the first current balancing input, and the second current output being coupled to the second current balancing input. The current balancing circuit can be configured to generate a first balancing current at the first current output and a second balancing current at the second current output in response to the difference between the first current and the second current.

18. The device of claim 17, wherein the current balancing circuit is configured to generate the first balancing current and the second balancing current in response to the difference between the average value of the first current and the average value of the second current.

19. The apparatus according to claim 17, wherein: The first current control circuit can be configured to combine the first error current and the first balance current by summing the first error current and the first balance current; and The second current control circuit can be configured to combine the second error current with the second balance current by summing the second error current with the second balance current.

20. The device of claim 17, wherein the current balancing circuit includes a first amplifier configured to generate a first signal at the output of the first amplifier, the first signal indicating the difference between the first current and the second current, and the first current control circuit further includes a first capacitor coupled to the output of the first amplifier via a first switch, the first capacitor being configured to maintain a voltage from the output of the first amplifier in response to the closing of the first switch.

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