A supply voltage selection circuit for a wide input range switching converter

Abstract

The application discloses a power supply voltage selection circuit for a wide input range switching converter, and belongs to the field of power management integrated circuits. The circuit comprises: a pre-stabilization circuit for adaptively selecting the higher one of an output voltage VOUT and an input voltage VIN as an internal high-voltage power supply VM; an internal power supply generation circuit for generating an internal low-voltage power supply VDD; a voltage rail generation circuit for generating a voltage rail VMSUB5V which is 5V lower than VM; a comparison circuit for comparing the sizes of VIN and VOUT in a low-voltage domain and generating a flag signal; a level shift circuit for converting the low-voltage domain flag signal into a high-voltage domain indication signal with VM and VMSUB5V as voltage rails; and an output stage for conducting the higher one of VIN and VOUT to an output end VMAX according to the high-voltage domain indication signal. The application has a wide working voltage range, high comparison accuracy, low static power consumption, and all devices are in a safe working area, and has a high application value.

Description

Technical Field

[0001] This invention belongs to the field of power management integrated circuit technology, and specifically relates to a power supply voltage selection circuit for a wide input range switching converter. Background Technology

[0002] In wide-input-range switching converters, internal control circuits and gate drive circuits require a relatively stable supply voltage. However, since the input and output voltages of a switching converter can vary over a wide range, and their relative voltage magnitudes are not fixed under different operating modes, reliably supplying power to the internal circuits across the entire operating range while outputting the higher of the two voltages without loss is a core challenge in power management integrated circuit design. Therefore, an integrated circuit solution is needed that can automatically select and output the supply voltage with high precision and high reliability over a wide input high-voltage range without requiring an external auxiliary power supply. Summary of the Invention

[0003] This invention addresses the problems existing in the prior art by providing a power supply voltage selection circuit for a wide input range switching converter. When the input voltage and output voltage change, the circuit can compare the magnitudes of the two and select the higher of the input and output voltages as the power supply voltage. This mainly solves the problems of existing power supply selection circuits being unsuitable for wide input high voltage scenarios, having poor device reliability, low accuracy, or low integration.

[0004] To solve the above technical problems, the present invention provides the following technical solution: a power supply voltage selection circuit for a wide input range switching converter, comprising a pre-regulation circuit, an internal power generation circuit, a voltage rail generation circuit, a comparator circuit, a level shifting circuit, and an output stage.

[0005] The pre-regulator circuit is connected to the output voltage VOUT and the input voltage VIN of the switching converter at its input terminal, and adaptively selects the higher of the output voltage VOUT and the input voltage VIN as the high voltage power supply VM inside the circuit.

[0006] The internal power generation circuit receives the internal high-voltage power supply VM and generates an internal low-voltage power supply VDD.

[0007] The voltage rail generation circuit receives the internal high-voltage power supply VM and is used to generate a voltage rail VMSUB5V that is 5V lower than the internal high-voltage power supply VM.

[0008] The comparator circuit receives the input voltage VIN and the output voltage VOUT and compares their magnitudes to generate an input voltage high voltage flag signal A_B and an output voltage high voltage flag signal A in the low voltage domain.

[0009] The level shifting circuit receives the input voltage high voltage flag signal A_B and the output voltage high voltage flag signal A and converts them into an input voltage high voltage indication signal VIH and an output voltage high voltage indication signal VOH with VM and VMSUB5V as voltage rails in the high voltage domain.

[0010] The output stage receives the input voltage high voltage indication signal VIH and the output voltage high voltage indication signal VOH, and conducts the higher value between the input and output voltages to the high voltage output terminal VMAX.

[0011] Furthermore, the aforementioned pre-regulatory circuit includes a first P-type field-effect transistor PM1, a second P-type field-effect transistor PM2, a third P-type field-effect transistor PM3, a fourth P-type field-effect transistor PM4, a fifth P-type field-effect transistor PM5, a sixth P-type field-effect transistor PM6, a first capacitor R1, and a second capacitor R2.

[0012] The drain of the first P-type field-effect transistor and the drain of the second P-type field-effect transistor PM2 are respectively connected to the output voltage VOUT and the input voltage VIN. The source of the first P-type field-effect transistor and the source of the second P-type field-effect transistor PM2 are connected to one end of the first resistor, the source of the third P-type field-effect transistor PM3, the source of the fourth P-type field-effect transistor PM4 and one end of the second resistor R2 to form the internal high-voltage power supply VM. The gate of the first P-type field-effect transistor PM1 is connected to the other end of the first resistor R1 and the gate and drain of the fifth field-effect transistor PM5. The source of the fifth P-type field-effect transistor PM5 is connected to the gate and drain of the third P-type field-effect transistor PM3. The gate of the second P-type field-effect transistor PM2 is connected to the other end of the second resistor R2 and the gate and drain of the sixth field-effect transistor PM6. The source of the sixth P-type field-effect transistor PM6 is connected to the gate and drain of the fourth P-type field-effect transistor PM4.

[0013] When the output voltage VOUT is higher than the input voltage VIN, PM1 is turned on and PM2 is turned off, and the internal high-voltage power supply VM follows the output voltage VOUT.

[0014] When the input voltage VIN is higher than the output voltage VOUT, PM2 is turned on first, PM1 is turned off, and the internal high-voltage power supply VM follows the input voltage VIN.

[0015] Furthermore, the aforementioned internal power generation circuit includes a third resistor R3, a first Zener diode D1, a first N-type field-effect transistor NM1, a fourth resistor R4, and a stacked-gate NMOS transistor group composed of second to fifth N-type field-effect transistors NM2 to NM5.

[0016] The stacked-gate NMOS transistor group is composed of NM2 to NM5 connected in series with the gate and drain shorted. One end of the stacked-gate NMOS transistor group is grounded, and the other end is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the source of the first N-type field-effect transistor NM1 and forms the internal low-voltage power supply VDD. The drain of the first N-type field-effect transistor is connected to the internal high-voltage power supply VM and to one end of the third resistor R3. The gate is connected to the other end of the third resistor R3 and the cathode of the first Zener diode D1. The anode of the first Zener diode D1 is grounded.

[0017] Furthermore, the aforementioned voltage rail generating circuit includes a second Zener diode D2, a fifth resistor R5, a seventh P-type field-effect transistor PM7, a first capacitor C1, and a second capacitor C2.

[0018] In this configuration, the cathode of the second Zener diode D2 is connected to one end of the first capacitor C1 and one end of the second capacitor C2, and is also connected to the internal high-voltage power supply VM. The anode of the second Zener diode D2 is connected to the other end of the first capacitor C1, one end of the fifth resistor R5, and the gate of the seventh P-type field-effect transistor. The other end of the fifth resistor R5 is grounded and connected to the drain of the seventh P-type field-effect transistor PM7. The source of the seventh P-type field-effect transistor PM7 is connected to the other end of the second capacitor C2 and generates a voltage rail VMSUB5V that is 5V lower than the internal high-voltage power supply VM.

[0019] Furthermore, the aforementioned comparison circuit includes a first voltage divider network, a second voltage divider network, and a differential input comparator;

[0020] The first voltage divider network includes resistors R6 and R7 connected in series. One end of resistor R6 is connected to the output voltage terminal VOUT, and the other end of resistor R7 is grounded. The intermediate node generates a voltage divider signal VO that is proportional to VOUT.

[0021] The second voltage divider network includes resistors R8 and R9 connected in series. One end of resistor R8 is connected to the input voltage terminal VIN, and the other end of resistor R9 is grounded. The intermediate node generates a voltage divider signal VI that is proportional to VIN.

[0022] The differential input comparator includes the eighth to thirteenth P-type field-effect transistors PM8~PM13, the sixth to ninth N-type field-effect transistors NM6~NM9, the tenth resistor R10, the eleventh resistor R11, the first inverter I1 and the second inverter I2;

[0023] In this configuration, the sources of the eighth P-type field-effect transistor PM8 and the ninth P-type field-effect transistor PM9 are connected to the voltage divider signals VO and VI, respectively, and their gates are connected together. The drain of the eighth P-type field-effect transistor PM8 is connected to its gate and to one end of the tenth resistor R10. The other end of the tenth resistor R10 is grounded and connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to the drain of the ninth P-type field-effect transistor PM9 and to the gates of the tenth P-type field-effect transistor PM10 and the sixth N-type field-effect transistor NM6. The sources of the sixth N-type field-effect transistor NM6 and the tenth P-type field-effect transistor PM10 are grounded and connected to the voltage divider signal VI. The drains of the sixth N-type field-effect transistor NM6 and the tenth P-type field-effect transistor PM10 are connected and to the gates of the eleventh P-type field-effect transistor PM11, the seventh N-type field-effect transistor NM7, and the ninth N-type field-effect transistor NM9. The source of the seventh N-type field-effect transistor NM7... The source of the eleventh P-type field-effect transistor PM11 is connected to the voltage divider signal VI. The drains of NM7 and PM11 are connected and connected to the gate of the eighth N-type field-effect transistor NM8. The drain of NM8 is connected to the drain of the twelfth P-type field-effect transistor PM12, and the gate of the thirteenth P-type field-effect transistor is connected to the input of the first inverter I1. The drain of the ninth N-type field-effect transistor NM9 is connected to the gate of the twelfth P-type field-effect transistor PM12 and the drain of the thirteenth P-type field-effect transistor PM13. The sources of NM8 and NM9 are connected and grounded. The sources of the twelfth P-type field-effect transistor PM12 and the thirteenth P-type field-effect transistor PM13 are connected and connected to the voltage divider signal VO. The first inverter generates and outputs the input voltage high-voltage flag signal A_B to the input of the second inverter I2. The second inverter I2 receives the input voltage high-voltage flag signal A_B and outputs an output voltage high-voltage flag signal A that is complementary to A_B.

[0024] If the output voltage VOUT is higher than the input voltage VIN, the output voltage high voltage flag signal A is high, and the input voltage high voltage flag signal A_B is low.

[0025] If the input voltage VIN is higher than the output voltage VOUT, the output voltage high voltage flag signal A is at a low level, and the input voltage high voltage flag signal A_B is at a high level.

[0026] Furthermore, the aforementioned level shifting circuit receives the input voltage high voltage flag signal A_B and the output voltage high voltage flag signal A, uses the internal high voltage power supply VM as the high voltage reference and the voltage rail VMSUB5V as the low voltage reference, performs level shifting on the A_B and A signals, and outputs the corresponding input voltage high voltage indicator signal VIH and output voltage high voltage indicator signal VOH.

[0027] If the output voltage VOUT is higher than the input voltage VIN, the output voltage high voltage indicator signal VOH is low and the input voltage high voltage indicator signal VIH is high; if the input voltage VIN is higher than the output voltage VOUT, the output voltage high voltage indicator signal VOH is high and the input voltage high voltage indicator signal VIH is low.

[0028] Furthermore, the aforementioned output stage includes a first switch S1 and a second switch S2, wherein the drain of the first switch S1 is connected to the output voltage VOUT, and the gate receives the high voltage indication signal VOH of the output voltage; the gate of the second switch S2 receives the high voltage indication signal VIH of the input voltage, and the source is connected to the source of the second switch S2, thus forming the high voltage output terminal VMAX.

[0029] If the output voltage VOUT is higher than the input voltage VIN, S1 is turned on and S2 is turned off, and the high voltage output terminal VMAX voltage follows the output voltage VOUT; if the input voltage VIN is higher than the output voltage VOUT, S1 is turned off and S2 is turned on, and the high voltage output terminal VMAX voltage follows the input voltage VIN.

[0030] Furthermore, the aforementioned pre-regulator circuit, internal power generation circuit, voltage rail generation circuit, comparator circuit, level shifting circuit, and output stage are all integrated on the same semiconductor substrate, and all field-effect transistors are within the safe operating area during circuit operation.

[0031] Furthermore, the ratio of resistor R6 to resistor R7 in the first voltage divider network and the ratio of resistor R8 to resistor R9 in the second voltage divider network are the same, so that the voltage divider signals VO and VI are equal when the corresponding input voltages VOUT and VIN are equal.

[0032] Furthermore, in the aforementioned internal power generation circuit, the voltage value of the internal low-voltage power supply VDD is set by adjusting the resistance values ​​of the third resistor R3 and the fourth resistor R4, as well as the number of N-type field-effect transistors connected in series in the stacked-gate NMOS transistor group.

[0033] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:

[0034] 1. Wide operating voltage range: Through a voltage divider network and a low-voltage comparator, combined with a level shifting circuit, it can adapt to a wide input / output voltage range from a few volts to tens of volts.

[0035] 2. High comparison accuracy: High-precision comparison is performed in the low-voltage domain, avoiding comparator misalignment and speed problems under high-voltage processes.

[0036] Low quiescent power consumption: The design of the internal low-voltage power supply and low-power comparator results in extremely low overall quiescent current.

[0037] 3. High device reliability: By generating a VMSUB5V voltage rail, it is ensured that the gate-source, gate-drain, and source-drain voltages of all MOSFETs are within the safe operating range allowed by the process, with no risk of overvoltage.

[0038] 4. High integration: All circuits can be integrated on-chip, eliminating the need for external components and reducing system cost and size. Attached Figure Description

[0039] Figure 1 This is a system block diagram of the power supply voltage selection circuit designed for a wide input range switching converter according to the present invention.

[0040] Figure 2 This is a circuit diagram of the pre-stabilized voltage circuit in the design of this invention;

[0041] Figure 3 This is a circuit diagram of the internal power generation circuit in the design of this invention;

[0042] Figure 4 This is a circuit diagram of the voltage rail generation circuit in the design of this invention;

[0043] Figure 5 This is a circuit diagram of the comparison circuit in the design of this invention;

[0044] Figure 6 This is a timing waveform diagram of an application embodiment of the present invention. Detailed Implementation

[0045] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0046] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0047] Figure 1As shown, the design includes a pre-regulator circuit, an internal power generation circuit, a voltage rail generation circuit, a comparator circuit, a level shifter circuit, and an output stage. The circuit comprises the following components: a pre-regulator circuit, whose input terminal is connected to the output voltage VOUT and input voltage VIN of the switching converter, and adaptively selects the higher of the two voltages as the internal high-voltage power supply VM; an internal power generation circuit receives the internal high-voltage power supply VM and generates an internal low-voltage power supply VDD; a voltage rail generation circuit receives the internal high-voltage power supply VM and generates a voltage rail VMSUB5V that is 5V lower than VM; a comparator circuit receives the input voltage VIN and the output voltage VOUT and compares their magnitudes to generate a high-voltage input voltage flag signal A_B and a high-voltage output voltage flag signal A in the low-voltage domain; a level shifting circuit receives the high-voltage input voltage flag signal A_B and the high-voltage output voltage flag signal A and converts them into a high-voltage input voltage high-voltage indicator signal VIH and an output voltage high-voltage indicator signal VOH in the high-voltage domain, with VM and VMSUB5V as the voltage rails; and an output stage receives the high-voltage input voltage high-voltage indicator signal VIH and the high-voltage output voltage high-voltage indicator signal VOH and conducts the higher value between the input and output voltages to the high-voltage output terminal VMAX. After power-on, each module operates in sequence: the pre-regulator circuit first establishes the internal high-voltage power supply VM, drives the internal power generation circuit to generate the internal low-voltage power supply VDD, the voltage rail generation circuit generates the voltage rail VMSUB5V, then the comparator circuit and the level shifter circuit enter normal operation, and the output stage completes the final voltage selection output.

[0048] like Figure 2As shown, the pre-regulator circuit includes a first P-type field-effect transistor PM1, a second P-type field-effect transistor PM2, a third P-type field-effect transistor PM3, a fourth P-type field-effect transistor PM4, a fifth P-type field-effect transistor PM5, a sixth P-type field-effect transistor PM6, a first capacitor R1, and a second capacitor R2. The drains of the first P-type field-effect transistor and the second P-type field-effect transistor PM2 are respectively connected to the output voltage VOUT and the input voltage VIN. The sources of the first P-type field-effect transistor and the second P-type field-effect transistor PM2 are connected together and connected to one end of the first resistor and the third P-type field-effect transistor PM6. The source of transistor PM3, the source of the fourth P-type field-effect transistor PM4, and one end of the second resistor R2 constitute the internal high-voltage power supply VM. The gate of the first P-type field-effect transistor PM1, the other end of the first resistor R1, and the gate and drain of the fifth field-effect transistor PM5 are connected. The source of the fifth P-type field-effect transistor PM5 is connected to the gate and drain of the third P-type field-effect transistor PM3. The gate of the second P-type field-effect transistor PM2, the other end of the second resistor R2, and the gate and drain of the sixth field-effect transistor PM6 are connected. The source of the sixth P-type field-effect transistor PM6 is connected to the gate and drain of the fourth P-type field-effect transistor PM4.

[0049] In practical applications, if the output voltage VOUT is higher than the input voltage VIN, PM1 is turned on and PM2 is turned off, and the internal high-voltage power supply VM follows the output voltage VOUT; if the input voltage VIN is higher than the output voltage VOUT, PM2 is turned on first and PM1 is turned off, and the internal high-voltage power supply VM follows the input voltage VIN.

[0050] like Figure 3 As shown, the internal power generation circuit includes a third resistor R3, a first Zener diode D1, a first N-type field-effect transistor NM1, a fourth resistor R4, and a stacked-gate NMOS transistor group composed of second to fifth N-type field-effect transistors NM2 to NM5. The stacked-gate NMOS transistor group is formed by connecting NM2 to NM5 in series using a diode connection with gate-drain shorting. One end of the stacked-gate NMOS transistor group is grounded, and the other end is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the source of the first N-type field-effect transistor NM1 to form the internal low-voltage power supply VDD. The drain of the first N-type field-effect transistor is connected to the internal high-voltage power supply VM and to one end of the third resistor R3. The gate of the first N-type field-effect transistor is connected to the other end of the third resistor R3 and the cathode of the first Zener diode D1. The anode of the first Zener diode D1 is grounded.

[0051] like Figure 4As shown, the voltage rail generating circuit includes a second Zener diode D2, a fifth resistor R5, a seventh P-type field-effect transistor PM7, a first capacitor C1, and a second capacitor C2. The cathode of the second Zener diode D2 is connected to one end of the first capacitor C1 and one end of the second capacitor C2, and is also connected to the internal high-voltage power supply VM. The anode of the second Zener diode D2 is connected to the other end of the first capacitor C1, one end of the fifth resistor R5, and the gate of the seventh P-type field-effect transistor. The other end of the fifth resistor R5 is grounded and connected to the drain of the seventh P-type field-effect transistor PM7. The source of the seventh P-type field-effect transistor PM7 is connected to the other end of the second capacitor C2, generating a voltage rail VMSUB5V that is 5V lower than the internal high-voltage power supply VM.

[0052] like Figure 5As shown, the comparator circuit includes a first voltage divider network, a second voltage divider network, and a differential input comparator. The first voltage divider network is composed of resistors R6 and R7 connected in series. One end of R6 is connected to the output voltage terminal VOUT, and the other end of R7 is grounded. The intermediate node generates a voltage divider signal VO proportional to VOUT. The second voltage divider network is composed of resistors R8 and R9 connected in series. One end of R8 is connected to the input voltage terminal VIN, and the other end of R9 is grounded. The intermediate node generates a voltage divider signal VI proportional to VIN. The differential input comparator includes the eighth to thirteenth P-type field-effect transistors PM8~PM8. 13. Sixth to ninth N-type field-effect transistors NM6~NM9, tenth resistor R10, eleventh resistor R11, first inverter I1 and second inverter I2; wherein, the sources of the eighth P-type field-effect transistor PM8 and the ninth P-type field-effect transistor PM9 are respectively connected to the voltage divider signals VO and VI, and their gates are connected together. The drain of PM8 is connected to the gate of PM8 and connected to one end of the tenth resistor R10. The other end of R10 is grounded and connected to one end of R11. The other end of R11 is connected to the drain of the ninth P-type field-effect transistor PM9 and connected to the tenth P-type field-effect transistor PM10 and the sixth N-type field-effect transistor NM6. The gates of the sixth N-type field-effect transistor NM6 and the tenth P-type field-effect transistor PM10 are grounded and connected to the voltage divider signal VI. The drains of NM6 and PM10 are connected to the gates of the eleventh P-type field-effect transistor PM11, the seventh N-type field-effect transistor NM7, and the ninth N-type field-effect transistor NM9. The source of the seventh N-type field-effect transistor NM7 is grounded. The source of the eleventh P-type field-effect transistor PM11 is connected to the voltage divider signal VI. The drains of NM7 and PM11 are connected to the gate of the eighth N-type field-effect transistor NM8. The drain of NM8 is connected to the drain of the twelfth P-type field-effect transistor PM12 and the tenth P-type field-effect transistor PM10. The gate of the three P-type field-effect transistor is connected to the input terminal of the first inverter I1. The drain of the ninth N-type field-effect transistor NM9 is connected to the gate of the twelfth P-type field-effect transistor PM12 and the drain of the thirteenth P-type field-effect transistor PM13. The source of NM8 and the source of NM9 are connected to ground. The sources of PM12 and PM13 are connected to the voltage divider signal VO. The first inverter generates and outputs the input voltage high voltage indicator signal A_B to the input terminal of the second inverter I2. The second inverter I2 receives the input voltage high voltage indicator signal A_B and outputs an output voltage high voltage indicator signal A that is complementary to A_B.

[0053] If the output voltage VOUT is higher than the input voltage VIN, the output voltage high voltage indicator signal A is high and the input voltage high voltage indicator signal A_B is low; if the input voltage VIN is higher than the output voltage VOUT, the output voltage high voltage indicator signal A is low and the input voltage high voltage indicator signal A_B is high.

[0054] In actual implementation, the level shifting circuit receives the input voltage high-voltage indicator signal A_B and the output voltage high-voltage indicator signal A, using the internal high-voltage power supply VM as the high-voltage reference and the voltage rail VMSUB5V as the low-voltage reference. It performs level shifting on the A_B and A signals to generate and output corresponding input voltage high-voltage indicator signal VIH and output voltage high-voltage indicator signal VOH to the output stage. The output stage includes a first switch S1 and a second switch S2. The drain of the first switch S1 is connected to the output voltage VOUT, and its gate receives the output voltage high-voltage indicator signal VOH. The gate of the second switch S2 receives the input voltage high-voltage indicator signal VIH, and its source is connected to the source of the second switch S2, forming the high-voltage output terminal VMAX.

[0055] If the output voltage VOUT is higher than the input voltage VIN, the output voltage high voltage indicator signal VOH is low and the input voltage high voltage indicator signal VIH is high. At this time, S1 is turned on and S2 is turned off, and the high voltage output terminal VMAX voltage follows the output voltage VOUT. If the input voltage VIN is higher than the output voltage VOUT, the output voltage high voltage indicator signal VOH is high and the input voltage high voltage indicator signal VIH is low. At this time, S1 is turned off and S2 is turned on, and the high voltage output terminal VMAX voltage follows the input voltage VIN.

[0056] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A power supply voltage selection circuit for a wide input range switching converter, characterized in that, It includes a pre-regulator circuit, an internal power generation circuit, a voltage rail generation circuit, a comparator circuit, a level shifter circuit, and an output stage. The pre-regulator circuit is connected to the output voltage VOUT and the input voltage VIN of the switching converter at its input terminal, and adaptively selects the higher of the output voltage VOUT and the input voltage VIN as the high voltage power supply VM inside the circuit. The internal power generation circuit receives the internal high-voltage power supply VM and generates an internal low-voltage power supply VDD. The voltage rail generation circuit receives the internal high-voltage power supply VM and is used to generate a voltage rail VMSUB5V that is 5V lower than the internal high-voltage power supply VM. The comparator circuit receives the input voltage VIN and the output voltage VOUT and compares their magnitudes to generate an input voltage high voltage flag signal A_B and an output voltage high voltage flag signal A in the low voltage domain. The level shifting circuit receives the input voltage high voltage flag signal A_B and the output voltage high voltage flag signal A and converts them into an input voltage high voltage indication signal VIH and an output voltage high voltage indication signal VOH with VM and VMSUB5V as voltage rails in the high voltage domain. The output stage receives the input voltage high voltage indication signal VIH and the output voltage high voltage indication signal VOH, and conducts the higher value between the input and output voltages to the high voltage output terminal VMAX.

2. The power supply voltage selection circuit for a wide input range switching converter according to claim 1, characterized in that, The pre-regulator circuit includes a first P-type field-effect transistor PM1, a second P-type field-effect transistor PM2, a third P-type field-effect transistor PM3, a fourth P-type field-effect transistor PM4, a fifth P-type field-effect transistor PM5, a sixth P-type field-effect transistor PM6, a first capacitor R1, and a second capacitor R2. The drain of the first P-type field-effect transistor and the drain of the second P-type field-effect transistor PM2 are respectively connected to the output voltage VOUT and the input voltage VIN. The source of the first P-type field-effect transistor and the source of the second P-type field-effect transistor PM2 are connected to one end of the first resistor, the source of the third P-type field-effect transistor PM3, the source of the fourth P-type field-effect transistor PM4 and one end of the second resistor R2 to form the internal high-voltage power supply VM. The gate of the first P-type field-effect transistor PM1 is connected to the other end of the first resistor R1 and the gate and drain of the fifth field-effect transistor PM5. The source of the fifth P-type field-effect transistor PM5 is connected to the gate and drain of the third P-type field-effect transistor PM3. The gate of the second P-type field-effect transistor PM2 is connected to the other end of the second resistor R2 and the gate and drain of the sixth field-effect transistor PM6. The source of the sixth P-type field-effect transistor PM6 is connected to the gate and drain of the fourth P-type field-effect transistor PM4. When the output voltage VOUT is higher than the input voltage VIN, PM1 is turned on and PM2 is turned off, and the internal high-voltage power supply VM follows the output voltage VOUT. When the input voltage VIN is higher than the output voltage VOUT, PM2 is turned on first, PM1 is turned off, and the internal high-voltage power supply VM follows the input voltage VIN.

3. The power supply voltage selection circuit for a wide input range switching converter according to claim 1, characterized in that, The internal power generation circuit includes a third resistor R3, a first Zener diode D1, a first N-type field-effect transistor NM1, a fourth resistor R4, and a stacked-gate NMOS transistor group composed of second to fifth N-type field-effect transistors NM2 to NM5. The stacked-gate NMOS transistor group is composed of NM2 to NM5 connected in series with the gate and drain shorted. One end of the stacked-gate NMOS transistor group is grounded, and the other end is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the source of the first N-type field-effect transistor NM1 and forms the internal low-voltage power supply VDD. The drain of the first N-type field-effect transistor is connected to the internal high-voltage power supply VM and to one end of the third resistor R3. The gate is connected to the other end of the third resistor R3 and the cathode of the first Zener diode D1. The anode of the first Zener diode D1 is grounded.

4. The power supply voltage selection circuit for a wide input range switching converter according to claim 1, characterized in that, The voltage rail generating circuit includes a second Zener diode D2, a fifth resistor R5, a seventh P-type field-effect transistor PM7, a first capacitor C1, and a second capacitor C2. In this configuration, the cathode of the second Zener diode D2 is connected to one end of the first capacitor C1 and one end of the second capacitor C2, and is also connected to the internal high-voltage power supply VM. The anode of the second Zener diode D2 is connected to the other end of the first capacitor C1, one end of the fifth resistor R5, and the gate of the seventh P-type field-effect transistor. The other end of the fifth resistor R5 is grounded and connected to the drain of the seventh P-type field-effect transistor PM7. The source of the seventh P-type field-effect transistor PM7 is connected to the other end of the second capacitor C2 and generates a voltage rail VMSUB5V that is 5V lower than the internal high-voltage power supply VM.

5. The power supply voltage selection circuit for a wide input range switching converter according to claim 1, characterized in that, The comparator circuit includes a first voltage divider network, a second voltage divider network, and a differential input comparator; The first voltage divider network includes resistors R6 and R7 connected in series. One end of resistor R6 is connected to the output voltage terminal VOUT, and the other end of resistor R7 is grounded. The intermediate node generates a voltage divider signal VO that is proportional to VOUT. The second voltage divider network includes resistors R8 and R9 connected in series. One end of resistor R8 is connected to the input voltage terminal VIN, and the other end of resistor R9 is grounded. The intermediate node generates a voltage divider signal VI proportional to VIN. The differential input comparator includes the eighth to thirteenth P-type field-effect transistors PM8~PM13, the sixth to ninth N-type field-effect transistors NM6~NM9, the tenth resistor R10, the eleventh resistor R11, the first inverter I1 and the second inverter I2; In this configuration, the sources of the eighth P-type field-effect transistor PM8 and the ninth P-type field-effect transistor PM9 are connected to the voltage divider signals VO and VI, respectively, and their gates are connected together. The drain of the eighth P-type field-effect transistor PM8 is connected to its gate and to one end of the tenth resistor R10. The other end of the tenth resistor R10 is grounded and connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is connected to the drain of the ninth P-type field-effect transistor PM9 and to the gates of the tenth P-type field-effect transistor PM10 and the sixth N-type field-effect transistor NM6. The sources of the sixth N-type field-effect transistor NM6 and the tenth P-type field-effect transistor PM10 are grounded and connected to the voltage divider signal VI. The drains of the sixth N-type field-effect transistor NM6 and the tenth P-type field-effect transistor PM10 are connected and to the gates of the eleventh P-type field-effect transistor PM11, the seventh N-type field-effect transistor NM7, and the ninth N-type field-effect transistor NM9. The source of the seventh N-type field-effect transistor NM7... The source of the eleventh P-type field-effect transistor PM11 is connected to the voltage divider signal VI. The drains of NM7 and PM11 are connected and connected to the gate of the eighth N-type field-effect transistor NM8. The drain of NM8 is connected to the drain of the twelfth P-type field-effect transistor PM12, and the gate of the thirteenth P-type field-effect transistor is connected to the input of the first inverter I1. The drain of the ninth N-type field-effect transistor NM9 is connected to the gate of the twelfth P-type field-effect transistor PM12 and the drain of the thirteenth P-type field-effect transistor PM13. The sources of NM8 and NM9 are connected and grounded. The sources of the twelfth P-type field-effect transistor PM12 and the thirteenth P-type field-effect transistor PM13 are connected and connected to the voltage divider signal VO. The first inverter generates and outputs the input voltage high-voltage flag signal A_B to the input of the second inverter I2. The second inverter I2 receives the input voltage high-voltage flag signal A_B and outputs an output voltage high-voltage flag signal A that is complementary to A_B. If the output voltage VOUT is higher than the input voltage VIN, the output voltage high voltage flag signal A is high, and the input voltage high voltage flag signal A_B is low. If the input voltage VIN is higher than the output voltage VOUT, the output voltage high voltage flag signal A is at a low level, and the input voltage high voltage flag signal A_B is at a high level.

6. The power supply voltage selection circuit for a wide input range switching converter according to claim 1, characterized in that, The level shifting circuit receives the input voltage high voltage flag signal A_B and the output voltage high voltage flag signal A, and uses the internal high voltage power supply VM as the high voltage reference and the voltage rail VMSUB5V as the low voltage reference. It performs level shifting on the A_B and A signals and outputs the corresponding input voltage high voltage indicator signal VIH and output voltage high voltage indicator signal VOH. If the output voltage VOUT is higher than the input voltage VIN, the output voltage high voltage indicator signal VOH is low and the input voltage high voltage indicator signal VIH is high; if the input voltage VIN is higher than the output voltage VOUT, the output voltage high voltage indicator signal VOH is high and the input voltage high voltage indicator signal VIH is low.

7. The power supply voltage selection circuit for a wide input range switching converter according to claim 1, characterized in that, The output stage includes a first switch S1 and a second switch S2, wherein the drain of the first switch S1 is connected to the output voltage VOUT, and the gate receives the high voltage indication signal VOH of the output voltage. The gate of the second switch S2 receives the high voltage indication signal VIH of the input voltage, and the source is connected to the source of the second switch S2, forming the high voltage output terminal VMAX. If the output voltage VOUT is higher than the input voltage VIN, S1 is turned on and S2 is turned off, and the high voltage output terminal VMAX voltage follows the output voltage VOUT; if the input voltage VIN is higher than the output voltage VOUT, S1 is turned off and S2 is turned on, and the high voltage output terminal VMAX voltage follows the input voltage VIN.

8. The power supply voltage selection circuit for a wide input range switching converter according to claim 1, characterized in that, The pre-regulator circuit, internal power generation circuit, voltage rail generation circuit, comparator circuit, level shifter circuit, and output stage are all integrated on the same semiconductor substrate, and all field-effect transistors are in the safe operating area during circuit operation.

9. A power supply voltage selection circuit for a wide input range switching converter according to claim 5, characterized in that, The ratio of resistor R6 to resistor R7 in the first voltage divider network and the ratio of resistor R8 to resistor R9 in the second voltage divider network are the same, so that the voltage divider signals VO and VI are equal when the corresponding input voltages VOUT and VIN are equal.

10. A power supply voltage selection circuit for a wide input range switching converter according to claim 3, characterized in that, In the internal power generation circuit, the voltage value of the internal low-voltage power supply VDD is set by adjusting the resistance values ​​of the third resistor R3 and the fourth resistor R4, as well as the number of N-type field-effect transistors connected in series in the stacked-gate NMOS transistor group.

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