Cot-based buck-boost converter and control method thereof

Abstract

The application discloses a buck-boost converter based on COT and a control method thereof, and comprises a four-tube buck-boost circuit, a voltage division circuit, an error amplifier EA, a comparator CMP1, a comparator CMP2, an adaptive constant time generator constant time generator 1, an adaptive constant time generator constant time generator 2 and a logic control module LOGIC & DRIVER. The application can make the buck-boost converter have the characteristics of a single spectrum in the whole working range in the condition of no clock signal, like the voltage or current mode control mode.

Description

Technical Field

[0001] This invention relates to a converter and its control method, particularly a COT-based buckboost converter and its control method, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In switching power supplies, with the increasing demand for wide input and output voltage ranges, the application of four-transistor buckboost converters is becoming more and more widespread. A typical four-transistor buckboost converter is as follows: Figure 7 As shown. For a four-transistor buck-boost converter, when the input voltage and output voltage difference is large, the system operates in buck or boost mode. In this case, switch A or switch D is in a shoot-through state, and the control mode is basically the same as buck or boost. However, when the input voltage and output voltage are relatively close, the system needs to operate in buck-boost mode to ensure output voltage stability. For four-transistor buck-boost converters using voltage or current control modes, since there is a fixed clock in the system, its control timing is relatively simple, such as... Figure 8 The diagram illustrates a commonly used control timing sequence. While the control method is simple for a four-transistor buck-boost converter using voltage or current mode control, its main drawback is poor output dynamic response. To address this, constant on-time (COT) control is typically employed. However, with COT, the operating frequency varies with input and output voltages, resulting in a wide frequency spectrum, which is detrimental to EMI design. To further address this, adaptive constant on-time (ACOT) control can be used. This method ensures a stable operating frequency in both buck and boost states. However, when the system operates in the buck-boost phase, the lack of a fixed clock signal makes it difficult to achieve stable phase shift control like voltage or current mode converters, leading to a less stable operating frequency and a wider frequency spectrum. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a COT-based buckboost converter and its control method, which enables the buckboost converter to be controlled in the same way as voltage or current mode without a clock signal.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A COT-based buckboost converter includes a four-transistor buckboost circuit, a voltage divider circuit, an error amplifier EA, comparators CMP1 and CMP2, an adaptive constant time generator 1, an adaptive constant time generator 2, and a logic control module (LOGIC & DRIVER). The input of the voltage divider circuit is connected to the output voltage VOUT. The output of the voltage divider circuit is connected to the inverting input of the error amplifier EA. The non-inverting input of the error amplifier EA is connected to the reference voltage Vref. The output of the error amplifier is connected to the non-inverting inputs of comparators CMP1 and CMP2. The inverting input of comparator CMP1 is connected to the valley current sampling slope1, and the inverting input of comparator CMP2 is connected to the peak current sampling slope2. The output of comparator CMP1 is connected to the input of the adaptive constant time generator 1 and generates a signal Vo1. The output of comparator CMP2 is connected to the adaptive constant time generator 1. The input terminal of generator2 generates signal Vo2. The two output terminals of the adaptive constant time generator1 are connected to the logic control module LOGIC&DRIVER and generate signals Vo3 and Vo4. The two output terminals of the adaptive constant time generator2 are connected to the logic control module LOGIC&DRIVER and generate signals Vo5 and Vo6.

[0006] Furthermore, the voltage divider circuit includes resistors R1 and R2. One end of resistor R1 serves as the input terminal of the voltage divider circuit and is connected to the output voltage VOUT. The other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the voltage divider circuit. The other end of resistor R2 is grounded.

[0007] Furthermore, the four-transistor buckboost circuit includes switching transistors MA, MB, MC, and MD, inductor L0, and resistor R. ESR Capacitor C OUT and resistance R LOAD The gates of transistors MA, MB, MC, and MD are sequentially connected to the four outputs of the logic control module LOGIC&DRIVER. The drain of transistor MA is connected to the input voltage VIN. The source of transistor MA is connected to the drain of transistor MB and one end of inductor L0. The other end of inductor L0 is connected to the drain of transistor MC and the source of transistor MD. The drain of transistor MD is connected to resistor R.ESR one end and resistor R LOAD One end is connected to the output voltage VOUT, and the resistor R ESR The other end is connected to capacitor C OUT One end is connected to the source of switching transistor MB, the source of switching transistor MC, and capacitor C. OUT The other end and resistor R LOAD The other end is grounded.

[0008] Furthermore, the valley current sampling slope1 is derived from the current sampling of the switching transistor MB, and the peak current sampling slope2 is derived from the current sampling of the switching transistor MC.

[0009] Furthermore, the adaptive constant time generators 1 and 2 respectively include an operational amplifier (OPA), comparators CMP3 and CMP4, PMOS transistors MP1, MP2, and MP3, NMOS transistors MN1 and MN2, resistor R3, and capacitors C1 and C2. The sources of PMOS transistors MP1 and MP2 are connected to the power supply VCC. The gates of PMOS transistors MP1 and MP2, as well as the drains of PMOS transistors MP1 and MN1, are connected. The gate of NMOS transistor MN1 is connected to the output of OPA and one end of capacitor C1. The source of NMOS transistor MN1 is connected to the inverting input of OPA and one end of resistor R3. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3. The gate of PMOS transistor MP3 is connected to the gate of NMOS transistor MN2 and serves as the adaptive constant time generator. The input terminals of generator1 and adaptive constant time generator2 are connected to the drain of PMOS transistor MP3, one end of capacitor C2, the drain of NMOS transistor MN2, the non-inverting input terminal of comparator CMP3, and the non-inverting input terminal of comparator CMP4. The output terminals of comparator CMP3 and comparator CMP4 serve as the two output terminals of adaptive constant time generator1 and adaptive constant time generator2. The other end of capacitor C1, the other end of resistor R3, the other end of capacitor C2, and the source of NMOS transistor MN2 are grounded. In the adaptive constant time generator 1, the non-inverting input terminal of the operational amplifier OPA is connected to signal K1. VIN, the inverting input of comparator CMP3 is connected to signal K1. VOUT, the inverting input of comparator CMP4 is connected to signal K2. VOUT; where K1 and K2 are constants; In the adaptive constant time generator 2, the non-inverting input terminal of the operational amplifier OPA is connected to signal K1. VOUT, the inverting input of comparator CMP3 is connected to signal K1. VIN, the inverting input of comparator CMP4 is connected to signal K2. VIN.

[0010] A control method for a COT-based buckboost converter includes the following steps: When the input voltage VIN is much greater than the output voltage VOUT, the COT-based buckboost converter operates in buck state; the switch MD is in shoot-through state, node SW2 is always high, and the operating frequency of node SW1 is determined by the internal time constant, which is a constant value. When the input voltage VIN is much smaller than the output voltage VOUT, the COT-based buckboost converter operates in boost mode; at this time, the switching transistor MA is in shoot-through mode, node SW1 is always high, and the operating frequency of node SW2 is determined by the internal system time constant, which is a constant value. When the input voltage VIN is close to the output voltage VOUT, the COT-based buckboost converter operates in buckboost mode. In buckboost mode, when the input voltage VIN is greater than the output voltage VOUT, the adaptive constant time generator 1 determines the high-level time of node SW1, as expressed by:

[0011] Where k is a constant value determined by the internal time constant; Therefore, for node SW1, its operating frequency remains consistent with that when it is in buck mode; while for node SW2, its falling edge is controlled by signal Vo4; the times t1 and t2 determined by signals Vo3 and Vo4 satisfy the following relationship:

[0012] Where k0 is a fixed value, t2 is subject to the following constraints:

[0013] Where T is the system operating cycle; by selecting an appropriate proportional coefficient k0, the frequency of node SW2 is controlled by node SW1; When the input voltage VIN is less than the output voltage VOUT, the adaptive on-time generator 2 determines the high-level time of node SW2, as expressed by:

[0014] Therefore, for node SW2, its operating frequency remains consistent with that when it is in boost mode; while for node SW1, its falling edge is controlled by signal Vo6; the times t6 and t7 determined by signals Vo5 and Vo6 also satisfy the following relationship:

[0015] Therefore, in this state, the operating frequency of node SW1 is controlled by node SW2.

[0016] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a Buckboost converter based on COT and its control method, which can solve the problem of the wide frequency range of the Buckboost converter operating in Buckboost state; In the control method proposed in the present invention, when the converter is in the Buckboost working stage, by adjusting two relatively independent controls to one active control and one passive follower, the frequency of SW2 follows SW1 or the frequency of SW1 follows SW2, so that the operating frequency of the entire system remains constant throughout the entire operating range. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a COT-based buckboost converter according to the present invention.

[0018] Figure 2 This is a schematic diagram of the adaptive constant on-time generator of the present invention.

[0019] Figure 3 This is a schematic diagram of the key node waveforms of a COT-based buckboost converter operating in buck mode according to the present invention.

[0020] Figure 4 This is a schematic diagram of the key node waveforms of a COT-based buckboost converter operating in boost mode according to the present invention.

[0021] Figure 5This is a schematic diagram of the key node waveforms of a COT-based buckboost converter of the present invention, operating in buckboost mode with VIN greater than VOUT.

[0022] Figure 6 This is a schematic diagram of the key node waveforms of a COT-based buckboost converter operating in buckboost mode with VIN less than VOUT.

[0023] Figure 7 This is a schematic diagram of a typical four-tube buckboost converter in the existing technology.

[0024] Figure 8 This is a schematic diagram of the control waveform of a Buckboost converter operating in Buckboost mode with a clock signal. Detailed Implementation

[0025] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0026] like Figure 1As shown, this invention discloses a COT-based buckboost converter, comprising a four-transistor buckboost circuit, a voltage divider circuit, an error amplifier EA, comparators CMP1 and CMP2, an adaptive constant time generator 1, an adaptive constant time generator 2, and a logic control module (LOGIC & DRIVER). The input of the voltage divider circuit is connected to the output voltage VOUT. The output of the voltage divider circuit is connected to the inverting input of the error amplifier EA. The non-inverting input of the error amplifier EA is connected to the reference voltage Vref. The output of the error amplifier is connected to the non-inverting inputs of comparators CMP1 and CMP2. The inverting input of comparator CMP1 is connected to the valley current sampling slope1, and the inverting input of comparator CMP2 is connected to the peak current sampling slope2. The output of comparator CMP1 is connected to the input of the adaptive constant time generator 1 and generates a signal Vo1. The output of comparator CMP2 is connected to the adaptive constant time generator 1. The two outputs of the adaptive constant time generator 1 are connected to the logic control module LOGIC&DRIVER and generate signals Vo3 and Vo4. The two outputs of the adaptive constant time generator 2 are connected to the logic control module LOGIC&DRIVER and generate signals Vo5 and Vo6.

[0027] The voltage divider circuit includes resistors R1 and R2. One end of resistor R1 serves as the input terminal of the voltage divider circuit and is connected to the output voltage VOUT. The other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the voltage divider circuit. The other end of resistor R2 is grounded.

[0028] A four-transistor buckboost circuit includes switching transistors MA, MB, MC, and MD, inductor L0, and resistor R. ESR Capacitor C OUT and resistance R LOAD The gates of transistors MA, MB, MC, and MD are sequentially connected to the four outputs of the logic control module LOGIC&DRIVER. The drain of transistor MA is connected to the input voltage VIN. The source of transistor MA is connected to the drain of transistor MB and one end of inductor L0. The other end of inductor L0 is connected to the drain of transistor MC and the source of transistor MD. The drain of transistor MD is connected to resistor R. ESRone end and resistor R LOAD One end is connected to the output voltage VOUT, and the resistor R ESR The other end is connected to capacitor C OUT One end is connected to the source of switching transistor MB, the source of switching transistor MC, and capacitor C. OUT The other end and resistor R LOAD The other end is grounded.

[0029] Valley current sampling slope1 is derived from the current sampling of switch MB, and peak current sampling slope2 is derived from the current sampling of switch MC.

[0030] The adaptive constant-time generators 1 and 2 each include an operational amplifier (OPA), comparators CMP3 and CMP4, PMOS transistors MP1, MP2, and MP3, NMOS transistors MN1 and MN2, resistor R3, and capacitors C1 and C2. The sources of PMOS transistors MP1 and MP2 are connected to the power supply VCC. The gates of PMOS transistors MP1 and MP2, and MP1 and MN1 are connected. The gate of NMOS transistor MN1 is connected to the output of OPA and one end of capacitor C1. The source of NMOS transistor MN1 is connected to the inverting input of OPA and one end of resistor R3. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3. The gate of PMOS transistor MP3 is connected to the gate of NMOS transistor MN2 and serves as the adaptive constant-time generator. The input terminals of generator1 and adaptive constant time generator2 are connected to the drain of PMOS transistor MP3, one end of capacitor C2, the drain of NMOS transistor MN2, the non-inverting input terminal of comparator CMP3, and the non-inverting input terminal of comparator CMP4. The output terminals of comparator CMP3 and comparator CMP4 serve as the two output terminals of adaptive constant time generator1 and adaptive constant time generator2. The other end of capacitor C1, the other end of resistor R3, the other end of capacitor C2, and the source of NMOS transistor MN2 are grounded. In the adaptive constant time generator 1, the non-inverting input terminal of the operational amplifier OPA is connected to signal K1. VIN, the inverting input of comparator CMP3 is connected to signal K1. VOUT, the inverting input of comparator CMP4 is connected to signal K2. VOUT; where K1 and K2 are constants; In the adaptive constant time generator 2, the non-inverting input terminal of the operational amplifier OPA is connected to signal K1. VOUT, the inverting input of comparator CMP3 is connected to signal K1. VIN, the inverting input of comparator CMP4 is connected to signal K2. VIN.

[0031] When the circuit is in buck mode, switching transistor MA is off by default, and switching transistor MB is on by default. Switching transistor MC remains off, and switching transistor MD remains on. At this time, the valley current sampling slope1 and comparator CMP1 start working, while the peak current sampling slope2 and comparator CMP2 are not working. When the signal Vo1 output by comparator CMP1 equals 1, switching transistor MB turns off, switching transistor MA turns on, and simultaneously triggers the adaptive constant time generator 1 to start timing. When time t1 is reached, signal Vo3 equals 1, at which point switching transistor MA turns off and switching transistor MB turns on, completing one switching cycle.

[0032] When the circuit is in boost mode, switching transistor MA remains on, switching transistor MB remains off, switching transistor MC is on by default, and switching transistor MD is off by default. At this time, peak current sampling slope2 and comparator CMP2 begin operating, while valley current sampling slope1 and comparator CMP1 are inactive. When the signal Vo2 output by comparator CMP2 equals 1, switching transistor MC turns off and switching transistor MD turns on, simultaneously triggering the adaptive constant time generator 2 to start timing. When time t6 is reached, signal Vo5 equals 1, at which point switching transistor MD turns off and switching transistor MC turns on, completing one cycle.

[0033] When the circuit is in buckboost mode, the valley current sampling slope1, peak current sampling slope2, and comparators CMP1 and CMP2 are all active. Specifically, based on the absolute values ​​of the input voltage VIN and output voltage VOUT in this state, there are two operating states: input voltage VIN is greater than output voltage VOUT, and input voltage VIN is less than output voltage VOUT. Key node waveforms are shown below. Figure 5 , Figure 6As shown. When the circuit switches from buck mode to buckboost mode, the input voltage VIN is greater than the output voltage VOUT. At this time, the switching transistor MA is off by default, the switching transistor MB is on by default, the switching transistor MC is off by default, and the switching transistor MD is on by default. The valley current sampling slope1 and comparator CMP1 work first. When the output of comparator CMP1 is 1, the switching transistor MB is off, the switching transistor MA is on, and the switching transistors MC and MD remain in their original states. At the same time, the adaptive constant time generator 1 starts timing. When the timing time reaches t2, the signal Vo4 equals 1. At this time, the switching transistors MA and MB remain in their original states, the switching transistor MC is on, and the switching transistor MD is off. Simultaneously, peak current sampling slope2 and comparator CMP2 are triggered to operate. When the comparator output signal Vo2 becomes 1, switches MA and MB remain unchanged, switch MC is off, and switch MD is on. At the same time, the adaptive constant time generator 2 starts timing. During this process, the adaptive constant time generator 1 will time to t1 (t1>t2). At this point, switch MA is off, switch MB is on, and switches MC and MD remain unchanged. Simultaneously, valley current sampling slope1 and comparator CMP1 are triggered to start operating. This completes one cycle. When the circuit switches from boost state to buck-boost state, the input voltage VIN is less than the output voltage VOUT. At this time, switch MA is on by default, switch MB is off by default, switch MC is on by default, and switch MD is off by default. Peak current sampling slope2 and comparator CMP2 start operating. When the comparator CMP2 output signal Vo2 equals 1, switches MA and MB remain unchanged, switch MC is off, and switch MD is on.Simultaneously, the adaptive constant time generator 2 is triggered to start working. When the timing reaches t7, switch MA is turned off, switch MB is turned on, and switches MC and MD remain unchanged. At the same time, the valley current sampling slope1 and comparator CMP1 are triggered to start working. When the signal Vo1 output by comparator CMP1 becomes 1, switch MA is turned on, switch MB is turned off, and switches MC and MD remain unchanged. Simultaneously, the adaptive constant time generator 1 is triggered to start timing. During this process, the timing of the adaptive constant time generator 2 will reach t6 (t6>t7). At this time, switches MA and MB remain unchanged, switch MC is turned on, switch MD is turned off, and the peak current sampling slope2 and comparator CMP2 are triggered to start working. Thus, one periodic cycle is completed.

[0034] A control method for a COT-based buckboost converter includes the following steps: like Figure 3 As shown, when the input voltage VIN is much greater than the output voltage VOUT, the COT-based buckboost converter operates in buck state; the switch MD is in shoot-through state, node SW2 is always high, and the operating frequency of node SW1 is determined by the internal time constant, which is a constant value.

[0035] like Figure 4 As shown, when the input voltage VIN is much smaller than the output voltage VOUT, the COT-based buckboost converter operates in boost mode; at this time, the switching transistor MA is in shoot-through mode, node SW1 is always high, and the operating frequency of node SW2 is determined by the internal system time constant, which is a constant value.

[0036] When the input voltage VIN is close to the output voltage VOUT, the COT-based buckboost converter operates in buckboost mode. In this mode, it is further divided into two sub-states according to the absolute values ​​of the input and output voltages.

[0037] like Figure 5 As shown, in BuckBoost mode, when the input voltage VIN is slightly greater than the output voltage VOUT, the adaptive constant time generator 1 determines the high-level time of node SW1, as expressed in the following expression:

[0038] Where k is a constant value determined by the internal time constant; Therefore, for node SW1, its operating frequency remains consistent with that when it is in buck mode; while for node SW2, its falling edge is controlled by signal Vo4; the times t1 and t2 determined by signals Vo3 and Vo4 satisfy the following relationship:

[0039] Where k0 is a fixed value, t2 is subject to the following constraints:

[0040] Where T is the system operating cycle; by selecting an appropriate proportional coefficient k0, the frequency of node SW2 is controlled by node SW1; thus ensuring the stability of the system operating frequency.

[0041] like Figure 6 As shown, when the input voltage VIN is less than the output voltage VOUT, the adaptive on-time generator 2 determines the high-level time of node SW2, and the expression is:

[0042] Therefore, for node SW2, its operating frequency remains consistent with that when it is in boost mode; while for node SW1, its falling edge is controlled by signal Vo6; the times t6 and t7 determined by signals Vo5 and Vo6 also satisfy the following relationship:

[0043] Therefore, in this state, the operating frequency of node SW1 is controlled by node SW2. This also ensures the stability of the system's operating frequency. In summary, the system's operating frequency remains constant throughout the entire range.

[0044] This invention provides a COT-based buckboost converter and its control method, which can solve the problem of wide frequency range of buckboost converters operating in buckboost mode. In the control method proposed in this invention, when the converter is in the buckboost working phase, by adjusting two relatively independent controls to one active control and one passive follower, the frequency of SW2 follows SW1 or the frequency of SW1 follows SW2, so that the operating frequency of the entire system remains constant throughout the entire operating range.

[0045] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A COT-based buckboost converter, characterized in that: This system includes a four-transistor buckboost circuit, a voltage divider circuit, an error amplifier EA, comparators CMP1 and CMP2, an adaptive constant time generator 1, an adaptive constant time generator 2, and a logic control module (LOGIC & DRIVER). The input of the voltage divider circuit is connected to the output voltage VOUT. The output of the voltage divider circuit is connected to the inverting input of the error amplifier EA. The non-inverting input of the error amplifier EA is connected to the reference voltage Vref. The output of the error amplifier is connected to the non-inverting inputs of both comparators CMP1 and CMP2. The inverting input of comparator CMP1 is connected to the valley current sampling slope1, and the inverting input of comparator CMP2 is connected to the peak current sampling slope2. The output of comparator CMP1 is connected to the input of the adaptive constant time generator 1 and generates a signal Vo1. The output of comparator CMP2 is connected to the adaptive constant time generator 1. The input terminal of generator2 generates signal Vo2. The two output terminals of the adaptive constant time generator1 are connected to the logic control module LOGIC&DRIVER and generate signals Vo3 and Vo4. The two output terminals of the adaptive constant time generator2 are connected to the logic control module LOGIC&DRIVER and generate signals Vo5 and Vo6.

2. The COT-based buckboost converter according to claim 1, characterized in that: The voltage divider circuit includes resistors R1 and R2. One end of resistor R1 serves as the input terminal of the voltage divider circuit and is connected to the output voltage VOUT. The other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the voltage divider circuit. The other end of resistor R2 is grounded.

3. The COT-based buckboost converter according to claim 1, characterized in that: The four-transistor buckboost circuit includes switching transistors MA, MB, MC, and MD, inductor L0, and resistor R. ESR Capacitor C OUT and resistance R LOAD The gates of transistors MA, MB, MC, and MD are sequentially connected to the four outputs of the logic control module LOGIC&DRIVER. The drain of transistor MA is connected to the input voltage VIN. The source of transistor MA is connected to the drain of transistor MB and one end of inductor L0. The other end of inductor L0 is connected to the drain of transistor MC and the source of transistor MD. The drain of transistor MD is connected to resistor R. ESR one end and resistor R LOAD One end is connected to the output voltage VOUT, and the resistor R ESR The other end is connected to capacitor C OUT One end is connected to the source of switching transistor MB, the source of switching transistor MC, and capacitor C. OUT The other end and resistor R LOAD The other end is grounded.

4. The COT-based buckboost converter according to claim 3, characterized in that: The valley current sampling slope1 is derived from the current sampling of the switching transistor MB, and the peak current sampling slope2 is derived from the current sampling of the switching transistor MC.

5. The COT-based buckboost converter according to claim 1, characterized in that: The adaptive constant time generators 1 and 2 respectively include an operational amplifier (OPA), comparators CMP3 and CMP4, PMOS transistors MP1, MP2, and MP3, NMOS transistors MN1 and MN2, resistor R3, and capacitors C1 and C2. The sources of PMOS transistors MP1 and MP2 are connected to the power supply VCC. The gates of PMOS transistors MP1 and MP2, and the drains of PMOS transistors MP1 and MN1 are connected. The gate of NMOS transistor MN1 is connected to the output of OPA and one end of capacitor C1. The source of NMOS transistor MN1 is connected to the inverting input of OPA and one end of resistor R3. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3. The gate of PMOS transistor MP3 is connected to the gate of NMOS transistor MN2 and serves as the adaptive constant time generator. The input terminals of generator1 and adaptive constant time generator2 are connected to the drain of PMOS transistor MP3, one end of capacitor C2, the drain of NMOS transistor MN2, the non-inverting input terminal of comparator CMP3, and the non-inverting input terminal of comparator CMP4. The output terminals of comparator CMP3 and comparator CMP4 serve as the two output terminals of adaptive constant time generator1 and adaptive constant time generator2. The other end of capacitor C1, the other end of resistor R3, the other end of capacitor C2, and the source of NMOS transistor MN2 are grounded. In the adaptive constant time generator 1, the non-inverting input terminal of the operational amplifier OPA is connected to signal K1. VIN, the inverting input of comparator CMP3 is connected to signal K1. VOUT, the inverting input of comparator CMP4 is connected to signal K2. VOUT; where K1 and K2 are constants; In the adaptive constant time generator 2, the non-inverting input terminal of the operational amplifier OPA is connected to signal K1. VOUT, the inverting input of comparator CMP3 is connected to signal K1. VIN, the inverting input of comparator CMP4 is connected to signal K2. VIN.

6. A control method for a COT-based buckboost converter as described in any one of claims 1-5, characterized in that... Includes the following steps: When the input voltage VIN is much greater than the output voltage VOUT, the COT-based buckboost converter operates in buck state; the switch MD is in shoot-through state, node SW2 is always high, and the operating frequency of node SW1 is determined by the internal time constant, which is a constant value. When the input voltage VIN is much smaller than the output voltage VOUT, the COT-based buckboost converter operates in boost mode; at this time, the switching transistor MA is in shoot-through mode, node SW1 is always high, and the operating frequency of node SW2 is determined by the internal system time constant, which is a constant value. When the input voltage VIN is close to the output voltage VOUT, the COT-based buckboost converter operates in buckboost mode. In buckboost mode, when the input voltage VIN is greater than the output voltage VOUT, the adaptive constant time generator 1 determines the high-level time of node SW1, as expressed by: Where k is a constant value determined by the internal time constant; Therefore, for node SW1, its operating frequency remains consistent with that when it is in buck mode; while for node SW2, its falling edge is controlled by signal Vo4; the times t1 and t2 determined by signals Vo3 and Vo4 satisfy the following relationship: Where k0 is a fixed value, t2 is subject to the following constraints: Where T is the system operating cycle; by selecting an appropriate proportional coefficient k0, the frequency of node SW2 is controlled by node SW1; When the input voltage VIN is less than the output voltage VOUT, the adaptive on-time generator 2 determines the high-level time of node SW2, as expressed by: Therefore, for node SW2, its operating frequency remains consistent with that when it is in boost mode; while for node SW1, its falling edge is controlled by signal Vo6; the times t6 and t7 determined by signals Vo5 and Vo6 also satisfy the following relationship: Therefore, in this state, the operating frequency of node SW1 is controlled by node SW2.

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