Power conversion device

Abstract

The application discloses a power conversion device for reducing voltage stress of components, comprising an input positive terminal Vin+, an input negative terminal Vin-, an output positive terminal Vo+, an output negative terminal Vo-, two circuit units A1 and A2, an input filter inductor Lin connected in series between the input positive terminal Vin+ and one of the circuit units, and an output filter capacitor Co connected in parallel between the output positive terminal Vo+ and the output negative terminal Vo-; the circuit units A1 and A2 comprise first input capacitors Cin1 and Cin2, primary side upper switch tubes Q1 and Q3, primary side lower switch tubes Q2 and Q4, primary side upper resonance capacitors Cr1 and Cr3, primary side lower resonance capacitors Cr2 and Cr4, resonance inductors Lr1 and Lr2, transformers T1 and T2, and two full-bridge rectifier circuits arranged in parallel. On one hand, the control timing of the switches in each circuit unit is set, and four control signals are used to achieve stable output of the circuit unit.

Description

Technical Field

[0001] This invention belongs to the field of high-frequency power supply technology, and particularly relates to a power conversion device. Background Technology

[0002] Against the backdrop of accelerated global digitalization, next-generation information technologies, represented by artificial intelligence (AI), cloud computing, and the Internet of Things (IoT), have led to a surge in demand for data center computing power, with single-rack power increasing from the traditional 6kW to 600kW or even higher. To reduce power distribution losses and cabling costs, AIDC power supply architectures are gradually evolving from traditional 12V / 48V buses to ±400V / 800V high-voltage direct current (HVDC) buses. In 800V HVDC input scenarios, traditional single-stage power conversion devices face challenges such as high voltage stress on switching transistors, large magnetic component size, and difficult heat dissipation. Summary of the Invention

[0003] The purpose of this invention is to provide a power conversion device that reduces voltage stress on components.

[0004] To achieve this objective, the technical solution adopted by the present invention is: a power conversion device, including an input positive terminal Vin+, an input negative terminal Vin-, an output positive terminal Vo+, an output negative terminal Vo-, two circuit units A1 and A2, an input filter inductor Lin connected in series between the input positive terminal Vin+ and one of the circuit units, and an output filter capacitor Co connected across the output positive terminal Vo+ and the output negative terminal Vo-. Circuit units A1 and A2 include first input capacitors Cin1 and Cin2, primary-side upper switching transistors Q1 and Q3, primary-side lower switching transistors Q2 and Q4, primary-side upper resonant capacitors Cr1 and Cr3, primary-side lower resonant capacitors Cr2 and Cr4, resonant inductors Lr1 and Lr2, transformers T1 and T2, and two full-bridge rectifier circuits connected in parallel. The input capacitors Cin1 and Cin2 of the two circuit units are connected in series and then bridged between the end of the input filter inductor Lin and the input negative terminal Vin-; the midpoint between the two input capacitors Cin1 and Cin2 is denoted as the input midpoint Mgnd; the sources of the primary side upper switching transistors Q1 and Q3 and the drains of the primary side lower switching transistors Q2 and Q4 are electrically connected to the first node Mp1 and Mp3 of the primary side, forming the primary side switching bridge arm of circuit units A1 and A2; one end of the primary side upper resonant capacitors Cr1 and Cr3 and the primary side lower resonant capacitors Cr2 and Cr3 are connected to the primary side lower resonant capacitors Cr1 and Cr3. One end of 4 is electrically connected to the second node Mp2 and Mp4 on the primary side, forming the resonant capacitor bridge arm of circuit unit A1 and A2; the primary side switch bridge arm and the resonant capacitor bridge arm are connected in parallel across the input filter inductor Lin or between the input negative terminal Vin- and the input midpoint Mgnd; the first node Mp1 and Mp3 on the primary side are connected in sequence to the same-name terminals of the resonant inductors Lr1 and Lr2 and the primary sides of transformers T1 and T2 through wires; the opposite-name terminals of the primary sides of transformers T1 and T2 are connected to the second node Mp2 and Mp4 on the primary side through wires. The sources of the first upper-side switching transistors S1, S5, S9, and S13, and the drains of the first lower-side switching transistors S2, S6, S10, and S14 of the full-bridge rectifier circuit are electrically connected to the first nodes Ms1, Ms3, Ms5, and Ms7 on the secondary side, forming the first switching arm of the full-bridge rectifier circuit. The drains of the first upper-side switching transistors S1, S5, S9, and S13 are connected to the positive output terminal Vo+ via wires, and the sources of the first lower-side switching transistors S2, S6, S10, and S14 are connected to the negative output terminal Vo- via wires. The sources of the second upper-side switching transistors S3, S7, S11, and S15, and the drains of the second lower-side switching transistor S4... The drains of S8, S12, and S16 are electrically connected to the second secondary nodes Ms2, Ms4, Ms6, and Ms8, forming the second switching arm of the full-bridge rectifier circuit; the drains of the second upper switching transistors S3, S7, S11, and S15 are connected to the positive output terminal Vo+ via wires, and the sources of the second lower switching transistors S4, S8, S12, and S16 are connected to the negative output terminal Vo- via wires; one end of the secondary windings of transformers T1 and T2 is electrically connected to the first secondary nodes Ms1, Ms3, Ms5, and Ms7, and the other end is electrically connected to the second secondary nodes Ms2, Ms4, Ms6, and Ms8.

[0005] As a preferred embodiment, the first control signal of the circuit unit is used to control the primary-side upper switch, the second control signal is used to control the primary-side lower switch; the third control signal is used to control the first upper switch and the second lower switch of the full-bridge synchronous rectifier circuit; the fourth control signal is used to control the first lower switch and the second upper switch of the full-bridge synchronous rectifier circuit; the first control signal and the second control signal are out of phase by 180 degrees, the third control signal is complementary to the second control signal, and the fourth control signal is complementary to the first control signal.

[0006] As a preferred approach, the four sets of corresponding control signals of the two circuit units are set to have the same frequency, duty cycle, and phase relationship.

[0007] As another preferred option, the four sets of corresponding control signals of the two circuit units are set with different frequencies, duty cycles or phase relationships to cope with the effects of actual circuit asymmetry or differences in resonance parameters.

[0008] As a preferred embodiment, the two transformers share a single integrated magnetic core. The resonant inductors Lr1 and Lr2 are the leakage inductances of the transformers themselves. The integrated magnetic core includes an upper substrate and a lower substrate, which have the same cross-sectional area. Between the upper substrate and the lower substrate, there are two transformer side posts and two transformer center posts with the same cross-sectional area, and the sum of the cross-sectional areas of the side posts is not less than the cross-sectional area of ​​a single center post. The primary winding of the first transformer is wound around the first transformer center post in a first direction, and the primary winding of the second transformer is wound around the second transformer center post in a second direction. The first and second directions are opposite.

[0009] As a preferred embodiment, the magnetic cores of the two transformers are two discrete magnetic cores arranged in parallel, and the resonant inductors Lr1 and Lr2 are the leakage inductance of the transformer itself; the magnetic core includes an upper substrate and a lower substrate, with the two side posts arranged between the upper substrate and the lower substrate, and the right middle post and the left middle post arranged inside the two side posts between the upper substrate and the lower substrate; the primary winding is wound around the left middle post and the right middle post of the transformer in a figure-eight pattern, and the total number of winding turns is determined according to the application requirements, and the length of the primary winding of the two transformers is the same.

[0010] As a preferred embodiment, the circuit board is also included, which has four through holes for the two side posts and two middle posts of the transformer core to pass through. The first full-bridge rectifier circuit on the secondary side of each circuit unit is arranged adjacent to one side of the core, and the second full-bridge rectifier circuit on the secondary side is arranged adjacent to the other side of the core.

[0011] As a preferred embodiment, each capacitor of the output filter capacitor Co is arranged adjacent to the first full-bridge rectifier circuit and / or the secondary side second full-bridge rectifier circuit.

[0012] As a preferred embodiment, one of the input capacitors Cin1 is located on the surface of the circuit board and is disposed adjacent to the primary-side upper switch Q1 and the primary-side lower switch Q2 of the first circuit unit; the other input capacitor Cin2 is located on the surface of the circuit board and is disposed adjacent to the primary-side upper switch Q3 and the primary-side lower switch Q4 of the second circuit unit. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of a power conversion device; Figure 2 As a control strategy; Figure 3 This is another control strategy; Figure 4 , 5 This refers to a form and winding method of magnetic components; Figure 6 , 7 This represents another form and winding method of magnetic components; Figure 8 This is a three-dimensional top view of the power conversion device; Figure 9 This is a three-dimensional bottom view of the power conversion device; Figure 10 This is a top-down exploded view of the power conversion device. Detailed Implementation

[0014] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0016] Figure 1 A circuit diagram of the power conversion device provided in this embodiment is shown. The power conversion device includes an input positive terminal Vin+, an input negative terminal Vin-, an output positive terminal Vo+, an output negative terminal Vo-, two circuit units A1 and A2, an input filter inductor Lin connected in series between the input positive terminal Vin+ and one of the circuit units, and an output filter capacitor Co connected across the output positive terminal Vo+ and the output negative terminal Vo-. Circuit units A1 and A2 include first input capacitors Cin1 and Cin2, primary-side upper switching transistors Q1 and Q3, primary-side lower switching transistors Q2 and Q4, primary-side upper resonant capacitors Cr1 and Cr3, primary-side lower resonant capacitors Cr2 and Cr4, resonant inductors Lr1 and Lr2, transformers T1 and T2, and two full-bridge rectifier circuits connected in parallel. The input capacitors Cin1 and Cin2 of the two circuit units are connected in series and then bridged between the end of the input filter inductor Lin and the input negative terminal Vin-; the midpoint between the two input capacitors Cin1 and Cin2 is denoted as the input midpoint Mgnd; the sources of the primary side upper switching transistors Q1 and Q3 and the drains of the primary side lower switching transistors Q2 and Q4 are electrically connected to the first node Mp1 and Mp3 of the primary side, forming the primary side switching bridge arm of circuit units A1 and A2; one end of the primary side upper resonant capacitors Cr1 and Cr3 and the primary side lower resonant capacitors Cr2 and Cr3 are connected to the primary side lower resonant capacitors Cr1 and Cr3. One end of 4 is electrically connected to the second node Mp2 and Mp4 on the primary side, forming the resonant capacitor bridge arm of circuit unit A1 and A2; the primary side switch bridge arm and the resonant capacitor bridge arm are connected in parallel across the input filter inductor Lin or between the input negative terminal Vin- and the input midpoint Mgnd; the first node Mp1 and Mp3 on the primary side are connected in sequence to the same-name terminals of the resonant inductors Lr1 and Lr2 and the primary sides of transformers T1 and T2 through wires; the opposite-name terminals of the primary sides of transformers T1 and T2 are connected to the second node Mp2 and Mp4 on the primary side through wires. The sources of the first upper-side switching transistors S1, S5, S9, and S13, and the drains of the first lower-side switching transistors S2, S6, S10, and S14 of the full-bridge rectifier circuit are electrically connected to the first nodes Ms1, Ms3, Ms5, and Ms7 on the secondary side, forming the first switching arm of the full-bridge rectifier circuit. The drains of the first upper-side switching transistors S1, S5, S9, and S13 are connected to the positive output terminal Vo+ via wires, and the sources of the first lower-side switching transistors S2, S6, S10, and S14 are connected to the negative output terminal Vo- via wires. The sources of the second upper-side switching transistors S3, S7, S11, and S15, and the drains of the second lower-side switching transistor S4... The drains of S8, S12, and S16 are electrically connected to the second secondary nodes Ms2, Ms4, Ms6, and Ms8, forming the second switching arm of the full-bridge rectifier circuit; the drains of the second upper switching transistors S3, S7, S11, and S15 are connected to the positive output terminal Vo+ via wires, and the sources of the second lower switching transistors S4, S8, S12, and S16 are connected to the negative output terminal Vo- via wires; one end of the secondary windings of transformers T1 and T2 is electrically connected to the first secondary nodes Ms1, Ms3, Ms5, and Ms7, and the other end is electrically connected to the second secondary nodes Ms2, Ms4, Ms6, and Ms8.

[0017] Figure 2The diagram shows the timing of the control signals. The first control signal PWM1 of the circuit unit controls the primary-side upper switches Q1 and Q3; the second control signal PWM2 controls the primary-side lower switches Q2 and Q4; the third control signal PWM3 controls the first upper switches S1, S5, S9, and S13, and the second lower switches S4, S8, S12, and S16 of the full-bridge rectifier circuit; the fourth control signal PWM4 controls the first lower switches S2, S6, S10, and S14, and the second upper switches S3, S7, S11, and S15 of the full-bridge rectifier circuit. The first control signal PWM1 and the second control signal PWM2 are out of phase by 180 degrees. The third control signal PWM3 is complementary to the second control signal PWM2, and the fourth control signal PWM4 is complementary to the first control signal PWM1. The four sets of corresponding control signals for the two circuit units are set to the same frequency, duty cycle, and have adjusted phase relationships.

[0018] Figure 3 The diagram shown is a timing diagram of the control signals in another embodiment. The four sets of corresponding control signals PWM1-PWM8 of the two circuit units are set with different frequencies, duty cycles or phase relationships to cope with the effects of actual circuit asymmetry or differences in resonance parameters.

[0019] To enable soft switching of the switches in the power conversion circuit, a certain dead time is set between the first control signal PWM1 (PWM5) and the fourth control signal PWM4 (PWM8), and a certain dead time is set between the second control signal PWM2 (PWM6) and the third control signal PWM3 (PWM7).

[0020] like Figure 4 , 5 As shown, two transformers share a single integrated magnetic core. The resonant inductors Lr1 and Lr2 are the leakage inductances of the transformers themselves. The integrated magnetic core includes an upper substrate and a lower substrate, which have the same cross-sectional area. Between the upper substrate and the lower substrate, there are two transformer side posts E and F with the same cross-sectional area, and two transformer middle posts C and D with the same cross-sectional area. The sum of the cross-sectional areas of the side posts is not less than the cross-sectional area of ​​a single middle post. The primary winding of the first transformer is wound around the first transformer middle post C in a first direction, and the primary winding of the second transformer is wound around the second transformer middle post D in a second direction. The first direction and the second direction are opposite.

[0021] like Figure 6 , 7As shown, the magnetic cores of the two transformers T1 and T2 are two discrete magnetic cores arranged in parallel. The resonant inductors Lr1 and Lr2 are the leakage inductances of the transformers themselves. The magnetic core includes an upper substrate and a lower substrate. The side posts E1, E2, F1, and F2 are located between the upper substrate and the lower substrate. The right center posts C1 and C2, and the left center posts D1 and D2 are located inside the two side posts E1, E2, F1, and F2 located between the upper substrate and the lower substrate. The primary winding of the first transformer is wound in a figure-eight pattern around the left center post D1 and the right center post C1. The primary winding of the second transformer is wound in a figure-eight pattern around the left center post D2 and the right center post C2. The total number of turns is determined according to the application requirements, and the primary winding lengths of the two transformers are the same.

[0022] like Figure 8-10 As shown, the power conversion device also includes a circuit board 10, which has four through slots 111, 112, 113, and 114 for the two side posts and two middle posts of the transformer core to pass through, respectively. The first full-bridge rectifier circuit on the secondary side of each circuit unit is arranged adjacent to one side of the core, and the second full-bridge rectifier circuit on the secondary side is arranged adjacent to the other side of the core.

[0023] An input capacitor Cin1 is located on the surface of the circuit board and is positioned near the primary-side upper switch Q1 and primary-side lower switch Q2 of the first circuit unit; another input capacitor Cin2 is located on the surface of the circuit board and is positioned near the primary-side upper switch Q3 and primary-side lower switch Q4 of the second circuit unit.

[0024] The primary side resonant capacitor Cr1 of the first circuit unit is located on the lower surface 102 of the circuit substrate 10, opposite to the primary side switch Q1 on the upper surface 101 of the circuit substrate 10. The two electrodes of the primary side resonant capacitor Cr1 are arranged parallel to the line connecting the drain and source of the primary side switch Q1. The primary side lower resonant capacitor Cr2 is located on the lower surface 102 of the circuit substrate 10, opposite to the primary side lower switch Q2 on the upper surface 101 of the circuit substrate 10. The two electrodes of the primary side lower resonant capacitor Cr2 are arranged parallel to the line connecting the drain and source of the primary side lower switch Q2. The primary side resonant capacitor Cr3 of the second circuit unit is located on the lower surface 102 and the upper surface 101 of the circuit substrate 10, opposite to the primary side switch Q3 of the second circuit unit. The two electrodes of the primary side resonant capacitor Cr3 are arranged parallel to the line connecting the drain and source of the primary side switch Q3 of the second circuit unit. The primary side lower resonant capacitor Cr4 of the second circuit unit is located on the lower surface 102 and the upper surface 101 of the circuit substrate 10, opposite to the primary side switch Q4 of the second circuit unit. The two electrodes of the primary side lower resonant capacitor Cr4 are arranged parallel to the line connecting the drain and source of the primary side switch Q4 of the second circuit unit.

[0025] The first upper switch S1, the first lower switch S2, the second upper switch S3, and the second lower switch S4 of the first full-bridge rectifier circuit of the first circuit unit A are disposed on the circuit board near one of the central pillars, next to the first side 211 of the magnetic core assembly. The first upper switch S5, the first lower switch S6, the second upper switch S7, and the second lower switch S8 of the second full-bridge rectifier circuit of the first circuit unit A are disposed on the circuit board near the central pillars, next to the second side 212 of the magnetic core assembly. The first upper switch S9, the first lower switch S10, the second upper switch S11, and the second lower switch S12 of the first full-bridge rectifier circuit of the second circuit unit B are disposed on the circuit board near the other central pillar, next to the first side 211 of the magnetic core assembly. The first upper switch S13, the first lower switch S14, the second upper switch S15, and the second lower switch S16 of the second full-bridge rectifier circuit of the second circuit unit B are disposed on the circuit board near the central pillar, next to the second side 212 of the magnetic core assembly.

[0026] Each individual capacitor of the output filter capacitor Co is positioned adjacent to the first full-bridge rectifier circuit and / or the secondary-side second full-bridge rectifier circuit. Two capacitor units 411 and 412 of the output capacitor Co are located on the upper surface 101 of the circuit board, while the other two output capacitor units 413 and 414 are located on the lower surface 102 of the circuit board, adjacent to the switching transistors of the full-bridge rectifier circuit. By placing the magnetic components, the switching transistors of the full-bridge rectifier circuit, and the output capacitors close together, the power path is shortened, reducing AC losses.

[0027] When the switching transistors S1 to S16 are used in high-power applications, they can be connected in parallel. The parallel switching transistors can be set on the lower surface 102 of the circuit board, opposite to the switching transistors on the upper surface 101.

[0028] This device is particularly suitable for applications with high input voltage levels, such as 800V high-voltage direct current (HVDC) power supply systems, and is especially suitable for use in the power architecture of artificial intelligence data centers (AIDC).

[0029] Figure 10 An exploded view of the power conversion device provided in this embodiment is shown. A heat dissipation substrate is provided on the circuit board, and a thermally conductive interface material layer is provided on the side of the heat dissipation substrate facing the circuit board. The magnetic core is also in contact with the heat dissipation substrate through thermally conductive adhesive or thermally conductive pads. The heat dissipation substrate is preferably an aluminum substrate or a copper substrate, and its upper surface may be further processed with heat dissipation fins or directly attached to the surface of the liquid cooling plate. Under the operating state of 800V HVDC input and full load output, the heat dissipation substrate can effectively diffuse the concentrated heat generated by the switching transistor and the distributed heat generated by the magnetic components laterally and transfer it longitudinally to the system air duct or liquid cooling circulation, ensuring that the junction temperature inside the power conversion device is lower than the rated derating temperature.

[0030] In this embodiment, the power conversion device is designed for AIDC (Artificial Intelligence Data Center) applications, with the input side directly connected to an 800V high-voltage DC bus. Due to the structure where the first and second circuit units are connected in series across the positive and negative input terminals, each circuit unit actually withstands an input voltage of only 400V. This allows the device to utilize lower-voltage, higher-performance medium-voltage switching transistors (such as 650V GaNHEMTs or SiC MOSFETs) even under 800V high-voltage input conditions, significantly reducing switching and conduction losses in high-voltage applications and meeting the stringent requirements of AIDC for high efficiency and ultra-high power density in power modules.

[0031] The above embodiments are merely illustrative of the principles and effects of the present invention, as well as some examples of its application, and are not intended to limit the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements are all within the scope of protection of the present invention.

Claims

1. A power conversion device, comprising an input positive terminal Vin+, an input negative terminal Vin-, an output positive terminal Vo+, an output negative terminal Vo-, two circuit units A1 and A2, an input filter inductor Lin connected in series between the input positive terminal Vin+ and one of the circuit units, and an output filter capacitor Co connected across the output positive terminal Vo+ and the output negative terminal Vo-. Its features are: The circuit units A1 and A2 include first input capacitors Cin1 and Cin2, primary-side upper switching transistors Q1 and Q3, primary-side lower switching transistors Q2 and Q4, primary-side upper resonant capacitors Cr1 and Cr3, primary-side lower resonant capacitors Cr2 and Cr4, resonant inductors Lr1 and Lr2, transformers T1 and T2, and two full-bridge rectifier circuits connected in parallel. The input capacitors Cin1 and Cin2 of the two circuit units are connected in series and then bridged between the end of the input filter inductor Lin and the input negative terminal Vin-; the midpoint between the two input capacitors Cin1 and Cin2 is denoted as the input midpoint Mgnd; the sources of the primary side upper switching transistors Q1 and Q3 and the drains of the primary side lower switching transistors Q2 and Q4 are electrically connected to the first node Mp1 and Mp3 of the primary side, forming the primary side switching bridge arm of circuit units A1 and A2; one end of the primary side upper resonant capacitors Cr1 and Cr3 and the primary side lower resonant capacitors Cr2 and Cr3 are connected to the primary side lower resonant capacitors Cr1 and Cr3. One end of 4 is electrically connected to the second node Mp2 and Mp4 on the primary side, forming the resonant capacitor bridge arm of circuit unit A1 and A2; the primary side switch bridge arm and the resonant capacitor bridge arm are connected in parallel across the input filter inductor Lin or between the input negative terminal Vin- and the input midpoint Mgnd; the first node Mp1 and Mp3 on the primary side are connected in sequence to the same-name terminals of the resonant inductors Lr1 and Lr2 and the primary sides of transformers T1 and T2 through wires; the opposite-name terminals of the primary sides of transformers T1 and T2 are connected to the second node Mp2 and Mp4 on the primary side through wires. The sources of the first upper-side switching transistors S1, S5, S9, and S13, and the drains of the first lower-side switching transistors S2, S6, S10, and S14 of the full-bridge rectifier circuit are electrically connected to the first nodes Ms1, Ms3, Ms5, and Ms7 on the secondary side, forming the first switching arm of the full-bridge rectifier circuit. The drains of the first upper-side switching transistors S1, S5, S9, and S13 are connected to the positive output terminal Vo+ via wires, and the sources of the first lower-side switching transistors S2, S6, S10, and S14 are connected to the negative output terminal Vo- via wires. The sources of the second upper-side switching transistors S3, S7, S11, and S15, and the drains of the second lower-side switching transistor S4... The drains of S8, S12, and S16 are electrically connected to the second secondary nodes Ms2, Ms4, Ms6, and Ms8, forming the second switching arm of the full-bridge rectifier circuit; the drains of the second upper switching transistors S3, S7, S11, and S15 are connected to the positive output terminal Vo+ via wires, and the sources of the second lower switching transistors S4, S8, S12, and S16 are connected to the negative output terminal Vo- via wires; one end of the secondary windings of transformers T1 and T2 is electrically connected to the first secondary nodes Ms1, Ms3, Ms5, and Ms7, and the other end is electrically connected to the second secondary nodes Ms2, Ms4, Ms6, and Ms8.

2. The power conversion device as described in claim 1, characterized in that: The first control signal of the circuit unit is used to control the primary side upper switch, and the second control signal is used to control the primary side lower switch; the third control signal is used to control the first upper switch and the second lower switch of the full-bridge rectifier circuit; the fourth control signal is used to control the first lower switch and the second upper switch of the full-bridge rectifier circuit; the first control signal and the second control signal are out of phase by 180 degrees, the third control signal is complementary to the second control signal, and the fourth control signal is complementary to the first control signal.

3. The power conversion device as described in claim 2, characterized in that: The four sets of corresponding control signals of the two circuit units are set to have the same frequency, duty cycle, and phase relationship.

4. A power conversion device as described in claim 2, characterized in that: The four sets of corresponding control signals of the two circuit units are set with different frequencies, duty cycles or phase relationships to cope with the effects of actual circuit asymmetry or differences in resonance parameters.

5. A power conversion device as described in claim 1, characterized in that: Two transformers share a single integrated magnetic core. The resonant inductors Lr1 and Lr2 are the leakage inductances of the transformers themselves. The integrated magnetic core includes an upper substrate and a lower substrate with the same cross-sectional area. Between the upper substrate and the lower substrate, there are two transformer side posts with the same cross-sectional area and two transformer center posts with the same cross-sectional area, and the sum of the cross-sectional areas of the side posts is not less than the cross-sectional area of ​​a single center post. The primary winding of the first transformer is wound around the first transformer center post in a first direction, and the primary winding of the second transformer is wound around the second transformer center post in a second direction. The first direction and the second direction are opposite.

6. The power conversion device as described in claim 1, characterized in that: The magnetic cores of the two transformers are two discrete magnetic cores arranged in parallel. The resonant inductors Lr1 and Lr2 are the leakage inductance of the transformer itself. The magnetic core includes an upper substrate and a lower substrate. The two side posts are arranged between the upper substrate and the lower substrate. The right middle post and the left middle post are arranged inside the two side posts between the upper substrate and the lower substrate. The primary winding is wound around the left middle post and the right middle post of the transformer in a figure-eight pattern. The total number of turns of the winding is determined according to the application requirements, and the length of the primary winding of the two transformers is the same.

7. A power conversion device as described in any one of claims 1-6, characterized in that: It also includes a circuit board with four through holes for the two side posts and two center posts of the transformer core to pass through. The first full-bridge rectifier circuit on the secondary side of each circuit unit is located adjacent to one side of the core, and the second full-bridge rectifier circuit on the secondary side is located adjacent to the other side of the core.

8. A power conversion device as described in claim 7, characterized in that: Each individual capacitor of the output filter capacitor Co is arranged adjacent to the first full-bridge rectifier circuit and / or the secondary side second full-bridge rectifier circuit.

9. A power conversion device as described in claim 7, characterized in that: One of the input capacitors, Cin1, is located on the surface of the circuit board and is disposed near the primary-side upper switch Q1 and the primary-side lower switch Q2 of the first circuit unit; the other input capacitor, Cin2, is located on the surface of the circuit board and is disposed near the primary-side upper switch Q3 and the primary-side lower switch Q4 of the second circuit unit.

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