Wide range soft-switching phase-shifted full-bridge converter and control method thereof

Abstract

The present application relates to the technical field of DC converter, and discloses a wide-range soft-switching phase-shifted full-bridge converter and a control method thereof, which comprises a primary side circuit, a secondary side rectifier circuit and an auxiliary circuit.The primary side circuit comprises a leading arm and a lagging arm, and the auxiliary circuit is connected in parallel across the lagging arm and internally comprises two auxiliary switch tubes connected in series and a shared auxiliary inductor; during the dead time of the lagging arm when the upper and lower tubes are switched, the control loop outputs a pulse signal to drive the corresponding auxiliary switch tube to conduct for a short time, and the auxiliary inductor provides a discharge circuit for the parasitic capacitor of the lagging arm main switch tube which is about to conduct.The present application uses the auxiliary inductor to draw the charge in the parasitic capacitor, solves the technical pain point of the difficulty of soft switching of the lagging arm, realizes wide-range zero-voltage turn-on and reduces the conduction loss, and simultaneously adopts a topology structure of alternating multiplexing single auxiliary inductor, effectively reduces the number of components, and reduces the size and manufacturing cost of the converter.

Description

Technical Field

[0001] This invention relates to the field of DC-DC converter technology, specifically to a wide-range soft-switching phase-shifting full-bridge converter and its control method. Background Technology

[0002] A phase-shifted full-bridge converter is a high-frequency soft-switching DC-DC converter topology. Its basic structure consists of an H-bridge composed of four primary-side switches, a series resonant inductor, a high-frequency transformer, and a secondary-side rectifier circuit. This converter controls the output voltage by adjusting the phase shift angle and features high switching frequency, high power density, and high reliability. It is commonly used in DC / DC converters for new energy vehicles to convert high-voltage power into low-voltage power to supply batteries and low-voltage systems.

[0003] Traditional phase-shifted full-bridge converters suffer from the technical challenge of achieving soft switching in the lagging arm during operation. Before the lagging arm switch switches, the transformer primary side is short-circuited, and the secondary-side filter inductor cannot provide energy to the primary side. This makes it difficult to completely remove the charge stored in the parasitic capacitance of the lower or upper lagging arm switch. This situation increases the difficulty of achieving zero-voltage turn-on for the lagging arm, limiting the overall soft-switching operating range of the converter and increasing conduction losses.

[0004] To address the limited range of soft switching in the lagging arm, existing topology optimization primarily focuses on adding auxiliary circuits to the main circuit. While introducing passive auxiliary circuits in existing solutions avoids complex control programs, the energy required for their operation is often extracted from the soft switching process of the leading arm. This actually increases losses in the main circuit during actual operation, resulting in limited overall improvement. To achieve precise energy injection, existing active auxiliary network solutions typically add two independent auxiliary branches on the lagging arm side to inject auxiliary energy into the lagging arm at specific times. However, this independent branch design requires the simultaneous configuration of two switches, two inductors, and two capacitors. The excessive number of passive and active components complicates the converter's hardware structure, increasing manufacturing costs and occupying more physical space, ultimately reducing the overall power density of the system. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a wide-range soft-switching phase-shifted full-bridge converter and its control method, which solves the problems of the traditional phase-shifted full-bridge converter's lagging arm being unable to achieve wide-range zero-voltage turn-on, and the large size and high cost caused by the large number of auxiliary circuit components.

[0006] To achieve the above objectives, the present invention provides a wide-range soft-switching phase-shifted full-bridge converter, comprising a DC input voltage terminal, a phase-shifted full-bridge circuit, a secondary-side rectifier circuit, and an auxiliary circuit. The phase-shifted full-bridge circuit includes a leading arm and a lagging arm connected in parallel across the DC input voltage terminal. The center point of the leading arm is connected to the primary side of a transformer via a resonant inductor Lr. The primary side of the transformer is connected to the center point of the lagging arm. The secondary-side rectifier circuit is connected to the secondary side of the transformer. The auxiliary circuit is connected in parallel across the lagging arm. The auxiliary circuit includes a series-connected MOS5 and MOS6 switch and an auxiliary inductor La. One end of the auxiliary inductor La is connected to the series center point of the MOS5 and MOS6 switch, and the other end of the auxiliary inductor La is connected to the center point of the lagging arm.

[0007] Preferably, the leading arm includes a series-connected MOS1 leading arm upper transistor and MOS2 leading arm lower transistor, and the lagging arm includes a series-connected MOS3 lagging arm upper transistor and MOS4 lagging arm lower transistor.

[0008] The MOS1 upper lead arm transistor, the MOS2 lower lead arm transistor, the MOS3 upper lagging arm transistor, and the MOS4 lower lagging arm transistor are all connected in parallel with parasitic capacitance Coss.

[0009] Preferably, the secondary rectifier circuit is a full-wave synchronous rectifier circuit;

[0010] The secondary side of the transformer is connected to MOS7 and MOS8 switches. The MOS7 and MOS8 switches are connected together and then connected to one end of the filter inductor Lf. The other end of the filter inductor Lf is connected to one end of the filter capacitor Cf and one end of the load resistor Rd.

[0011] The secondary side of the transformer has a central shaft head, which is grounded and connected to the other end of the filter capacitor Cf and the other end of the load resistor Rd.

[0012] Preferably, it further includes a control circuit, which outputs a pulse signal to drive the MOS6 switch to turn on during the dead time before the upper transistor of the lagging arm of MOS3 is turned off and the lower transistor of the lagging arm of MOS4 is turned on, and provides a discharge circuit for the center point of the lagging arm through the auxiliary inductor La. It also outputs a pulse signal to drive the MOS5 switch to turn on during the dead time before the lower transistor of the lagging arm of MOS4 is turned off and the upper transistor of the lagging arm of MOS3 is turned on, and provides a discharge circuit for the center point of the lagging arm through the auxiliary inductor La.

[0013] A control method for a wide-range soft-switching phase-shifting full-bridge converter includes the following steps:

[0014] The dual closed-loop feedback signal is acquired, and the phase shift angle is output after control calculation.

[0015] Based on the phase shift angle, the set switching frequency, the dead time, and the current system time, the switching cycle, the timing node position of the current system time relative to the switching cycle, and the delay time are calculated. After condition judgment, the main drive signal used to control the conduction and turn-off of MOS1 upper leading arm transistor, MOS2 lower leading arm transistor, MOS3 upper lagging arm transistor, and MOS4 lower lagging arm transistor is output.

[0016] After the main drive signal of the upper transistor of the lagging arm of MOS3 becomes off, the first pulse signal is output to control the MOS6 switch to be turned on for a first preset time, and the auxiliary inductor La provides a discharge circuit for the parasitic capacitance Coss connected in parallel to the lower transistor of the lagging arm of MOS4.

[0017] After the main drive signal of the lower transistor of the MOS4 lagging arm becomes off, the second pulse signal is output to control the MOS5 switch to turn on for a second preset time, and the auxiliary inductor La provides a discharge circuit for the parasitic capacitance Coss connected in parallel to the upper transistor of the MOS3 lagging arm.

[0018] Preferably, the output is a main drive signal used to control the on / off state of the MOS1 leading arm upper transistor, the MOS2 leading arm lower transistor, the MOS3 lagging arm upper transistor, and the MOS4 lagging arm lower transistor, specifically including:

[0019] The upper transistor of the MOS1 front arm and the lower transistor of the MOS2 front arm are controlled to conduct alternately in the same cycle, and there is a dead time between the turn-off of one transistor and the turn-on of the other transistor.

[0020] The upper MOSFET of the hysteresis arm of MOS3 and the lower MOSFET of the hysteresis arm are controlled to conduct alternately within the same cycle, and there is a dead time between the turn-off of one MOSFET and the turn-on of the other MOSFET.

[0021] Preferably, in the main drive signal, the conduction state of the lagging arm lags behind the conduction state of the leading arm by a delay time, and the delay time is determined by the phase shift angle.

[0022] Preferably, the step of acquiring the dual closed-loop feedback signal and calculating the output phase shift angle by control specifically includes: acquiring the output voltage and output current as the dual closed-loop feedback signal, and outputting the phase shift angle by proportional-integral control.

[0023] Preferably, the triggering time of the first pulse signal is the falling edge of the main drive signal of the upper transistor of the MOS3 hysteresis arm;

[0024] The trigger time of the second pulse signal is the falling edge of the main drive signal of the lower MOSFET of the MOS4 hysteresis arm.

[0025] Preferably, the duration of the first preset time satisfies the following condition: before the lower MOSFET of the MOS4 lagging arm is turned on, the voltage across the lower MOSFET of the MOS4 lagging arm drops to zero.

[0026] The duration of the second preset time satisfies the following condition: before the upper transistor of the MOS3 lagging arm is turned on, the voltage across the upper transistor of the MOS3 lagging arm drops to zero.

[0027] The above solution achieves the following beneficial technical effects:

[0028] This application solves the technical problem of the lagging arm in traditional phase-shifted full-bridge converters being unable to achieve zero-voltage turn-on due to primary-side short circuits. By connecting an auxiliary circuit consisting of an auxiliary switch and an auxiliary inductor in parallel across the lagging arm of the phase-shifted full-bridge converter, and controlling the corresponding auxiliary switch to briefly turn on during the dead time before the main switch of the lagging arm turns on, an additional discharge loop is provided for the center point of the lagging arm. By utilizing the energy accumulated inside the auxiliary inductor, the charge in the parasitic capacitance of the lagging arm switch is completely removed. This reduces the conduction loss of the switch and enables the converter to maintain a soft-switching state over a wider load power range and improve overall operating efficiency.

[0029] This application employs a topology architecture in which two series-connected auxiliary switches share the same auxiliary inductor, allowing the upper and lower switches of the lagging arm to alternately share the auxiliary inductor for discharge. Compared with the traditional approach of configuring a resonant network independently for each switch, this design minimizes the number of magnetic components and semiconductor devices required while achieving equivalent soft-switching functionality. This reduces the additional conduction losses introduced by the auxiliary circuit itself and effectively controls the overall size and manufacturing cost of the converter hardware.

[0030] This application employs a full-wave synchronous rectification circuit based on the center shaft head in the secondary rectifier circuit of the transformer, utilizing a MOSFET with low on-resistance for rectification. Compared to conventional full-bridge rectification or diode rectification topologies, this design reduces the forward conduction voltage drop and power loss on the rectifier side. Combined with the loss reduction effect of the primary side wide-range soft-switching technology, this converter system exhibits higher thermal stability and power conversion efficiency in practical applications with low-voltage, high-current output. Attached Figure Description

[0031] Figure 1 A circuit topology diagram of a wide-range soft-switching phase-shifting full-bridge converter provided in an embodiment of the present invention;

[0032] Figure 2This is a simulation waveform diagram of the soft-switching implementation without auxiliary circuitry in an embodiment of the present invention;

[0033] Figure 3 This is a simulation waveform diagram of the soft-switching implementation under light load conditions in an embodiment of the present invention;

[0034] Figure 4 This is a simulation waveform diagram of the soft-switching implementation under heavy load conditions in an embodiment of the present invention;

[0035] Figure 5 This is a flowchart illustrating a control method for a wide-range soft-switching phase-shifting full-bridge converter according to an embodiment of the present invention.

[0036] Among them, 1. DC input voltage terminal; 2. MOS1 upper leading arm transistor; 3. MOS2 lower leading arm transistor; 4. MOS3 upper lagging arm transistor; 5. MOS4 lower lagging arm transistor; 6. Parasitic capacitance Coss; 7. Resonant inductor Lr; 8. Transformer; 9. MOS7 switch transistor; 10. MOS8 switch transistor; 11. Filter inductor Lf; 12. Filter capacitor Cf; 13. Load resistor Rd; 14. Auxiliary inductor La; 15. MOS5 switch transistor; 16. MOS6 switch transistor. Detailed Implementation

[0037] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] See attached document Figure 1 This invention provides a wide-range soft-switching phase-shifted full-bridge converter, characterized by comprising a DC input voltage terminal 1, a phase-shifted full-bridge circuit, a secondary-side rectifier circuit, and an auxiliary circuit. The phase-shifted full-bridge circuit includes an advanced arm and a lagging arm connected in parallel across the DC input voltage terminal 1. The center point of the advanced arm is connected to the primary side of a transformer 8 via a resonant inductor Lr7. The primary side of the transformer 8 is connected to the center point of the lagging arm. The secondary-side rectifier circuit is connected to the secondary side of the transformer 8. The auxiliary circuit is connected in parallel across the lagging arm and includes a series-connected MOS5 switch 15 and MOS6 switch 16, and an auxiliary inductor La14. One end of the auxiliary inductor La14 is connected to the series center point of the MOS5 switch 15 and MOS6 switch 16, and the other end of the auxiliary inductor La14 is connected to the center point of the lagging arm.

[0039] Specifically, the phase-shifted full-bridge circuit uses four MOSFETs to form an H-bridge topology. By adjusting the phase difference of the main drive signals of the leading and lagging arms, the power transmitted to the secondary side of transformer 8 is controlled. During this operation, the switching transistors of the leading arm mainly rely on the series resonant inductor Lr7 and the energy referred from the secondary side of transformer 8 to the primary side to complete the state switching and achieve zero-voltage turn-on. However, for the lagging arm, since the primary side of transformer 8 is in a short-circuit state before its state switching, it cannot provide enough energy to extract the charge inside the parasitic capacitor. In order to solve the technical defect of soft switching failure of the lagging arm, this invention connects an auxiliary circuit in parallel at the center point of the lagging arm. Unlike the structure of two independent auxiliary branches used in the prior art, the auxiliary circuit of this invention uses a structure of MOSFET5 switch 15 and MOSFET6 switch 16 connected in series and alternately sharing the same auxiliary inductor La14. While providing precise discharge energy to the lagging arm, it effectively reduces the number of magnetic components and active devices in the system, thereby reducing the overall physical size of the converter and improving the overall power density of the system.

[0040] The leading arm includes the upper MOSFET 2 of MOS1 leading arm and the lower MOSFET 3 of MOS2 leading arm connected in series, and the lagging arm includes the upper MOSFET 4 of MOS3 lagging arm and the lower MOSFET 5 of MOS4 lagging arm connected in series.

[0041] The upper transistor of MOS1 (lead arm 2), the lower transistor of MOS2 (lead arm 3), the upper transistor of MOS3 (lagging arm 4), and the lower transistor of MOS4 (lagging arm 5) are all connected in parallel with parasitic capacitance Coss6.

[0042] Specifically, the leading and lagging arms together form a full-bridge inverter network. The four main switches, under the drive signal output from the control loop, alternately turn on and off according to a specific timing sequence, converting the DC input voltage provided at terminal 1 into high-frequency AC and transmitting it to the resonant network. MOS1 leading arm upper transistor 2, MOS2 leading arm lower transistor 3, MOS3 lagging arm upper transistor 4, and MOS4 lagging arm lower transistor 5 are all power semiconductor devices. When the switches are off, the DC side voltage causes the parasitic capacitor Coss6 connected in parallel to them to be in a charging state and store charge. In hard-switching mode, at the instant the switches are turned on, the charge stored inside the parasitic capacitor Coss6 is directly released through the internal conduction channel of the switches, generating transient current and converting it into heat energy, leading to a sharp increase in conduction losses. Therefore, to achieve high-frequency operation of the converter, before each switch receives the turn-on signal, the charge across the parasitic capacitor Coss6 must be completely removed through a specific topology loop, reducing the voltage across the switches to zero to meet the physical conditions for soft-switching.

[0043] The secondary rectifier circuit is a full-wave synchronous rectifier circuit;

[0044] The secondary side of transformer 8 is connected to MOS7 switch 9 and MOS8 switch 10. After MOS7 switch 9 and MOS8 switch 10 are connected together, they are connected to one end of filter inductor Lf11. The other end of filter inductor Lf11 is connected to one end of filter capacitor Cf12 and one end of load resistor Rd13.

[0045] The secondary side of transformer 8 has a central shaft head, which is grounded and connected to the other end of filter capacitor Cf12 and the other end of load resistor Rd13.

[0046] Specifically, transformer 8 mainly serves as an electrical isolation and voltage conversion unit, coupling the high-frequency AC energy from the primary side to the secondary circuit. The secondary side uses a transformer winding with a central shaft head structure, combined with MOS7 switch 9 and MOS8 switch 10 to form a full-wave synchronous rectification network. Existing phase-shifted full-bridge converters often use diodes for rectification on the secondary side. The inherent forward voltage drop of diodes will generate rectification losses. This invention uses wide-bandgap semiconductor switches with low on-resistance to replace diodes. The two synchronous rectification switches alternately conduct, converting the high-frequency AC output from the secondary side of transformer 8 into pulsating DC, thereby reducing the power loss on the secondary side and improving the conversion efficiency. Subsequently, the pulsating DC enters a low-pass filter network composed of filter inductor Lf11 and filter capacitor Cf12. Filter inductor Lf11 limits the sudden change of current and stores magnetic field energy, while filter capacitor Cf12 absorbs voltage ripple and smooths the output waveform. The two work together to convert the pulsating DC into stable DC, which is finally delivered to the load resistor Rd13 for use by the external low-voltage system.

[0047] It also includes a control circuit. During the dead time before the upper transistor 4 of the lagging arm of MOS3 is turned off and the lower transistor 5 of the lagging arm of MOS4 is turned on, the control circuit outputs a pulse signal to drive the MOS6 switch 16 to turn on, and provides a discharge circuit for the center point of the lagging arm through the auxiliary inductor La14. During the dead time before the lower transistor 5 of the lagging arm of MOS4 is turned off and the upper transistor 4 of the lagging arm of MOS3 is turned on, the control circuit outputs a pulse signal to drive the MOS5 switch 15 to turn on, and provides a discharge circuit for the center point of the lagging arm through the auxiliary inductor La14.

[0048] Specifically, the control loop intervenes in the auxiliary circuit through a predetermined logic timing. Taking the working cycle before the lower transistor of the lagging arm is turned on as an example, when the upper transistor 4 of the lagging arm of MOS3 receives the turn-off command and stops conducting, both the upper and lower transistors of the lagging arm are in the dead time of turn-off. Since the primary side of transformer 8 is short-circuited at this time, the main circuit current of the primary side cannot discharge the parasitic capacitance of the lower transistor. During this dead time, the control loop outputs a specific pulse signal to make the MOS6 switch transistor 16 enter the conducting state. At this time, one end of the auxiliary inductor La14 is grounded through the MOS6 switch transistor 16, and the other end is connected to the center point of the lagging arm, thereby constructing a bypass channel outside the main circuit. The charge stored inside the parasitic capacitance Coss6 of the lower MOSFET 5 in the lagging arm of MOS4 flows into the auxiliary inductor La14 along this channel, and the voltage across the parasitic capacitance Coss6 drops accordingly. In the other half of the operating cycle, when the lower MOSFET 5 in the lagging arm of MOS4 is turned off and enters the dead time, the control circuit outputs a pulse signal to drive the MOSFET 5 switch 15 to turn on. During this half cycle, the auxiliary inductor La14 is reused to provide a physical path for the release of charge of the parasitic capacitance Coss6 of the upper MOSFET 4 in the lagging arm of MOS3.

[0049] See attached document Figure 4 The present invention also provides a control method for a wide-range soft-switching phase-shifting full-bridge converter, comprising the following steps:

[0050] The dual closed-loop feedback signal is acquired, and the phase shift angle is output after control calculation.

[0051] Based on the phase shift angle, the set switching frequency, the dead time, and the current system time, the switching cycle, the timing node position of the current system time relative to the switching cycle, and the delay time are calculated. After condition judgment, the main drive signal is output to control the conduction and turn-off of MOS1 upper arm 2, MOS2 lower arm 3, MOS3 upper arm 4, and MOS4 lower arm 5.

[0052] After the main drive signal of the upper transistor 4 of the lagging arm of MOS3 becomes off, the first pulse signal is output to control the switching transistor 16 of MOS6 to conduct for a first preset time, and the parasitic capacitance Coss6 connected in parallel to the lower transistor 5 of MOS4 is provided by the auxiliary inductor La14.

[0053] After the main drive signal of the lower transistor 5 of the lagging arm of MOS4 becomes off, the second pulse signal is output to control the switching transistor 15 of MOS5 to conduct for a second preset time, and the parasitic capacitance Coss6 connected in parallel to the upper transistor 4 of the lagging arm of MOS3 is provided by the auxiliary inductor La14.

[0054] Specifically, the current output state is obtained through sampling, and a closed-loop algorithm is used to generate the phase shift angle that determines the transmission power. In the calculation of the specific control flow, the system converts the input setting switching frequency into the corresponding switching cycle and obtains the current simulation time in real time. By calculating the remainder of the current simulation time divided by the switching cycle, the specific relative position of the current time point within the control cycle is accurately determined. At the same time, the specific delay time of the lagging arm relative to the leading arm is calculated using the phase shift angle calculated by the closed loop. Finally, the control loop judges the above remainder and delay time through the set logic conditions, and outputs the basic control timing of the four primary-side main switches respectively. It is required that the upper and lower arms of the leading and lagging arms should avoid conducting simultaneously within the same cycle, so as to ensure the safety of the devices and stabilize the output voltage at the set reference value.

[0055] The output is used to control the on / off state of MOS1 (leader arm upper transistor 2), MOS2 (leader arm lower transistor 3), MOS3 (lag arm upper transistor 4), and MOS4 (lag arm lower transistor 5), specifically including:

[0056] The upper transistor 2 of the leading arm of MOS1 and the lower transistor 3 of the leading arm of MOS2 are alternately turned on in the same cycle, and there is a dead time between the turn-off of one transistor and the turn-on of the other transistor.

[0057] The upper transistor 4 of the lagging arm of MOS3 and the lower transistor 5 of the lagging arm of MOS4 are alternately turned on in the same cycle, and there is a dead time between the turn-off of one transistor and the turn-on of the other transistor.

[0058] Specifically, the switching transistors are driven by generating a complementary pulse width modulation signal with a dead time. The main engineering significance of setting the dead time is to prevent bridge arm shoot-through short-circuit faults. Because there is a certain physical delay in the recombination of charge carriers and the discharge of junction capacitance after receiving a turn-off command, absolutely instantaneous turn-off cannot be achieved. If a turn-on command is immediately sent to the transistor before the upper transistor in the same bridge arm has been completely turned off, the positive and negative terminals of DC input voltage terminal 1 will form a low-impedance shoot-through circuit directly through the upper and lower transistors. The resulting short-circuit surge current will directly burn out the power device. In addition, the dead time also provides the necessary time window for the discharge of parasitic capacitance Coss6 and the natural conduction of the anti-parallel body diode inside the switching device. Only when the charge transfer operation is completed within this time interval, so that the transistor voltage drop returns to zero, can the subsequent main drive turn-on signal meet the zero-voltage turn-on condition.

[0059] The main drive signal causes the conduction state of the lagging arm to be delayed by a certain period of time compared to the conduction state of the leading arm. The delay period is determined by the phase shift angle.

[0060] Specifically, the phase-shifted full-bridge topology does not rely on changing the basic switching frequency or the duty cycle of a single transistor to adjust power. Instead, it controls power transfer by controlling the time overlap of the diagonal switches of the leading and lagging arms being in the same conducting state. In steady-state operation, the main drive signal of the leading arm is triggered as a reference phase, while the main drive signal of the lagging arm is delayed by a fixed time difference relative to this reference phase. This time difference is reflected in the specific phase shift angle. The primary winding of transformer 8 will only form a voltage difference and construct a closed loop for energy transfer when the upper transistor of the leading arm and the lower transistor of the lagging arm, or the lower transistor of the leading arm and the upper transistor of the lagging arm, are simultaneously conducting. Therefore, the magnitude of the phase shift angle directly determines the effective time proportion of energy transfer from the primary side to the secondary side of transformer 8 within a complete switching cycle. When the load changes and an increase in output power is required, the control loop reduces the delay time, making the phase shift angle smaller and increasing the pulse width of the primary side energy transfer. This increases the delay time to reduce the amount of energy transferred, thereby maintaining constant output parameters.

[0061] The process involves acquiring dual closed-loop feedback signals and calculating the output phase shift angle. Specifically, this includes acquiring the output voltage and output current as dual closed-loop feedback signals and controlling the output phase shift angle using proportional-integral control.

[0062] Specifically, the measurement circuit acquires the actual output voltage across the load resistor Rd13 and the actual output current flowing through the filter inductor Lf11 in real time, and continuously inputs these feedback signals to the microcontroller. The controller internally performs a mathematical subtraction operation between the sampled actual feedback value and a pre-set reference target value in the program to generate an error signal. Subsequently, a proportional-integral (PI) controller processes this error signal using an algorithm. The proportional control amplifies the error signal to accelerate the system's response to drastic fluctuations in output voltage or current, while the integral control performs time-integral accumulation of the error signal. Its main function is to eliminate steady-state errors in the control system and ensure the output voltage accuracy of the converter during long-term operation. The final output value of the PI control algorithm is directly mapped to the phase shift angle parameter required by the PWM module to generate the drive signal, realizing a dynamic negative feedback adjustment mechanism.

[0063] The trigger time of the first pulse signal is the falling edge of the main drive signal of the upper transistor 4 of the MOS3 hysteresis arm;

[0064] The trigger time of the second pulse signal is the falling edge of the main drive signal of the lower transistor 5 of the MOS4 hysteresis arm.

[0065] Specifically, the falling edge of the main drive signal transitioning from high to low represents, at the circuit physical level, the control port officially issuing a turn-off command to the main switch. This node is also the starting boundary for the system state to transition from the conduction phase to the dead-time phase. Using the falling edge as the reference zero point for triggering the auxiliary pulse signal aims to ensure the synchronization of the timing of the main working circuit and the operation of the auxiliary discharge circuit. If the auxiliary pulse signal is triggered after the start of the dead time, the originally limited dead time will be partially wasted, preventing the auxiliary inductor La14 from obtaining sufficient conduction duration to establish sufficient discharge current, thus causing incomplete charge extraction from the parasitic capacitor Coss6. If the signal is triggered prematurely before the falling edge, it will cause the main switch and auxiliary circuit devices to conduct simultaneously, disrupting the normal operation of the original bridge arm. Strictly using the falling edge of the main drive signal as the pulse trigger point ensures that the auxiliary circuit intervenes immediately at the first instant of dead-time activation.

[0066] The duration of the first preset time is satisfied that the voltage across the lower MOSFET 5 of the MOSFET 4 lagging arm drops to zero before the lower MOSFET 5 of the MOSFET 4 lagging arm is turned on.

[0067] The second preset time duration satisfies the following condition: before the upper transistor 4 of the lagging arm of MOS3 is turned on, the voltage across the upper transistor 4 of the lagging arm of MOS3 drops to zero.

[0068] Specifically, the first and second preset times define the actual physical duration for which MOS6 switch 16 and MOS5 switch 15 in the auxiliary circuit maintain a high-level conduction state after responding to the pulse signal. During this conduction duration, the auxiliary inductor La14 continuously provides charge extraction current. Combined with waveform monitoring results during operation, the voltage between the drain and source of the lagging arm main switch (e.g., the lower MOS4 lagging arm switch 5) exhibits a continuous decreasing trajectory. When the preset time ends, and the rising edge of the subsequent main drive signal triggers the main switch to formally receive the conduction command, the voltage across the main switch has already dropped to 0V in advance due to the discharge effect of the auxiliary inductor. At this time, the internal channel of the switch is opened in a physical state where there is no potential difference between the drain and source, avoiding the power dissipation phenomenon caused by the overlap of voltage and current waveforms at the moment of conduction in the traditional hard-switching mode. By setting an accurate preset conduction time to force the voltage drop of the switch to zero, the lagging arm is given zero-voltage conduction characteristics across the entire load range, reducing conduction losses.

[0069] To further verify the technical effectiveness of the proposed solution, please refer to the appendix. Figure 2 To be continued Figure 4 A comparative analysis of the simulation waveforms is performed. In the figure, the rectangular pulse waveform represents the main drive signal of the corresponding MOSFET, and the smooth waveform represents the voltage drop across the corresponding MOSFET.

[0070] See attached document Figure 2 The simulation results for soft switching without auxiliary circuitry show that, under the traditional phase-shifted full-bridge topology, the measured voltage drops Vlead1 and Vlead2 of the leading arm transistors can drop to zero before the drive signal is turned on, thanks to the energy of the primary circuit. However, for the lagging arm composed of MOS3 and MOS4, their voltage drops Vlag3 and Vlag4 fail to return to zero completely before the rising edge of the drive signal arrives, forcing the switching transistors to conduct while a potential difference exists between their ends, resulting in a hard switching phenomenon.

[0071] See attached document Figure 3 The simulation results of the soft-switching implementation under light load conditions are shown in the attached diagram. Figure 4 The simulation results of the soft-switching implementation under heavy load conditions, as shown, demonstrate that after introducing the auxiliary circuit and matching control timing of this invention, regardless of whether the converter is operating under light or heavy load conditions, the measured voltage drops of the leading arm transistors Vlead1 and Vlead2, as well as the voltage drops of the lagging arm transistors Vlag3 and Vlag4, all exhibit a decreasing trajectory, and have already dropped to 0V before the corresponding drive signal transitions to the on state. These measurement results clearly show that after adding the auxiliary inductor circuit of this invention for dead-time discharge intervention, the voltage and current overlap region at the moment of turn-on of each switching device is eliminated, achieving zero-voltage turn-on operation.

[0072] Compared with the original phase-shifted full-bridge converter without auxiliary circuitry, the technical solution of this invention overcomes the technical defect of soft switching failure of the hysteresis arm, broadens the load operating range for the converter to achieve soft switching, and reduces the overall switching loss of the system.

[0073] Working principle: When using this converter, after the main drive signal of the upper MOSFET 4 of the lagging arm of MOS3 becomes off, the system enters the dead time of the lagging arm. At this time, the control circuit outputs the first pulse signal to drive the MOS6 switch 16 in the auxiliary circuit to conduct for a first preset time. At this time, the auxiliary inductor La14 is connected to the circuit to provide a discharge circuit for the parasitic capacitance Coss6 connected in parallel with the lower MOSFET 5 of the lagging arm of MOS4. This discharge circuit removes the charge stored in the parasitic capacitance Coss6, so that the voltage across the lower MOSFET 5 of the lagging arm of MOS4 drops to zero before it is turned on. Then, the lower MOSFET 5 of the lagging arm of MOS4 is controlled to conduct, thereby realizing the zero-voltage turn-on of the lower MOSFET of the lagging arm.

[0074] In the other half of the cycle, when the main drive signal of the lower MOSFET 5 of the lagging arm of MOS4 becomes off, the system enters the dead time again. The control loop outputs the second pulse signal, which drives the MOSFET 5 switch 15 in the auxiliary circuit to conduct for the second preset time. The auxiliary inductor La14 is connected to the circuit again, providing a discharge circuit for the parasitic capacitance Coss6 connected in parallel on the upper MOSFET 4 of the lagging arm of MOS3. The discharge of the parasitic capacitance Coss6 causes the voltage across the upper MOSFET 4 of the lagging arm of MOS3 to drop to zero before it is turned on. Then, the upper MOSFET 4 of the lagging arm of MOS3 is controlled to conduct, completing the zero-voltage turn-on of the upper MOSFET of the lagging arm. During this process, the upper MOSFET 4 of the lagging arm of MOS3 and the lower MOSFET 5 of the lagging arm of MOS4 alternately share the same auxiliary inductor La14 for charging and discharging.

[0075] In the secondary rectifier circuit of transformer 8, the transmitted energy is output through the central shaft head structure. The low on-resistance MOS7 switch 9 and MOS8 switch 10 are used for full-wave synchronous rectification to reduce conduction losses. The rectified power is filtered by filter inductor Lf11 and filter capacitor Cf12 and finally output to load resistor Rd13.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wide-range soft-switching phase-shifting full-bridge converter, characterized in that, The circuit includes a DC input voltage terminal (1), a phase-shifted full-bridge circuit, a secondary rectifier circuit, and an auxiliary circuit. The phase-shifted full-bridge circuit includes a leading arm and a lagging arm connected in parallel across the DC input voltage terminal (1). The center point of the leading arm is connected to the primary side of the transformer (8) via a resonant inductor Lr (7). The primary side of the transformer (8) is connected to the center point of the lagging arm. The secondary rectifier circuit is connected to the secondary side of the transformer (8). The auxiliary circuit is connected in parallel across the lagging arm. The auxiliary circuit includes a series-connected MOS5 switch (15) and MOS6 switch (16) and an auxiliary inductor La (14). One end of the auxiliary inductor La (14) is connected to the series center point of the MOS5 switch (15) and the MOS6 switch (16). The other end of the auxiliary inductor La (14) is connected to the center point of the lagging arm.

2. The wide-range soft-switching phase-shifting full-bridge converter according to claim 1, characterized in that, The leading arm includes a series of MOS1 leading arm upper transistor (2) and MOS2 leading arm lower transistor (3), and the lagging arm includes a series of MOS3 lagging arm upper transistor (4) and MOS4 lagging arm lower transistor (5). The MOS1 upper lead arm transistor (2), the MOS2 lower lead arm transistor (3), the MOS3 upper lagging arm transistor (4), and the MOS4 lower lagging arm transistor (5) are all connected in parallel with parasitic capacitance Coss (6).

3. A wide-range soft-switching phase-shifting full-bridge converter according to claim 2, characterized in that, The secondary rectifier circuit is a full-wave synchronous rectifier circuit; The secondary side of the transformer (8) is connected to the MOS7 switch (9) and the MOS8 switch (10). The MOS7 switch (9) and the MOS8 switch (10) are connected together and then connected to one end of the filter inductor Lf (11). The other end of the filter inductor Lf (11) is connected to one end of the filter capacitor Cf (12) and one end of the load resistor Rd (13). The secondary side of the transformer (8) has a central shaft head, which is grounded and connected to the other end of the filter capacitor Cf (12) and the other end of the load resistor Rd (13).

4. A wide-range soft-switching phase-shifting full-bridge converter according to claim 2, characterized in that, It also includes a control circuit, which outputs a pulse signal to drive the MOS6 switch (16) to turn on during the dead time before the upper transistor (4) of the lagging arm of MOS3 is turned off and the lower transistor (5) of the lagging arm of MOS4 is turned on, and provides a discharge circuit for the center point of the lagging arm through the auxiliary inductor La (14). It also outputs a pulse signal to drive the MOS5 switch (15) to turn on during the dead time before the lower transistor (5) of the lagging arm of MOS4 is turned off and the upper transistor (4) of the lagging arm of MOS3 is turned on, and provides a discharge circuit for the center point of the lagging arm through the auxiliary inductor La (14).

5. A control method for a wide-range soft-switching phase-shifting full-bridge converter, characterized in that, The wide-range soft-switching phase-shifting full-bridge converter applied to any one of claims 1 to 4 includes the following steps: The dual closed-loop feedback signal is acquired, and the phase shift angle is output after control calculation. Based on the phase shift angle, the set switching frequency, the dead time, and the current system time, the switching cycle, the timing node position of the current system time relative to the switching cycle, and the delay time are calculated. After condition judgment, the main drive signal is output to control the on and off of MOS1 upper arm transistor (2), MOS2 lower arm transistor (3), MOS3 upper arm transistor (4), and MOS4 lower arm transistor (5). After the main drive signal of the upper transistor (4) of the MOS3 lag arm becomes off, the first pulse signal is output to control the MOS6 switch (16) to turn on for a first preset time, and the auxiliary inductor La (14) provides a discharge circuit for the parasitic capacitance Coss (6) connected in parallel to the lower transistor (5) of the MOS4 lag arm; After the main drive signal of the lower transistor (5) of the MOS4 lag arm becomes off, the second pulse signal is output to control the MOS5 switch (15) to turn on for a second preset time, and the auxiliary inductor La (14) provides a discharge circuit for the parasitic capacitance Coss (6) connected in parallel to the upper transistor (4) of the MOS3 lag arm.

6. The control method for a wide-range soft-switching phase-shifting full-bridge converter according to claim 5, characterized in that, The output is the main drive signal used to control the on and off of the MOS1 upper lead arm transistor (2), the MOS2 lower lead arm transistor (3), the MOS3 upper lagging arm transistor (4), and the MOS4 lower lagging arm transistor (5), specifically including: The upper transistor (2) of the MOS1 front arm and the lower transistor (3) of the MOS2 front arm are controlled to alternately conduct in the same cycle, and there is a dead time between the turn-off of one transistor and the turn-on of the other transistor; The upper transistor (4) of the MOS3 lag arm and the lower transistor (5) of the MOS4 lag arm are controlled to conduct alternately in the same cycle, and there is a dead time between the turn-off of one transistor and the turn-on of the other transistor.

7. The control method for a wide-range soft-switching phase-shifting full-bridge converter according to claim 5, characterized in that, In the main drive signal, the conduction state of the lagging arm lags behind the conduction state of the leading arm by a delay time, and the delay time is determined by the phase shift angle.

8. The control method for a wide-range soft-switching phase-shifting full-bridge converter according to claim 5, characterized in that, The process of acquiring the dual closed-loop feedback signal and calculating the output phase shift angle specifically includes: acquiring the output voltage and output current as the dual closed-loop feedback signal, and outputting the phase shift angle through proportional-integral control.

9. The control method for a wide-range soft-switching phase-shifting full-bridge converter according to claim 5, characterized in that, The triggering time of the first pulse signal is the falling edge of the main drive signal of the upper transistor (4) of the MOS3 hysteresis arm; The trigger time of the second pulse signal is the falling edge of the main drive signal of the lower MOSFET (5) of the MOS4 hysteresis arm.

10. The control method for a wide-range soft-switching phase-shifting full-bridge converter according to claim 5, characterized in that, The duration of the first preset time satisfies the following condition: before the lower MOSFET (5) of the MOS4 lag arm is turned on, the voltage across the lower MOSFET (5) of the MOS4 lag arm drops to zero; The duration of the second preset time satisfies the following condition: before the upper tube (4) of the MOS3 lagging arm is turned on, the voltage across the upper tube (4) of the MOS3 lagging arm drops to zero.

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