A dual-frequency transistor-based rectifier capable of emitting second harmonic and a design method thereof

Abstract

The application discloses a dual-frequency transistor-based rectifier capable of emitting second harmonic and a design method thereof. The method first constructs a rectifier topology based on the principle of inverse-time duality, and determines a theoretical impedance design space; then an improved single-stage quadrature coupler is used as an output matching network, and a periodic transformation trajectory of the input impedance Z1 of the first port under any impedance Z3 of the third port is derived; then the optimal source impedance of the transistor under dual frequencies is obtained through source traction, and is matched to the third port of the quadrature coupler through a phase compensation line, so that the microstrip line integrated design of the input matching network and the phase shift network is realized; finally, a second harmonic output network is connected to a direct current output end to extract the second harmonic of the high-frequency fundamental wave. The application realizes efficient integration of impedance transformation and phase control, and takes into account high-efficiency rectification and harmonic extraction, and is suitable for a wireless energy transmission and scattering communication integrated system.

Description

Technical Field

[0001] This invention relates to the fields of wireless communication and wireless power transfer technology, and in particular to a dual-frequency transistor-based rectifier capable of emitting second harmonics and its design method. Background Technology

[0002] With the rapid development of low-altitude unmanned aerial vehicles (UAVs) and airborne sensing platforms, the demands for mobility and endurance in wireless systems are constantly increasing. Wireless Power Transfer (WPT) has become a key technology for solving the endurance bottleneck of airborne equipment. The rectifier, as a core component of the WPT system, is responsible for converting radio frequency energy into DC power. Meanwhile, to meet the requirements of system miniaturization and multi-standard compatibility, dual-frequency, multi-frequency, and multi-functional rectifiers have become a research hotspot. These rectifiers not only achieve efficient energy conversion but also support functions such as signal feedback and scatter communication, making them suitable for Wireless Information and Power Transfer (SWIPT) systems.

[0003] In rectifier circuits, nonlinear devices such as Schottky diodes and gallium nitride transistors (GaN HEMTs) generate high-order harmonics. Traditional Class-F and inverse Class-F rectifiers primarily suppress harmonics. Recent research indicates that harmonics can be recycled to improve efficiency or used as carrier signals in scattering communications. Existing rectifiers capable of generating second harmonics are mostly based on Schottky diodes, with power capacities in the watt range and second harmonic output power in the milliwatt range, limiting the transmission distance and antenna design flexibility of SWIPT systems. GaN transistors, on the other hand, offer advantages such as high breakdown voltage, low on-resistance, and high power density, making them suitable for high-power applications. However, existing GaN HEMT-based rectifiers mainly focus on improving RF-DC conversion efficiency and expanding bandwidth and input power range, lacking transistor-based dual-frequency rectifiers capable of generating second harmonics, making them unsuitable for the future development needs of SWIPT systems.

[0004] The core challenge of dual-frequency rectifiers lies in achieving perfect matching of the output matching network at both target frequencies simultaneously. Existing solutions achieve dual-frequency matching through multi-segment networks and harmonic control structures, but these require additional passive components, resulting in high circuit complexity, large size, and difficulty in integrating harmonic generation and signal feedback functions. Some solutions use quadrature couplers for dual-frequency rectification, but the third port of the quadrature coupler is always open / short-circuited, leading to poor design flexibility and requiring additional phase-shifting networks, further increasing complexity.

[0005] In summary, in order to ensure the stability of the wireless power transmission system and improve the functionality of the rectifier circuit, it is urgent to develop a GaN transistor-based dual-frequency rectifier with second harmonic generation capability for high-power SWIPT scenarios. Summary of the Invention

[0006] The purpose of this invention is to provide a dual-frequency transistor-based rectifier capable of emitting second harmonics and its design method. A dual-frequency rectifier based on GaN transistors is designed, which can generate second harmonics for scattering communication. First, an orthogonal coupler is used as the output matching network of the GaN transistor-based rectifier. The impedance transformation of the coupler's input port is analyzed to obtain the input impedance variation trajectory. Its periodic impedance transformation characteristics are utilized to achieve dual-frequency matching. Based on the inverse-time duality, one operating mode of the power amplifier is selected to perform impedance and efficiency analysis on the rectifier. Based on the design objectives, the optimal operating mode design parameters and theoretical impedance design space are obtained. The input impedance variation trajectory of the coupler is compared with the theoretical impedance design space in this operating mode to obtain the final operating mode design parameters and theoretical impedance value that can be used for design. Based on the obtained theoretical impedance value, the orthogonal coupler is designed to meet the impedance transformation requirements. Simultaneously, the third port of the orthogonal coupler is directly connected to the gate of the transistor via a microstrip line, thereby integrating the input matching network and phase shift network into a phase compensation line. In addition, the DC output of the rectifier's output port is equipped with a second harmonic output network to extract the second harmonic generated by the transistor's nonlinearity as a carrier signal for communication, thereby enabling the simultaneous transmission of information and energy.

[0007] In one aspect, the present invention provides a dual-frequency transistor-based rectifier capable of emitting second harmonics, comprising a transistor, an output matching network, a phase compensation line, a second harmonic output network, a gate bias circuit, and a DC output circuit; an input signal enters the output matching network, and port 1 of the output matching network is connected to the drain of the transistor; one end of the phase compensation line is connected to port 3 of the output matching network, and the other end of the phase compensation line is connected to the gate of the transistor; the gate bias circuit is connected to the gate of the transistor; the DC output circuit is connected to port 2 of the output matching network, and the second harmonic output network is connected to the DC output circuit.

[0008] Furthermore, the gate bias circuit consists of a microstrip line TO6 and a capacitor C. g Composition, used for gate bias voltage V GS Power is supplied to the transistor gate; voltage V GS The negative terminal is grounded, and the positive terminal is connected to capacitor C. g One end of the microstrip line TO6 and one end of the capacitor C g The other end of the line is grounded, and the other end of the microstrip line TO6 is connected to the transistor gate.

[0009] Furthermore, the DC output circuit consists of a filter capacitor C. d Together with the microstrip line TO5, it forms the output DC signal, and the capacitor C d One end of the microstrip line TO5 is used as a DC output port, and capacitor C dThe other end of the microstrip line TO5 is grounded, and the other end of the microstrip line TO5 is connected to port 2 of the output matching network.

[0010] Furthermore, the phase compensation line consists of a microstrip line TO7, with its two ends connected to port 3 of the output matching network and the transistor gate, respectively.

[0011] Furthermore, the second harmonic output network is composed of microstrip lines, with one end of the second harmonic output network connected to one end of TO5, and the other end serving as the second harmonic output port.

[0012] Furthermore, the output matching network is composed of microstrip lines TO1, TO2, TO3, and TO4 in a U-shape. Microstrip lines TO1 and TO2 are parallel to each other, and microstrip lines TO3 and TO4 are parallel to each other. One end of microstrip line TO1, one end of microstrip line TO4, and the other end of microstrip line TO5 of the DC output circuit are directly connected at port 2. The other end of microstrip line TO1 and one end of microstrip line TO3 are directly connected to the drain of the transistor at port 1. One end of microstrip line TO2 and the other end of microstrip line TO3 are connected to the phase shift compensation line TO7 at port 3. The other end of microstrip line TO2 and the other end of microstrip line TO4 are directly connected to the signal input terminal at port 4.

[0013] Furthermore, the characteristic impedances of microstrip lines TO1, TO2, and TO5 are: The characteristic impedances of microstrip lines TO3 and TO4 are: The electrical lengths of microstrip lines TO1, TO2, TO3, TO4, and TO5 are all λ / 4, while the electrical length of microstrip line TO6 is λ / 2, where λ refers to the wavelength of the operating frequency.

[0014] A design method for a dual-frequency transistor-based rectifier capable of emitting second harmonics, employing the following scheme: Step 1: Based on gallium nitride (GaN) HEMTs, construct a rectifier according to the principle of inverse-time duality (rectifiers and power amplifiers have structural and energy symmetry). The input and output terminals of the power amplifier are interchanged to form the rectifier structure: the DC drain input terminal of the power amplifier serves as the DC output terminal of the rectifier, and the output terminal of the power amplifier serves as the RF input segment of the rectifier. Simultaneously, the power amplifier's operating mode is used as the rectifier's operating mode.

[0015] Step 2: Analyze the input impedance of the first port of the quadrature coupler structure at the reference frequency. In this design, the impedance configuration of the third port of the quadrature coupler is released, and the impedance of the third port is... Set to any value, including real impedance, virtual impedance, and complex impedance. Through derivation, it is found that under different... Input impedance under certain conditions The impedance trajectory.

[0016] Step 3: Based on the design parameters of the operating mode, analyze the expressions for the transistor drain output voltage, current and operating efficiency in this operating mode, and obtain the theoretical impedance design space in this operating mode.

[0017] Furthermore, the design parameters based on the operating mode specifically include: conduction angle. α Continuous mode parameters γ Phase shift parameters .

[0018] Furthermore, by analyzing the voltage and current expressions under the operating mode, the voltage component expressions for DC, fundamental, second harmonic, and third harmonic are obtained as follows: The expression for the current component is: Then the DC power expression is obtained as follows: The power expressions for each harmonic component are as follows: , where n represents the order of the harmonics. In rectifier design, because the energy carried by higher-order harmonics is negligible, the impact of harmonic components on energy conversion efficiency is usually only evaluated up to the third harmonic.

[0019] Furthermore, the expression for rectification efficiency is: The second harmonic output efficiency is .in and These represent the RF power applied to the gate and drain, respectively, and the total input power is equal to... and The sum, ρ The definition of The above formulas are used to obtain the curves showing the changes in rectification efficiency and second harmonic output efficiency as a function of the parameters of the operating mode. Based on the target efficiency, the design parameters of the operating mode are obtained, and then based on the design parameters, the theoretical impedance design space under this operating mode is obtained.

[0020] Step 4: Compare the theoretical impedance design and the input impedance of the quadrature coupler under different operating modes. Z The trajectories of 1 and their overlapping regions represent the usable theoretical impedance value. Based on the obtained theoretical impedance value, an orthogonal coupler is used as the output matching network, and its parameters are obtained. The two target frequencies ( , The fundamental impedance and second harmonic impedance of the circuit are both matched to the output terminal.

[0021] Step 5: Use the RF simulation software ADS (Advanced Design Software) to obtain the source impedance at the two target frequencies. , In this design, the optimal source impedance obtained by source pulling ( , A phase compensation line is used to match the third port of the quadrature coupler. This enables the integrated design of impedance matching and phase response. Furthermore, since the influence of phase shift parameters on rectification efficiency has been analyzed, it shows that high-efficiency rectification can also be achieved with a non-180-degree phase shift.

[0022] Step 6: Obtain the output impedance of the second harmonic of the target output at the output port of the rectifier, and then use a microstrip line to design a second harmonic output network to convert the second harmonic impedance to a 50-ohm terminal for extraction and output of the second harmonic.

[0023] Furthermore, by combining all the designed rectifier components (output matching network, phase compensation line, and second harmonic output network) for overall optimization, a dual-frequency transistor-based rectifier circuit that can ultimately generate a second harmonic signal is obtained.

[0024] Beneficial effects of this invention: This invention constructs a rectifier topology based on the principle of inverse-time duality, using an improved quadrature coupler as the output matching network of the rectifier. This releases the fixed impedance limitation of the third port of the traditional quadrature coupler and reduces its impedance. Set to any value and utilize its input impedance. The system leverages the periodic impedance transformation characteristics of the source, simultaneously matching the optimal source impedance obtained from source pulling to the third port of the quadrature coupler via a phase compensation line. Impedance transformation and phase response are integrated into the design. Furthermore, a second harmonic output network is connected in parallel at the DC output terminal to extract and output the second harmonic. This results in perfect impedance matching at two target operating frequencies, the integration of the input matching network and phase shift network into a single microstrip line structure, and efficient extraction of the second harmonic as a scattering communication carrier signal while maintaining high conversion efficiency. This solves the problems of high complexity, large size, and low integration of traditional rectifier circuits, as well as the small power capacity and weak second harmonic output of existing Schottky diode-based rectifiers, making them unsuitable for the development needs of high-power SWIPT systems. Attached Figure Description

[0025] Figure 1 For rectifier topology; Figure 2 It is a rectifier structure based on orthogonal couplers; Figure 3 For different corresponding The impedance trajectory, of which Figure (a) For pure real numbers, the graph (b) For positive pure imaginary numbers, Figure (c) For negative pure imaginary numbers, the graph (d) It is a complex number; Figure 4 For different corresponding The real and imaginary parts, where (a) corresponds to the real and imaginary parts. When it is a pure real number The real part, (b) is the corresponding When it is a pure real number The imaginary part, (c) is the part corresponding to When it is a pure imaginary number The real part, (d) is the corresponding When it is a pure real number The imaginary part, (e), corresponds to When it is a complex number The real part, (f) corresponds to When it is a complex number The imaginary part; Figure 5 The rectifier efficiency at α=210° and γ (-1<γ<1) and (-0.2π< The relationship is <0.2π); Figure 6 The second harmonic output efficiency at α=210° and γ (-1<γ<1) and (-0.2π< The relationship is <0.2π); Figure 7 When α=210°, the fundamental impedance and second harmonic impedance change with γ and Change relationship ( =-0.2π~0.2π, -1≤γ≤1); Figure 8 For in different The following is the usable frequency range and impedance trajectory, where Figure (a) shows... Figure (b) Figure (c) Figure (d) Figure (e) Figure (f) ; Figure 9 For the designed phase shift compensation line; Figure 10 For the output matching network of the design; Figure 11 For the output load impedance trace; Figure 12 The input signal and gate / drain phase shift are simulated; Figure 13 This is the topology of the second harmonic output network; Figure 14 For second harmonic output network; Figure 15 The S-parameters of the simulated second harmonic output network; Figure 16 The diagram shows a complete rectifier, where Figure (a) is the circuit schematic and Figure (b) is the physical diagram. Figure 17 The drain voltage and current waveforms are simulated in the intrinsic plane, where Figure (a) shows the operating frequency of 1.1 GHz and Figure (b) shows the operating frequency of 2.4 GHz. Figure 18 The rectification efficiency curve for saturated RF input power; Figure 19 The rectifier efficiency curve and the second harmonic output efficiency curve are for variable RF input power. Detailed Implementation

[0026] The following are specific embodiments of the present invention, and the technical solutions of the present invention will be further described in conjunction with the accompanying drawings. However, the present invention is not limited to these embodiments.

[0027] In this embodiment, taking the general F-class working mode as an example, a working frequency of [missing information] is designed. =1.1GHz and A dual-frequency rectifier with a frequency of 2.4 GHz outputs a second harmonic of... =4.8GHz, the rectifier is based on the commercially available CGH40010F GaN transistor and Rogers4350B dielectric substrate ( The design was carried out using the following parameters: = 3.66, H = 30 mils.

[0028] In one aspect, the present invention provides a dual-frequency transistor-based rectifier capable of emitting second harmonics, comprising a transistor, an output matching network, a phase compensation line, a second harmonic output network, a gate bias circuit, and a DC output circuit; an input signal enters the output matching network, and port 1 of the output matching network is connected to the drain of the transistor; one end of the phase compensation line is connected to port 3 of the output matching network, and the other end of the phase compensation line is connected to the gate of the transistor; the gate bias circuit is connected to the gate of the transistor; the DC output circuit is connected to port 2 of the output matching network, and the second harmonic output network is connected to the DC output circuit.

[0029] The gate bias circuit consists of a microstrip line TO6 and a capacitor C. g Composition, used for gate bias voltage V GS Power is supplied to the transistor gate; voltage V GS The negative terminal is grounded, and the positive terminal is connected to capacitor C.g One end of the microstrip line TO6 and one end of the capacitor C g The other end is grounded, and the other end of the microstrip line TO6 is connected to the transistor gate. The DC output circuit consists of a filter capacitor C. d Together with the microstrip line TO5, it forms the output DC signal, and the capacitor C d One end of the microstrip line TO5 is used as a DC output port, and capacitor C d The other end of the microstrip line TO5 is grounded, and the other end of the microstrip line TO5 is connected to port 2 of the output matching network. The phase compensation line consists of a microstrip line TO7, with its two ends connected to port 3 of the output matching network and the transistor gate, respectively. The second harmonic output network is composed of microstrip lines, with one end of the second harmonic output network connected to one end of TO5, and the other end serving as the second harmonic output port. The output matching network consists of microstrip lines TO1, TO2, TO3, and TO4 arranged in a U-shape. Microstrip lines TO1 and TO2 are parallel to each other, and microstrip lines TO3 and TO4 are also parallel to each other. One end of microstrip line TO1, one end of microstrip line TO4, and the other end of microstrip line TO5 in the DC output circuit are directly connected at port 2. The other end of microstrip line TO1 and one end of microstrip line TO3 are directly connected to the transistor drain at port 1. One end of microstrip line TO2 and the other end of microstrip line TO3 are connected to the phase shift compensation line TO7 at port 3. The other end of microstrip line TO2 and the other end of microstrip line TO4 are directly connected to the signal input terminal at port 4. The characteristic impedance of microstrip lines TO1, TO2, and TO5 is... The characteristic impedances of microstrip lines TO3 and TO4 are: The electrical lengths of microstrip lines TO1, TO2, TO3, TO4, and TO5 are all λ / 4, while the electrical length of microstrip line TO6 is λ / 2, where λ refers to the wavelength of the operating frequency.

[0030] A design method for a dual-frequency transistor-based rectifier capable of emitting second harmonics specifically includes the following steps: Step 1, such as Figure 1 As shown, a rectifier is constructed based on gallium nitride transistors (GaN HEMT) according to the principle of inverse time duality (rectifier and power amplifier have structural and energy symmetry). The structure of the rectifier is formed by swapping the input and output terminals of the power amplifier: the DC input terminal of the power amplifier's drain is used as the DC output terminal of the rectifier, and the output terminal of the power amplifier is used as the RF input segment of the rectifier.

[0031] Furthermore, the proposed rectifier architecture's output matching network consists of a single-stage improved quadrature coupler, while the input matching network and the phase-dependent network are integrated into a single phase-shift compensation line. A second harmonic output network is added to the DC output port to guide and output the second harmonic. In this embodiment, the rectifier adopts a general Class F operating mode, with the gate bias voltage... Set to -3.7V to obtain the conduction angle for general Class F operating mode.

[0032] Step Two: Based on, for example Figure 2 The improved quadrature coupler shown is used to derive its electrical characteristics at the operating frequency. Below, the characteristic impedances of the transmission lines are respectively and ,in The standard terminating impedance is equal to the impedance of port 4. The transmission matrix of this coupler is: in, These represent the voltages at ports 1, 2, 3, and 4, respectively. j It is the imaginary unit. Similarly, This represents the current flowing into each port. The impedance of each port. ( ) is defined as: Since port 2 is connected to a short-circuited transmission line, the impedance of port 2 can be expressed as: in, f It is the operating frequency, and because port 4 is the RF input port, therefore You can get Then we can obtain the current relationships for ports 2, 3, and 4: Substituting this expression and the impedance of port 2 into the coupler's transfer matrix yields... Based on the above expression, we can solve for... Based on the above derivation, the input impedance of the orthogonal coupler can be finally obtained as follows: exist Under the condition of 50Ω and a frequency range of 0.5-2.5 GHz, different Corresponding input impedance It is mapped onto the Smith chart. For example... Figure 3 As shown, with Changes, Figure 3 (a) in the middle is Take pure real numbers, Figure 3 (b) in the middle is Take positive pure imaginary numbers, Figure 3 (c) in the middle is Take the negative pure imaginary number. Figure 3 (d) in the middle is Taking complex numbers generates a series of correspondences. The impedance traces are shown below. These impedances shift counterclockwise on the Smith chart as the frequency increases. From Figure 3 It can be seen that when When changing from 0 (short circuit state) to infinity (open circuit state), The trajectory gradually moves from the right side of the Smith chart to the left. Furthermore, as... Figure 3 As shown in (b), (c) and (d) in the figure, when When taking complex numbers or purely imaginary numbers, the result is The trajectory forms an irregular closed curve, rather than a standard circle. Furthermore, for ... The value, its corresponding The trajectory is symmetric about the real axis of the Smith chart. In practical designs, this differs from that in traditional circuits. Only when the conditions are different (open circuit or short circuit) It can be designed with any complex impedance value. This increases design flexibility, reduces complexity, and facilitates the integration of subsequent phase-shifting networks and input matching networks. Figure 4 Showing different value corresponding The real and imaginary parts, among which Figure 4 (a), (c), and (e) in the text are respectively Take the real part of the real impedance, imaginary impedance, and complex impedance. Figure 4 (b), (d), and (f) in the text are respectively By taking the imaginary parts of the real impedance, imaginary impedance, and complex impedance, it was proven that... Different impedance configurations The real and imaginary parts of the impedance have different effects. Furthermore, the figure shows that the input impedance of the proposed coupler exhibits a periodicity of twice the normalized frequency. This periodicity means that the same or similar impedance conditions are repeated at multiple frequency points, thus achieving multi-band and wideband impedance matching capability.

[0033] Step 3: A general-purpose Class F rectifier is proposed, which incorporates all key parameters in the rectifier design (conduction angle α, phase offset, etc.). Including the continuous mode parameter γ in the drain voltage, we obtain the voltage and current expressions for the general Class F operating mode: in, and These represent the maximum drain voltage and current, respectively. It is the real part of the third harmonic current. These parameters (conduction angle α, phase offset) The continuous mode parameter γ can be used to adjust the voltage and current waveforms of a general-purpose Class F rectifier, thereby affecting its efficiency.

[0034] Furthermore, the voltage can be obtained through Fourier analysis. ) and current ( The DC component, fundamental component, second harmonic component, and third harmonic component of the proposed general Class F mode can be obtained. Simultaneously, the DC power, fundamental power, second harmonic power, and third harmonic power of the proposed general Class F mode can also be obtained. The expression for: Furthermore, RF-DC rectification efficiency is defined as the DC output power ( The ratio of the second harmonic output power to the RF input power. The second harmonic output efficiency is further defined as the ratio of the second harmonic output power (…). The ratio of the input RF power to the input RF power: in, ρ Defined as . and These represent the RF input power at the gate and drain, respectively. The total RF input power equals... and The sum of.

[0035] Furthermore, a larger conduction angle can suppress higher harmonic components, concentrating more energy on the fundamental component. Therefore, after weighing the relationship between rectification efficiency and second harmonic output efficiency, the conduction angle α in this example is 210°. According to the efficiency expression, Figure 5 and Figure 6 The continuous mode parameter γ and phase offset parameter are shown respectively when the conduction angle α = 210°. The impact of the continuous mode parameter γ on rectification efficiency and second harmonic generation efficiency. Observations show that when the continuous mode parameter γ and the phase shift parameter... When γ and SH have the same sign, the rectification efficiency is low, and the second harmonic generation efficiency becomes negative. Therefore, in order to achieve high RF-DC rectification efficiency while maintaining positive RF-SH (RF-second harmonic) conversion efficiency, γ and SH should be optimized. Having opposite signs (e.g., γ is positive, ... (Negative).

[0036] At the same time, with phase shift As the fundamental load impedance increases, the real part becomes negative, resulting in negative power output and an efficiency exceeding 100%. This outcome is impossible to achieve in practical circuits. Therefore, in this example, the phase shift... The range is limited to between -0.2π and -0.2π.

[0037] Furthermore, based on the previous expressions for voltage and current, as well as the conduction angle, the corresponding impedance expressions for the fundamental and second harmonic waves can be derived. Additionally, for Class F rectifiers, the impedance of the third harmonic wave should ideally be infinite.

[0038] Based on the impedance expression, and taking into account the continuous mode parameter γ and the phase shift parameter The relationship between these factors allows us to define the corresponding theoretical design space for the fundamental and second harmonic impedances, such as... Figure 7 As shown. When specifying the impedance at port 3 of the proposed quadrature coupler. At that time, the corresponding... The impedance trajectory. By comparing this theoretical trajectory with... Figure 7 By comparing the impedance design spaces of the general-purpose Class F rectifier, the overlapping regions can be identified. These overlapping regions indicate the feasible operating frequency band for achieving the load impedance required for the general-purpose Class F rectifier. The impedance within these regions not only satisfies the load conditions required for the general-purpose Class F rectifier but also allows for effective impedance transformation through the proposed quadrature coupler.

[0039] Furthermore, Figure 8 Showing when When set to certain representative values The impedance trajectory. It can be seen that... The trajectory partially overlaps with the impedance design space of the general Class F operating mode. Figure 8 The arrows in the diagram indicate the trend of impedance trajectory changes with frequency. Different... The value will lead to The impedance trajectories are different, thus in Figure 7 The theoretical impedance design space shown generates different overlapping regions. Therefore, different operating frequency bands and load impedance ranges can be achieved. This characteristic provides significant flexibility for the design of dual-frequency and multi-frequency rectifiers. Figure 8 The red curve in the middle represents The overlap between the impedance trajectory and the theoretical impedance design space. Table 1 summarizes the selected... The operating frequency range that the value can achieve and its corresponding load impedance range.

[0040] Table 1. Available design parameters for the rectifier

[0041] Step 4: As mentioned above, the impedance of the third port of the quadrature coupler ( The impedance is not fixed and can be flexibly adjusted within a certain design range. Therefore, the matching target of the input matching network (IMN) has changed from the traditional fixed impedance requirement to the impedance environment defined by the coupler. Meanwhile, this example has shown that high rectification efficiency and second harmonic output can still be achieved under non-180° phase conditions. Since there is a coupling relationship between impedance and phase in the transmission line network, the required phase shift can be partially incorporated into the impedance transformation process. In this example, a single phase compensation line is used to achieve input impedance matching and phase shift, greatly simplifying the traditional architecture.

[0042] At the two frequencies, the optimal source impedances obtained using ADS source pulling are respectively and ,and Setting the Ω to 10±j·22Ω, and using a single phase compensation line to achieve the gate-drain phase shift required for input matching and high-efficiency rectification, the following can be obtained: Figure 9 The transmission microstrip line structure shown is shown.

[0043] Step 5: In Once confirmed, you can get The input impedance trajectory, corresponding to the impedance at the target operating frequency, is selected as follows: , To simplify circuit design, the initial characteristic impedance of the quadrature coupler is... The initial design impedance was set at 50Ω, and the initial characteristic impedance and electrical length were 2.4 GHz. However, in practical circuits, transistor parasitic parameters and microstrip line dispersion effects can cause additional impedance deviations, thus requiring impedance compensation through coupler parameter optimization. Furthermore, dual-frequency operation requires the coupler to meet impedance transformation conditions at both 1.1 GHz and 2.4 GHz. Considering transistor packaging and parasitic effects, the characteristic impedance of the coupler and the electrical length of each microstrip segment were further optimized, resulting in the output matching network shown below. Figure 10 As shown. Figure 11 This is the simulated load impedance trajectory. It can be seen that at the two target frequencies... and Under these conditions, the fundamental impedance points all fall within the theoretical impedance region. Furthermore, the second harmonic impedance also remains within the corresponding impedance region required for the general Class F operating mode. These results demonstrate that the proposed output matching network based on orthogonal couplers possesses excellent impedance transformation capabilities.

[0044] Furthermore, once the output matching network and phase shift compensation line are designed, the phase difference between the input RF signal and the gate and drain can be obtained, such as... Figure 12 As shown, at frequencies of 1.1 GHz and 2.4 GHz, The values ​​are -143.7° and 83.6° respectively, while The values ​​are 23.2° and -123.7° at the two frequencies, respectively. and At a given frequency, the phase difference between the gate and drain The phase offsets are 166.9° and 207.3° respectively, which meet the phase offset requirements for high-efficiency rectification.

[0045] Step Six: To ensure effective isolation between the DC and RF paths, a DC blocking capacitor is inserted in the harmonic branch to suppress DC leakage. Meanwhile, the design of the DC output branch... It exhibits high impedance (approximately open circuit) at certain frequencies. This leads to the establishment of a frequency-selective signal separation mechanism, which can efficiently extract the RF component while maintaining RF-DC functionality. For example... Figure 13 As shown, the second harmonic output network consists of a π-type structure (TH1, TH2, and TH3) and two transmission lines TH4 and TH5. This design can be understood as a two-stage process: first, TH4 and TH5 are used to... Complex impedance at frequency Transformed into pure real impedance This provides a real reference impedance, simplifying the design of subsequent circuits. To ensure effective isolation between the DC signal and the second harmonic path, a DC blocking capacitor is inserted in the harmonic branch to suppress DC leakage. Meanwhile, the design of the DC output branch... It exhibits high impedance (approximately open circuit) at certain frequencies. Therefore, a frequency-selective signal separation mechanism is established, which can efficiently extract the second harmonic component while maintaining rectification functionality.

[0046] Furthermore, the corresponding ABCD matrix of the π-type network can be calculated as follows: The input impedance of the front end of a π-type network can be expressed as: ,in Z L The load impedance is 50Ω. (Through...) This allows us to solve for the unknown parameters. Based on the simulation results, at the frequency... The input complex impedance of the second harmonic output matching network is Impedance matching is performed on the Smith chart, and... Matched This allows us to obtain the parameters for TH4 and TH5, i.e. = 44Ω, = 47Ω, = 12.7°, =19.4°. In this design, to simplify calculations, [the following is used:] , and All are set to 50Ω. Then, by substituting the complex impedances mentioned above into the formula, all unknown parameters can be obtained. This allows us to determine the impedance at 4.8GHz. and The angles are 39.6° and 17.2° respectively, and the final second harmonic output network is as follows: Figure 14 As shown. Figure 15 The S-parameters of the designed second harmonic output network are shown; at 4.8 GHz, S11 is -21.18 dB, while S21 is approximately -0.17 dB. These results demonstrate that the designed SH output network can efficiently pass the desired second harmonic (4.8 GHz) signal.

[0047] Step 7: Connect the designed output matching network, phase bias line, second harmonic output network, and other components. The complete circuit schematic and physical diagram of the rectifier are shown below. Figure 16 As shown in (a) and (b) in the figure. Figure 17 Figures (a) and (b) show the simulated voltage and current waveforms of the transistor current source plane at 1.1 GHz and 2.4 GHz, respectively, which are highly consistent with the theoretical waveforms of the general class F operating mode.

[0048] Furthermore, under continuous wave signal conditions, the fabricated rectifier exhibits... = -3.7 V and Characteristic tests were conducted under the condition of 130 Ω. Rectification efficiency is defined as the DC output power ( ) and RF input power ( The ratio of ) is expressed as The second harmonic generation efficiency is defined as the second harmonic output power (…). The ratio of the input RF power to the input RF power is expressed as: The overall energy conversion efficiency of a rectifier is defined as the sum of the rectification efficiency and the second harmonic output efficiency, expressed as: . Figure 18 The rectification efficiency versus operating frequency curves were plotted, demonstrating excellent dual-frequency operating characteristics. With an input RF power of 40 dBm, the peak rectification efficiencies at 1.1 GHz and 2.4 GHz are 73% and 52.5%, respectively; the corresponding peak second harmonic output power at 2.4 GHz reaches 28.8 dBm. The second harmonic output efficiency is 7.6%, and the overall rectifier energy conversion efficiency at the two operating frequencies is 73% and 60.1%, respectively. Figure 19 This study demonstrates how rectification efficiency varies with input power under the same gate bias and DC load conditions. The rectification efficiency increases with increasing RF input power. Test results show that the designed rectifier achieves high second harmonic output while maintaining high rectification efficiency.

[0049] The above description of the embodiments is merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined in this application can be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown in this application, but is to be accorded the widest scope consistent with the principles and novel features disclosed in this application.

Claims

1. A dual-frequency transistor-based rectifier capable of emitting second harmonics, characterized in that, This includes transistors, output matching networks, phase compensation lines, second harmonic output networks, gate bias circuits, and DC output circuits. The input signal enters the output matching network, and port 1 of the output matching network is connected to the drain of the transistor; one end of the phase compensation line is connected to port 3 of the output matching network, and the other end of the phase compensation line is connected to the gate of the transistor. The gate bias circuit is connected to the transistor gate; The DC output circuit is connected to port 2 of the output matching network, and the second harmonic output network is connected to the DC output circuit.

2. The dual-frequency transistor-based rectifier capable of emitting second harmonics according to claim 1, characterized in that, The gate bias circuit consists of a microstrip line TO6 and a capacitor. C g Composition, used for gate bias voltage V GS Power is supplied to the transistor gate; voltage V GS The negative terminal is grounded, and the positive terminal is connected to a capacitor. C g One end and one end of the microstrip line TO6, capacitor C g The other end of the line is grounded, and the other end of the microstrip line TO6 is connected to the transistor gate. The DC output circuit consists of a filter capacitor. C d Together with the microstrip line TO5, it forms the output DC signal, and the capacitor... C d One end of the microstrip line TO5 is used as a DC output port, and the capacitor... C d The other end of the microstrip line TO5 is grounded, and the other end of the microstrip line TO5 is connected to port 2 of the output matching network. The phase compensation line consists of a microstrip line TO7, with the two ends of the microstrip line TO7 connected to port 3 of the output matching network and the gate of the transistor, respectively. The second harmonic output network is composed of microstrip lines. One end of the second harmonic output network is connected to one end of TO5, and the other end serves as the second harmonic output port.

3. A dual-frequency transistor-based rectifier capable of emitting second harmonics according to claim 2, characterized in that, The output matching network is composed of microstrip lines TO1, TO2, TO3, and TO4 in a U-shape. Microstrip lines TO1 and TO2 are parallel to each other, and microstrip lines TO3 and TO4 are parallel to each other. One end of microstrip line TO1, one end of microstrip line TO4, and the other end of microstrip line TO5 of the DC output circuit are directly connected at port 2. The other end of microstrip line TO1 and one end of microstrip line TO3 are directly connected to the drain of the transistor at port 1. One end of microstrip line TO2 and the other end of microstrip line TO3 are connected to the phase shift compensation line TO7 at port 3. The other end of microstrip line TO2 and the other end of microstrip line TO4 are directly connected to the signal input terminal at port 4. The characteristic impedances of microstrip lines TO1, TO2, and TO5 are: The characteristic impedances of microstrip lines TO3 and TO4 are: The electrical lengths of microstrip lines TO1, TO2, TO3, TO4, and TO5 are all λ / 4, while the electrical length of microstrip line TO6 is λ / 2, where λ refers to the wavelength of the operating frequency.

4. A design method for a dual-frequency transistor-based rectifier capable of emitting second harmonics, used to implement the dual-frequency transistor-based rectifier according to any one of claims 1 or 3, characterized in that, Includes the following steps: Step 1: Based on the principle of inverse time duality, construct a rectifier using gallium nitride transistors. Interchange the input and output terminals of the power amplifier to form the rectifier structure, and use the power amplifier's operating mode as the rectifier's operating mode. Step 2: Analyze the input impedance of the first port of the quadrature coupler structure at the reference frequency. ; Step 3: Based on the design parameters of the operating mode, analyze the expressions for voltage, current and efficiency under the operating mode to obtain the theoretical impedance design space under this operating mode; Step 4: Design space and input impedance based on theoretical impedance under operating mode The theoretical impedance value obtained is matched to the output terminal with the theoretical impedance value of the target frequency to obtain the optimal source impedance at the target frequency. Step 5: Obtain the output impedance of the second harmonic of the target output at the output port of the rectifier, and then use a microstrip line to design a second harmonic output network to convert the second harmonic impedance to the terminal for extraction and output of the second harmonic.

5. The design method of a dual-frequency transistor-based rectifier capable of emitting second harmonics according to claim 4, characterized in that, Step two is specifically implemented as follows: releasing the impedance configuration of the third port of the orthogonal coupler, and setting the impedance of the third port... Set to any value, including real impedance, virtual impedance, and complex impedance; Calculations show that in different Input impedance under certain conditions The impedance trajectory.

6. The design method of a dual-frequency transistor-based rectifier capable of emitting second harmonics according to claim 5, characterized in that, The specific implementation process of step three is as follows: Based on the design parameters of the operating mode, the expressions for the transistor drain voltage and current under the operating mode are analyzed, and the expressions for the DC, fundamental, second harmonic, and third harmonic voltage components are obtained as follows: The expression for the current component is: Then the DC power expression is obtained as follows: The power expressions for each harmonic component are as follows: , where n represents the order of the harmonic; The expression for the rectifier's efficiency is: The second harmonic output efficiency is ,in and These represent the RF power applied to the gate and drain, respectively, and the total input power is equal to... and The sum, ρ The definition of ; The above formulas yield curves showing the changes in rectification efficiency and second harmonic output efficiency as a function of the operating mode parameters. Based on the target efficiency, the design parameters for the operating mode, including the conduction angle, are obtained. α Continuous mode parameters γ Phase shift parameters Then, based on the design parameters, the theoretical impedance design space under this operating mode is obtained.

7. The design method of a dual-frequency transistor-based rectifier capable of emitting second harmonics according to claim 6, characterized in that, Step four is implemented as follows: Step 4.1: Compare the theoretical impedance design space under the operating mode with the input impedance of the quadrature coupler. The trajectories of the two target frequencies overlap, and the region between them represents the usable theoretical impedance value. Based on this theoretical impedance value, an orthogonal coupler is used as the output matching network to connect the two target frequencies. , The theoretical impedance values ​​are all matched to the output terminal; Step 4.2: Use RF simulation software to obtain the optimal source impedance at the two target frequencies. , ; Optimal source impedance , By using a phase compensation line matched to the third port of the quadrature coupler, an integrated design of impedance matching and phase response is achieved.

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