Improved carrier layering PWM modulation method and device for three-level inverter

Abstract

The application discloses an improved carrier layering PWM modulation method and device for a three-level inverter, and the method comprises the following steps: constructing a carrier according to the switching frequency of a switching tube; the carrier comprises a first triangular carrier with a variation range of 0 to 1 and a second triangular carrier with a variation range of -1 to 0; constructing a modulation wave according to the modulation degree and the fundamental frequency output by an inverter closed-loop controller; the modulation wave comprises a first sinusoidal modulation wave and a second sinusoidal modulation wave with a phase angle difference of 180 DEG; dividing one fundamental period of the first sinusoidal modulation wave into four intervals; presetting a pair of complementary switching switching tubes in each interval; setting any switching tube outside the complementary switching switching tubes in each interval as a preset fixed modulation signal; comparing the carrier and the modulation wave in each interval to obtain the PWM modulation signal of the complementary switching switching tube in each interval.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and in particular to an improved carrier-layered PWM modulation method and apparatus for three-level inverters. Background Technology

[0002] With the increasing demands for efficiency and power density in power electronic systems, three-level inverter topologies are widely used in key areas such as new energy power generation and motor drives due to their advantages such as low output voltage harmonics and low voltage stress on switching transistors. Three-level inverter topologies can be mainly divided into TNPC (T-Type Neutral Point Clamped), DNPC (Diode Neutral Point Clamped), and ANPC (Active Neutral Point Clamped).

[0003] Three-level inverter topologies often face the problem of midpoint potential deviation in the DC-side split capacitors. This stems from the non-ideal characteristics of the actual system, such as capacitance and aging deviations of the upper and lower capacitors, inconsistent drive signal transmission delays, and asymmetric parasitic parameters in the PCB layout. Current technologies primarily address the midpoint potential balance problem in three-level inverters by sampling the midpoint potential deviation with sensors and adjusting the duration of the smaller vector in the space vector modulation in real time. This control method, by injecting a correction component into the ideal modulation wave, alters the original output characteristics, sacrificing some output voltage waveform quality. While it achieves midpoint potential balance, high fidelity of the output voltage waveform is crucial for three-level inverters.

[0004] Therefore, a new technical solution is urgently needed to address the technical problem of how to perform three-level inverter modulation that balances output waveform quality and midpoint potential. Summary of the Invention

[0005] This invention provides an improved carrier-layered PWM modulation method and apparatus for three-level inverters, which solves the technical problem of how to perform three-level inverter modulation while taking into account both output waveform quality and midpoint potential balance.

[0006] To achieve the above objectives, this invention provides an improved carrier-layered PWM modulation method for three-level inverters, comprising: The carrier wave is constructed based on the switching frequency of the switching transistor; the carrier wave includes a first triangular carrier wave with a range of 0 to 1 and a second triangular carrier wave with a range of -1 to 0; the modulation wave is constructed based on the modulation index and fundamental frequency of the inverter closed-loop controller output; the modulation wave includes a first sinusoidal modulation wave and a second sinusoidal modulation wave with a phase angle difference of 180°. The fundamental period of the first sinusoidal modulation wave is divided into four intervals; a pair of complementary switching transistors are preset in each interval; any switching transistor other than the complementary switching transistors in each interval is set to a preset fixed modulation signal; the PWM modulation signal of the complementary switching transistors in each interval is obtained by comparing the carrier wave and the modulation wave.

[0007] Preferably, the first sinusoidal modulating wave and the second sinusoidal modulating wave include: ; ; in, V Aref and V Bref These represent the first sinusoidal modulation wave and the second sinusoidal modulation wave, respectively. m Indicates the adjustment system; Indicates the fundamental frequency; t Indicates time.

[0008] Preferably, one fundamental period of the first sinusoidal modulated wave is divided into four intervals, including: The inverter operating range is divided into four intervals based on one fundamental period of the first sinusoidal modulation wave: the first interval [0, 0.5], the second interval [0.5, 1], the third interval [-0.5, 0], and the fourth interval [-1, -0.5].

[0009] Preferably, a pair of complementary switching transistors are pre-set in each interval, including: Define the upper split capacitor in the TNPC three-level inverter. C U The negative terminal of the split capacitor is connected. C D The positive terminal, the split capacitor C U The positive terminal is connected to the positive terminal of the DC bus, and the lower split capacitor is connected. C D The negative terminal is connected to the negative terminal of the DC bus; the upper split capacitor C U With the lower split capacitor C D The intermediate node O is electrically connected to the drain of the second switch P2 and the drain of the sixth switch P6; the source of the second switch P2 is electrically connected to the source of the third switch P3, and the drain of the third switch P3 is electrically connected to the source of the first switch P1, the drain of the fourth switch P4, and the filter inductor. LOne end; the drain of the first switch P1 is electrically connected to the positive terminal of the DC bus and the drain of the fifth switch P5; the source of the fourth switch P4 is connected to the negative terminal of the DC bus and the source of the eighth switch P8; the source of the sixth switch P6 is connected to the source of the seventh switch P7, and the drain of the seventh switch P7 is connected to the source of the fifth switch P5, the drain of the eighth switch P8, and the filter capacitor. C o The negative terminal of the load or the negative terminal of the power grid; filter inductor L The other end is electrically connected to a filter capacitor. C o The negative terminal of the load or the positive terminal of the power grid; for TNPC three-level inverters: In the first interval, the first switch P1 and the third switch P3 are preset to be complementary switching switches; In the second interval, the sixth switch P6 and the eighth switch P8 are preset to be complementary switching switches; In the third interval, the second switch P2 and the fourth switch P4 are preset to be complementary switching switches; In the fourth interval, the fifth switch P5 and the seventh switch P7 are preset to be complementary switching switches.

[0010] Preferably, the method of pre-setting a pair of complementary switching transistors in each interval further includes: Define the upper split capacitor in a DNPC three-level inverter. C U The negative terminal of the split capacitor is connected. C D The positive terminal, the split capacitor C U The positive terminal is connected to the positive terminal of the DC bus, and the lower split capacitor is connected. C D The negative terminal is connected to the negative terminal of the DC bus; the upper split capacitor C U With the lower split capacitor C D The intermediate node O is electrically connected to the anode of the first clamping diode D1 and the third clamping diode D3, and the cathode of the second clamping diode D2 and the fourth clamping diode D4; the drain P1 of the first switching transistor is connected to the positive terminal of the DC bus, the source of the first switching transistor P1 is connected to the drain of the second switching transistor P2 and the cathode of the first clamping diode D1, and the source of the second switching transistor P2 is connected to the drain of the third switching transistor P3 and the filter inductor. LAt one end, the source of the third switch P3 is connected to the drain of the fourth switch P4 and the anode of the second clamping diode D2; the source of the fourth switch P4 is connected to the negative terminal of the DC bus; the drain of the fifth switch P5 is connected to the positive terminal of the DC bus; the source of the fifth switch P5 is connected to the drain of the sixth switch P6 and the cathode of the third clamping diode D3; the source of the sixth switch P6 is connected to the drain of the seventh switch P7 and the filter capacitor. C o The negative terminal of the load or the negative terminal of the power grid is connected to the negative terminal of the load. The source of the seventh switch P7 is connected to the drain of the eighth switch P8 and the anode of the fourth clamping diode D4. The source of the eighth switch P8 is connected to the negative terminal of the DC bus. (Filter inductor) L The other end is connected to a filter capacitor. C o The negative terminal of the load or the positive terminal of the power grid; for DNPC three-level inverters: In the first interval, the first switch P1 and the third switch P3 are preset to be complementary switching switches; In the second interval, the sixth switch P6 and the eighth switch P8 are preset to be complementary switching switches; In the third interval, the second switch P2 and the fourth switch P4 are preset to be complementary switching switches; In the fourth interval, the fifth switch P5 and the seventh switch P7 are preset to be complementary switching switches.

[0011] Preferably, the method of pre-setting a pair of complementary switching transistors in each interval further includes: The ANPC three-level inverter is defined by replacing the four clamping diodes of the DNPC three-level inverter with four switching transistors, specifically replacing the first clamping diode D1, the second clamping diode D2, the third clamping diode D3, and the fourth clamping diode D4 with the ninth switching transistor P9 and the tenth switching transistor P1. 10 Eleventh switch P 11 and the twelfth switch P 12 The cathode and anode of the replaced clamping diode correspond to the drain and source of the replaced switching transistor, respectively. The connection relationships of the remaining switching transistors and components are the same as those of the DNPC three-level inverter. For the ANPC three-level inverter: In the first interval, the first switch P1 and the third switch P3 are preset to be complementary switching switches; In the second interval, the sixth switch P6 and the eighth switch P8 are preset to be complementary switching switches; In the third interval, the second switch P2 and the fourth switch P4 are preset to be complementary switching switches; In the fourth interval, the fifth switch P5 and the seventh switch P7 are preset to be complementary switching switches; Within each interval, the switching state of the ninth switch P9 is the same as that of the fourth switch P4; the tenth switch P 10 The switching state of the eleventh switch is the same as that of the first switch P1; 11 The switching state of the twelfth switch P is the same as that of the eighth switch P8; 12 The switching state is the same as that of the fifth switch P5.

[0012] Preferably, the PWM modulation signal of the complementary switching transistor in each interval is obtained by comparing the carrier wave and the modulation wave within each interval, including: Whenever the comparison result between the modulated wave and the triangular carrier changes, the complementary switching transistor in the corresponding modulated wave interval performs an on or off action. Within the first interval, the switching logic for P1 and P3 includes: ; Within the second interval, the switching logic for P6 and P8 includes: ; Within the third interval, the switching logic for P2 and P4 includes: ; Within the fourth interval, the switching logic for P5 and P7 includes: ; in, V Ac Indicates the first triangular carrier wave; V Bc This indicates the second triangular carrier wave.

[0013] Preferably, setting any switching transistor other than the complementary switching transistor in each interval to a preset fixed modulation signal includes: ; ; ; ; The present invention also provides an improved carrier-layered PWM modulation device for three-level inverters, the device being used to implement the method of the present invention.

[0014] The method of the present invention has the following beneficial effects: 1. The method of the present invention divides the fundamental frequency period into four working intervals and proposes the switching logic of the switching transistors in the intervals, so that when the midpoint potential shifts, the NPC full bridge automatically generates a volt-second imbalance in the positive and negative half cycles, thereby exciting a DC bias current on the filter inductor and driving the midpoint potential to automatically restore balance. 2. The midpoint potential balance achieved by the method of this invention does not require a voltage equalization control loop, and no correction or compensation components are introduced during the modulation process, ensuring the quality of the output waveform. Simultaneously, it eliminates the midpoint voltage sampling circuit and voltage equalization regulator found in traditional schemes, effectively avoiding the balance failure problem caused by sensor malfunctions or sudden changes in operating conditions in traditional modulation and control strategies. This method is simple to implement, reducing the cost and size of the inverter.

[0015] The improved carrier-layered PWM modulation device for three-level inverters of the present invention is used to implement the method of the present invention and has the same beneficial effects as the method of the present invention.

[0016] In addition to the objectives, features, and advantages described above, the present invention has other objectives, features, and advantages. The invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of a three-level inverter according to a preferred embodiment of the present invention. (a) represents a TNPC three-level inverter, (b) represents a DNPC three-level inverter, and (c) represents an ANPC three-level inverter.

[0018] Figure 2 This is a schematic diagram of the method flow of a preferred embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the switching transistor driving timing according to a preferred embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of the wave generation logic of complementary switching transistors within the corresponding switching cycles of each interval in a preferred embodiment of the present invention. (a) represents the wave generation logic of complementary switching transistors P1 and P3 in the first interval; (b) represents the wave generation logic of complementary switching transistors P6 and P8 in the second interval; (c) represents the wave generation logic of complementary switching transistors P2 and P4 in the third interval; and (d) represents the wave generation logic of complementary switching transistors P5 and P7 in the fourth interval.

[0021] Figure 5 This is a waveform comparison diagram of a three-level inverter according to a preferred embodiment of the present invention. (a) represents the waveform of the conventional modulation method; (b) represents the waveform of the method of the present invention.

[0022] Figure 6This is a schematic diagram of the additional discharge path of a three-level inverter according to a preferred embodiment of the present invention, wherein (a) corresponds to the TNPC inverter when the inverter output voltage polarity is positive; (b) corresponds to the TNPC inverter when the inverter output voltage polarity is negative; (c) corresponds to the DNPC inverter when the inverter output voltage polarity is positive; (d) corresponds to the DNPC inverter when the inverter output voltage polarity is negative; (e) corresponds to the ANPC inverter when the inverter output voltage polarity is positive; and (f) corresponds to the ANPC inverter when the inverter output voltage polarity is negative.

[0023] Figure 7 This is a schematic diagram of the dynamic simulation waveform of the midpoint potential balance in a preferred embodiment of the present invention. Wherein (a) represents the upper and lower split capacitors. V CU and V CD (a) Voltage simulation waveform; (b) Represents the DC bias current at the midpoint. The simulated waveform. Detailed Implementation

[0024] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0025] See Figure 1 The three-level inverter in the preferred embodiment of the present invention includes a TNPC three-level inverter, a DNPC three-level inverter, and an ANPC three-level inverter.

[0026] See Figure 1 (a) The TNPC three-level inverter includes an upper split capacitor. C U upper split capacitor C U The negative terminal of the split capacitor is connected. C D The positive terminal, the split capacitor C U The positive terminal is connected to the positive terminal of the DC bus, and the lower split capacitor is connected. C D The negative terminal is connected to the negative terminal of the DC bus; the upper split capacitor C U With the lower split capacitor C D The intermediate node O is electrically connected to the drain of the second switch P2 and the drain of the sixth switch P6; the source of the second switch P2 is electrically connected to the source of the third switch P3, and the drain of the third switch P3 is electrically connected to the source of the first switch P1, the drain of the fourth switch P4, and the filter inductor. LOne end; the drain of the first switch P1 is electrically connected to the positive terminal of the DC bus and the drain of the fifth switch P5; the source of the fourth switch P4 is connected to the negative terminal of the DC bus and the source of the eighth switch P8; the source of the sixth switch P6 is connected to the source of the seventh switch P7, and the drain of the seventh switch P7 is connected to the source of the fifth switch P5, the drain of the eighth switch P8, and the filter capacitor. C o The negative terminal of the load or the negative terminal of the power grid; filter inductor L The other end is electrically connected to a filter capacitor. C o The negative terminal of the load or the positive terminal of the power grid.

[0027] See Figure 1 (b) The DNPC three-level inverter includes an upper split capacitor. C U upper split capacitor C U The negative terminal of the split capacitor is connected. C D The positive terminal, the split capacitor C U The positive terminal is connected to the positive terminal of the DC bus, and the lower split capacitor is connected. C D The negative terminal is connected to the negative terminal of the DC bus; the upper split capacitor C U With the lower split capacitor C D The intermediate node O is electrically connected to the anode of the first clamping diode D1 and the third clamping diode D3, and the cathode of the second clamping diode D2 and the fourth clamping diode D4; the drain P1 of the first switching transistor is connected to the positive terminal of the DC bus, the source of the first switching transistor P1 is connected to the drain of the second switching transistor P2 and the cathode of the first clamping diode D1, and the source of the second switching transistor P2 is connected to the drain of the third switching transistor P3 and the filter inductor. L At one end, the source of the third switch P3 is connected to the drain of the fourth switch P4 and the anode of the second clamping diode D2; the source of the fourth switch P4 is connected to the negative terminal of the DC bus; the drain of the fifth switch P5 is connected to the positive terminal of the DC bus; the source of the fifth switch P5 is connected to the drain of the sixth switch P6 and the cathode of the third clamping diode D3; the source of the sixth switch P6 is connected to the drain of the seventh switch P7 and the filter capacitor. C o The negative terminal of the load or the negative terminal of the power grid is connected to the negative terminal of the load. The source of the seventh switch P7 is connected to the drain of the eighth switch P8 and the anode of the fourth clamping diode D4. The source of the eighth switch P8 is connected to the negative terminal of the DC bus. (Filter inductor) L The other end is connected to a filter capacitor. C o The negative terminal of the load or the positive terminal of the power grid.

[0028] See Figure 1 (c) The ANPC three-level inverter replaces the four clamping diodes of the DNPC three-level inverter with four switching transistors. Specifically, the first clamping diode D1, the second clamping diode D2, the third clamping diode D3, and the fourth clamping diode D4 are replaced with the ninth switching transistor P9 and the tenth switching transistor P1. 10 Eleventh switch P 11 and the twelfth switch P 12 The cathode and anode of the original clamping diode correspond to the drain and source of the replaced switching transistor, respectively. The connection relationships of the remaining switching transistors and components are the same as those of the DNPC three-level inverter.

[0029] exist Figure 1 middle, and V out These represent the input voltage and the output voltage, respectively.

[0030] See Figure 2 In a preferred embodiment of the present invention, an improved carrier-layered PWM modulation method for three-level inverters is provided, comprising: S1. Construct a carrier wave based on the switching frequency of the switching transistor; the carrier wave includes a first triangular carrier wave with a range of 0 to 1 and a second triangular carrier wave with a range of -1 to 0.

[0031] S2. Construct a modulation wave based on the modulation index and fundamental frequency output by the inverter closed-loop controller; the modulation wave includes a first sinusoidal modulation wave and a second sinusoidal modulation wave with a phase angle difference of 180°.

[0032] In a preferred embodiment of the present invention, the first sinusoidal modulation wave and the second sinusoidal modulation wave include: ; ; in, V Aref and V Bref These represent the first sinusoidal modulation wave and the second sinusoidal modulation wave, respectively. m Indicates the adjustment system; Indicates the fundamental frequency; t Indicates time.

[0033] S3. Divide one fundamental period of the first sinusoidal modulation wave into four intervals; and preset a pair of complementary switching transistors in each interval.

[0034] In a preferred embodiment of the present invention, dividing one fundamental period of the first sinusoidal modulation wave into four intervals includes: The inverter operating range is divided into four intervals based on one fundamental period of the first sinusoidal modulation wave: the first interval [0, 0.5], the second interval [0.5, 1], the third interval [-0.5, 0], and the fourth interval [-1, -0.5].

[0035] In a preferred embodiment of the present invention, a pair of complementary switching transistors are preset in each interval, including: For TNPC three-level inverters, DNPC three-level inverters, and ANPC three-level inverters: In the first interval, the first switch P1 and the third switch P3 are preset to be complementary switching switches; In the second interval, the sixth switch P6 and the eighth switch P8 are preset to be complementary switching switches; In the third interval, the second switch P2 and the fourth switch P4 are preset to be complementary switching switches; In the fourth interval, the fifth switch P5 and the seventh switch P7 are preset to be complementary switching switches.

[0036] In addition, for ANPC three-level inverters: Within each interval, the switching state of the ninth switch P9 is the same as that of the fourth switch P4; the tenth switch P 10 The switching state of the eleventh switch is the same as that of the first switch P1; 11 The switching state of the twelfth switch P is the same as that of the eighth switch P8; 12 The switching state is the same as that of the fifth switch P5.

[0037] S4. Set any switching transistor other than the complementary switching transistor in each interval to a preset fixed modulation signal; compare the carrier wave and the modulation wave in each interval to obtain the PWM modulation signal of the complementary switching transistor in each interval.

[0038] In a preferred embodiment of the present invention, setting any switching transistor other than the complementary switching transistor in each interval to a preset fixed modulation signal includes: ; ; ; ; The compare(·) function represents comparison.

[0039] In a preferred embodiment of the present invention, obtaining the PWM modulation signal of the complementary switching transistor in each interval by comparing the carrier wave and the modulation wave includes: Whenever the comparison result between the modulated wave and the triangular carrier changes, the complementary switching transistor within the corresponding modulated wave interval performs an on or off operation; if the inverter's output voltage V out If the polarity remains unchanged, only a single split capacitor will charge and discharge. When the three-level inverter operates at half the positive half-cycle of the fundamental frequency, only the upper split capacitor... C U Absorbing or releasing charge. When the three-level inverter operates at 1 / 2 level of the negative half-fundamental cycle, only the lower split capacitor is present. C D It absorbs or releases charge. The midpoint potential shift causes a volt-second imbalance in the NPC full-bridge output during the fundamental cycle. Exciting the filter inductor to generate a DC bias current can achieve midpoint potential balance.

[0040] Within the first interval, the switching logic for P1 and P3 includes: ; Within the second interval, the switching logic for P6 and P8 includes: ; Within the third interval, the switching logic for P2 and P4 includes: ; Within the fourth interval, the switching logic for P5 and P7 includes: ; in, V Ac Indicates the first triangular carrier wave; V Bc This indicates the second triangular carrier wave.

[0041] In summary, the combinations of switching transistors involved in high-frequency switching and their conduction states in different ranges of the three-level inverter are shown in Table 1, and their on / off times are as follows: Figures 3 to 4 .

[0042] Table 1 Switch Combinations and On-State Table ; That is, only one pair of complementary switches operates within each switching cycle. In interval 1, only P1 and P3 operate; in interval 2, only P6 and P8 operate; in interval 3, only P2 and P4 operate; and in interval 4, only P5 and P7 operate. Intervals 1, 2, 3, and 4 correspond to the first, second, third, and fourth intervals, respectively.

[0043] By modulating the signals of each switch transistor and driving each switch transistor to operate, the AC-DC conversion of a three-level inverter can be achieved. This invention eliminates the need for capacitor voltage sampling and control loop design, enhancing the inverter's immunity to disturbances and reducing its cost and size.

[0044] This invention divides the fundamental frequency cycle into four operating intervals and proposes switching logic within each interval. This allows the NPC full-bridge to automatically generate a volt-second imbalance in the positive and negative half-cycles when the midpoint potential shifts, thereby exciting a DC bias current in the filter inductor and driving the midpoint potential to automatically restore balance. The midpoint potential balancing method of this invention eliminates the need for a voltage equalization control loop and does not introduce any correction or compensation components during modulation, ensuring output waveform quality. It also eliminates the need for a midpoint voltage sampling circuit and voltage equalization regulator found in traditional solutions, effectively avoiding balance failures caused by sensor malfunctions or sudden changes in operating conditions. This method is simple to implement and reduces the cost and size of the inverter.

[0045] In a preferred embodiment of the present invention, an improved carrier-layered PWM modulation device for three-level inverters is also provided, the device being used to implement the method of the present invention.

[0046] The improved carrier-layered PWM modulation device for three-level inverters of the present invention is used to implement the method of the present invention and has the same beneficial effects as the method of the present invention.

[0047] Verification section: A waveform comparison between the traditional modulation method of a three-level inverter and the method of this invention: Figure 5 As shown in the figure. V outa For the upper split capacitor C U Voltage higher than the lower split capacitor C D The output voltage waveform when the voltage is applied. V outb This represents the ideal output voltage waveform when the midpoint potential is balanced. Wherein, Figure 5 In Figures (a) and (b), the modulation signal and output voltage waveforms of a three-level inverter are shown in the conventional method and the method of this invention, respectively. In the conventional modulation method, when the inverter output voltage... V out When the polarity remains constant, the two split capacitors discharge alternately, and the midpoint potential fluctuates continuously within the fundamental frequency period. V outaThe waveform remains symmetrical, the volt-second product of the output voltage is zero, and a continuous and constant-direction DC bias current cannot be generated, making it difficult for the midpoint potential to converge. In the method of this invention, when the polarity of the inverter output voltage remains unchanged, only a single split capacitor charges and discharges. If the midpoint potential shifts, the amplitudes of the positive and negative half-cycles of the output voltage within the fundamental period are not equal. V outb The waveform is asymmetrical, and the volt-second product is not zero, which generates a continuous and constant DC bias current, causing the midpoint potential to converge rapidly to an equilibrium state.

[0048] like Figure 6 The figure shows the voltage of the split capacitor. V CU Greater than the voltage of the lower split capacitor V CD At this time, the additional discharge path caused by the DC bias current of the three-level inverter. When the inverter output voltage polarity is positive, only the split capacitor is connected. C U Discharge, additional charge release, decrease in midpoint potential offset; the additional discharge paths for TNPC, DNPC, and ANPC inverters are as follows: Figure 6 As shown in (a), (c), and (e); when the output voltage polarity is negative, only the split capacitor is used. C D Charging, the DC bias current causes it to absorb additional charge, and the midpoint potential offset continues to decrease. The additional discharge paths corresponding to the three inverters are as follows: Figure 6 As shown in (b), (d), and (f), under the method of this invention, the midpoint potential continues to rise until it reaches an equilibrium state.

[0049] Figure 7 The simulation waveform for midpoint potential balance using the method of this invention is shown. When using a traditional modulation method, due to non-ideal factors such as asynchronous drive signals, asymmetrical midpoint current, and differences in capacitance values, the two split capacitors will exhibit a steady-state midpoint potential shift. To facilitate observation of the impact of non-ideal factors on the midpoint potential shift, the capacitance values ​​of the upper and lower split capacitors in the simulation are 350μF and 250μF, respectively. The fundamental frequency of the converter output is 500Hz. Figure 7 When using traditional modulation methods, V CU and V CD The steady-state unbalanced voltage is 132V. Replacing the traditional modulation method with the method of this invention at 0.5s, the midpoint potential will converge to an equilibrium state after 320ms. During the convergence process, the DC bias current... The flow continues from the neutral point until the midpoint potential converges to the equilibrium point.

[0050] In summary, the method of this invention can achieve self-balancing of the midpoint potential of a three-level inverter from the modulation level without adding sensors and closed-loop control.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An improved carrier-layered PWM modulation method for three-level inverters, characterized in that, include: A carrier wave is constructed based on the switching frequency of the switching transistor; the carrier wave includes a first triangular carrier wave with a range of 0 to 1 and a second triangular carrier wave with a range of -1 to 0; a modulation wave is constructed based on the modulation index and fundamental frequency output by the inverter closed-loop controller; the modulation wave includes phase angle and phase difference. The first and second sinusoidal modulating waves; The fundamental period of the first sinusoidal modulation wave is divided into four intervals; a pair of complementary switching transistors are preset in each interval; any switching transistor other than the complementary switching transistors in each interval is set to a preset fixed modulation signal; the PWM modulation signal of the complementary switching transistors in each interval is obtained by comparing the carrier wave and the modulation wave.

2. The improved carrier-layered PWM modulation method for three-level inverters according to claim 1, characterized in that, The first and second sinusoidal modulating waves include: ； ； in, V Aref and V Bref These represent the first sinusoidal modulation wave and the second sinusoidal modulation wave, respectively. m Indicates the adjustment system; Indicates the fundamental frequency; t Indicates time.

3. The improved carrier-layered PWM modulation method for three-level inverters according to claim 2, characterized in that, The fundamental period of the first sinusoidal modulation wave is divided into four intervals: The inverter operating range is divided into four intervals: the first interval [0, 0.5], the second interval [0.5, 1], the third interval [-0.5, 0], and the fourth interval [-1, -0.5].

4. The improved carrier-layered PWM modulation method for three-level inverters according to claim 3, characterized in that, Each interval includes a pair of complementary switching transistors: Define the upper split capacitor in the TNPC three-level inverter. C U The negative terminal of the split capacitor is connected. C D The positive terminal, the split capacitor C U The positive terminal is connected to the positive terminal of the DC bus, and the lower split capacitor is connected. C D The negative terminal is connected to the negative terminal of the DC bus; the upper split capacitor C U With the lower split capacitor C D The intermediate node O is electrically connected to the drain of the second switch P2 and the drain of the sixth switch P6; the source of the second switch P2 is electrically connected to the source of the third switch P3, and the drain of the third switch P3 is electrically connected to the source of the first switch P1, the drain of the fourth switch P4, and the filter inductor. L One end; the drain of the first switch P1 is electrically connected to the positive terminal of the DC bus and the drain of the fifth switch P5; the source of the fourth switch P4 is connected to the negative terminal of the DC bus and the source of the eighth switch P8; the source of the sixth switch P6 is connected to the source of the seventh switch P7, and the drain of the seventh switch P7 is connected to the source of the fifth switch P5, the drain of the eighth switch P8, and the filter capacitor. C o The negative terminal of the load or the negative terminal of the power grid; filter inductor L The other end is electrically connected to a filter capacitor. C o The negative terminal of the load or the positive terminal of the power grid; for TNPC three-level inverters: In the first interval, the first switch P1 and the third switch P3 are preset to be complementary switching switches; In the second interval, the sixth switch P6 and the eighth switch P8 are preset to be complementary switching switches; In the third interval, the second switch P2 and the fourth switch P4 are preset to be complementary switching switches; In the fourth interval, the fifth switch P5 and the seventh switch P7 are preset to be complementary switching switches.

5. The improved carrier-layered PWM modulation method for three-level inverters according to claim 3, characterized in that, Pre-setting a pair of complementary switching transistors in each interval also includes: Define the upper split capacitor in a DNPC three-level inverter. C U The negative terminal of the split capacitor is connected. C D The positive terminal, the split capacitor C U The positive terminal is connected to the positive terminal of the DC bus, and the lower split capacitor is connected. C D The negative terminal is connected to the negative terminal of the DC bus; the upper split capacitor C U With the lower split capacitor C D The intermediate node O is electrically connected to the anode of the first clamping diode D1 and the third clamping diode D3, and the cathode of the second clamping diode D2 and the fourth clamping diode D4; the drain P1 of the first switching transistor is connected to the positive terminal of the DC bus, the source of the first switching transistor P1 is connected to the drain of the second switching transistor P2 and the cathode of the first clamping diode D1, and the source of the second switching transistor P2 is connected to the drain of the third switching transistor P3 and the filter inductor. L At one end, the source of the third switch P3 is connected to the drain of the fourth switch P4 and the anode of the second clamping diode D2; the source of the fourth switch P4 is connected to the negative terminal of the DC bus; the drain of the fifth switch P5 is connected to the positive terminal of the DC bus; the source of the fifth switch P5 is connected to the drain of the sixth switch P6 and the cathode of the third clamping diode D3; the source of the sixth switch P6 is connected to the drain of the seventh switch P7 and the filter capacitor. C o The negative terminal of the load or the negative terminal of the power grid is connected to the negative terminal of the load. The source of the seventh switch P7 is connected to the drain of the eighth switch P8 and the anode of the fourth clamping diode D4. The source of the eighth switch P8 is connected to the negative terminal of the DC bus. (Filter inductor) L The other end is connected to a filter capacitor. C o The negative terminal of the load or the positive terminal of the power grid; for DNPC three-level inverters: In the first interval, the first switch P1 and the third switch P3 are preset to be complementary switching switches; In the second interval, the sixth switch P6 and the eighth switch P8 are preset to be complementary switching switches; In the third interval, the second switch P2 and the fourth switch P4 are preset to be complementary switching switches; In the fourth interval, the fifth switch P5 and the seventh switch P7 are preset to be complementary switching switches.

6. The improved carrier-layered PWM modulation method for three-level inverters according to claim 3, characterized in that, Pre-setting a pair of complementary switching transistors in each interval also includes: The ANPC three-level inverter is defined by replacing the four clamping diodes of the DNPC three-level inverter with four switching transistors, specifically replacing the first clamping diode D1, the second clamping diode D2, the third clamping diode D3, and the fourth clamping diode D4 with the ninth switching transistor P9 and the tenth switching transistor P1. 10 Eleventh switching transistor P 11 and the twelfth switch P 12 The cathode and anode of the replaced clamping diode correspond to the drain and source of the replaced switching transistor, respectively. The connection relationships of the remaining switching transistors and components are the same as those of the DNPC three-level inverter. For the ANPC three-level inverter: In the first interval, the first switch P1 and the third switch P3 are preset to be complementary switching switches; In the second interval, the sixth switch P6 and the eighth switch P8 are preset to be complementary switching switches; In the third interval, the second switch P2 and the fourth switch P4 are preset to be complementary switching switches; In the fourth interval, the fifth switch P5 and the seventh switch P7 are preset to be complementary switching switches; Within each interval, the switching state of the ninth switch P9 is the same as that of the fourth switch P4; the tenth switch P 10 The switching state of the eleventh switch is the same as that of the first switch P1; 11 The switching state of the twelfth switch P is the same as that of the eighth switch P8; 12 The switching state is the same as that of the fifth switch P5.

7. The improved carrier-layered PWM modulation method for three-level inverters according to any one of claims 4 to 6, characterized in that, Within each interval, the PWM modulation signal of the complementary switching transistor is obtained by comparing the carrier wave and the modulation wave. Whenever the comparison result between the modulated wave and the triangular carrier changes, the complementary switching transistor in the corresponding modulated wave interval performs an on or off action. Within the first interval, the switching logic for P1 and P3 includes: ； Within the second interval, the switching logic for P6 and P8 includes: ； Within the third interval, the switching logic for P2 and P4 includes: ； Within the fourth interval, the switching logic for P5 and P7 includes: ； in, V Ac Indicates the first triangular carrier wave; V Bc This indicates the second triangular carrier wave.

8. The improved carrier-layered PWM modulation method for three-level inverters according to claim 7, characterized in that, All switching transistors other than the complementary switching transistors within each interval are configured to use a preset fixed modulation signal, including: ； ； ； 。 9. An improved carrier-layered PWM modulation device for three-level inverters, characterized in that, The apparatus is used to implement the method according to any one of claims 1 to 8.

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