Intelligent power module and control method thereof for preventing up-and-down bridge straight-through

Abstract

The application discloses an intelligent power module preventing up-and-down bridge straight-through and a control method thereof, which comprises a packaging shell, an upper bridge arm power switch device, a lower bridge arm power switch device and a low-voltage side control chip; further comprising a sampling resistor, an operational amplifier and a passage cut-off switch device; the sampling resistor is connected in series between the emitter of the lower bridge arm power switch device and the negative terminal pin of a DC bus; the same-phase input end and the opposite-phase input end of the operational amplifier are respectively connected to the two ends of the sampling resistor, and the output end is connected to the voltage detection input end of the low-voltage side control chip; the passage cut-off switch device is connected in series in the current passage between the emitter of the lower bridge arm power switch device and the negative terminal pin of the DC bus, the control end is connected to the switch control output end of the low-voltage side control chip, and the passage cut-off switch device is in a conducting state by default. According to the application, the voltage between the emitter of the lower bridge arm and the negative terminal of the DC bus is detected by the sampling resistor, so that the passage cut-off switch device can cut off the straight-through loop in the initial stage of abnormal conduction, and the burning risk is reduced.

Description

Technical Field

[0001] This invention relates to the field of motor drive technology, specifically to an intelligent power module and its control method for preventing direct connection between upper and lower bridges. Background Technology

[0002] An Intelligent Power Module (IPM) is a power semiconductor module that integrates power switching devices (typically Insulated Gate Bipolar Transistors (IGBTs) or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)) along with their drive circuits, various protection circuits, and logic control circuits into a single package. It is widely used in motor drives, variable frequency speed control, servo systems, and power conversion. Its high integration significantly simplifies peripheral circuit design, shortens product development cycles, and improves overall system reliability, making it a core power conversion component in modern power electronic equipment.

[0003] A typical three-phase IPM employs a three-phase inverter bridge topology, consisting of upper and lower bridge arm power switching devices. During normal operation, the corresponding phases of the upper and lower bridge arms are alternately turned on according to PWM control signals, inverting the DC bus voltage into a three-phase AC output voltage. To prevent a short circuit on the DC bus caused by simultaneous conduction of the upper and lower bridge arms, the IPM typically includes conventional protection functions such as dead-time control, overcurrent protection (OC), undervoltage protection (UV), overheat protection (OH), and fault alarm output (FO).

[0004] However, in actual operation, IPMs still frequently experience serious faults such as shoot-through burnout of the upper and lower bridge arm power switching devices. The root cause of this fault is that, under the influence of parasitic inductance in the PCB (Printed Circuit Board) layout, stray parameters in the power loop, or external electromagnetic interference coupling, when an abnormal voltage spike or surge occurs between the emitter of the lower bridge arm power switching device and the negative terminal (Vnc) of the DC bus, the lower bridge arm power switching device may automatically turn on without receiving a valid turn-on command. If the upper bridge arm power switching device is in a normal conducting state at this time, a low-impedance shoot-through loop is formed at the positive terminal of the DC bus through the upper bridge arm power switching device, the lower bridge arm power switching device, and Vnc. The instantaneous short-circuit current can reach hundreds of amperes, causing the IGBT junction temperature to rise sharply within microseconds and resulting in thermal breakdown and burnout.

[0005] To address the aforementioned faults, existing IPMs primarily rely on overcurrent protection mechanisms, which detect the power circuit current and shut down the gate drive signal of the power switching device in the event of an overcurrent. This mechanism has the following inherent drawbacks when dealing with momentary false turn-on of the lower arm caused by parasitic inductance and electromagnetic interference: First, overcurrent protection is a reactive measure, requiring the short-circuit current to rise to a threshold before triggering. However, the short-circuit current caused by false turn-on can reach hundreds of amperes within microseconds, meaning the device often experiences excessive electrical and thermal stress before the protection response. Second, current detection cannot distinguish between normal load current and abnormal shoot-through current, making it prone to false triggering under heavy load startup, stall conditions, etc. Third, when electromagnetic interference causes false turn-on, the gate drive signal itself may already be malfunctioning due to interference. In this case, a soft turn-off scheme that only shuts down the gate cannot reliably shut down the device that has already been falsely turned on, inevitably leading to protection failure.

[0006] Therefore, there is an urgent need for an IPM protection scheme that can identify and intervene in the early stage of abnormal conduction of the lower bridge arm, fundamentally cut off the shoot-through circuit, and is unaffected by the gate drive state, so as to effectively reduce the risk of shoot-through burnout of the upper and lower bridge arms. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides an intelligent power module and its control method for preventing direct connection between upper and lower bridges. This module effectively identifies and intervenes in the early stages of abnormal self-conduction of the lower bridge arm, fundamentally cutting off the direct connection circuit and significantly reducing the risk of burnout due to direct connection between upper and lower bridges.

[0008] According to a first aspect of the present invention, a smart power module for preventing up-and-down bridge shoot-through is provided, comprising a package housing, an upper bridge arm power switching device, a lower bridge arm power switching device, and a low-voltage side control chip. The smart power module further includes a sampling resistor, an operational amplifier, and a path-cutting switch. The sampling resistor is connected in series between the emitter of the lower bridge arm power switching device and the negative terminal pin of the DC bus; The non-inverting and inverting input terminals of the operational amplifier are respectively connected to the two ends of the sampling resistor, and the output terminal of the operational amplifier is connected to the voltage detection input terminal of the low-voltage side control chip. The path cut-off switch is connected in series in the current path between the emitter of the lower bridge arm power switch and the negative terminal pin of the DC bus. The control terminal of the path cut-off switch is connected to the switch control output terminal of the low-voltage side control chip. The path cut-off switch is in the on state by default.

[0009] Furthermore, the lower bridge arm power switching device includes a first phase lower bridge IGBT, a second phase lower bridge IGBT, and a third phase lower bridge IGBT; the path disconnection switching device includes a first phase disconnection IGBT, a second phase disconnection IGBT, and a third phase disconnection IGBT; the first phase disconnection IGBT is connected in series between the emitter of the first phase lower bridge IGBT and the negative terminal pin of the DC bus, the second phase disconnection IGBT is connected in series between the emitter of the second phase lower bridge IGBT and the negative terminal pin of the DC bus, and the third phase disconnection IGBT is connected in series between the emitter of the third phase lower bridge IGBT and the negative terminal pin of the DC bus.

[0010] Furthermore, the collectors of the first phase cutoff IGBT, the second phase cutoff IGBT, and the third phase cutoff IGBT are respectively connected to the emitters of the first phase lower bridge IGBT, the second phase lower bridge IGBT, and the third phase lower bridge IGBT. The emitters of the first phase cutoff IGBT, the second phase cutoff IGBT, and the third phase cutoff IGBT are all connected to the negative terminal pin of the DC bus. The gates of the first phase cutoff IGBT, the second phase cutoff IGBT, and the third phase cutoff IGBT are all connected to the switch control output terminal of the low-voltage side control chip.

[0011] Furthermore, the sampling resistor is a common sampling resistor, one end of which is connected to the emitter of each phase IGBT in the lower bridge arm power switching device, and the other end of which is connected to the negative terminal pin of the DC bus.

[0012] Furthermore, the sampling resistor includes a first sampling resistor, a second sampling resistor, and a third sampling resistor; the first sampling resistor is connected in series between the emitter of the first phase lower bridge IGBT and the negative terminal pin of the DC bus, the second sampling resistor is connected in series between the emitter of the second phase lower bridge IGBT and the negative terminal pin of the DC bus, and the third sampling resistor is connected in series between the emitter of the third phase lower bridge IGBT and the negative terminal pin of the DC bus.

[0013] Furthermore, it also includes a fault output pin, which is disposed on the package housing and connected to the fault signal output terminal of the low-voltage side control chip.

[0014] Furthermore, it also includes a protection enable pin, which is disposed on the package housing and connected to the enable signal input terminal of the low-voltage side control chip.

[0015] Furthermore, a pull-down resistor is connected between the protection enable pin and the low-voltage side control chip, and the other end of the pull-down resistor is grounded.

[0016] Furthermore, the low-voltage side control chip is configured to: maintain the circuit cut-off switch on when the detection voltage output by the operational amplifier is less than a preset threshold; and control the circuit cut-off switch to turn off and output a fault signal through the fault output pin when the detection voltage is greater than or equal to the preset threshold.

[0017] According to a second aspect of the present invention, a power device is provided. The power device includes a main control chip and the intelligent power module described in the first aspect of the present invention; the fault signal input terminal of the main control chip is connected to the fault output pin of the intelligent power module, and the PWM output terminal of the main control chip is connected to the drive signal input terminal of the intelligent power module.

[0018] According to a third aspect of the present invention, a method for preventing bridge over / underpass bypass control of the intelligent power module according to the first aspect of the present invention is provided, which is executed at the low-voltage side control chip. The method includes the following steps: The detection voltage output by the operational amplifier is acquired in real time, and the detection voltage reflects the voltage between the emitter of the lower bridge arm power switching device and the negative terminal of the DC bus. The detected voltage is compared with a preset threshold. When the detected voltage is greater than or equal to the preset threshold, it is determined that there is a risk of abnormal conduction in the lower bridge arm, and a turn-off signal is output to the circuit cut-off switching device to physically cut off the current path of the lower bridge arm power switching device.

[0019] Furthermore, the method also includes: when the detected voltage is greater than or equal to the preset threshold, outputting a fault signal to the main control chip through the fault output pin, so that the main control chip shuts down the PWM wave output.

[0020] Furthermore, the method also includes: Detect the level state of the protection enable pin; When the protection enable pin receives a valid level signal, the steps of shielding voltage comparison and shutting off the path disconnection switching device are performed to maintain the path disconnection switching device on.

[0021] Furthermore, the effective level signal is a high level signal.

[0022] Furthermore, the detection voltage output by the operational amplifier is obtained in the following manner: The voltage between the emitter of the lower bridge arm power switching device and the negative terminal of the DC bus is converted into a voltage signal by the sampling resistor, and then amplified by the operational amplifier to output the detection voltage.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The voltage between the emitter of the lower bridge arm power switching device and the negative terminal of the DC bus is selected as the protection trigger index. When parasitic inductance or electromagnetic interference causes an abnormal shift in the emitter potential, this voltage change is detected before the formation of the short-circuit current. Existing overcurrent protections all select current as the detection object, the fundamental reason being that overcurrent protection targets the already formed short-circuit current; while this application targets the potential anomaly before the occurrence of false conduction. In this scenario, current detection not only has a delayed response but also cannot distinguish between normal load current and abnormal shoot-through current, and is prone to misjudgment under heavy load conditions. This invention achieves a technical leap from post-current remedy to pre-voltage prediction by changing the detection index from current. Experimental studies show that the protection response time is shortened to 1 to 3 microseconds, which greatly improves the protection effectiveness, and the detection sensitivity and accuracy are better than traditional current detection schemes. 2. This method physically disconnects the lower bridge arm circuit directly through a circuit-breaking switch connected in series in the main current path, unlike traditional overcurrent protection methods that only turn off the gate drive signal. There is a fundamental difference between physical disconnection and soft turn-off, which only turns off the gate drive signal of the power switching device: soft turn-off relies on the power switching device's gate still being able to receive the drive signal normally; when the gate becomes uncontrolled due to electromagnetic interference, soft turn-off fails. Physical disconnection, on the other hand, directly disconnects the main current path through an independent circuit-breaking switch, unaffected by the gate state of the lower bridge arm power switching device. Even if the lower bridge arm power switching device has been mis-turned on due to interference and its gate cannot be turned off, the circuit-breaking switch can still reliably disconnect the circuit. Therefore, even if the lower bridge arm power switching device fails to turn off due to gate drive failure caused by interference, the circuit-breaking switch can still reliably disconnect the main current path, significantly improving anti-interference capability and protection reliability. 3. A protection enable pin is set to allow the protection function to be actively disabled in application scenarios where the risk of abnormal conduction of the lower bridge has been confirmed by actual testing. This avoids false protection affecting the normal operation of the system, thus balancing protection security and application flexibility. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the circuit structure of an intelligent power module for preventing direct connection between upper and lower bridges in one embodiment of the present invention; Explanation of reference numerals in the attached figures: P—DC bus voltage input terminal; HVIC – High-voltage side driver chip; Q1 – First phase IGBT on the bridge; Q2 – Second phase IGBT; Q3 – Third-phase IGBT; U—U-phase AC output terminal; V—V-phase AC output terminal; W-W phase AC output terminal; M – Motor load; LVIC—Low-voltage side control chip; Q4 – First phase downbridge IGBT; Q5 – Second phase downbridge IGBT; Q6 – Third phase downbridge IGBT; Q7 – The first phase disconnects the IGBT; Q8 – The second phase disconnects the IGBT; Q9 – The third phase disconnects the IGBT; NU – Emitter lead-out node of the first phase lower bridge IGBT; NV – Emitter lead-out node of the second phase lower bridge IGBT; NW—Emitter lead-out node of the third phase lower bridge IGBT; U1 — Operational amplifier; RS—Sampling resistor; INT—Protection Enable Pin; FO—Fault signal output pin; Vnc—Negative terminal of DC bus; GND – Ground terminal. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0026] It should be noted that in this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0027] In this invention, if there are descriptions involving "first," "second," "third," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first," "second," or "third" may explicitly or implicitly include at least one of those features.

[0028] According to a first aspect of the present invention, an intelligent power module is provided to prevent direct connection between upper and lower bridges.

[0029] like Figure 1 As shown, in one embodiment, the smart power module includes a package housing, an upper bridge arm power switch, a lower bridge arm power switch, a low-voltage side control chip LVIC, a sampling resistor RS, an operational amplifier U1, and a path cut-off switch.

[0030] The package housing adopts an aluminum insulated base plate structure, with a control pin spacing of 2.54mm and a power pin spacing of 10mm, providing good heat dissipation performance and electromagnetic compatibility. The package housing includes a DC bus positive terminal pin P, a DC bus negative terminal pin Vnc, three-phase output pins U, V, and W, a drive signal input pin, a protection enable pin INT, a fault signal output pin FO, and a ground pin GND.

[0031] The upper bridge arm power switching devices include a first-phase upper bridge IGBT Q1, a second-phase upper bridge IGBT Q2, and a third-phase upper bridge IGBT Q3. The collectors of Q1, Q2, and Q3 are all connected to the positive terminal pin P of the DC bus, and the emitters of Q1, Q2, and Q3 are connected to the three-phase output pins U, V, and W, respectively. The gates of Q1, Q2, and Q3 are all connected to the drive output terminal of the high-voltage side driver chip HVIC. The high-voltage side driver chip HVIC has a built-in high-voltage level conversion circuit, which is used to convert the low-voltage side control signal into the floating drive signal required by the upper bridge arm power switching devices, thereby realizing the high-side drive of the upper bridge arm.

[0032] The lower bridge power switching devices include a first-phase lower bridge IGBT Q4, a second-phase lower bridge IGBT Q5, and a third-phase lower bridge IGBT Q6. The collectors of Q4, Q5, and Q6 are connected to the three-phase output pins U, V, and W, respectively, forming a three-phase half-bridge inverter topology with the corresponding upper bridge power switching devices. The gates of Q4, Q5, and Q6 are all connected to the lower bridge drive output terminal of the low-voltage side control chip LVIC.

[0033] The sampling resistor RS is connected in series between the emitter of the lower bridge power switching device and the negative terminal pin Vnc of the DC bus. Specifically, the emitters of the three-phase lower bridge IGBTs are led out to nodes NU, NV, and NW, respectively. NU, NV, and NW are all connected to one end of the sampling resistor RS, and the other end of the sampling resistor RS is connected to the negative terminal pin Vnc of the DC bus. The sampling resistor RS is a high-precision, low-temperature-drift alloy resistor, and its resistance value is selected according to the IPM's rated current and voltage detection range, typically in the milliohm range, to ensure detection sensitivity while reducing power loss.

[0034] The non-inverting and inverting inputs of the operational amplifier U1 are connected to the two ends of the sampling resistor RS, respectively. Specifically, the non-inverting input is connected to the common node of NU / NV / NW, and the inverting input is connected to the Vnc node. The output of operational amplifier U1 is connected to the voltage detection input of the low-voltage side control chip LVIC. Operational amplifier U1 is a precision operational amplifier with high common-mode rejection ratio and low input offset voltage, used to amplify the weak voltage difference across the sampling resistor RS to a level range recognizable by the low-voltage side control chip LVIC. The amplification factor of operational amplifier U1 is reasonably configured according to a preset threshold and the resistance value of the sampling resistor, so that when the voltage across the sampling resistor RS reaches the threshold specified in the datasheet, operational amplifier U1 outputs the corresponding level.

[0035] The circuit-breaking switching device is connected in series in the current path between the emitter of the lower-phase power switching device and the negative terminal pin Vnc of the DC bus. The circuit-breaking switching device includes a first-phase cutoff IGBT Q7, a second-phase cutoff IGBT Q8, and a third-phase cutoff IGBT Q9. The collector of Q7 is connected to the emitter of the first-phase lower-phase IGBT Q4 (node ​​NU), and the emitter of Q7 is connected to one end of the sampling resistor RS. The collector of Q8 is connected to the emitter of the second-phase lower-phase IGBT Q5 (node ​​NV), and the emitter of Q8 is connected to one end of the sampling resistor RS. The collector of Q9 is connected to the emitter of the third-phase lower-phase IGBT Q6 (node ​​NW), and the emitter of Q9 is connected to one end of the sampling resistor RS. The gates of Q7, Q8, and Q9 are all connected to the switching control output of the low-voltage side control chip LVIC.

[0036] It should be noted that Q7, Q8, and Q9 must withstand the full DC bus voltage when turned off; therefore, their withstand voltage rating should be the same as that of Q4, Q5, and Q6. For example, for a 650V IPM, Q7~Q9 should all be IGBTs with a 650V withstand voltage rating. The circuit-breaking switching device can also be implemented using MOSFETs, relays, or other semiconductor switching devices with controllable switching capabilities, as long as their withstand voltage rating meets the bus voltage requirements, their on-resistance is sufficiently low, and their switching speed meets the protection response time requirements. In this embodiment, IGBTs are used because they are compatible with the lower bridge arm power switching device in terms of process and driving method, facilitating integration within the same IPM package.

[0037] Q7, Q8, and Q9 are in the default conducting state. This default conducting state is achieved in the following ways: when the low-voltage side control chip LVIC is powered on and initialized, it outputs a high-level drive signal to the gates of Q7, Q8, and Q9, causing the three IGBTs to be in a saturated conducting state; or pull-up resistors are set between the gates and emitters of Q7, Q8, and Q9, automatically pulling the gate potential up to above the conduction threshold upon power-up. The default conducting state ensures that the lower bridge arm current path is unobstructed during normal IPM operation and does not affect normal inverter output.

[0038] The low-voltage side control chip LVIC is the core control unit of the entire protection scheme, integrating a voltage comparator, logic judgment circuit, and drive output circuit. The LVIC's voltage detection input receives the detection voltage output from operational amplifier U1, and the internal comparator compares the detection voltage with a preset threshold. The preset threshold is the maximum permissible voltage between the emitter of the lower bridge arm and the negative terminal of the DC bus, as specified in the IPM datasheet. This value is determined comprehensively based on the IGBT's drive characteristics, package parasitic parameters, and safe operating area. For common 650V / 50A IPMs, the typical range of the preset threshold is 0.5V to 2V, for example, it can be set to 0.8V or 1V. The threshold setting is based on the fact that the gate-emitter threshold voltage Vge(th) of each phase's lower bridge IGBT is typically between 2V and 5V. As analyzed above, when the gate is clamped to 0V relative to Vnc, the amplitude of the gate-emitter voltage Vge is equal to the voltage amplitude of the emitter relative to Vnc. Considering the voltage drop caused by parasitic inductance during switching transients, the common-mode interference tolerance of the drive circuit, and an appropriate safety margin, the voltage protection threshold is set between 0.5V and 2V. This threshold is lower than the actual gate mis-turn-on threshold of each phase's lower-bridge IGBT, ensuring sensitive identification of abnormal conduction while avoiding false triggering during normal switching transients. When the detected voltage is less than the preset threshold, the LVIC determines that the lower-bridge arm is working normally, maintaining the conduction state of Q7, Q8, and Q9, and the IPM performs the inverter function normally. When the detected voltage is greater than or equal to the preset threshold, the LVIC determines that there is a risk of abnormal conduction in the lower-bridge arm and immediately outputs a turn-off signal to the gates of Q7, Q8, and Q9, causing each phase's lower-bridge IGBT to turn off simultaneously, thereby physically cutting off the current path of the three-phase lower-bridge arm.

[0039] The physical disconnection described here refers to completely disconnecting the power circuit electrically by turning off the switching devices connected in series in the power circuit. Physical disconnection differs fundamentally from the soft turn-off method, which only turns off the IGBT gate drive signal: soft turn-off relies on the IGBT gate still being able to receive the drive signal normally; when the gate becomes uncontrolled due to interference, soft turn-off fails. Physical disconnection, on the other hand, directly disconnects the main current path by cutting off the switching devices through an independent path, unaffected by the gate states of the lower-phase IGBTs Q4, Q5, and Q6 in the lower-arm power switching devices. Even if Q4~Q6 have been mis-turned on due to interference and their gates cannot be turned off, the turn-off of Q7~Q9 can still reliably disconnect the circuit.

[0040] The working principle of this embodiment is as follows: During normal operation of the IPM, parasitic inductance of the PCB layout, stray parameters of the power loop, or external electromagnetic interference may cause abnormal voltage spikes or surges in the emitter potential of the lower arm power switching device relative to Vnc. If this abnormal voltage reaches the IGBT's mis-turn-on threshold, it will cause the lower arm power switching device to turn on automatically without receiving a turn-on command. If the upper IGBT in the upper arm corresponding to this abnormality is in the on state at this time, the positive terminal P of the DC bus is connected to the negative terminal Vnc of the DC bus in sequence through the upper IGBT, the corresponding phase output terminal, the mis-turned lower IGBT, the corresponding phase cut-off IGBT, and the sampling resistor RS, thereby forming a low-impedance shoot-through short-circuit loop.

[0041] It is important to note that this embodiment differs fundamentally from startup self-test solutions. Existing technologies include solutions that probe for short-circuit damage in the lower bridge during the power-on startup phase by testing the upper bridge's semi-conductivity. This approach relies on the upper bridge arm being in a controlled semi-conducting state, detecting whether the lower bridge has suffered a permanent short-circuit damage to prevent the fault from escalating during startup. However, this solution cannot be applied during operation—during normal operation, the upper and lower bridges alternately conduct, and there is always load current across the sampling resistor, rendering its detection principle completely ineffective. In contrast, this embodiment targets momentary false triggering caused by dynamic interference throughout the entire operating cycle. It detects abnormal shifts in the emitter potential rather than the load current, and can operate in real-time throughout the entire operating cycle.

[0042] In this embodiment, the sampling resistor RS detects the voltage between the emitters NU / NV / NW of each phase of the lower bridge arm and the negative terminal Vnc of the DC bus in real time. The operational amplifier U1 amplifies this voltage and sends it to the low-voltage side control chip LVIC. Once the voltage exceeds a preset threshold, the LVIC completes the logic judgment and outputs a turn-off signal within a typical time of 1 to 3 microseconds. The circuit-cutting switching devices in each phase switch IGBTs Q7, Q8, and Q9 switch from on to off, physically cutting off the current path of the lower bridge arm. Even if the power switching devices of the lower bridge arm are mistakenly turned on, a continuous short-circuit current cannot be formed, thereby effectively preventing the upper and lower bridges from being burned out by shoot-through.

[0043] In a classic operating condition analysis, for a 650V / 50A IPM, under the conditions of a DC bus voltage of 380V and typical short-circuit impedance: traditional overcurrent protection takes about 5 to 10 microseconds from the occurrence of a short circuit to triggering shutdown. At this time, the short-circuit current has reached 300 to 500 amperes, and the junction temperature of the power switching device rises transiently by more than 80 degrees Celsius, posing a risk of thermal breakdown. In contrast, the voltage prediction protection in this embodiment takes about 1 to 3 microseconds from the abnormal emitter voltage to the complete shutdown of the circuit cut-off switch. At this time, the short-circuit current has not yet exceeded 100 amperes, and the electrical and thermal stresses of the power switching device are within the safe operating range, significantly improving the reliability of the protection.

[0044] Compared to existing solutions that rely solely on overcurrent protection, this embodiment offers significant technical advantages: Existing overcurrent protection requires the short-circuit current to form and rise to the overcurrent threshold before triggering, with response times typically ranging from 5 to 20 microseconds. However, short-circuit currents can reach hundreds of amperes within microseconds, resulting in a delayed response. IGBTs often suffer irreversible damage before the protection system responds. This embodiment, by detecting abnormal voltage between the emitter and Vnc, triggers protection as soon as the lower bridge arm enters a false turn-on state, before the short-circuit current has fully built up, improving response speed by more than an order of magnitude. Furthermore, existing overcurrent protection achieves protection by turning off the IGBT gate, which cannot reliably turn off the gate when the gate drive fails due to interference. This embodiment physically disconnects the main circuit through an independent path to cut off the switching device, unaffected by the gate state of the lower bridge arm power switching device, significantly improving protection reliability.

[0045] In a further preferred embodiment, the circuit-breaking switching device employs three independent IGBTs: a first-phase IGBT Q7, a second-phase IGBT Q8, and a third-phase IGBT Q9, connected in series in the current paths of the three-phase lower bridge arms. The collectors of these three IGBTs are connected to the emitters of Q4, Q5, and Q6, respectively. The emitters of all three IGBTs are connected to one end of the sampling resistor RS, and the gates of all three IGBTs are connected to the switching control output of the LVIC. The advantages of using three independent IGBTs instead of a single common switch are: each phase path is independent, and an abnormality in one phase will not affect the detection and protection of other phases; simultaneously, the three IGBTs share the short-circuit current, reducing the current stress on each IGBT, allowing for the use of devices with lower current ratings, thus reducing cost and package size. When the LVIC detects an abnormal voltage, it simultaneously outputs a turn-off signal to the three IGBTs, ensuring that the three-phase lower bridge paths are simultaneously cut off, avoiding protection failure caused by incomplete turn-off of one phase.

[0046] In a further preferred embodiment, the sampling resistor RS adopts a common sampling resistor scheme, that is, a single sampling resistor is connected in series between the common emitter and Vnc of the three-phase lower arm. One end of the common sampling resistor is connected to the emitters of Q7, Q8, and Q9, and the other end is connected to Vnc. Operational amplifier U1 detects the voltage across the common sampling resistor. The advantage of this scheme is its simple circuit structure, requiring only one sampling resistor and one operational amplifier channel, resulting in low cost and small package area. The common sampling resistor detects the voltage corresponding to the total current of the three-phase lower arm. If any phase experiences abnormal conduction, causing an abnormal total current, the voltage across the sampling resistor will rise, thereby triggering protection. For most application scenarios, the common sampling scheme can meet the protection requirements and has a high cost-performance ratio.

[0047] In a further preferred embodiment, a three-phase independent sampling scheme is adopted for the sampling resistors, namely, a first sampling resistor, a second sampling resistor, and a third sampling resistor are connected in series between NU and Vnc, between NV and Vnc, and between NW and Vnc, respectively. The operational amplifier can acquire the voltage across each phase sampling resistor through a multiplexer or three independent channels. The advantage of this scheme is that it can realize phase-by-phase detection and fault location. When an abnormal conduction occurs in a phase, the voltage of the corresponding phase's sampling resistor rises, and the LVIC can accurately identify the faulty phase and output the faulty phase information through the fault output pin, which facilitates system maintenance and fault diagnosis. In addition, phase-by-phase detection can avoid the detection blind zone caused by the mutual cancellation of three-phase currents, and is more sensitive to the identification of single-phase abnormal conduction. In practical applications, a common sampling or independent sampling scheme can be selected according to cost and detection accuracy requirements.

[0048] In a further preferred embodiment, the intelligent power module also includes a fault output pin FO. The fault output pin FO is located on the package housing and connected to the fault signal output terminal of the low-voltage side control chip LVIC. When the LVIC detects that the voltage across the sampling resistor RS exceeds a preset threshold and simultaneously shuts down Q7, Q8, and Q9, it outputs a fault signal to the outside through the FO pin. The fault signal can be active low or in open-drain output form. Upon detecting this signal, the external main control chip immediately shuts down the PWM wave output, stopping all drive signals for the upper and lower bridge arms, further ensuring the IPM is in a safe state. The FO pin enables the linkage between the IPM's internal protection and external system control, promptly reporting the fault status to the main control chip and preventing the system from continuing to operate under fault conditions, thus avoiding greater losses. The FO pin also has a fault latching function; once protection is triggered, the fault signal continues to be output until the system is powered off and reset or a clear command is received, preventing repeated fault triggering.

[0049] In a further preferred embodiment, the intelligent power module also includes a protection enable pin INT. The protection enable pin INT is located on the package housing and connected to the enable signal input of the low-voltage side control chip LVIC. The INT pin is used to receive control signals from the external main control chip to selectively shield the shutdown action in the voltage detection protection function. It should be noted that when the INT pin receives a valid level signal, the LVIC shields the shutdown control action of Q7, Q8, and Q9, i.e., keeps Q7, Q8, and Q9 continuously conducting; however, the voltage detection circuit and the FO fault reporting function still operate normally. When a voltage exceeding the threshold is detected, the FO pin can still output a fault signal, but it will not perform a physical shutdown action.

[0050] This design allows the system to monitor abnormal states while shielding protective actions, facilitating fault recording and early warning by the main control chip, thus balancing operational continuity and state observability. In practical applications, some scenarios involve fixed PCB layouts that cannot be changed, or external electromagnetic interference that cannot be completely avoided. However, extensive testing has verified that the risk of abnormal conduction in the bridge arm is low. In such cases, overly sensitive protection functions may lead to false triggering, affecting normal system operation. Through the INT pin, the main control chip can flexibly configure whether to perform a physical disconnection action according to the actual application scenario, balancing safety and availability.

[0051] In a further preferred embodiment, a pull-down resistor is connected between the protection enable pin INT and the low-voltage side control chip LVIC, with the other end of the pull-down resistor grounded. The pull-down resistor ensures that the INT pin is in a low-level state by default when it is floating or not connected to an external signal, at which point the protection function is normally enabled. When the external main control chip inputs a high-level signal to the INT pin, the LVIC recognizes the enable signal as valid, disables the shutdown control of Q7, Q8, and Q9, and keeps Q7, Q8, and Q9 continuously conducting. The IPM operates in normal mode, while the FO pin can still report abnormal voltage conditions. The design using a pull-down resistor instead of a pull-up resistor ensures that the protection function is available by default during the power-on initialization phase, avoiding protection failure due to uncertain pin states, and conforming to functional safety design principles. The effective level of the INT pin can be adjusted to be active low according to circuit design requirements; only the internal logic and bias resistor configuration of the LVIC need to be adjusted accordingly.

[0052] In a further preferred embodiment, the low-voltage side control chip LVIC is configured with explicit three-state control logic. The first state is the normal operating state: when the detected voltage output by operational amplifier U1 is less than a preset threshold, LVIC maintains Q7, Q8, and Q9 on, the FO pin outputs a fault-free level, and the IPM performs normal three-phase inversion. The second state is the protection trigger state: when the detected voltage is greater than or equal to the preset threshold and the INT pin is not shielded, LVIC immediately turns off Q7, Q8, and Q9, while the FO pin outputs a fault signal and latches this state until reset. The third state is the protection shielded state: when the protection enable pin INT receives a valid level signal, the low-voltage side control chip LVIC shields the physical disconnection protection action of this application, that is, it does not output a turn-off signal to the circuit disconnection switch, and maintains the first-phase disconnected IGBT, the second-phase disconnected IGBT, and the third-phase disconnected IGBT continuously on. It is important to clarify that the shielding here only applies to the physical cut-off protection of the LVIC active shutdown path cut-off switch. The voltage detection circuit and the fault reporting function of the fault output pin FO still function normally. The external main control chip can still obtain the fault status through the FO pin and execute conventional system-level protections such as shutting down PWM. However, for lower arm mis-current short circuits caused by electromagnetic interference, since the gate drive of the lower arm power switching device itself is already out of control due to interference, the external main control cannot reliably shut down the mis-current device by shutting down PWM. In this case, after the physical cut-off protection of this application is shielded, this type of fault cannot be effectively protected. Therefore, the shielding of the physical cut-off protection function should only be used in application scenarios where the risk of mis-current is extremely low after sufficient testing. The three-state logic is clear and explicit, ensuring that the behavior of the IPM is predictable and controllable under various operating conditions. The selection of the preset threshold is based on the maximum allowable voltage between the lower arm emitter and Vnc in the IPM datasheet. This voltage is related to parameters such as the gate threshold voltage of the IGBT, package parasitic inductance, and drive circuit impedance, and is usually in the range of several hundred millivolts to several volts. Setting the threshold too low can lead to false protection, while setting it too high will result in a delayed protection response. The threshold needs to be optimized and determined based on the specific device parameters and application scenarios.

[0053] According to a second aspect of the present invention, an electrical device is provided.

[0054] In one embodiment, the power equipment of the present invention includes a main control chip and the aforementioned intelligent power module. The power equipment may be a frequency converter, servo driver, air conditioner controller, industrial motor driver, or other device requiring power conversion by an IPM.

[0055] The main control chip can be a microcontroller (MCU), digital signal processor (DSP), or field-programmable gate array (FPGA), responsible for generating PWM drive signals, receiving fault signals, and executing system-level protection logic. The PWM output of the main control chip is connected to the drive signal input of the intelligent power module, providing six PWM control signals to the HVIC and LVIC to achieve three-phase inverter output. The fault signal input of the main control chip is connected to the fault output pin FO of the intelligent power module to monitor the fault status of the IPM in real time. The enable signal output of the main control chip is connected to the protection enable pin INT of the intelligent power module, which can be configured to enable or disable the physical disconnection action of the IPM according to the application scenario.

[0056] The power equipment also includes peripheral components such as DC bus capacitors, current sensors, temperature sensors, and heat dissipation devices. The DC bus capacitor is connected in parallel between P and Vnc to smooth the bus voltage and absorb switching ripple current. The heat dissipation device uses aluminum profile heat sinks or liquid-cooled plates, which are tightly fitted to the aluminum insulating base plate of the IPM to dissipate the heat generated by the IGBTs and other devices in a timely manner.

[0057] The workflow of the power equipment in this embodiment is as follows: After the system is powered on, the main control chip initializes the peripherals and PWM module, and by default does not output an enable signal to the INT pin. The IPM's anti-shoot-through physical cut-off function is enabled. The main control chip outputs a PWM signal to drive the IPM to run, and the motor M starts to run. During operation, the IPM monitors the voltage between the emitter of the lower bridge arm and Vnc in real time. If an abnormal voltage spike occurs, causing a risk of false conduction in the lower bridge arm, the LVIC inside the IPM typically shuts down Q7, Q8, and Q9 within 1 to 3 microseconds and outputs a fault signal through the FO pin. After the main control chip detects the fault signal on the FO pin, it immediately shuts down the six PWM outputs, causing the entire IPM to stop switching, and the system enters a fault protection state. After the fault is cleared and the system is powered on again, it resumes normal operation. If the application scenario is evaluated and confirmed to have an extremely low risk of abnormal conduction, the main control chip can output a high-level signal to the INT pin to shield the physical cut-off action inside the IPM. However, the FO pin will still report an abnormal voltage status for the main control chip to record faults and provide early warnings, avoiding false protection that could affect the continuous operation of the system.

[0058] This embodiment of the power equipment significantly improves system reliability and safety by integrating an IPM with anti-shoo-through protection for bridge connections. Compared to solutions using ordinary IPMs, this power equipment can effectively prevent bridge burnout failures under harsh conditions such as PCB layout defects and electromagnetic interference, reducing equipment maintenance costs and downtime losses. Furthermore, the protection enable pin configuration allows for flexible configuration of protection strategies based on actual application scenarios, adapting to the needs of different industrial environments.

[0059] According to a third aspect of the present invention, a control method is provided for an intelligent power module for preventing direct connection between upper and lower bridges.

[0060] In one embodiment, the control method of the present invention is executed by the low-voltage side control chip LVIC.

[0061] The method includes the following steps: S1. Real-time acquisition of the detection voltage output by the operational amplifier, wherein the detection voltage reflects the voltage between the emitter of the lower bridge arm power switching device and the negative terminal of the DC bus.

[0062] Specifically, the low-voltage side control chip LVIC acquires the detection voltage output by operational amplifier U1 in real time. This detection voltage reflects the voltage between the emitter of the lower bridge arm power switching device and the negative terminal Vnc of the DC bus. Specifically, a sampling resistor RS is connected in series between the NU / NV / NW common node and Vnc, converting the voltage difference between them into a voltage signal across the resistor. The non-inverting input of operational amplifier U1 is connected to the NU / NV / NW common node, and the inverting input is connected to Vnc. The voltage difference across the sampling resistor RS is amplified and output to the voltage detection input of the LVIC. The analog-to-digital converter or comparator inside the LVIC acquires this detection voltage in real time.

[0063] S2. Compare the detected voltage with a preset threshold.

[0064] Specifically, the LVIC compares the acquired detection voltage with a preset threshold. This preset threshold is the maximum permissible voltage between the emitter of the lower bridge arm and the negative terminal of the DC bus, as specified in the IPM datasheet, typically ranging from 0.5V to 2V. The threshold is determined based on factors including: the IGBT's gate mis-turn-on threshold voltage, the voltage drop caused by the parasitic inductance of the package pins during switching transients, the common-mode interference tolerance of the drive circuit, and safety margins. The preset threshold is stored in an internal register or non-volatile memory of the LVIC and can be configured according to the parameters of different IPM models.

[0065] S3. When the detected voltage is greater than or equal to the preset threshold, it is determined that there is a risk of abnormal conduction in the lower bridge arm, and a turn-off signal is output to the path cut-off switching device to physically cut off the current path of the lower bridge arm power switching device.

[0066] Specifically, when the detected voltage is less than a preset threshold, the LVIC determines that the lower bridge arm is working normally and maintains the conduction state of each phase's cut-off IGBTs Q7, Q8, and Q9 in the circuit cut-off switching devices, and the IPM performs the inverter function normally. When the detected voltage is greater than or equal to the preset threshold, the LVIC determines that there is a risk of abnormal conduction in the lower bridge arm and outputs a turn-off signal to the gates of Q7, Q8, and Q9 within 1 to 3 microseconds. After receiving the turn-off signal, Q7, Q8, and Q9 switch from the saturated conduction state to the cut-off state, thereby physically cutting off the current path of the three-phase lower bridge arm. Even if the lower bridge IGBTs Q4, Q5, and Q6 in each phase of the lower bridge arm power switching devices are in a misleading conduction state due to interference, the main current path is interrupted due to the turn-off of Q7, Q8, and Q9, and a continuous shoot-through short-circuit current cannot be formed, fundamentally avoiding the burnout of the upper and lower bridges due to shoot-through. The physical disconnection mentioned here refers to completely disconnecting the power circuit electrically by turning off the switching device connected in series in the power circuit. This is different from the soft turn-off method, which only turns off the gate drive signal. Physical disconnection is not affected by the gate state of the lower bridge arm power switching device.

[0067] The core of this method lies in selecting the voltage between the emitter and Vnc of the lower bridge arm as the protection trigger indicator. Traditional overcurrent protection selects current as the detection target, and can only trigger after the short-circuit current forms and rises to the threshold, resulting in an inherent hysteresis. However, an abnormal voltage between the emitter and Vnc is a direct precursor to false triggering of the lower bridge arm—when parasitic inductance or interference causes an abnormal rise in the emitter potential, this voltage change is detected before the formation of the short-circuit current. Therefore, this method achieves a technological leap from post-event current detection to pre-event voltage prediction, reducing the protection response time from 5 to 20 microseconds to 1 to 3 microseconds, significantly improving protection effectiveness.

[0068] In a further preferred embodiment, when the detected voltage is greater than or equal to a preset threshold, the method further includes a fault reporting step. The low-voltage side control chip LVIC, while turning off Q7, Q8, and Q9, outputs a fault signal to the external main control chip through the fault output pin FO. The fault signal adopts a low-level active or open-drain output form to ensure reliable identification by the main control chip even in environments with strong electromagnetic interference. After detecting the fault signal on the FO pin, the main control chip immediately performs the following actions: shuts down the six-channel PWM wave output, stopping all IGBT drive signals of the upper and lower bridge arms; latches the fault status and reports it to the host computer or display device; and initiates a cooling or shutdown process. The fault reporting step achieves coordination between the IPM's internal hardware protection and external system control, forming a two-level protection mechanism: the first level physically disconnects the circuit within 1 to 3 microseconds using the IPM's internal path-cutting switching device, and the second level shuts down the system output in milliseconds using the main control chip. The two work together to ensure that the fault does not escalate. The fault signal output from the FO pin has a latching characteristic. Once triggered, it remains valid until the system is powered off and reset, preventing repeated fault occurrences that could lead to cumulative damage to the device.

[0069] In a further preferred embodiment, the method further includes a protection enabling step.

[0070] Specifically, the low-voltage side control chip LVIC monitors the level of the protection enable pin INT in real time. When the protection enable pin INT receives a valid level signal, the low-voltage side control chip LVIC shields the physical cut-off protection action of this application, that is, it does not output a turn-off signal to the path cut-off switch, and keeps the first phase cut-off IGBT, the second phase cut-off IGBT, and the third phase cut-off IGBT continuously conducting. It should be clarified that the shielding here only applies to the physical cut-off protection of the LVIC actively turning off the path cut-off switch. The voltage detection circuit and the fault reporting function of the fault output pin FO still work normally, and the external main control chip can still obtain the fault status through the FO pin and perform conventional system-level protection such as shutting down PWM. However, for the lower bridge arm mis-conduction short circuit caused by electromagnetic interference, since the gate drive of the lower bridge arm power switching device itself is already out of control due to interference, the external main control cannot reliably turn off the mis-conducted device by shutting down PWM. In this case, after the physical cut-off protection of this invention is shielded, this type of fault cannot be effectively protected. Therefore, the shielding of the physical cut-off protection function should only be used in application scenarios where the risk of mis-conduction has been fully verified by actual testing to be extremely low. In other words, when a voltage exceeding the threshold is detected, the FO pin still outputs a fault signal, but does not perform a physical cutoff. The protection function is fully enabled when the INT pin does not receive a valid level signal. The valid level signal is a high-level signal output by the external main control chip. The INT pin is grounded by default through a pull-down resistor, ensuring that the protection function is available by default upon power-up. The protection enable step is set based on the following practical considerations: In some application scenarios, the PCB layout is fixed and cannot be redesigned, or the working environment has unavoidable strong electromagnetic interference, causing frequent voltage spikes between the emitter and Vnc. However, the energy and duration of these spikes are insufficient to truly trigger a false circuit in the lower bridge arm. If the physical cutoff function is continuously enabled in this case, it may frequently trigger false circuits, affecting the normal operation of the system. Through the INT pin, the main control chip can temporarily disable the physical cutoff action during system debugging or under specific operating conditions, while retaining the FO reporting function for status monitoring. After sufficient verification, a decision is made on whether to enable it long-term, improving the application flexibility of the solution. It should be emphasized that disabling the physical cutoff action should be configured by authorized personnel through the main control chip, and the system should record the disabling operation for traceability, avoiding safety hazards caused by false disabling.

[0071] In a further preferred embodiment, the voltage detection step includes a signal conditioning sub-step. After the sampling resistor RS converts the voltage between the lower bridge arm emitter and Vnc into a voltage signal, it is first amplified by operational amplifier U1. Operational amplifier U1 employs a differential input structure; the non-inverting input is connected to the high-potential end of the sampling resistor RS, i.e., the NU / NV / NW common node, and the inverting input is connected to the low-potential end of the sampling resistor RS, i.e., the Vnc terminal. The differential input structure effectively suppresses common-mode interference, amplifying only the differential-mode voltage between the two input terminals, i.e., the true voltage drop across the sampling resistor RS. The amplification factor of operational amplifier U1 is configured according to a preset threshold and the input level range of the LVIC, typically ranging from 10 to 100 times, amplifying the millivolt-level voltage change across the sampling resistor RS to a volt-level level that the LVIC can stably recognize. The amplified signal is then filtered by a low-pass filter inside the LVIC to remove high-frequency noise before being sent to a comparator for comparison with a preset threshold. The signal conditioning sub-step ensures the accuracy and anti-interference capability of the voltage detection, avoiding misjudgments caused by noise or common-mode interference. The bandwidth of operational amplifier U1 should cover the main frequency components of abnormal voltage spikes, typically not less than 1MHz, to ensure the ability to track fast transient spikes.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A smart power module for preventing up-and-down bridge shoot-through, comprising a housing, an upper bridge power switching device, a lower bridge power switching device, and a low-voltage side control chip; characterized in that, It also includes sampling resistors, operational amplifiers, and path-cutting switches; The sampling resistor is connected in series between the emitter of the lower bridge arm power switch and the negative terminal pin of the DC bus; The non-inverting and inverting input terminals of the operational amplifier are respectively connected to the two ends of the sampling resistor, and the output terminal of the operational amplifier is connected to the voltage detection input terminal of the low-voltage side control chip. The path cut-off switch is connected in series in the current path between the emitter of the lower bridge arm power switch and the negative terminal pin of the DC bus. The control terminal of the path cut-off switch is connected to the switch control output terminal of the low-voltage side control chip. The path cut-off switch is in the on state by default.

2. The intelligent power module according to claim 1, characterized in that, The lower bridge arm power switching device includes a first phase lower bridge IGBT, a second phase lower bridge IGBT, and a third phase lower bridge IGBT; the circuit disconnecting switching device includes a first phase disconnecting IGBT, a second phase disconnecting IGBT, and a third phase disconnecting IGBT; the first phase disconnecting IGBT is connected in series between the emitter of the first phase lower bridge IGBT and the negative terminal pin of the DC bus, the second phase disconnecting IGBT is connected in series between the emitter of the second phase lower bridge IGBT and the negative terminal pin of the DC bus, and the third phase disconnecting IGBT is connected in series between the emitter of the third phase lower bridge IGBT and the negative terminal pin of the DC bus.

3. The intelligent power module according to claim 2, characterized in that, The collectors of the first phase cutoff IGBT, the second phase cutoff IGBT, and the third phase cutoff IGBT are respectively connected to the emitters of the first lower bridge phase IGBT, the second lower bridge IGBT, and the third lower bridge IGBT. The emitters of the first phase cutoff IGBT, the second phase cutoff IGBT, and the third phase cutoff IGBT are all connected to the negative terminal pin of the DC bus. The gates of the first phase cutoff IGBT, the second phase cutoff IGBT, and the third phase cutoff IGBT are all connected to the switch control output terminal of the low-voltage side control chip.

4. The intelligent power module according to claim 1, characterized in that, The sampling resistor is a common sampling resistor. One end of the common sampling resistor is connected to the emitter of each phase IGBT in the lower bridge arm power switching device, and the other end of the common sampling resistor is connected to the negative terminal pin of the DC bus.

5. The intelligent power module according to claim 1, characterized in that, The sampling resistor includes a first sampling resistor, a second sampling resistor, and a third sampling resistor; the first sampling resistor is connected in series between the emitter of the first phase lower bridge IGBT and the negative terminal pin of the DC bus, the second sampling resistor is connected in series between the emitter of the second phase lower bridge IGBT and the negative terminal pin of the DC bus, and the third sampling resistor is connected in series between the emitter of the third phase lower bridge IGBT and the negative terminal pin of the DC bus.

6. The intelligent power module according to claim 1, characterized in that, It also includes a fault output pin, which is disposed on the package housing and connected to the fault signal output terminal of the low-voltage side control chip.

7. The intelligent power module according to claim 1, characterized in that, It also includes a protection enable pin, which is disposed on the package housing and connected to the enable signal input terminal of the low-voltage side control chip.

8. The intelligent power module according to claim 7, characterized in that, A pull-down resistor is connected between the protection enable pin and the low-voltage side control chip, and the other end of the pull-down resistor is grounded.

9. The intelligent power module according to any one of claims 1 to 8, characterized in that, The low-voltage side control chip is configured to: maintain the circuit cut-off switch on when the detection voltage output by the operational amplifier is less than a preset threshold; and control the circuit cut-off switch to turn off and output a fault signal through the fault output pin when the detection voltage is greater than or equal to the preset threshold.

10. An electrical device, characterized in that, It includes a main control chip and the intelligent power module as described in any one of claims 1 to 9; the fault signal input terminal of the main control chip is connected to the fault output pin of the intelligent power module, and the PWM output terminal of the main control chip is connected to the drive signal input terminal of the intelligent power module.

11. A method for preventing bridge overpass / underpass shoot-through control of the intelligent power module according to any one of claims 1 to 8, executed at the low-voltage side control chip, characterized in that, Includes the following steps: The detection voltage output by the operational amplifier is acquired in real time, and the detection voltage reflects the voltage between the emitter of the lower bridge arm power switching device and the negative terminal of the DC bus. The detected voltage is compared with a preset threshold. When the detected voltage is greater than or equal to the preset threshold, it is determined that there is a risk of abnormal conduction in the lower bridge arm, and a turn-off signal is output to the circuit cut-off switching device to physically cut off the current path of the lower bridge arm power switching device.

12. The control method according to claim 11, characterized in that, Also includes: When the detected voltage is greater than or equal to the preset threshold, a fault signal is output to the main control chip through the fault output pin, causing the main control chip to shut down the PWM wave output.

13. The control method according to claim 11, characterized in that, Also includes: Detect the level state of the protection enable pin; When the protection enable pin receives a valid level signal, the steps of shielding voltage comparison and shutting off the path disconnection switching device are performed to maintain the path disconnection switching device on.

14. The control method according to claim 13, characterized in that, The effective level signal is a high level signal.

15. The control method according to claim 11, characterized in that, The detection voltage output by the operational amplifier is obtained in the following way: The voltage between the emitter of the lower bridge arm power switching device and the negative terminal of the DC bus is converted into a voltage signal by the sampling resistor, and then amplified by the operational amplifier to output the detection voltage.

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