An inverter device, motor system and control method thereof, vehicle, and robot

Abstract

The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field of power electronic devices. The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field of power electronic devices. The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field of power electronic devices. The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field of power electronic devices. The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field of power electronic devices. The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field of power electronic devices. The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field of power electronic devices. The application discloses an inverter device, a motor system and a control method thereof, a vehicle and a robot, and relates to the technical field

Description

Technical Field

[0001] This invention belongs to the field of dual-motor drive technology, specifically relating to an inverter device, a motor system and its control method, vehicles, and robots, and particularly to a drive circuit for a nine-switch inverter, a motor system and its control method, vehicles, and robots. The inverter device involves the manufacture of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor chips, and modules. Background Technology

[0002] In current motor control technology, dual-motor drive systems are widely used in industrial automation, electric vehicles, robotics, and other fields. In related solutions, each motor typically employs a three-phase, six-arm drive structure, with each arm consisting of two switching transistors. Therefore, a single motor requires six switching transistors, and a dual-motor drive system requires a total of twelve. While this twelve-switch inverter structure enables independent control of the two motors, it suffers from drawbacks such as a large number of switching transistors, complex drive circuitry for twelve transistors, and high system cost (i.e., the system containing the two motors). This inverter device involves the manufacturing of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor (IGBT) chips, and modules.

[0003] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The purpose of this invention is to provide an inverter device, a motor system and its control method, a vehicle, and a robot to solve the problems of large number of switches, complex structure, and high cost associated with inverters using a twelve-switch structure in dual-motor drive systems. The invention achieves this by using an inverter with nine switches and incorporating a central transistor drive circuit composed of logic chips, thereby reducing the number of switches, simplifying the structure, saving costs, and enabling stable operation of dual motors. This inverter device involves the manufacture of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor (IGBT) chips, and modules.

[0005] This invention provides an inverter device for supplying power to a dual-motor system consisting of a first motor and a second motor. The inverter device includes an inverter unit and a drive unit. The inverter unit includes a three-phase bridge arm, with an upper, middle, and lower transistor disposed on each phase arm. The drive unit includes a first drive module, a second drive module, a third drive module, and a main control module. The main control module is used to issue twelve drive control signals when the dual motors need to be driven. The first drive module is used to generate a first set of drive control signals from the twelve drive control signals. The first drive module outputs a first set of drive signals to drive the three upper tubes of the three-phase bridge arm; the second drive module outputs a second set of drive signals based on the second set of drive control signals in the twelve drive control signals to drive the three lower tubes of the three-phase bridge arm; the third drive module outputs a third set of drive signals based on the third set of drive control signals in the twelve drive control signals to drive the three middle tubes of the three-phase bridge arm; the third set of drive control signals includes: a complementary signal of the first set of drive control signals and a complementary signal of the second set of drive control signals.

[0006] In some embodiments, the three-phase bridge arm includes: a first phase bridge arm, a second phase bridge arm, and a third phase bridge arm; the three upper tubes of the three-phase bridge arm include: a first switch tube located in the first phase bridge arm, a second switch tube located in the second phase bridge arm, and a third switch tube located in the third phase bridge arm; the three middle tubes of the three-phase bridge arm include: a fourth switch tube located in the first phase bridge arm, a fifth switch tube located in the second phase bridge arm, and a sixth switch tube located in the third phase bridge arm; the three lower tubes of the three-phase bridge arm include: a seventh switch tube located in the first phase bridge arm... The system includes a switch, an eighth switch located in the second phase bridge arm, and a ninth switch located in the third phase bridge arm; wherein the common terminals of the first and fourth switches, the second and fifth switches, and the third and sixth switches are all connected to the power supply terminal of the first motor; the common terminals of the fourth and seventh switches, the fifth and eighth switches, and the sixth and ninth switches are all connected to the power supply terminal of the second motor.

[0007] In some embodiments, the first driving module includes: an enable module and a first driving chip; the first set of driving control signals includes: a first driving control signal, a third driving control signal, and a fifth driving control signal; the first set of driving signals includes: a driving signal for the upper tube of the first phase bridge arm, a driving signal for the upper tube of the second phase bridge arm, and a driving signal for the upper tube of the third phase bridge arm; wherein, the first driving module outputs the first set of driving signals based on the first set of driving control signals among the twelve driving control signals, including: the enable module being used to output an enable signal to the first driving chip based on an enable control signal issued by the main control module; the first driving chip being used, under the control of the enable signal, to output the driving signals for the upper tube of the first phase bridge arm, the upper tube of the second phase bridge arm, and the upper tube of the third phase bridge arm based on the first driving control signal, the third driving control signal, and the fifth driving control signal issued by the main control module.

[0008] In some embodiments, the second driving module includes: a second driving chip; a second set of driving control signals including: a second driving control signal, a fourth driving control signal, and a sixth driving control signal; the second set of driving signals including: a driving signal for the lower tube of the first phase bridge arm, a driving signal for the lower tube of the second phase bridge arm, and a driving signal for the lower tube of the third phase bridge arm; wherein, the second driving module outputs a second set of driving signals based on the second set of driving control signals among the twelve driving control signals, including: the second driving chip, used to output the driving signals for the lower tube of the first phase bridge arm, the lower tube of the second phase bridge arm, and the lower tube of the third phase bridge arm based on the second driving control signal, the fourth driving control signal, and the sixth driving control signal issued by the main control module, under the control of the enable control signal issued by the main control module.

[0009] In some embodiments, the third driving module includes: a first logic processing module, a second logic processing module, and a third logic processing module; the third set of driving control signals includes: complementary signals of the first driving control signal, the second driving control signal, the third driving control signal, the fourth driving control signal, the fifth driving control signal, and the sixth driving control signal; the third set of driving signals includes: driving signals of the middle tubes of the first phase bridge arm, the second phase bridge arm, and the third phase bridge arm; wherein, the third driving module is based on the twelve driving signals. The third set of drive control signals in the control signals outputs a third set of drive signals, including: a first logic processing module, used to output a drive signal for the middle tube of the first phase bridge arm based on the complementary signals of the first drive control signal and the second drive control signal; a second logic processing module, used to output a drive signal for the middle tube of the second phase bridge arm based on the complementary signals of the third drive control signal and the fourth drive control signal; and a third logic processing module, used to output a drive signal for the middle tube of the third phase bridge arm based on the complementary signals of the fifth drive control signal and the sixth drive control signal.

[0010] In some embodiments, the first logic processing module includes: a first NOT gate, a second NOT gate, and a first NAND gate; the first logic processing module outputs a drive signal for the middle tube of the first phase bridge arm based on the complementary signal of the first drive control signal and the complementary signal of the second drive control signal, including: the first NOT gate, used to output a first inverted signal based on the complementary signal of the first drive control signal; the second NOT gate, used to output a second inverted signal based on the complementary signal of the second drive control signal; and the first NAND gate, used to output the drive signal for the middle tube of the first phase bridge arm based on the first inverted signal and the second inverted signal.

[0011] And / or, the second logic processing module includes: a third NOT gate, a fourth NOT gate, and a second NAND gate; the second logic processing module outputs a drive signal for the middle tube of the second phase bridge arm based on the complementary signal of the third drive control signal and the complementary signal of the fourth drive control signal, including: the third NOT gate, used to output a third inverted signal based on the complementary signal of the third drive control signal; the fourth NOT gate, used to output a fourth inverted signal based on the complementary signal of the fourth drive control signal; and the second NAND gate, used to output a drive signal for the middle tube of the second phase bridge arm based on the third inverted signal and the fourth inverted signal.

[0012] And / or, the third logic processing module includes: a fifth NOT gate, a sixth NOT gate, and a third NAND gate; the third logic processing module outputs the drive signal of the middle tube of the third phase bridge arm based on the complementary signal of the fifth drive control signal and the complementary signal of the sixth drive control signal, including: the fifth NOT gate, used to output a fifth inverted signal based on the complementary signal of the fifth drive control signal; the sixth NOT gate, used to output a sixth inverted signal based on the complementary signal of the sixth drive control signal; the third NAND gate, used to output the drive signal of the middle tube of the third phase bridge arm based on the fifth inverted signal and the sixth inverted signal.

[0013] In conjunction with the above-described device, the present invention further provides a motor system, vehicle, or robot, including the inverter device described above.

[0014] In conjunction with the above-described device, the present invention further provides a vehicle comprising: the inverter device described above, or the motor system described above.

[0015] In conjunction with the above-described device, the present invention further provides a robot, comprising: the inverter device described above, or the motor system described above.

[0016] In conjunction with the aforementioned motor system, the present invention further provides a control method for the motor system, comprising: issuing twelve drive control signals when it is necessary to drive the dual motors; outputting a first set of drive signals based on a first set of drive control signals from the twelve drive control signals via a first drive module to drive the three upper tubes of the three-phase bridge arm; outputting a second set of drive signals based on a second set of drive control signals from the twelve drive control signals via a second drive module to drive the three lower tubes of the three-phase bridge arm; and outputting a third set of drive signals based on a third set of drive control signals from the twelve drive control signals via a third drive module to drive the three middle tubes of the three-phase bridge arm; wherein the third set of drive control signals includes: a complementary signal of the first set of drive control signals and a complementary signal of the second set of drive control signals.

[0017] The present invention addresses a drive system for dual motors (such as a first motor and a second motor). The inverter device comprises: an inverter unit and a drive unit. The inverter unit is, for example, a nine-switch inverter, and the drive unit is, for example, a drive circuit for a nine-switch inverter. The inverter unit includes: a three-phase bridge arm, with an upper transistor, a middle transistor, and a lower transistor disposed on each phase arm. The drive unit includes: a first drive module, a second drive module, a third drive module, and a main control module. The main control module is used to issue twelve drive control signals when the dual motors need to be driven. The first drive module is used to... The first set of drive control signals from the twelve drive control signals outputs a first set of drive signals to drive the three upper transistors of the three-phase bridge arm; the second drive module outputs a second set of drive signals based on the second set of drive control signals from the twelve drive control signals to drive the three lower transistors of the three-phase bridge arm; the third drive module outputs a third set of drive signals based on the third set of drive control signals from the twelve drive control signals to drive the three middle transistors of the three-phase bridge arm; the third set of drive control signals includes: a complementary signal of the first set of drive control signals and a complementary signal of the second set of drive control signals. Thus, by setting up an inverter with nine switches and a middle transistor drive circuit composed of logic chips, the number of switches is reduced, the structure is simplified, and costs are saved, while achieving stable operation of dual motors. This inverter device involves the manufacture of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor (IGBT) chips, and modules.

[0018] Specifically, in the solution of this invention, for a drive system of dual motors (such as a first motor and a second motor), a drive circuit with nine switching transistors (i.e., an inverter composed of nine switching transistors) is provided, and drive circuits for the upper, middle, and lower transistors among the nine switching transistors are provided. The drive circuit for the upper transistor includes a drive chip U1, the drive circuit for the lower transistor includes a drive chip U2, and the drive circuit for the middle transistor includes a middle transistor drive circuit for each phase arm (with a boost function). The middle transistor drive circuit for each phase arm includes two NOT gates and one NAND gate (the NAND gate has a boost function). Among the nine switching transistors, each of the first, second, and third phase arms has three switching transistors (i.e., an upper transistor, a middle transistor, and a lower transistor arranged from top to bottom). For example, in the first phase bridge arm, the upper tube is switch Q1, the middle tube is switch Q4, and the lower tube is switch Q7; in the second phase bridge arm, the upper tube is switch Q2, the middle tube is switch Q5, and the lower tube is switch Q8; in the third phase bridge arm, the upper tube is switch Q3, the middle tube is switch Q6, and the lower tube is switch Q9. Three-phase electricity is drawn from the common terminal of switch Q1 and switch Q4, the common terminal of switch Q2 and switch Q5, and the common terminal of switch Q3 and switch Q6 to power the first motor (e.g., motor M1); and three-phase electricity is drawn from the common terminal of switch Q4 and switch Q7, the common terminal of switch Q5 and switch Q8, and the common terminal of switch Q6 and switch Q9 to power the second motor (e.g., motor M2).When the first and second motors need to be driven, the main control chip (such as a DSP chip) of the dual-motor drive system outputs twelve PWM waves (i.e., EPWM_1A, EPWM_3A, and EPWM_5A; EPWM_2A, EPWM_4A, and EPWM_6A; EPWM_1B, EPWM_3B, and EPWM_5B; EPWM_2B, EPWM_4B, and EPWM_6B). Among them, three PWM waves, EPWM_1A, EPWM_3A, and EPWM_5A, are driven by driver chip U1 (a chip with isolation and boost functions) and output three PWM waves U_H, V_H, and W_H to drive the three upper transistors (i.e., switching transistors Q1, Q2, and Q3) in the three-phase bridge arm. The other three PWM waves, EPWM_2A, EPWM_4A, and EPWM_6A, are driven by driver chip U2 (a chip with isolation and boost functions) and output three PWM waves U_L, V_L, and W_H. W_L drives the three lower transistors (Q7, Q8, and Q9) in the three-phase bridge arm. One PWM wave (EPWM_1B) is input to NAND gate U3 after passing through NOT gate U6. Another PWM wave (EPWM_2B) is also input to NAND gate U3 after passing through NOT gate U7. NOT gate U3 outputs a PWM wave (U_M) that drives one middle transistor (Q4) in the three-phase bridge arm. One PWM wave (EPWM_3B) is input to NAND gate U4 after passing through NOT gate U8. EPWM_4B, after passing through NOT gate U9, is also input to NAND gate U4. NOT gate U4 outputs a PWM wave, V_M, which drives one of the intermediate transistors (switch Q5) in the three-phase bridge arm. Another PWM wave, EPWM_5B, is input to NAND gate U5 after passing through NOT gate U10. EPWM_6B, after passing through NOT gate U11, is also input to NAND gate U5. NOT gate U5 outputs a PWM wave, W_M, which drives one of the intermediate transistors (switch Q6) in the three-phase bridge arm, thus driving the dual motors. Therefore, by setting up an inverter with nine switches and using a transistor drive circuit composed of logic chips (such as NOT gates and NAND gates), the number of switches is reduced, the structure is simplified, and costs are saved, while achieving stable operation of the dual motors. This inverter device involves the manufacturing of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor chips, and modules.

[0019] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention.

[0020] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of an embodiment of the inverter device of the present invention;

[0022] Figure 2 This is a schematic diagram of the enable circuit of the switch driver chip;

[0023] Figure 3 The diagrams show the structure of the upper and lower transistor drive circuits (including the drive circuit of the drive chip). The upper diagram shows the structure of the upper transistor drive circuit, and the lower diagram shows the structure of the lower transistor drive circuit.

[0024] Figure 4 The diagrams show the structure of the driving circuit for the intermediate transistors. The top diagram shows the driving circuit for the U-phase intermediate transistor, the middle diagram shows the driving circuit for the V-phase intermediate transistor, and the bottom diagram shows the driving circuit for the W-phase intermediate transistor.

[0025] Figure 5 This is a schematic diagram of the drive output signals of the main control chip, such as a DSP chip, in a motor controller or frequency converter.

[0026] Figure 6 A schematic diagram showing the conversion from a twelve-arm inverter controlling two motors to a nine-arm inverter controlling two motors.

[0027] Figure 7 This is a schematic diagram of a nine-bridge inverter controlling two motors.

[0028] Figure 8 A flowchart illustrating a method for controlling the operation of two motors using a drive circuit with a nine-switch inverter.

[0029] Figure 9 This is a flowchart illustrating an embodiment of the control method for the motor system of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0031] Considering that the dual-motor drive system uses an inverter with a twelve-switch structure, it suffers from a large number of switches, complex structure, and high cost. With the increasing demands for cost control of power devices and system integration, how to reduce the number of switches and simplify the drive circuit structure while ensuring independent motor control performance has become a key technical challenge in current motor control technology.

[0032] While some solutions attempt to reduce the number of switching transistors—for example, by replacing the dual-motor drive topology (where each motor has three phases and six arms, totaling twelve transistors, can be simplified to nine-arm, five-arm, or three-arm drive architectures)—this approach often sacrifices the independent control capability of the two motors or increases control complexity, failing to achieve a balance between performance and cost.

[0033] Therefore, the present invention proposes an inverter device, specifically a drive circuit for a nine-switch inverter. By setting up a nine-switch inverter, and processing twelve preset PWM waves through hardware, nine PWM waves are output to control the operation of the dual motors, thereby reducing the number of switches, simplifying the complexity of the structure, and saving costs.

[0034] According to an embodiment of the present invention, an inverter device is provided. See also Figure 1 The diagram shows a structural schematic of an embodiment of the device of the present invention. This inverter device is used to supply power to a dual-motor system consisting of a first motor and a second motor, such as motor M1 and motor M2; in the embodiment of the present invention, as... Figure 1 As shown, the inverter device includes: an inverter unit and a drive unit, wherein the inverter unit is an inverter with nine switching transistors, and the drive unit is a drive circuit of the inverter with nine switching transistors.

[0035] The inverter unit includes: a three-phase bridge arm, with an upper tube, a middle tube, and a lower tube disposed on each phase of the three-phase bridge arm; each phase of the bridge arm is provided with an upper tube, a middle tube, and a lower tube, and the three upper tubes, three middle tubes, and three lower tubes forming the three-phase bridge arm; wherein, the common terminal between the corresponding bridge arm switching tubes of the three upper tubes and three middle tubes of the three-phase bridge arm is connected to the power supply terminal of the first motor for supplying power to the first motor, and the common terminal between the corresponding bridge arm switching tubes of the three middle tubes and three lower tubes of the three-phase bridge arm is connected to the second motor... The power supply terminal of the machine is used to supply power to the second motor; the three-phase bridge arm is as follows: the first phase bridge arm is the U-phase bridge arm, the second phase bridge arm is the V-phase bridge arm, and the third phase bridge arm is the W-phase bridge arm; the upper tube of the U-phase bridge arm is the switch Q1, the middle tube of the U-phase bridge arm is the switch Q4, and the lower tube of the U-phase bridge arm is the switch Q7; the upper tube of the V-phase bridge arm is the switch Q2, the middle tube of the V-phase bridge arm is the switch Q5, and the lower tube of the V-phase bridge arm is the switch Q6; the upper tube of the W-phase bridge arm is the switch Q3, the middle tube of the W-phase bridge arm is the switch Q6, and the lower tube of the W-phase bridge arm is the switch Q9.

[0036] The driving unit includes: a first driving module, a second driving module, a third driving module, and a main control module; the first driving module is such as driving chip U1, the second driving module is such as driving chip U2, and the third driving module is such as... Figure 4 The shown is a tube drive circuit, and the main control module is such as a DSP chip.

[0037] The main control module is used to issue twelve drive control signals when it is necessary to drive the dual motors. The twelve drive control signals include: a first drive control signal such as EPWM_1A, a second drive control signal such as EPWM_2A, a third drive control signal such as EPWM_3A, a fourth drive control signal such as EPWM_4A, a fifth drive control signal such as EPWM_5A, a sixth drive control signal such as EPWM_6A, and a complementary signal to the first drive control signal such as the complementary signal to EPWM_1A. The complementary signals of the second drive control signal, such as EPWM_1B, EPWM_2A, EPWM_2B, EPWM_3A, EPWM_3B, EPWM_4A, EPWM_4B, EPWM_5A, EPWM_5B, and EPWM_6A, EPWM_6B are all complementary signals of the sixth drive control signal.

[0038] The first driving module is used to output a first set of driving signals based on the first set of driving control signals in the twelve driving control signals, so as to drive the three upper transistors of the three-phase bridge arm; the first set of driving control signals includes: a first driving control signal such as EPWM_1A, a third driving control signal such as EPWM_3A, and a fifth driving control signal such as EPWM_5A; the first set of driving signals includes: the driving signal U_H for the upper transistor of the U-phase bridge arm, i.e., the switching transistor Q1, the driving signal V_H for the upper transistor of the V-phase bridge arm, i.e., the switching transistor Q2, and the driving signal W_H for the upper transistor of the W-phase bridge arm, i.e., the switching transistor Q3.

[0039] The second drive module is used to output a second set of drive signals based on the second set of drive control signals in the twelve drive control signals, so as to drive the three lower transistors of the three-phase bridge arm; the first set of drive control signals includes: a second drive control signal such as EPWM_2A, a fourth drive control signal such as EPWM_4A and a sixth drive control signal such as EPWM_6A; the second set of drive signals includes: the drive signal U_L for the lower transistor of the U-phase bridge arm, i.e., the switch Q7, the drive signal V_L for the lower transistor of the V-phase bridge arm, i.e., the switch Q8, and the drive signal W_L for the lower transistor of the W-phase bridge arm, i.e., the switch Q9.

[0040] The third drive module is used to output a third set of drive signals based on the third set of drive control signals in the twelve drive control signals, so as to drive the three intermediate tubes of the three-phase bridge arm; the third set of drive control signals includes: a complementary signal of the first set of drive control signals and a complementary signal of the second set of drive control signals. The third set of drive control signals includes: complementary signals of the first drive control signal, such as EPWM_1A and EPWM_1B; complementary signals of the second drive control signal, such as EPWM_2A and EPWM_2B; complementary signals of the third drive control signal, such as EPWM_3A and EPWM_3B; complementary signals of the fourth drive control signal, such as EPWM_4A and EPWM_4B; complementary signals of the fifth drive control signal, such as EPWM_5A and EPWM_5B; and complementary signals of the sixth drive control signal, such as EPWM_6A and EPWM_6B. The third set of drive signals includes: drive signal U_M for the middle tube of the U-phase bridge arm, i.e., switch Q4; drive signal V_M for the middle tube of the V-phase bridge arm, i.e., switch Q5; and drive signal W_M for the middle tube of the W-phase bridge arm, i.e., switch Q6.

[0041] Figure 6 This is a schematic diagram illustrating the conversion from a twelve-arm inverter controlling two motors to a nine-arm inverter controlling two motors. Figure 6 As shown, the twelve-arm inverter controlling two motors is converted to a nine-arm inverter controlling two motors. In the twelve-arm inverter, the lower transistors of the upper six-arm inverters (i.e., three-phase arms A, B, C) and the upper transistors of the lower six-arm inverters (i.e., three-phase arms U, V, W) can be reused to form the middle transistors (i.e., the transistors in three-phase arms AU, BV, CW). The twelve-arm inverter is converted to a nine-arm inverter. The nine-arm inverter (i.e., a nine-switch inverter) includes: the upper transistors of three-phase arms A, B, C; the middle transistors of three-phase arms AU, BV, CW; and the lower transistors of three-phase arms U, V, W. Three-phase lines A, B, C are led out between the upper and middle transistors, and three-phase lines U, V, W are led out between the middle and lower transistors.

[0042] Figure 7 This is a schematic diagram of a nine-bridge inverter controlling two motors, as shown below. Figure 7 As shown, the AC power supply is rectified by the rectifier to obtain the bus voltage U. dc Bus voltage U dcThe output side is sequentially equipped with a bus capacitor, a nine-switch inverter, and two motors (M1 and M2). The nine switches in the nine-switch inverter are: Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, and Q9. Switches Q1, Q4, and Q7 are arranged from top to bottom in the first phase arm, as the upper, middle, and lower switches of the first phase arm, respectively. Switches Q2, Q5, and Q8 are arranged from top to bottom in the second phase arm, as the upper, middle, and lower switches of the second phase arm, respectively. Switches Q3, Q6, and Q9 are arranged from top to bottom in the third phase arm, as the upper, middle, and lower switches of the third phase arm, respectively. In a three-phase bridge arm consisting of a first phase bridge arm, a second phase bridge arm, and a third phase bridge arm, the upper tubes of the three-phase bridge arm are switch tubes Q1, Q2, and Q3; the middle tubes are switch tubes Q4, Q5, and Q6; and the lower tubes are switch tubes Q7, Q8, and Q9. Three-phase power is drawn from the upper and middle tubes of the three-phase bridge arm to motor M1, and three-phase power is drawn from the middle and lower tubes of the three-phase bridge arm to motor M2.

[0043] The present invention proposes a drive circuit for a nine-switch inverter. The nine-switch inverter is configured with a hardware-processed set of twelve preset PWM waves to output nine PWM waves to control the operation of two motors. The drive circuit of the nine-switch inverter drives nine switches to achieve independent control of the two motors, which reduces the number of switches, simplifies the complexity of the structure, and saves costs.

[0044] In some embodiments, in the inverter unit, the three-phase bridge arm includes: a first phase bridge arm, a second phase bridge arm, and a third phase bridge arm. The three upper transistors of the three-phase bridge arm include: a first switching transistor located in the first phase bridge arm, a second switching transistor located in the second phase bridge arm, and a third switching transistor located in the third phase bridge arm. The three middle transistors of the three-phase bridge arm include: a fourth switching transistor located in the first phase bridge arm, a fifth switching transistor located in the second phase bridge arm, and a sixth switching transistor located in the third phase bridge arm. The three lower transistors of the three-phase bridge arm include: a seventh switch transistor located in the first phase bridge arm, an eighth switch transistor located in the second phase bridge arm, and a ninth switch transistor located in the third phase bridge arm; wherein, the first phase bridge arm is the U-phase bridge arm, the second phase bridge arm is the V-phase bridge arm, and the third phase bridge arm is the W-phase bridge arm; the first switch transistor is switch transistor Q1, the second switch transistor is switch transistor Q2, the third switch transistor is switch transistor Q3, the fourth switch transistor is switch transistor Q4, the fifth switch transistor is switch transistor Q5, the sixth switch transistor is switch transistor Q6, the seventh switch transistor is switch transistor Q7, the eighth switch transistor is switch transistor Q8, and the ninth switch transistor is switch transistor Q9.

[0045] The common terminals of the first and fourth switching transistors, the second and fifth switching transistors, and the third and sixth switching transistors are all connected to the power supply terminal of the first motor; the common terminals of the fourth and seventh switching transistors, the fifth and eighth switching transistors, and the sixth and ninth switching transistors are all connected to the power supply terminal of the second motor.

[0046] In the solution of this invention, a nine-switch inverter is set up. Through hardware processing of twelve preset PWM waves, nine PWM waves are output to control the operation of the dual motors, thereby optimizing the circuit of the dual motor drive (i.e., the inverter) and reducing the number of switching transistors; thus realizing the independent operation of the dual motors driven by nine switching transistors.

[0047] In some embodiments, the first driving module includes: an enabling module and a first driving chip, wherein the enabling module is as follows: Figure 2 The enable circuit shown includes a first driver chip such as chip U1; the first set of drive control signals includes: a first drive control signal, a third drive control signal, and a fifth drive control signal; the first set of drive signals includes: the drive signal for the upper transistor of the first phase bridge arm, the drive signal for the upper transistor of the second phase bridge arm, and the drive signal for the upper transistor of the third phase bridge arm. For example, both chip U1 and chip U2 can be level conversion chips, i.e., chips used to convert 3.3V signals to 5V signals.

[0048] The first driving module outputs a first set of driving signals based on the first set of driving control signals among the twelve driving control signals, including:

[0049] The enabling module is used to output an enabling signal to the first driver chip based on the enabling control signal issued by the main control module; the enabling control signal is such as the switch signal EPWM_OE, and the enabling signal is such as the signal OE.

[0050] The first driver chip is configured, under the control of the enable signal, to output drive signals for the upper transistors of the first phase bridge arm, the second phase bridge arm, and the third phase bridge arm, based on the first drive control signal, the third drive control signal, and the fifth drive control signal issued by the main control module. Specifically, the first drive control signal is such as EPWM_1A, the third drive control signal is such as EPWM_3A, and the fifth drive control signal is such as EPWM_5A; the drive signals for the upper transistors of the first phase bridge arm are such as the drive signal U_H for the upper transistor of phase U (i.e., switch Q1), the drive signals for the upper transistors of the second phase bridge arm are such as the drive signal V_H for the upper transistor of phase V (i.e., switch Q2), and the drive signals for the upper transistors of the third phase bridge arm are such as the drive signal W_H for the upper transistor of phase W (i.e., switch Q3).

[0051] Figure 2 This is a schematic diagram of the enable circuit for a switching transistor driver chip. (Example:) Figure 2 As shown, the enable circuit for the switching transistor driver chip includes: resistors R1 and R2, and transistor Q1. The enable control signal EPWM_OE output from the main control chip (such as a DSP chip) in the motor controller or frequency converter is input to the first connection terminal of resistor R1. The second connection terminal of resistor R1 is connected to the base of transistor Q1. The 3.3V power supply is connected to the collector of transistor Q1 via resistor R2. The collector of transistor Q1 outputs the enable signal OE to the enable terminal (i.e., the OE pin of chip U1) of the driver chip for the upper transistor in the three-phase bridge arm. The emitter of transistor Q1 is grounded.

[0052] Figure 3 These are schematic diagrams of the upper and lower transistor drive circuits (including the drive circuit of the driver chip). The upper diagram shows the structure of the upper transistor drive circuit, and the lower diagram shows the structure of the lower transistor drive circuit. Figure 3As shown, the input pins of chip U1 include: enable pin OE, and drive control signal pins for the three upper transistors in the three-phase bridge arm, such as pins EPWM_1A, EPWM_3A, and EPWM_5A; the output pins of chip U1 include: drive signal pins for the three upper transistors in the three-phase bridge arm, such as pins U_H, V_H, and W_H. The input pins of chip U2 include: enable pin OE, and drive control signal pins for the three lower transistors in the three-phase bridge arm, such as pins EPWM_2A, EPWM_4A, and EPWM_6A; the output pins of chip U2 include: drive signal pins for the three lower transistors in the three-phase bridge arm, such as pins U_L, V_L, and W_L.

[0053] like Figure 2 and Figure 3 As shown, the signal EPWM_OE output by the DSP chip is input to the enable circuit pin EPWM_OE of chip U1, and chip U1 outputs the enable signal OE to the pin OE of chip U1; the signals EPWM_1A, EPWM_3A, and EPWM_5A output by the DSP chip are output as signals U_H, V_H, and W_H after passing through chip U1. Signal U_H is output to the gate of switch Q1, signal V_H is output to the gate of switch Q2, and signal W_H is output to the gate of switch Q3.

[0054] In the solution of this invention, a nine-switch inverter is set up. Through hardware processing of twelve preset PWM waves, nine PWM waves are output to control the operation of the dual motors, so as to realize the normal driving operation of the dual motors. The two motors are controlled independently and do not interfere with each other. The number of switches required for dual motor driving is reduced. The hardware cost and wiring complexity of the drive system are reduced. The drive circuit of the dual motors is simplified and the integration of the dual motor drive system is improved.

[0055] In some embodiments, the second driving module includes: a second driving chip, such as chip U2; a second set of driving control signals, including: a second driving control signal, a fourth driving control signal, and a sixth driving control signal; and the second set of driving signals including: a driving signal for the lower tube of the first phase bridge arm, a driving signal for the lower tube of the second phase bridge arm, and a driving signal for the lower tube of the third phase bridge arm.

[0056] The second drive module, based on the second set of drive control signals among the twelve drive control signals, outputs a second set of drive signals, including:

[0057] The second driver chip is used, under the control of the enable control signal issued by the main control module, and based on the second, fourth, and sixth drive control signals issued by the main control module, to output drive signals for the lower transistors of the first phase bridge arm, the second phase bridge arm, and the third phase bridge arm. The enable control signal is, for example, the switch signal EPWM_OE; the second drive control signal is, for example, EPWM_2A; the fourth drive control signal is, for example, EPWM_4A; the sixth drive control signal is, for example, EPWM_6A; the drive signals for the lower transistors of the first phase bridge arm are, for example, the drive signal U_L for the lower transistor of phase U (i.e., switch Q7); the drive signals for the lower transistors of the second phase bridge arm are, for example, the drive signal V_L for the lower transistor of phase V (i.e., switch Q8); and the drive signal for the lower transistor of the third phase bridge arm is, for example, the drive signal W_L for the lower transistor of phase W (i.e., switch Q9).

[0058] like Figure 3 As shown, the signal EPWM_OE output by the DSP chip is sent to the enable pin EPWM_OE of chip U2. The DSP chip output signals EPWM_2A, EPWM_4A, and EPWM_6A are sent to the output signals U_L, V_L, and W_L after passing through chip U2. Signal U_L is output to the gate of switch Q7, signal V_L is output to the gate of switch Q8, and signal W_L is output to the gate of switch Q9.

[0059] Figure 3 In this invention, chip U1 and chip U2 are the upper and lower parts of the driver chip for the three-phase bridge arm. Driver chip U1 is the driver chip for the upper transistor in the three-phase bridge arm, and driver chip U2 is the driver chip for the lower transistor in the three-phase bridge arm. Driver chips U1 and U2 can be integrated together to form the upper and lower transistor driver chip U for the three-phase bridge arm. In this invention, a nine-switch inverter and a driver circuit for the nine-switch inverter are provided. This allows for independent drive control of the dual motors by driving nine switches, reducing the number of switches required for dual motor drive, lowering the cost of the drive system, and simplifying the drive circuit.

[0060] In some embodiments, the third driving module includes: a first logic processing module, a second logic processing module, and a third logic processing module, wherein the first logic processing module, the second logic processing module, and the third logic processing module are arranged in parallel, and the first logic processing module is as follows: Figure 4 The NOT gates U6, U7, and NAND gates U3 shown are used in the second logic processing module. Figure 4 The NOT gates U8, U9, and NAND gates U4 shown are used in the third logic processing module. Figure 4The NOT gates U10, U11, and U5 are shown; the third set of drive control signals includes: complementary signals of the first drive control signal, the second drive control signal, the third drive control signal, the fourth drive control signal, the fifth drive control signal, and the sixth drive control signal; the third set of drive signals includes: drive signals of the middle tube of the first phase bridge arm, drive signals of the middle tube of the second phase bridge arm, and drive signals of the middle tube of the third phase bridge arm.

[0061] The third drive module, based on the third set of drive control signals among the twelve drive control signals, outputs a third set of drive signals, including:

[0062] The first logic processing module is used to output the drive signal of the middle tube of the first phase bridge arm based on the complementary signal of the first drive control signal and the complementary signal of the second drive control signal; wherein, the complementary signal of the first drive control signal is such as the complementary signal of EPWM_1A as EPWM_1B, the complementary signal of the second drive control signal is such as the complementary signal of EPWM_2A as EPWM_2B, and the drive signal of the middle tube of the first phase bridge arm is such as the drive signal U_M of the middle tube of the U phase bridge arm, i.e., the switch Q4.

[0063] The second logic processing module is used to output the drive signal of the middle tube of the second phase bridge arm based on the complementary signal of the third drive control signal and the complementary signal of the fourth drive control signal; wherein, the complementary signal of the third drive control signal is such as the complementary signal of EPWM_3A as EPWM_3B, the complementary signal of the fourth drive control signal is such as the complementary signal of EPWM_4A as EPWM_4B, and the drive signal of the middle tube of the second phase bridge arm is such as the drive signal V_M of the middle tube of the V phase bridge arm, i.e., the switch Q5.

[0064] The third logic processing module is used to output the drive signal of the middle tube of the third phase bridge arm based on the complementary signals of the fifth drive control signal and the sixth drive control signal. Specifically, the complementary signal of the fifth drive control signal is, for example, the complementary signal of EPWM_5A is, EPWM_5B; the complementary signal of the sixth drive control signal is, for example, the complementary signal of EPWM_6A is, EPWM_6B; and the drive signal of the middle tube of the third phase bridge arm is, for example, the drive signal W_M of the middle tube of the W phase bridge arm, i.e., the switching transistor Q6.

[0065] A dual-motor system driven by nine switches requires simultaneous control of the on / off states of nine switches. The PWM drive signals for the upper and lower switches are directly generated by a DSP chip. Figure 2 and Figure 3As shown, the drive signal for the PWM wave of the middle MOSFET is obtained by processing the PWM waves of the upper and lower MOSFETs through corresponding logic operations. The upper MOSFET refers to... Figure 7 The switching transistors Q1, Q2, and Q3 in the middle refer to the transistors. Figure 7 Switches Q4, Q5, and Q6 in the middle, the lower transistor represents... Figure 7 The switching transistors Q7, Q8, and Q9 are used in the circuit. This means that a dead time cannot be incorporated for each bridge arm. During the transition from two switches to another two switches, there is a risk of shoot-through in three bridge arms. Shoo-through can cause overcurrent in the drive module, damaging the driver.

[0066] Therefore, a twelve-channel PWM signal and hardware circuit are designed to drive nine switching transistors. Taking the U-phase as an example, EPWM_1A drives the upper transistor, and EPWM_2A drives the lower transistor. Then, complementary signals EPWM_1B and EPWM_2B of EPWM_1A and EPWM_2A are generated synchronously. These two signals, EPWM_1B and EPWM_2B, are ORed to drive the middle transistor. Dead time is added to EPWM_1A and EPWM_1B through software configuration of the DSP chip, and dead time is added to EPWM_2A and EPWM_2B through software configuration of the DSP chip. This achieves nine-channel switching while avoiding shoot-through between driving transistors. The dead time of the PWM peripheral is set internally by configuring the value of the PWM peripheral dead time register. Since the middle transistor is driven by dual PWM signals, a special driving circuit is required, such as... Figure 4 As shown.

[0067] Figure 5 This is a schematic diagram of the drive output signals of the main control chip, such as a DSP chip, in a motor controller or frequency converter. Figure 5 As shown, the DSP chip outputs the enable control signal EPWM_OE and twelve PWM waves. The pins of the DSP chip that output the drive output signals for the twelve PWM waves are: pin EPWM_OE, pin EPWM_1A, pin EPWM_1B, pin EPWM_2A, pin EPWM_2B, pin EPWM_3A, pin EPWM_3B, pin EPWM_4A, pin EPWM_4B, pin EPWM_5A, pin EPWM_5B, pin EPWM_6A, and pin EPWM_6B.

[0068] The twelve PWM waves include: three drive control signals for the three upper transistors (e.g., Q1, Q2, and Q3) among the nine transistors, such as EPWM_1A for Q1, EPWM_3A for Q2, and EPWM_5A for Q3; three drive control signals for the three lower transistors (e.g., Q7, Q8, and Q9), such as EPWM_1A for Q7, EPWM_3A for Q8, and EPWM_5A for Q9; and six drive control signals for the three middle transistors (e.g., Q4, Q5, and Q6), such as EPWM_1B and EPWM_2B for Q4, EPWM_3B and EPWM_4B for Q5, and EPWM_5B and EPWM_6B for Q6.

[0069] In the solution of this invention, for the switching transistor drive circuit of the inverter in the nine-switch architecture state, the twelve preset PWM waves are processed by hardware to output nine PWM waves to control the operation of the dual motors. Using this drive method, the stable operation of the dual motors under the nine-switch architecture can be achieved. By adding dead-time control of the dead time of the switching transistors, the operational safety of the entire dual-motor operating system is ensured and the transistors are prevented from exploding.

[0070] In the solution of this invention, a nine-switch inverter and a drive circuit for the nine-switch inverter are set up. The main focus is on the drive control circuit under the nine-switch topology. By processing twelve preset PWM waves through hardware, nine PWM waves are output to control the operation of the dual motors, which can achieve stable operation of the dual motors under the nine-switch architecture. The drive method and circuit in the solution of this invention can avoid the situation where three bridge arms are simultaneously turned on during the dual motor control process, which would cause damage to the driver.

[0071] In some embodiments, the first logic processing module includes: a first NOT gate, a second NOT gate, a first NAND gate, the first NOT gate being an example of NOT gate U6, the second NOT gate being an example of NOT gate U7, and the first NAND gate being an example of NAND gate U3. The first logic processing module, based on the complementary signal of the first drive control signal and the complementary signal of the second drive control signal, outputs a drive signal for the middle tube of the first phase bridge arm, including:

[0072] The first NOT gate is used to output a first inverted signal based on the complementary signal of the first drive control signal; the complementary signal of the first drive control signal is such as EPWM_1A and the complementary signal is such as EPWM_1B.

[0073] The second NOT gate is used to output a second inverted signal based on the complementary signal of the second drive control signal; the complementary signal of the second drive control signal is such as EPWM_2A and the complementary signal is such as EPWM_2B.

[0074] The first NAND gate is used to output the drive signal of the middle tube of the first phase bridge arm based on the first inverted signal and the second inverted signal; the drive signal of the middle tube of the first phase bridge arm is like the drive signal U_M of the middle tube of the U phase bridge arm, i.e., the switch Q4.

[0075] And / or, the second logic processing module includes: a third NOT gate, a fourth NOT gate, a second NAND gate, a third NOT gate U8, a fourth NOT gate U9, and a second NAND gate U4. The second logic processing module, based on the complementary signal of the third drive control signal and the complementary signal of the fourth drive control signal, outputs the drive signal for the middle tube of the second phase bridge arm, including:

[0076] The third NOT gate is used to output a third inverted signal based on the complementary signal of the third drive control signal; the complementary signal of the third drive control signal is, for example, EPWM_3A, and the complementary signal is, for example, EPWM_3B.

[0077] The fourth NOT gate is used to output a fourth inverted signal based on the complementary signal of the fourth drive control signal; the complementary signal of the fourth drive control signal is, for example, EPWM_4A, and the complementary signal is, for example, EPWM_4B.

[0078] The second NAND gate is used to output the drive signal of the middle tube of the second phase bridge arm based on the third inverted signal and the fourth inverted signal; the drive signal of the middle tube of the second phase bridge arm is like the drive signal V_M of the middle tube of the V phase bridge arm, i.e., the switch tube Q5.

[0079] And / or, the third logic processing module includes: a fifth NOT gate, a sixth NOT gate, a third NAND gate, a fifth NOT gate-like NOT gate U10, a sixth NOT gate-like NOT gate U11, and a third NAND gate-like NAND gate U5. The third logic processing module, based on the complementary signals of the fifth drive control signal and the sixth drive control signal, outputs the drive signal for the middle tube of the third phase bridge arm, including:

[0080] The fifth NOT gate is used to output a fifth inverted signal based on the complementary signal of the fifth drive control signal; the complementary signal of the fifth drive control signal is, for example, EPWM_5A, and the complementary signal is, for example, EPWM_5B.

[0081] The sixth NOT gate is used to output a sixth inverted signal based on the complementary signal of the sixth drive control signal; the complementary signal of the sixth drive control signal is such as EPWM_6A and the complementary signal is such as EPWM_6B.

[0082] The third NAND gate is used to output the drive signal of the middle tube of the third phase bridge arm based on the fifth and sixth inverted signals. The drive signal of the middle tube of the third phase bridge arm is, for example, the drive signal W_M of the middle tube of the W phase bridge arm, i.e., the switch Q6.

[0083] Figure 4 The diagrams show the structural schematics of the intermediate transistor drive circuits. The top diagram shows the drive circuit for the U-phase intermediate transistor, the middle diagram shows the drive circuit for the V-phase intermediate transistor, and the bottom diagram shows the drive circuit for the W-phase intermediate transistor. Figure 4 As shown, the signal EPWM_1B output by the DSP chip is output to the first input terminal of NAND gate U3 after passing through NOT gate U6; the signal EPWM_2B output by the DSP chip is output to the second input terminal of NAND gate U3 after passing through NOT gate U7; and the output terminal of NAND gate U3 outputs signal U_M to the gate of switch Q4. The signal EPWM_3B output by the DSP chip is output to the first input terminal of NAND gate U4 after passing through NOT gate U8; the signal EPWM_4B output by the DSP chip is output to the second input terminal of NAND gate U4 after passing through NOT gate U9; and the output terminal of NAND gate U4 outputs signal V_M to the gate of switch Q5. The signal EPWM_5B output by the DSP chip is output to the first input terminal of NAND gate U5 after passing through NOT gate U10; the signal EPWM_6B output by the DSP chip is output to the second input terminal of NAND gate U5 after passing through NOT gate U11; and the output terminal of NAND gate U5 outputs signal W_M to the gate of switch Q6.

[0084] Figure 4 In the diagram, chips U3, U4, and U5 are the same type of chip, namely NAND gate chips, and chips U6, U7, U8, U9, U10, and U11 are the same type of chip, namely NOT gate chips. NAND gate chips (i.e., chips U3, U4, and U5) have a boost function, so the transistor drive circuit of a phase bridge arm composed of two NOT gates and one NAND gate can drive the transistor of the corresponding bridge arm. Figure 5 Output twelve PWM waves, via Figure 3 and Figure 3Nine PWM waves are then output. The three drive signals for the three upper transistors (such as Q1, Q2, and Q3) are U_H, V_H, and W_H; the three drive signals for the three middle transistors (such as Q4, Q5, and Q6) are U_M, V_M, and W_M; and the three drive signals for the three lower transistors (such as Q7, Q8, and Q9) are U_L, V_L, and W_L.

[0085] Using the above-mentioned methods Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The entire drive circuit of the nine-switch inverter shown requires switching nine switches on and off to drive the dual motors when controlling their operation. At the moment when driving the dual motors is needed, the nine switches are switched on and off. Figure 5 The DSP chip sends a switching signal EPWM_OE, which directly controls the operation of chip U2 and synchronously controls the turn-on of transistor Q1, making... Figure 2 When the control signal OE output by the enable circuit shown goes low, the signal OE can simultaneously drive the control chip U1 to work.

[0086] Therefore, once chips U1 and U2 are operational, they can... Figure 5 The drive signals EPWM_1A, EPWM_3A, and EPWM_5A output by the DSP chip are converted into U, V, and W signals driving the upper transistor in the nine-switch transistor array; the drive signals EPWM_2A, EPWM_4A, and EPWM_6A are converted into U, V, and W signals driving the lower transistor in the nine-switch transistor array; the complementary signals EPWM_1B and EPWM_2B generated by the DSP chip are logically inverted and then passed through a NAND gate to generate the drive signal for the U phase of the middle transistor. This scheme avoids the risk of shoot-through in the upper, middle, and lower transistors of the nine-switch transistor array, and also facilitates the normal turn-on and turn-off of the middle transistor. It avoids special processing of the middle transistor's drive signal in the software; that is, the middle transistor signal is completely converted and processed by hardware, without the need for software (algorithm) calculation.

[0087] In the present invention, a nine-switch inverter is provided, and a drive circuit for the nine-switch inverter is provided. The drive circuit for the nine-switch inverter needs to be designed in conjunction with the nine-switch drive method proposed in the present invention. Figure 2 and Figure 3 The driving method shown in the diagram can employ a three-phase, six-arm drive circuit; however... Figure 4The driving circuit shown is designed to work in conjunction with the PWM output method of this invention. The driving of the intermediate transistor in this invention uses six switching signals, which need to be converted into switching signals for three intermediate transistors by the driving circuit of the nine-switch inverter to drive the switching of the intermediate transistors, thereby avoiding shoot-through of the upper, middle, and lower bridge arms that could cause transistor failure. This is significantly different from related solutions that use three PWM waves to drive the intermediate transistors of nine switches. That is, the intermediate transistors in related solutions are not implemented using the hardware solution of this invention, but rather the signals are calculated using a software algorithm.

[0088] The present invention provides a drive system for dual motors (such as a first motor and a second motor). The inverter unit comprises an inverter unit and a drive unit. The inverter unit is, for example, a nine-switch inverter, and the drive unit is, for example, a drive circuit for a nine-switch inverter. The inverter unit includes a three-phase bridge arm, with an upper, middle, and lower transistor disposed on each phase arm. The drive unit includes a first drive module, a second drive module, a third drive module, and a main control module. The main control module is used to issue twelve drive control signals when the dual motors need to be driven. The first drive module is used for... Based on the first set of drive control signals from the twelve drive control signals, a first set of drive signals is output to drive the three upper transistors of the three-phase bridge arm; the second drive module is used to output a second set of drive signals based on the second set of drive control signals from the twelve drive control signals to drive the three lower transistors of the three-phase bridge arm; the third drive module is used to output a third set of drive signals based on the third set of drive control signals from the twelve drive control signals to drive the three middle transistors of the three-phase bridge arm; the third set of drive control signals includes: a complementary signal of the first set of drive control signals and a complementary signal of the second set of drive control signals. Thus, by setting up an inverter with nine switches and a middle transistor drive circuit composed of logic chips, the number of switches is reduced, the structure is simplified, and costs are saved, while achieving stable operation of dual motors. This inverter device involves the manufacturing of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor (IGBT) chips, and modules.

[0089] Specifically, in the solution of this invention, a drive circuit with nine switching transistors (i.e., an inverter composed of nine switching transistors) is set up for a drive system of dual motors (such as a first motor and a second motor). Drive circuits for the upper, middle, and lower transistors are also provided. The drive circuit for the upper transistor includes a driver chip U1, the drive circuit for the lower transistor includes a driver chip U2, and the drive circuit for the middle transistor includes a middle transistor drive circuit for each phase arm (with a boost function). The middle transistor drive circuit for each phase arm includes two NOT gates and one NAND gate (the NAND gate has a boost function). Each of the nine switching transistors in the first, second, and third phase arms has three switching transistors (i.e., an upper transistor, a middle transistor, and a lower transistor arranged from top to bottom). For example, in the first phase bridge arm, the upper tube is switch tube Q1, the middle tube is switch tube Q4, and the lower tube is switch tube Q7; in the second phase bridge arm, the upper tube is switch tube Q2, the middle tube is switch tube Q5, and the lower tube is switch tube Q8; in the third phase bridge arm, the upper tube is switch tube Q3, the middle tube is switch tube Q6, and the lower tube is switch tube Q9. Three-phase electricity is drawn from the common terminal of switch tubes Q1 and Q4, the common terminal of switch tubes Q2 and Q5, and the common terminal of switch tubes Q3 and Q6 to power the first motor (e.g., motor M1); and three-phase electricity is drawn from the common terminal of switch tubes Q4 and Q7, the common terminal of switch tubes Q5 and Q8, and the common terminal of switch tubes Q6 and Q9 to power the second motor (e.g., motor M2).When the first and second motors need to be driven, the main control chip (such as a DSP chip) of the dual-motor drive system outputs twelve PWM waves (i.e., EPWM_1A, EPWM_3A, and EPWM_5A; EPWM_2A, EPWM_4A, and EPWM_6A; EPWM_1B, EPWM_3B, and EPWM_5B; EPWM_2B, EPWM_4B, and EPWM_6B). Among them, three PWM waves, EPWM_1A, EPWM_3A, and EPWM_5A, are driven by driver chip U1 (a chip with isolation and boost functions) and output three PWM waves U_H, V_H, and W_H to drive the three upper transistors (i.e., switching transistors Q1, Q2, and Q3) in the three-phase bridge arm. The other three PWM waves, EPWM_2A, EPWM_4A, and EPWM_6A, are driven by driver chip U2 (a chip with isolation and boost functions) and output three PWM waves U_L, V_L, and W_H. W_L drives the three lower transistors (Q7, Q8, and Q9) in the three-phase bridge arm. One PWM wave (EPWM_1B) is input to NAND gate U3 after passing through NOT gate U6. Another PWM wave (EPWM_2B) is also input to NAND gate U3 after passing through NOT gate U7. NOT gate U3 outputs a PWM wave (U_M) that drives one middle transistor (Q4) in the three-phase bridge arm. One PWM wave (EPWM_3B) is input to NAND gate U4 after passing through NOT gate U8. EPWM_4B, after passing through NOT gate U9, is also input to NAND gate U4. NOT gate U4 outputs a PWM wave, V_M, which drives one of the three-phase bridge arms' intermediate transistors, i.e., switch Q5. Another PWM wave, EPWM_5B, is input to NAND gate U5 after passing through NOT gate U10. EPWM_6B, after passing through NOT gate U11, is also input to NAND gate U5. NOT gate U5 outputs a PWM wave, W_M, which drives one of the three-phase bridge arms' intermediate transistors, i.e., switch Q6, thus driving the dual motors. Therefore, by setting up an inverter with nine switches and using a intermediate transistor drive circuit composed of logic chips (such as NOT gates and NAND gates), the number of switches is reduced, the structure is simplified, and costs are saved. It also avoids the risk of shoot-through in the top, middle, and bottom three transistors of the nine switches and makes it easier to drive the intermediate transistors to turn on and off normally, achieving stable operation of the dual motors. This inverter device involves the manufacturing of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor chips, and modules.

[0090] According to an embodiment of the present invention, a motor system corresponding to an inverter is also provided. This motor system may include the inverter described above. The inverter relates to the manufacture of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor chips, and modules.

[0091] Since the processing and functions implemented by the motor system in this embodiment are basically the same as those in the embodiments, principles and examples of the device, any details not covered in this embodiment can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0092] According to an embodiment of the present invention, a vehicle corresponding to an inverter device is also provided. The vehicle may include: the inverter device described above, or the motor system described above. The inverter device relates to the manufacture of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor chips, and modules.

[0093] Since the processing and functions implemented by the vehicle in this embodiment are basically the same as those in the embodiments, principles and examples of the device, any details not covered in this embodiment can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0094] According to an embodiment of the present invention, a robot corresponding to an inverter device is also provided. The robot may include the inverter device described above, or the motor system described above. The inverter device relates to the manufacture of power electronic components such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor chips, and modules.

[0095] Since the processing and functions implemented by the robot in this embodiment are basically the same as those in the embodiments, principles and examples of the device, any details not covered in this embodiment can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0096] According to embodiments of the present invention, a control method for a motor system corresponding to a motor system is also provided, such as... Figure 9 The diagram shown is a flowchart of an embodiment of the method of the present invention. The control method of the motor system may include:

[0097] The main control module issues twelve drive control signals when it is necessary to drive the dual motors. These twelve drive control signals include: a first drive control signal such as EPWM_1A, a second drive control signal such as EPWM_2A, a third drive control signal such as EPWM_3A, a fourth drive control signal such as EPWM_4A, a fifth drive control signal such as EPWM_5A, a sixth drive control signal such as EPWM_6A, and a complementary signal to the first drive control signal such as a complementary signal to EPWM_1A. Examples of complementary signals for the following drive control signals include EPWM_1B, EPWM_2B (complementary signal of the second drive control signal), EPWM_3B (complementary signal of the third drive control signal), EPWM_4B (complementary signal of the fourth drive control signal), EPWM_5B (complementary signal of the fifth drive control signal), and EPWM_6B (complementary signal of the sixth drive control signal).

[0098] The first drive module outputs a first set of drive signals based on the first set of drive control signals among the twelve drive control signals to drive the three upper transistors of the three-phase bridge arm. The first set of drive control signals includes: a first drive control signal such as EPWM_1A, a third drive control signal such as EPWM_3A, and a fifth drive control signal such as EPWM_5A. The first set of drive signals includes: the drive signal U_H for the upper transistor of the U-phase bridge arm, i.e., the switch Q1; the drive signal V_H for the upper transistor of the V-phase bridge arm, i.e., the switch Q2; and the drive signal W_H for the upper transistor of the W-phase bridge arm, i.e., the switch Q3.

[0099] The second drive module outputs a second set of drive signals based on the second set of drive control signals in the twelve drive control signals to drive the three lower transistors of the three-phase bridge arm. The first set of drive control signals includes: a second drive control signal such as EPWM_2A, a fourth drive control signal such as EPWM_4A, and a sixth drive control signal such as EPWM_6A. The second set of drive signals includes: the drive signal U_L for the lower transistor of the U-phase bridge arm, i.e., switch Q7; the drive signal V_L for the lower transistor of the V-phase bridge arm, i.e., switch Q8; and the drive signal W_L for the lower transistor of the W-phase bridge arm, i.e., switch Q9.

[0100] The third drive module outputs a third set of drive signals based on the third set of drive control signals in the twelve drive control signals to drive the three intermediate tubes of the three-phase bridge arm; the third set of drive control signals includes: a complementary signal of the first set of drive control signals and a complementary signal of the second set of drive control signals. The third set of drive control signals includes: complementary signals of the first drive control signal, such as EPWM_1A and EPWM_1B; complementary signals of the second drive control signal, such as EPWM_2A and EPWM_2B; complementary signals of the third drive control signal, such as EPWM_3A and EPWM_3B; complementary signals of the fourth drive control signal, such as EPWM_4A and EPWM_4B; complementary signals of the fifth drive control signal, such as EPWM_5A and EPWM_5B; and complementary signals of the sixth drive control signal, such as EPWM_6A and EPWM_6B. The third set of drive signals includes: drive signal U_M for the middle tube of the U-phase bridge arm, i.e., switch Q4; drive signal V_M for the middle tube of the V-phase bridge arm, i.e., switch Q5; and drive signal W_M for the middle tube of the W-phase bridge arm, i.e., switch Q6.

[0101] Figure 8 This is a flowchart illustrating a method for controlling the operation of two motors using a drive circuit with a nine-switch inverter. Figure 8 As shown, the method for controlling the operation of two motors using a nine-switch inverter drive circuit includes:

[0102] Step 1: Enable the driver (i.e., the driver circuit of the nine-switch transistor) signal, and then proceed to Step 2.

[0103] In step 1, the DSP chip sends a switching signal EPWM_OE to control the driver chip. This switching signal EPWM_OE directly controls the operation of chip U2 and synchronously controls the turn-on of transistor Q1, making... Figure 2 When the control signal OE output by the enable circuit shown goes low, the signal OE can simultaneously drive the control chip U1 to work.

[0104] Step 2: The driver sends a drive signal, and then Step 3 is executed.

[0105] In step 2, the DSP chip outputs twelve PWM waves (i.e., twelve drive signals). The A-phase signals (EPWM_1A, EPWM_3A, and EPWM_5A) of three drive signals EPWM_1, EPWM_3, and EPWM_5 control the upper transistor, while the A-phase signals (EPWM_2A, EPWM_4A, and EPWM_6A) of three drive signals EPWM_2, EPWM_4A, and EPWM_6 control the lower transistor. The B-phase signals (EPWM_1B, EPWM_3B, EPWM_5B, EPWM_2B, EPWM_4B, and EPWM_6B) of EPWM_1, EPWM_3, EPWM_5, EPWM_2, EPWM_4, and EPWM_6 are processed by the aforementioned circuitry (e.g., EPWM_1B, EPWM_3B, EPWM_5B, EPWM_2B, EPWM_4B, and EPWM_6B). Figure 4 (To control the central tube)

[0106] Step 3: Drive the dual motors: The nine PWM waves (i.e., the three PWM waves of the upper MOSFET U_H, V_H, W_H, the three PWM waves of the middle MOSFET U_M, V_M, W_M, and the three PWM waves of the lower MOSFET U_L, V_L, W_L) are output normally, driving the dual motors to operate normally.

[0107] In the present invention, a nine-switch inverter is set up. For the nine-switch inverter, the twelve preset PWM waves are processed by hardware to output nine PWM waves to control the operation of the two motors. The drive circuit of the nine-switch inverter drives nine switches to realize independent control of the two motors, which reduces the number of switches, simplifies the complexity of the structure, and saves costs.

[0108] Since the processing and functions implemented by the method in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned motor system, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0109] In summary, it is readily understood by those skilled in the art that, without conflict, the aforementioned advantageous methods can be freely combined and superimposed.

[0110] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of the claims of the present invention.

Claims

1. An inverter device, characterized in that, Used to supply power to a dual motor consisting of a first motor and a second motor; The inverter device includes: an inverter unit and a drive unit; wherein, The inverter unit includes: a three-phase bridge arm, and an upper tube, a middle tube, and a lower tube disposed on each phase of the three-phase bridge arm; The drive unit includes: a first drive module, a second drive module, a third drive module, and a main control module; wherein, The main control module is used to issue twelve drive control signals when it is necessary to drive the dual motors. The first drive module is used to output a first set of drive signals based on the first set of drive control signals in the twelve drive control signals, so as to drive the three upper tubes of the three-phase bridge arm; The second drive module is used to output a second set of drive signals based on the second set of drive control signals in the twelve drive control signals, so as to drive the three lower tubes of the three-phase bridge arm; The third drive module is used to output a third set of drive signals based on the third set of drive control signals in the twelve drive control signals, so as to drive the three intermediate tubes of the three-phase bridge arm; the third set of drive control signals includes: a complementary signal of the first set of drive control signals and a complementary signal of the second set of drive control signals.

2. The inverter device according to claim 1, characterized in that, The three-phase bridge arm includes: a first phase bridge arm, a second phase bridge arm, and a third phase bridge arm; The three upper tubes of the three-phase bridge arm include: a first switch tube located in the first phase bridge arm, a second switch tube located in the second phase bridge arm, and a third switch tube located in the third bridge arm; The three intermediate tubes of the three-phase bridge arm include: a fourth switch tube located in the first phase bridge arm, a fifth switch tube located in the second phase bridge arm, and a sixth switch tube located in the third phase bridge arm. The three lower tubes of the three-phase bridge arm include: the seventh switch tube located in the first phase bridge arm, the eighth switch tube located in the second phase bridge arm, and the ninth switch tube located in the third phase bridge arm. in, The common terminal of the first switch and the fourth switch, the common terminal of the second switch and the fifth switch, and the common terminal of the third switch and the sixth switch are all connected to the power supply terminal of the first motor. The common terminals of the fourth and seventh switches, the fifth and eighth switches, and the sixth and ninth switches are all connected to the power supply terminal of the second motor.

3. The inverter device according to claim 1 or 2, characterized in that, The first driving module includes: an enable module and a first driving chip; the first set of driving control signals includes: a first driving control signal, a third driving control signal, and a fifth driving control signal; the first set of driving signals includes: a driving signal for the upper tube of the first phase bridge arm, a driving signal for the upper tube of the second phase bridge arm, and a driving signal for the upper tube of the third phase bridge arm. in, The first driving module, based on the first group of driving control signals among the twelve driving control signals, outputs a first group of driving signals, including: The enabling module is used to output an enabling signal to the first driver chip based on the enabling control signal issued by the main control module. The first driver chip is configured to, under the control of the enable signal, output the drive signal of the upper tube of the first phase bridge arm, the drive signal of the upper tube of the second phase bridge arm, and the drive signal of the upper tube of the third phase bridge arm based on the first drive control signal, the third drive control signal, and the fifth drive control signal issued by the main control module.

4. The inverter device according to any one of claims 1 to 3, characterized in that, The second driving module includes: a second driving chip; the second set of driving control signals includes: a second driving control signal, a fourth driving control signal, and a sixth driving control signal; the second set of driving signals includes: a driving signal for the lower tube of the first phase bridge arm, a driving signal for the lower tube of the second phase bridge arm, and a driving signal for the lower tube of the third phase bridge arm. in, The second drive module, based on the second set of drive control signals in the twelve drive control signals, outputs a second set of drive signals, including: The second driving chip is used to output the driving signal of the lower tube of the first phase bridge arm, the driving signal of the lower tube of the second phase bridge arm, and the driving signal of the lower tube of the third phase bridge arm, based on the second driving control signal, the fourth driving control signal, and the sixth driving control signal issued by the main control module, under the control of the enable control signal issued by the main control module.

5. The inverter device according to any one of claims 1 to 4, characterized in that, The third driving module includes: a first logic processing module, a second logic processing module, and a third logic processing module; the third set of driving control signals includes: complementary signals of the first driving control signal, complementary signals of the second driving control signal, complementary signals of the third driving control signal, complementary signals of the fourth driving control signal, complementary signals of the fifth driving control signal, and complementary signals of the sixth driving control signal; the third set of driving signals includes: driving signals of the middle tube of the first phase bridge arm, driving signals of the middle tube of the second phase bridge arm, and driving signals of the middle tube of the third phase bridge arm; in, The third drive module outputs a third set of drive signals based on the third set of drive control signals among the twelve drive control signals, including: The first logic processing module is used to output the drive signal of the middle tube of the first phase bridge arm based on the complementary signal of the first drive control signal and the complementary signal of the second drive control signal. The second logic processing module is used to output the drive signal of the middle tube of the second phase bridge arm based on the complementary signal of the third drive control signal and the complementary signal of the fourth drive control signal. The third logic processing module is used to output the drive signal of the middle tube of the third phase bridge arm based on the complementary signal of the fifth drive control signal and the complementary signal of the sixth drive control signal.

6. The inverter device according to claim 5, characterized in that, in, The first logic processing module includes: a first NOT gate, a second NOT gate, and a first NAND gate; The first logic processing module, based on the complementary signal of the first drive control signal and the complementary signal of the second drive control signal, outputs the drive signal of the middle tube of the first phase bridge arm, including: The first NOT gate is used to output a first inverted signal based on the complementary signal of the first drive control signal; The second NOT gate is used to output a second inverted signal based on the complementary signal of the second drive control signal; The first NAND gate is used to output the drive signal of the middle tube of the first phase bridge arm based on the first inverted signal and the second inverted signal; And / or, The second logic processing module includes: a third NOT gate, a fourth NOT gate, and a second NAND gate; The second logic processing module, based on the complementary signals of the third and fourth drive control signals, outputs the drive signal for the middle tube of the second phase bridge arm, including: The third NOT gate is used to output a third inverted signal based on the complementary signal of the third drive control signal; The fourth NOT gate is used to output a fourth inverted signal based on the complementary signal of the fourth drive control signal; The second NAND gate is used to output the drive signal of the middle tube of the second phase bridge arm based on the third inverted signal and the fourth inverted signal; And / or, The third logic processing module includes: a fifth NOT gate, a sixth NOT gate, and a third NAND gate; The third logic processing module, based on the complementary signals of the fifth and sixth drive control signals, outputs the drive signal for the middle tube of the third phase bridge arm, including: The fifth NOT gate is used to output a fifth inverted signal based on the complementary signal of the fifth drive control signal; The sixth NOT gate is used to output a sixth inverted signal based on the complementary signal of the sixth drive control signal; The third NAND gate is used to output the drive signal of the middle tube of the third phase bridge arm based on the fifth inverted signal and the sixth inverted signal.

7. A motor system, characterized in that, include: The inverter device as described in any one of claims 1 to 6.

8. A vehicle, characterized in that, include: The inverter device as described in any one of claims 1 to 6, or the motor system as described in claim 7.

9. A robot, characterized in that, include: The inverter device as described in any one of claims 1 to 6, or the motor system as described in claim 7.

10. A control method for a motor system as described in claim 7, characterized in that, include: When it is necessary to drive the dual motors, twelve drive control signals are issued. The first drive module outputs a first set of drive signals based on the first set of drive control signals in the twelve drive control signals to drive the three upper tubes of the three-phase bridge arm. The second drive module outputs a second set of drive signals based on the second set of drive control signals in the twelve drive control signals to drive the three lower tubes of the three-phase bridge arm. The third drive module outputs a third set of drive signals based on the third set of drive control signals in the twelve drive control signals to drive the three intermediate tubes of the three-phase bridge arm. The third set of drive control signals includes: complementary signals of the first set of drive control signals and complementary signals of the second set of drive control signals.

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