Permanent magnet synchronous motor shaft voltage suppression pwm driving method and storage medium

Abstract

The application relates to the motor technical field and discloses a permanent magnet synchronous motor shaft voltage suppression PWM driving method and a storage medium. The permanent magnet synchronous motor shaft voltage suppression PWM driving method comprises the following steps: at least utilizing an ARU interconnection timer output module ATOM of a general timer module GTM, controlling the arbitrary flip of the starting level of a PWM waveform in the form of a PWM period combination, and removing zero vectors in the PWM waveform. The application can at least suppress the generation of the shaft voltage of the permanent magnet synchronous motor, prevent the shaft voltage from causing harm to bearings and stator windings, and is beneficial to guaranteeing the safe operation of the motor. In addition, the application realizes the arbitrary flip of the starting level of the PWM waveform in the form of a PWM size period combination, can satisfy the output of an expected waveform, so as to achieve the effect of removing zero vectors in the PWM waveform, and in addition, the PWM pulse below 2 mu s is suppressed, the protection of an inverter can be realized, and the service life of the inverter is prolonged.

Description

Technical Field

[0001] This invention relates to the field of motor technology, and in particular to a PWM drive method and storage medium for suppressing shaft voltage in a permanent magnet synchronous motor. Background Technology

[0002] During operation, permanent magnet synchronous motors generate shaft voltage at the bearing ends or between the motor shaft and the bearing. When the shaft voltage reaches a certain level, it can break down the lubricating oil film inside the bearing, generating shaft current. This shaft current increases the internal temperature of the bearing, accelerates the aging and deterioration of the lubricating grease, reduces lubrication effectiveness, and further exacerbates bearing wear. Furthermore, shaft voltage not only damages the bearing but can also discharge through the insulation gap between the shaft and the stator windings, causing insulation damage to the stator windings and leading to short circuits and other motor malfunctions. Summary of the Invention

[0003] The purpose of this invention is to provide a PWM driving method and storage medium for suppressing shaft voltage in permanent magnet synchronous motors, which can at least suppress the generation of shaft voltage in permanent magnet synchronous motors, prevent shaft voltage from damaging bearings and stator windings, and help ensure the safe operation of the motor.

[0004] To address the aforementioned technical problems, in a first aspect, the present invention provides a PWM driving method for suppressing shaft voltage of a permanent magnet synchronous motor. This method utilizes at least the ARU interconnected timer output module ATOM of the general-purpose timer module GTM to control the arbitrary flipping of the PWM waveform's start level through a combination of PWM cycles, and removes zero vectors from the PWM waveform.

[0005] Optionally, the ATOM implements PWM output based on at least the first register, the second register, the third register, the fourth register, and the fifth register; In response to the third register starting to count from 0 in any cycle, when the count value of the third register reaches the set value of the second register, the PWM output waveform level is switched; when the count value of the third register reaches the preset value of the first register, the PWM output waveform level is switched again; when the third register is reset, at least the value of the fifth register is updated in the second register, and the value of the fourth register is updated in the first register to control the PWM output of the next cycle.

[0006] Optionally, it involves at least six-phase PWM output channels, a PWM output reference channel, and a full-cycle reference channel; Each phase of the PWM output channel is composed of two half-cycle PWM waveforms to form a complete PWM waveform; The PWM output reference channel is used at least to provide a reference for the counting synchronization reset of the third register corresponding to the six-phase PWM output channel; The period of the PWM output reference channel is at least half the period of the full-cycle reference channel.

[0007] Optionally, motor field-oriented control (FOC) is executed at the beginning position of the output waveform of the full-cycle reference channel to calculate at least the fourth and fifth register values ​​of the PWM output reference channel in the first half of any cycle, the fourth and fifth register values ​​of the PWM output reference channel in the second half of any cycle, the fourth and fifth register values ​​of the six-phase PWM output channel in the first half of any cycle, and the fourth and fifth register values ​​of the six-phase PWM output channel in the second half of any cycle.

[0008] Optionally, during a preset time period before the end of the carrier frequency, a preset data transmission control mechanism is triggered to transfer the values ​​of the fourth and fifth registers of the first half of the next carrier frequency cycle. When the carrier frequency ends, the preset data transmission control mechanism is triggered to transfer the values ​​of the fourth and fifth registers for the second half of the next carrier frequency cycle.

[0009] Optionally, the preset data transmission control mechanism is triggered through a preset ATOM channel to transfer the fourth register value and the fifth register value.

[0010] Optionally, the rising edge of the output waveform of the first ATOM channel triggers the preset data transmission control mechanism to transfer the PWM output reference channel corresponding to the first half of the next carrier frequency cycle, as well as the fourth and fifth register values ​​of the six-phase PWM output channel. The falling edge of the output waveform of the second ATOM channel triggers the preset data transmission control mechanism to transfer the fourth and fifth register values ​​of the six-phase PWM output channel corresponding to the second half of the next carrier frequency cycle.

[0011] Optionally, the number of mechanism channels required to transport the fourth and fifth register values ​​corresponding to the first half cycle of the six-phase PWM output channel and the PWM output reference channel is 7; The number of mechanism channels required to transfer the fourth register value and the fifth register value corresponding to the second half cycle of the six-phase PWM output channel is 6; Each preset data transmission control mechanism is connected via a daisy chain, where data is transferred from one mechanism channel to the next through a daisy chain.

[0012] Optionally, before the end of the carrier frequency, an interrupt is triggered by the rising edge of the third ATOM channel during a set period. Within the interrupt, at least the first and second registers of the current PWM second half cycle are adjusted to adapt to the PWM small pulse suppression requirements and the PWM start level switching requirements of the next cycle.

[0013] Based on the same concept, in a second aspect, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps in the permanent magnet synchronous motor shaft voltage suppression PWM drive method according to any one of the first aspects.

[0014] The technical solution provided by this invention utilizes at least the ARU interconnected timer output module ATOM of the general-purpose timer module GTM to control the arbitrary flipping of the PWM waveform's start level through PWM cycle combinations, and removes zero vectors from the PWM waveform. Therefore, this invention can at least suppress the generation of shaft voltage in permanent magnet synchronous motors, preventing shaft voltage from damaging bearings and stator windings, and thus ensuring the safe operation of the motor. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the upper three bridges switching the PWM waveform during any carrier frequency cycle of a traditional PWM. Figure 2 This is a schematic diagram of the PWM waveform switching performed by the upper three bridges during the carrier frequency cycle of the shaft voltage suppression in the existing technology; Figure 3 This is a schematic diagram of a PWM drive waveform provided in an embodiment of the present invention; Figure 4 This is a timing diagram illustrating a DMA transfer of the SR1 / SR0 registers provided in an embodiment of the present invention; Figure 5 This is a timing diagram of a small pulse suppression process provided in an embodiment of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0017] It should be noted that any symbols and / or numbers present in the specification that are not marked in the accompanying drawings are not reference numerals.

[0018] As described in the background section, during operation, permanent magnet synchronous motors generate shaft voltage at the two bearing ends or between the motor shaft and the bearing. When the shaft voltage reaches a certain level, it can break down the lubricating oil film inside the bearing, generating shaft current. The generation of shaft current increases the internal temperature of the bearing, accelerates the aging and deterioration of the lubricating grease, reduces lubrication effectiveness, and further exacerbates bearing wear. In addition, shaft voltage not only damages the bearing but may also discharge through the insulation gap between the shaft and the stator windings, causing insulation damage to the stator windings and leading to faults such as short circuits in the motor.

[0019] Currently, shaft voltage suppression technologies based on control strategy optimization mainly include three-vector synthesized PWM technology, four-vector synthesized PWM technology, and flip PWM technology. The core of these technologies is to remove the zero vector in the PWM waveform (the zero vector will cause the motor shaft end to generate a shaft voltage of ±1 / 2Udc). Figure 1 This is a schematic diagram showing the switching of the PWM waveform by the upper three bridges during any carrier frequency cycle of a traditional PWM circuit, as shown below. Figure 1 As shown, in a traditional seven-segment PWM, the starting level of the upper three bridge PWM waveforms is low in each carrier frequency cycle, while the starting level of the lower three bridge PWM waveforms is high. To remove zero vectors from the PWM waveform... Figure 2 This is a schematic diagram of the PWM waveform switching performed by the upper three bridges during the carrier frequency cycle of the shaft voltage suppression in existing technology, such as... Figure 2 As shown, when switching between any two carrier frequency cycles, the PWM waveform needs to achieve the flipping of the start level. That is, the start level of the PWM waveform can be either high or low, requiring 3 to 4 edges to be generated in each carrier frequency cycle. However, the traditional PWM drive design method can only generate 2 edges in each carrier frequency cycle.

[0020] In view of this, the present invention aims to provide a shaft voltage suppression PWM drive design scheme, so as to at least realize the arbitrary flipping of the PWM waveform start level, remove the zero vector in the PWM waveform, and at the same time realize the small pulse suppression function of the PWM waveform, thereby extending the inverter life.

[0021] Based on the above technical concepts Figure 3 This is a schematic diagram of a PWM drive waveform provided in an embodiment of the present invention. See also... Figure 3 The permanent magnet synchronous motor shaft voltage suppression PWM drive method utilizes at least the ARU interconnected timer output module ATOM of the general-purpose timer module GTM to control the arbitrary flipping of the PWM waveform start level through PWM cycle combination and remove the zero vector in the PWM waveform.

[0022] GTM includes at least the following: 1. ARU (Advanced Routing Unit) The GTM's internal high-speed hardware bus eliminates the need for a CPU and DMA, directly sending the data captured by TIM, DPLL phase, and MCS timing to ATOM / TOM, and updating the PWM duty cycle / period in real time.

[0023] The ATOM is special because it natively connects to the ARU, while the TOM does not have a native ARU channel.

[0024] 2. CMU (Clock Management Unit) Used to provide independent time bases for ATOM and TIM, and to generate multiple clocks by frequency division.

[0025] 3. Output module (PWM generation) ATOM: ARU interconnect timer output module, 24-bit counter, supports ARU dynamic refresh PWM; TOM: Timer output module, 16-bit, with built-in hardware dead time, suitable for three-phase inverter complementary PWM.

[0026] 4. TIM (Timer Input Module) Input Capture Module External signal edge capture, filtering, and timestamp measurement; for motor applications, the process can be: motor Hall / encoder signal acquisition → ARU → ATOM dynamic PWM adjustment.

[0027] 5. DTM (Dead Time Module) The TOM bridge generates a complementary drive dead zone between the upper and lower bridges.

[0028] 6. DPLL Digital Phase-Locked Loop Suitable for crankshaft / cam signal phase locking, angle synchronization, engine electronic control, etc.

[0029] 7. MCS Multichannel Sequencer Actions can be triggered by angle / time sequence and ADC sampling can be synchronized.

[0030] 8. TBU Common Time Base Unit GTM uses a unified global timestamp to achieve strict synchronization across multiple channels.

[0031] In one specific implementation, optionally, the ATOM implements PWM output based on at least the first register, the second register, the third register, the fourth register, and the fifth register; In response to the third register starting to count from 0 in any cycle, when the count value of the third register reaches the set value of the second register, the PWM output waveform level is switched; when the count value of the third register reaches the preset value of the first register, the PWM output waveform level is switched again; when the third register is reset, at least the value of the fifth register is updated in the second register, and the value of the fourth register is updated in the first register to control the PWM output of the next cycle.

[0032] In another specific implementation, optionally, at least a six-phase PWM output channel, a PWM output reference channel, and a full-cycle reference channel are involved; Each phase PWM output channel is composed of two half-cycle PWM waveforms to form a complete PWM waveform; The PWM output reference channel is used at least to provide a reference for the counting synchronization reset of the third register corresponding to the six-phase PWM output channel; The period of the PWM output reference channel is at least half the period of the full-cycle reference channel.

[0033] In another specific implementation, optionally, motor field-oriented control (FOC) is executed at the beginning of the output waveform of the whole cycle reference channel to calculate at least the fourth and fifth register values ​​of the PWM output reference channel in the first half of any cycle, the fourth and fifth register values ​​of the PWM output reference channel in the second half of any cycle, the fourth and fifth register values ​​of the six-phase PWM output channel in the first half of any cycle, and the fourth and fifth register values ​​of the six-phase PWM output channel in the second half of any cycle.

[0034] In another specific implementation, optionally, during a preset period before the end of the carrier frequency, a preset data transmission control mechanism is triggered to transfer the values ​​of the fourth and fifth registers of the first half of the next carrier frequency cycle. When the carrier frequency ends, a preset data transmission control mechanism is triggered to transfer the values ​​of the fourth and fifth registers for the second half of the next carrier frequency cycle.

[0035] Specifically, PWM output can be implemented based on the ATOM of the GTM peripheral module of the TC277 chip, mainly involving five registers: CM0, CM1, CN0, SR0, and SR1. It can be understood that the first register could refer to the CM0 register, the second to the CM1 register, the third to the CN0 register, the fourth to the SR0 register, and the fifth to the SR1 register.

[0036] The CN0 register starts counting from 0. When it reaches the set value of CM1, the PWM output waveform level switches. When it reaches the set value of CM0, the PWM output waveform level switches again. Furthermore, SR1 / SR0 are shadow registers. When the CN0 register is reset, the values ​​of the SR1 / SR0 registers are updated in the CM1 / CM0 registers to control the PWM output in the next cycle.

[0037] See also Figure 3 The system has six channels, ATOM0_1 to ATOM0_6, which are six-phase PWM output channels. Each phase of the PWM output channel consists of two half-cycle PWM waveforms forming a complete PWM waveform. Channel ATOM0_0 serves as the reference channel for all six PWM outputs, i.e., the short-cycle reference channel, used to synchronously reset the CN0 counters of at least six PWM channels, ensuring the synchronization of the six PWM outputs. Channel ATOM0_7 is the full-cycle reference channel, i.e., the long-cycle reference channel. The period of channel ATOM0_0 is half the period of channel ATOM0_7. The FOC operation is executed at the beginning of the ATOM0_7 output waveform, calculating the SR1 / SR0 register values ​​for the first half and the second half of the cycle for the ATOM0_0 reference channel and the 6 PWM output channels respectively. 8μs before the end of the carrier frequency (i.e., the aforementioned preset time period is 8μs; it can be understood that in other embodiments, the preset time period can also be 7μs, 9μs, etc.), the DMA is triggered to transfer the SR1 / SR0 register values ​​for the first half of the next carrier frequency cycle. When the carrier frequency ends (i.e., the carrier frequency operation begins in the next cycle), the DMA is triggered to transfer the SR1 / SR0 register values ​​for the second half of the next carrier frequency cycle, thus realizing the combined output of the PWM waveform.

[0038] Based on the above technical solutions, Figure 4 This is a timing diagram illustrating a DMA transfer of the SR1 / SR0 registers provided in an embodiment of the present invention. See [link / reference]. Figure 4 In another specific implementation, optionally, the fourth register value and the fifth register value are transferred by triggering a preset data transmission control mechanism through a preset ATOM channel.

[0039] It is known that the preset data transfer control mechanism can be DMA, i.e., direct memory access. It is understood that the preset ATOM channels include the first ATOM channel (corresponding to ATOM1_0 below), the second ATOM channel (corresponding to ATOM1_1 below), and the third ATOM channel (corresponding to ATOM1_2 below).

[0040] In another specific implementation, optionally, the rising edge of the output waveform of the first ATOM channel triggers a preset data transmission control mechanism to transfer the PWM output reference channel corresponding to the first half of the next carrier frequency cycle, as well as the fourth and fifth register values ​​of the six-phase PWM output channel. The falling edge of the output waveform of the second ATOM channel triggers a preset data transmission control mechanism to transfer the fourth and fifth register values ​​of the six-phase PWM output channel corresponding to the second half of the next carrier frequency cycle.

[0041] In another specific implementation, optionally, the number of mechanism channels required to transport the fourth register value and the fifth register value corresponding to the first half cycle of the six-phase PWM output channel and the PWM output reference channel is 7. The number of mechanism channels required to transfer the values ​​of the fourth and fifth registers corresponding to the second half of the cycle of the six-phase PWM output channel is 6. Each preset data transmission control mechanism is connected via a daisy chain, where data is transferred from one mechanism channel to the next through a daisy chain.

[0042] See also Figure 4 The DMA transfer of SR1 / SR0 register values ​​is triggered via the ATOM channel. The rising edge of the ATOM1_0 output waveform triggers the DMA transfer of the first half-cycle SR1 / SR0 register values ​​of the small-cycle reference channel and the six PWM output channels (i.e., the aforementioned six-phase PWM output channels) for the next carrier frequency cycle. In this case, the time interval between the rising and falling edges can be 8μs. The falling edge of the ATOM1_1 output waveform triggers the DMA transfer of the second half-cycle SR1 / SR0 register values ​​of the six PWM output channels for the next carrier frequency cycle. Since the SR1 / SR0 register values ​​of the reference channel are the same in the first and second half-cycles, transferring the register values ​​of the reference channel requires one DMA channel. Furthermore, transferring the first half-cycle SR1 / SR0 register values ​​of the small-cycle reference channel and the six PWM output channels requires seven DMA channels. The DMA channels can be daisy-chained, with each DMA channel triggering the next for data transfer. Similarly, transferring the second half-cycle SR1 / SR0 register values ​​of the six PWM output channels requires six DMA channels, and the DMA channels are daisy-chained to trigger the transfer.

[0043] Based on the above technical solutions, Figure 5 This is a timing diagram of a small pulse suppression process provided in an embodiment of the present invention. See also... Figure 5In another specific implementation, optionally, an interrupt is triggered by the rising edge of the third ATOM channel during a set period before the end of the carrier frequency. Within the interrupt, at least the first and second registers of the current PWM second half cycle are adjusted to adapt to the PWM small pulse suppression requirements and the PWM start level switching requirements of the next cycle.

[0044] It is known that, Figure 5 An example is shown where the set time period is 15μs. 15μs before the end of the carrier frequency, an interrupt is triggered by the rising edge of ATOM1_2. In this interrupt, the CM1 / CM0 registers of the current PWM second half cycle are adjusted to meet the requirements of PWM small pulse suppression and the requirement of PWM start level flipping for the next cycle.

[0045] In summary, the technical solution provided by this invention utilizes the ARU interconnected timer output module ATOM of the general-purpose timer module GTM to control the arbitrary flipping of the PWM waveform's starting level through PWM cycle combinations, and removes zero vectors from the PWM waveform. Therefore, this invention can at least suppress the generation of shaft voltage in permanent magnet synchronous motors, preventing shaft voltage from damaging bearings and stator windings, thus ensuring motor operating safety. Furthermore, this invention achieves arbitrary flipping of the PWM waveform's starting level through PWM cycle combinations, satisfying the desired waveform output, thereby achieving the effect of removing zero vectors from the PWM waveform. In addition, the addition of suppression of PWM pulses below 2μs can protect the inverter and extend its lifespan.

[0046] It should be noted that, in practical applications, the following specific scheme can be used to execute the shaft voltage suppression PWM drive process of a permanent magnet synchronous motor: 1. The PWM drive scheme adopts a design combining large and small cycles. Each phase PWM output channel is composed of two half-cycles of PWM waveforms to form a complete PWM waveform. The small-cycle reference channel synchronously resets the CN0 counters of the six PWM channels, ensuring the synchronization of the six PWM outputs. The period of the small-cycle reference channel is half the period of the large-cycle reference channel. Starting from the beginning of the large-cycle reference channel output waveform, the FOC operation is performed to calculate the SR1 / SR0 register values ​​for the first half-cycle and the second half-cycle of the small-cycle reference channel and the six PWM output channels, respectively. 8μs before the end of the carrier frequency cycle, DMA is triggered to transfer the SR1 / SR0 register values ​​for the first half-cycle of the next carrier frequency cycle. At the end of the carrier frequency cycle, DMA is triggered again to transfer the SR1 / SR0 register values ​​for the second half-cycle of the next carrier frequency cycle, thus achieving the combined output of the PWM waveforms.

[0047] 2. The rising edge of the ATOM1_0 output waveform triggers the DMA to transfer the SR0 / SR1 register values ​​of the small-cycle reference channel and the first half-cycle of the 6 PWM output channels for the next carrier frequency cycle. The time interval between the rising and falling edges is 8μs. The falling edge of the ATOM1_1 output waveform triggers the DMA to transfer the SR1 / SR0 register values ​​of the second half-cycle of the 6 PWM output channels for the next carrier frequency cycle. Since the SR1 / SR0 register values ​​of the reference channel are the same in the first and second half-cycles, transferring the register values ​​of the reference channel requires one DMA channel, and transferring the SR1 / SR0 register values ​​of the first half-cycle of the 6 PWM output channels requires six DMA channels. The DMA channels are daisy-chained, with the previous DMA channel triggering the next DMA channel for data transfer. Simultaneously, transferring the SR0 / SR1 register values ​​of the second half-cycle of the 6 PWM output channels requires six DMA channels, and the DMA channels are daisy-chained to trigger the transfer.

[0048] 3. 15μs before the end of the carrier frequency, an interrupt is triggered by the rising edge of ATOM1_2. In this interrupt, the CM1 / CM0 registers of the second half of the current PWM cycle are adjusted to meet the requirements of PWM small pulse suppression and the requirement of PWM start level flipping in the next cycle.

[0049] This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the permanent magnet synchronous motor shaft voltage suppression PWM drive method provided in all embodiments of the present invention: at least using the ARU interconnected timer output module ATOM of the general-purpose timer module GTM, the PWM waveform start level is arbitrarily flipped through the form of PWM cycle combination, and zero vectors in the PWM waveform are removed.

[0050] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0051] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0052] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0053] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, and C++—as well as conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PWM drive method for suppressing shaft voltage in a permanent magnet synchronous motor, characterized in that, At least the ARU interconnect timer output module ATOM of the general-purpose timer module GTM is used to control the arbitrary flipping of the start level of the PWM waveform through the combination of PWM cycles, and to remove the zero vector in the PWM waveform.

2. The permanent magnet synchronous motor shaft voltage suppression PWM drive method according to claim 1, characterized in that, The ATOM uses at least the first, second, third, fourth, and fifth registers to implement PWM output; In response to the third register starting to count from 0 in any cycle, when the count value of the third register reaches the set value of the second register, the PWM output waveform level is switched; when the count value of the third register reaches the preset value of the first register, the PWM output waveform level is switched again. When the third register is reset, the value of the fifth register is updated to the second register, and the value of the fourth register is updated to the first register to control the PWM output of the next cycle.

3. The permanent magnet synchronous motor shaft voltage suppression PWM drive method according to claim 2, characterized in that, Before the end of the carrier frequency, an interrupt is triggered by the rising edge of the third ATOM channel. Within the interrupt, at least the first and second registers of the current PWM second half cycle are adjusted to adapt to the PWM small pulse suppression requirements and the PWM start level switching requirements of the next cycle.

4. The permanent magnet synchronous motor shaft voltage suppression PWM drive method according to claim 2, characterized in that, It involves at least six-phase PWM output channels, PWM output reference channels, and full-cycle reference channels; Each phase of the PWM output channel is composed of two half-cycle PWM waveforms to form a complete PWM waveform; The PWM output reference channel is used at least to provide a reference for the counting synchronization reset of the third register corresponding to the six-phase PWM output channel; The period of the PWM output reference channel is at least half the period of the full-cycle reference channel.

5. The permanent magnet synchronous motor shaft voltage suppression PWM drive method according to claim 4, characterized in that, Motor field-oriented control (FOC) is executed at the beginning position of the output waveform of the full-cycle reference channel to calculate at least the fourth and fifth register values ​​of the PWM output reference channel in the first half of any cycle, the fourth and fifth register values ​​of the PWM output reference channel in the second half of any cycle, the fourth and fifth register values ​​of the six-phase PWM output channel in the first half of any cycle, and the fourth and fifth register values ​​of the six-phase PWM output channel in the second half of any cycle.

6. The PWM drive method for suppressing shaft voltage of a permanent magnet synchronous motor according to claim 2, characterized in that, During a preset time period before the end of the carrier frequency cycle, a preset data transmission control mechanism is triggered to transfer the values ​​of the fourth and fifth registers for the first half of the next carrier frequency cycle. When the carrier frequency ends, the preset data transmission control mechanism is triggered to transfer the values ​​of the fourth and fifth registers for the second half of the next carrier frequency cycle.

7. The permanent magnet synchronous motor shaft voltage suppression PWM drive method according to claim 6, characterized in that, The preset data transmission control mechanism is triggered by the preset ATOM channel to transfer the values ​​of the fourth and fifth registers.

8. The permanent magnet synchronous motor shaft voltage suppression PWM drive method according to claim 7, characterized in that, The rising edge of the output waveform of the first ATOM channel triggers the preset data transmission control mechanism to transfer the PWM output reference channel corresponding to the first half of the next carrier frequency cycle, as well as the fourth and fifth register values ​​of the six-phase PWM output channel. The falling edge of the output waveform of the second ATOM channel triggers the preset data transmission control mechanism to transfer the fourth and fifth register values ​​of the six-phase PWM output channel corresponding to the second half of the next carrier frequency cycle.

9. The PWM drive method for suppressing shaft voltage of a permanent magnet synchronous motor according to claim 8, characterized in that, The number of mechanism channels required to transport the fourth and fifth register values ​​corresponding to the first half cycle of the six-phase PWM output channel and the PWM output reference channel is 7. The number of mechanism channels required to transfer the fourth register value and the fifth register value corresponding to the second half cycle of the six-phase PWM output channel is 6; Each preset data transmission control mechanism is connected via a daisy chain, where data is transferred from one mechanism channel to the next through a daisy chain.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps in the permanent magnet synchronous motor shaft voltage suppression PWM drive method according to any one of claims 1-9.

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