A current-mode sense amplifier

Abstract

The application relates to a current-mode sensing amplifier and relates to the technical field of microelectronics, and solves the problem that a traditional silicon-based CMOS sensing amplifier cannot be applied to a memory under an all-indium gallium zinc oxide process. The application relates to a current-mode sensing amplifier, which comprises a first-stage positive feedback amplification circuit, a second-stage comparison amplification circuit and an output shaping circuit, the first-stage positive feedback amplification circuit comprises a pair of first and second input transistors which are cross-coupled, the first and second input ends of the first-stage positive feedback amplification circuit are connected with the first and second input transistors respectively, the first and second input ends are connected to a bit line signal end and a reference signal end of a memory cell array respectively, and the signals output by the bit line signal end and the reference signal end are current signals; the second-stage comparison amplification circuit comprises a pair of first and second differential input transistors which adopt a differential input structure; and the input end of the output shaping circuit is connected with a single-end output end of the second-stage comparison amplification circuit.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and more particularly to a current-type sensing amplifier. Background Technology

[0002] As integrated circuits evolve towards 3D integration and back-end processing (BEOL) compatibility, indium gallium zinc oxide thin-film transistors (IGZO TFTs) have become ideal devices for constructing embedded dynamic random access memory (eDRAM) due to their extremely low leakage current and low-temperature processing characteristics. In eDRAM arrays, the sense amplifier (SA) is the core circuit for reading the weak signals from the memory cells.

[0003] However, existing sense amplifier technologies have significant drawbacks when directly applied to this new process. First, traditional silicon-based CMOS sense amplifiers heavily rely on the complementary characteristics of N-type and P-type transistors to achieve high gain and full-swing output. However, current indium gallium zinc oxide (IGNOW) materials can only fabricate stable and reliable N-type thin-film transistors, lacking usable P-type devices. This makes it impossible to directly transplant traditional CMOS structures into an all-IGNOW process.

[0004] Secondly, most existing sensing amplifiers use voltage-type sensing. In embedded memory arrays, bit lines are usually accompanied by huge parasitic capacitances. Voltage-type sensing amplifiers must wait a long time until the bit line capacitance charges and discharges to generate a sufficiently large voltage difference before they can start amplifying. This mechanism results in extremely slow read speeds, which cannot meet the stringent high-speed read requirements of modern storage systems.

[0005] Furthermore, to implement an all-N type amplifier circuit, the logic circuit composed of single-polarity devices inevitably suffers from threshold voltage loss when the output level is high, leading to a severe voltage margin deficiency. This inherent level loss makes it extremely difficult for traditional all-N type amplifiers to maintain the correct logic state under low supply voltages, and it is also difficult to completely turn off during the reset phase in the non-operating state. This not only limits the output voltage swing but also easily causes erroneous switching in the connected digital logic circuits, resulting in instantaneous short-circuit power consumption in the next stage circuit during the reset phase. These drawbacks greatly limit its application in modern low-power, low-voltage chip systems. Summary of the Invention

[0006] Based on the above analysis, the present invention aims to provide a current-mode sensing amplifier to solve the problem that traditional silicon-based CMOS sensing amplifiers cannot be applied to memories using all-indium gallium zinc oxide processes.

[0007] This invention provides a current-mode sensing amplifier, comprising: The circuit consists of a first-stage positive feedback amplifier circuit, a second-stage comparator amplifier circuit, and an output shaping circuit. The first-stage positive feedback amplifier circuit includes a pair of cross-coupled first input transistors and second input transistors. The first input terminal and the second input terminal of the first-stage positive feedback amplifier circuit are respectively connected to the first input transistor and the second input transistor. The first input terminal and the second input terminal are respectively connected to the bit line signal terminal and the reference signal terminal of the memory cell array. The signals output by the bit line signal terminal and the reference signal terminal are current signals. The second-stage comparator amplifier circuit includes a pair of first differential input transistors and second differential input transistors with a differential input structure. The first differential input transistor and the second differential input transistor are respectively connected to the first output terminal and the second output terminal of the first-stage positive feedback amplifier circuit. The input terminal of the output shaping circuit is connected to the single-ended output terminal of the second-stage comparator amplifier circuit.

[0008] Based on the further improvement of the current-type sensing amplifier described above, the first-stage positive feedback amplifier circuit further includes a first load transistor and a second load transistor connected in a diode configuration. The source of the first load transistor is connected to the drain of the first input transistor, and the source of the second load transistor is connected to the drain of the second input transistor. The second-stage comparator amplifier circuit further includes a third load transistor and a fourth load transistor connected in a diode configuration. The source of the third load transistor is connected to the drain of the first differential input transistor, and the source of the fourth load transistor is connected to the drain of the second differential input transistor.

[0009] Based on the further improvement of the current-type sensing amplifier, the output shaping circuit is an inverter, which includes a fifth load transistor connected in the form of a diode and a driving transistor. The source of the fifth load transistor is connected to the drain of the driving transistor.

[0010] Based on the further improvement of the current-type sensing amplifier described above, the inverter also includes a pull-down transistor connected in parallel with the driving transistor. One of the source and drain terminals of the pull-down transistor is grounded, and the other terminal is directly connected to the single-ended output terminal of the inverter. The gate is controlled by the inverting clock signal.

[0011] Based on the further improvements of the current-mode sensing amplifier described above, the first input transistor, the second input transistor, the first differential input transistor, the second differential input transistor, the first load transistor, the second load transistor, the third load transistor, the fourth load transistor, the fifth load transistor, the driving transistor, and the pull-down transistor are all N-type oxide thin-film transistors.

[0012] Based on the further improvement of the current-type sensing amplifier, the first-stage positive feedback amplifier circuit further includes a first bias current source transistor whose drain is connected to the source of the first input transistor and the second input transistor and whose source is grounded. The second-stage comparator amplifier circuit further includes a second bias current source transistor whose drain is connected to the source of the first differential input transistor and the second differential input transistor and whose source is grounded. The gates of the first bias current source transistor and the second bias current source transistor are controlled by a positive clock signal.

[0013] Based on the further improvement of the current-mode sensing amplifier described above, the current-mode sensing amplifier is configured to include a non-readout reset phase, which is obtained through the following configuration: Set the positive phase clock signal to a low level; Set the inverted clock signal to a high level.

[0014] Based on the further improvement of the current-type sensing amplifier described above, the current-type sensing amplifier is configured to include a stage for reading data "1", and the stage for reading data "1" is obtained through the following configuration: Set the positive phase clock signal to a high level; Set the inverted clock signal to a low level; The current signal corresponding to the data "1" causes the second input transistor and the first differential input transistor to turn off, and the first input transistor and the second differential input transistor to turn on.

[0015] Based on the further improvement of the current-mode sensing amplifier described above, the current-mode sensing amplifier is configured to include a stage for reading data "0", and the stage for reading data "0" is obtained through the following configuration: Set the positive phase clock signal to a high level; Set the inverted clock signal to a low level; The current signal corresponding to the data "0" causes the second input transistor and the first differential input transistor to turn on, and the first input transistor and the second differential input transistor to turn off.

[0016] Based on the further improvement of the current-type sensing amplifier, the first bias current source transistor and the second bias current source transistor are used to provide stable operating current for the first stage positive feedback amplifier circuit and the second stage comparator amplifier circuit, respectively, and both the first bias current source transistor and the second bias current source transistor are N-type oxide thin film transistors.

[0017] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: 1. The core idea of ​​this invention is to abandon the traditional voltage waiting mechanism and instead adopt a current-type sensing mechanism. The weak current of the bit line and reference line of the memory is rapidly amplified through the first-stage cross-coupling structure. Then, the signals on both sides of the first-stage output are compared and amplified in the second stage using the second-stage differential structure. Finally, the signals are shaped to generate a logic level with steep edges.

[0018] 2. This invention proposes a basic scheme for a two-stage current-mode sensing amplifier composed entirely of N-type thin-film transistors. Based on this, the invention adds an inverter composed entirely of N-type transistors at the output terminal for signal shaping. Innovatively, a pull-down N-type thin-film transistor controlled by an inverting clock signal is connected in parallel between the output node of the inverter and ground. The additional pull-down transistor is used to force the output node to be pulled down to absolute ground potential during the reset phase, avoiding interference from the previous readout result or node drift on the subsequent readout process. This improves the repeatability and decision reliability of the sensing process, successfully giving the circuit the ability to perform high-speed and stable logic readouts even at power supply voltages as low as 1.5V.

[0019] 3. This invention successfully constructs a current-mode sensing amplifier capable of stable operation at a low voltage of 1.5V, despite the limitations of N-type devices and threshold voltage loss in the manufacturing process. Although all-N-type logic inevitably suffers from threshold voltage loss when outputting a high level, preventing it from reaching the true power supply voltage, the extremely high signal gain provided by the first two cascaded stages ensures that the final output logic signal maintains sufficient clarity even with voltage drop. This high-gain characteristic from the two-stage architecture, combined with the ground potential forced by the pull-down transistor during the reset phase, allows the entire sensing amplifier to maintain extremely high read accuracy and stability even at power supply voltages as low as 1.5V. This completely solves the technical problems of slow read speed, low gain, and limited output level swing caused by the lack of P-type devices in the all-indium gallium zinc oxide process.

[0020] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0021] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Figure 1 This is a basic structural diagram of a current-mode sensing amplifier according to an embodiment of the present invention.

[0022] Figure 2 A timing diagram of a current-mode sensing amplifier according to an embodiment of the present invention is shown.

[0023] Figure 3 The diagram illustrates the operating state of each device in a current-type sensing amplifier during the amplification phase when reading data "1".

[0024] Figure 4 The diagram illustrates the operating state of each device in a current-type sensing amplifier according to an embodiment of the present invention when reading data "0" during the amplification stage. Detailed Implementation

[0025] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0026] Figure 1 This is a basic structural diagram of a current-mode sensing amplifier according to an embodiment of the present invention.

[0027] The following is combined Figure 1 An embodiment of the present invention will be described.

[0028] like Figure 1 As shown, this current-type sensing amplifier includes a first-stage positive feedback amplifier circuit, a second-stage comparator amplifier circuit, and an output shaping circuit. DD V is the power supply voltage. out This is the output voltage.

[0029] The first-stage positive feedback amplifier circuit includes a pair of cross-coupled first input transistors T2 and T3. This circuit has two input terminals: a bit line signal terminal Irbl connected to the memory cell array and a reference signal terminal Iref. The bit line signal terminal Irbl is connected to the drain of the first input transistor T2, and the reference signal terminal Iref is connected to the drain of the second input transistor T3. Utilizing the cross-coupled positive feedback characteristic, the cross-coupled first input transistor T2 and second input transistor T3 can rapidly amplify the weak current difference in the input and convert it into a voltage signal output to the second stage. The cross-coupling connection refers to the connection between the gate of the first input transistor T2 and the drain of the second input transistor T3, and vice versa.

[0030] The bit line signal terminal Irbl comes from the bit lines of the memory array and receives the current signal from those bit lines. The reference signal terminal Iref comes from a current source and receives a current signal with a fixed value.

[0031] In some embodiments, the first-stage positive feedback amplifier circuit may further include a first load transistor T4 and a second load transistor T5 connected in a diode configuration. The term "diode configuration" as used herein refers to the gate and drain of a transistor being connected together. For example, in... Figure 1 In the first load transistor T4, both the gate and drain are connected to V. DD Above, the gate and drain of the second load transistor T5 are both connected to V. DD Above. The first load transistor T4 and the second load transistor T5 provide load for the first-stage positive feedback amplifier circuit.

[0032] In some embodiments, the first-stage positive feedback amplifier circuit may further include a first bias current source transistor T1, whose drain is connected to the source of the first input transistor T2 and the second input transistor T3 and whose source is grounded. The first bias current source transistor T1 can provide a stable quiescent operating point for the first-stage positive feedback amplifier circuit.

[0033] In this embodiment, the drains of the first input transistor T2 and the second input transistor T3 serve as the first output terminal and the second output terminal of the first-stage positive feedback amplifier circuit, respectively, and the voltages output at both terminals are the two output signals of the first-stage positive feedback amplifier circuit.

[0034] In this embodiment, the second-stage comparator amplifier circuit includes a pair of first differential input transistors T7 and T8 employing a differential input structure. The gate of the first differential input transistor T7 is connected to the drain of the first input transistor T2, and the gate of the second differential input transistor T8 is connected to the drain of the second input transistor T3. The two voltage signals output from the first-stage positive feedback amplifier circuit are respectively input to the gates of the first differential input transistor T7 and the second differential input transistor T8.

[0035] In some embodiments, the second-stage comparator amplifier circuit may further include load transistors T9 and T10 arranged in a diode configuration. The term "diode configuration" as used herein refers to two transistors whose gates and drains are connected together. For example, in… Figure 1 In this circuit, the gates of load transistors T9 and T10 are connected together, and their drains are connected together. Load transistors T9 and T10 provide the load for the second-stage comparator amplifier circuit.

[0036] In some embodiments, the second-stage comparator amplifier circuit may further include a bias current source transistor T6, whose drain is connected to the source of the first differential input transistor T7 and the second differential input transistor T8, and whose source is grounded. The bias current source transistor T6 can provide a stable quiescent operating point for the second-stage comparator amplifier circuit.

[0037] In this embodiment, the drain of the second differential input transistor T8 is the single-ended output terminal of the second-stage comparator amplifier circuit, and its output voltage is the single-ended output signal of the second-stage comparator amplifier circuit. The second-stage comparator amplifier circuit can further compare and amplify the two amplified signals output from the first-stage positive feedback amplifier circuit to improve the common-mode rejection ratio and overall gain.

[0038] In this embodiment, the output shaping circuit is responsible for generating the final logic level. Figure 1 In the example shown, the output shaping circuit is an inverter consisting of a load transistor T12 connected in diode configuration and a drive transistor T11. The gate of the drive transistor T11 is the input terminal of the output shaping circuit and is connected to the single-ended output terminal of the second-stage comparator amplifier circuit.

[0039] In some embodiments, the output shaping circuit further includes a pull-down transistor T13 connected in parallel with the driving transistor T11. The source of the pull-down transistor T13 is grounded, and its drain is directly connected to the single-ended output terminal V of the output shaping circuit. out Connected.

[0040] In this embodiment, the gates of bias current source transistors T1 and T6 are controlled by a positive clock signal. Figure 1 The gate of pull-down transistor T13, marked as "CLK", is controlled by an inverted clock signal. Figure 1 (Illustrated as "CLKB" in Chinese). Traditional all-N-type (pseudo-NMOS) inverters are limited by the intrinsic physical defects of proportional logic, and their output can never reach absolute ground. This small residual voltage causes continuous static leakage current in subsequent circuits. To address this defect, this invention uses a pull-down transistor T13 to forcibly turn on the current-mode sensing amplifier during the reset phase (described in detail below), clamping the output node completely to ground. This structure allows the output node to maintain a defined initial state between each read operation, avoiding interference from the previous read result or node drift in the subsequent read process, thereby improving the repeatability and reliability of the sensing process. Furthermore, it avoids subthreshold short-circuit current in the next stage circuit caused by the node maintaining an intermediate level for a long time, thus reducing the instantaneous short-circuit power consumption of the next stage circuit during the reset phase.

[0041] Figure 1 The current-mode sensing amplifier in the middle has two working stages: the amplification stage and the reset stage. Figure 2 A timing diagram of a current-mode sensing amplifier according to an embodiment of the present invention is shown. Figure 2 As shown, the current-mode sensing amplifier in this embodiment of the invention is configured to include an amplification stage and a reset stage (also known as a "precharge stage").

[0042] The amplification stage and the reset stage are explained below.

[0043] Figure 3 This illustration shows the operating states of each component in a current-type sensing amplifier during the amplification phase when reading data "1". For example... Figure 2 and 3 As shown, when the current-type sensing amplifier needs to read the data "1", it can use a positive clock signal ( Figure 2 The "clk signal" is set to high level, which inverts the clock signal ( Figure 2 The "clkb signal" is set to low. Since the clk signal is high, bias current source transistors T1 and T6 are turned on, and the first-stage positive feedback amplifier circuit and the second-stage comparator amplifier circuit are operational. Because the clkb signal is low, pull-down transistor T13 is turned off and does not operate.

[0044] When the current-mode sensing amplifier reads the data "1", a high current is input to the bit line signal terminal Irbl, and a low current is input to the reference signal terminal Iref. Since the drain of the first input transistor T2 has a high current, after the current flows through the load transistor, due to the voltage divider principle, the load transistor receives a large voltage, causing the drain voltage of the first input transistor T2 to become low. Since the first input transistor T2 and the second input transistor T3 are cross-coupled, the gate of the second input transistor T3 is low, and the second input transistor T3 is turned off. Since the drain of the second input transistor T3 is connected to the reference signal terminal Iref, the drain of the second input transistor T3 has a low current. Due to the voltage divider principle, the load transistor receives a small voltage, and the drain of the second input transistor T3 is high. Since the first input transistor T2 and the second input transistor T3 are cross-coupled, the gate of the first input transistor T2 is high, and the first input transistor T2 is turned on. Through this positive feedback mode, the output voltages on the left and right sides of the first stage circuit are initially differentiated, and the signal is input to the second stage amplifier circuit for secondary amplification.

[0045] The two output terminals of the first-stage positive feedback amplifier circuit are connected to the gates of the first differential input transistor T7 and the second differential input transistor T8, respectively. The output signal of the first-stage positive feedback amplifier circuit at the reference signal terminal Iref is high, so the second differential input transistor T8 is turned on. The output signal of the first-stage positive feedback amplifier circuit at the bit line signal terminal Irbl is low, so the first differential input transistor T7 is turned off. After the second differential input transistor T8 is turned on, there is a high current at its drain. Due to the voltage divider principle, the voltage across the load transistor is very large, so the drain of the second differential input transistor T8 is low.

[0046] The second-stage comparator amplifier circuit outputs a low-level signal to an inverter, which converts the low-level signal to a high-level signal. At this point, V... out It is a high level.

[0047] Figure 4 The diagram illustrates the operating state of each device in a current-type sensing amplifier according to an embodiment of the present invention when reading data "0" during the amplification stage.

[0048] like Figure 2 and 4 As shown, when the current-type sensing amplifier needs to read the data "0", it can use a positive clock signal ( Figure 2 The "clk signal" is set to high level, which inverts the clock signal ( Figure 2The "clkb signal" is set to low. Since the clk signal is high, bias current source transistors T1 and T6 are turned on, and the first-stage positive feedback amplifier circuit and the second-stage comparator amplifier circuit are operational. Since the clkb signal is low, pull-down transistor T13 is turned off.

[0049] When the current-mode sensing amplifier reads the data "0", the bit line signal terminal Irbl outputs a low current, and the reference signal terminal Iref outputs a high current. Since the drain of the first input transistor T2 has a low current, after the current flows through the load transistor, due to the voltage divider principle, the voltage across the load transistor is very low, so the drain of the first input transistor T2 is at a high level. Since the first input transistor T2 and the second input transistor T3 are cross-coupled, the gate of the second input transistor T3 is at a high level, and the second input transistor T3 is turned on. Because the drain of the second input transistor T3 is connected to the reference signal terminal Iref, the drain of the second input transistor T3 has a high current. Due to the voltage divider principle, the voltage across the load transistor is very high, so the drain of the second input transistor T3 is at a low level. Since the first input transistor T2 and the second input transistor T3 are cross-coupled, the gate of the first input transistor T2 is at a low level, and the first input transistor T2 is turned off. Through this positive feedback mode, the output voltages on the left and right sides of the first stage circuit are initially differentiated, and the signal is input to the second stage amplifier circuit for secondary amplification.

[0050] The two output terminals of the first-stage positive feedback amplifier circuit are connected to the gates of the first differential input transistor T7 and the second differential input transistor T8, respectively. The output signal of the first-stage positive feedback amplifier circuit at the reference signal terminal Iref is low, so the second differential input transistor T8 is turned off; the output signal of the first-stage positive feedback amplifier circuit at the bit line signal terminal Irbl is high, so the first differential input transistor T7 is turned on. After the second differential input transistor T8 is turned on, there is a low current at its drain. Due to the voltage divider principle, the voltage across the load transistor is very small, so the drain of the second differential input transistor T8 is at a high level.

[0051] The second-stage comparator amplifier circuit outputs a high-level signal to an inverter, which converts the high-level signal to a low-level signal. At this point, V... out It is a low level.

[0052] like Figure 2 As shown, when the current-type sensing amplifier is about to enter the reset phase, the positive clock signal ( Figure 2 The "clk signal" is set low to invert the clock signal ( Figure 2The "clkb signal" is set to a high level. Since the clk signal is low, bias current source transistors T1 and T6 are turned off, and neither the first-stage positive feedback amplifier nor the second-stage comparator amplifier operates. Because the clk signal is high, pull-down transistor T13 is turned on. When the current-mode sense amplifier is in the reset phase, pull-down transistor T13 is forcibly turned on, completely clamping the output node to ground.

[0053] In some embodiments, Figure 1 The transistors T1-T13 shown are all N-type oxide thin-film transistors. For example, they are all indium gallium zinc oxide thin-film transistors.

[0054] The current-mode sensing amplifier provided in this embodiment of the invention can be used in the following three application scenarios: 1. High-bandwidth 3D stacked eDRAM cache for AI accelerators: Artificial intelligence chips require extremely high on-chip cache bandwidth. Leveraging the back-to-end (BEOL) compatibility of IGZO TFTs, high-density eDRAM arrays can be directly 3D stacked on top of logic chips (such as GPUs / NPUs). The sensing amplifier of this invention can be directly fabricated within the stacked layer, utilizing its high-speed current-mode readout characteristics to meet the demands of AI computing for rapid throughput of massive amounts of data, while not occupying the area of ​​the underlying silicon-based CMOS.

[0055] 2. In-pixel storage and compensation circuitry in flexible displays: In high-end OLED or Micro-LED flexible displays, memory units need to be integrated inside pixels to achieve high refresh rates and image quality compensation. Since flexible substrates can only use TFT processes (such as IGZO), the all-N-type SA of this invention can be perfectly integrated onto the glass or flexible PI substrate of the display panel, quickly reading the weak charge signals within the pixels to achieve high-precision display compensation.

[0056] 3. Monolithic 3D microcontroller for ultra-low power IoT edge nodes: IoT devices have extremely high requirements for standby power consumption. IGZO eDRAM is characterized by its extremely low leakage current, long data retention time, and low refresh rate. Applying the sensing amplifier of this invention to the on-chip memory of such IoT chips can not only eliminate static power consumption during reset through a full N-type pull-down structure, but also reduce the chip size through monolithic 3D integration, making it very suitable for applications sensitive to size and power consumption, such as smart wearable devices and remote sensors.

[0057] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: 1. The core idea of ​​this invention is to abandon the traditional voltage waiting mechanism and instead adopt a current-type sensing mechanism. The weak current of the bit line and reference line of the memory is rapidly amplified through the first-stage cross-coupling structure. Then, the signals on both sides of the first-stage output are compared and amplified in the second stage using the second-stage differential structure. Finally, the signals are shaped to generate a logic level with steep edges.

[0058] 2. This invention proposes a basic scheme for a two-stage current-mode sensing amplifier composed entirely of N-type thin-film transistors. Based on this, the invention adds an inverter composed entirely of N-type transistors at the output terminal for signal shaping. Innovatively, a pull-down N-type thin-film transistor controlled by an inverting clock signal is connected in parallel between the output node of the inverter and ground. The additional pull-down transistor is used to force the output node to be pulled down to absolute ground potential during the reset phase, avoiding interference from the previous readout result or node drift on the subsequent readout process. This improves the repeatability and decision reliability of the sensing process, successfully giving the circuit the ability to perform high-speed and stable logic readouts even at power supply voltages as low as 1.5V.

[0059] 3. This invention successfully constructs a current-mode sensing amplifier capable of stable operation at a low voltage of 1.5V, despite the limitations of N-type devices and threshold voltage loss in the manufacturing process. Although all-N-type logic inevitably suffers from threshold voltage loss when outputting a high level, preventing it from reaching the true power supply voltage, the extremely high signal gain provided by the first two cascaded stages ensures that the final output logic signal maintains sufficient clarity even with voltage drop. This high-gain characteristic from the two-stage architecture, combined with the ground potential forced by the pull-down transistor during the reset phase, allows the entire sensing amplifier to maintain extremely high read accuracy and stability even at power supply voltages as low as 1.5V. This completely solves the technical problems of slow read speed, low gain, and limited output level swing caused by the lack of P-type devices in the all-indium gallium zinc oxide process.

[0060] It should be understood that although various elements may be described herein using terms such as first, second, etc., these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the teachings of this disclosure.

[0061] This document describes several examples using block diagrams and / or flowcharts, where each block represents a section of circuitry, modular blocks, or code comprising one or more executable instructions for implementing a specified logical function. It should also be noted that in other implementations, the functions described in the blocks may occur in a different order. For example, depending on the function involved, two blocks shown consecutively may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order.

[0062] The phrases “according to…example” or “in…example” used in this document mean that a particular feature, structure, or characteristic described in connection with the example can be included in at least one implementation of this disclosure. The phrases “according to…example” or “in…example” appearing in different places throughout this document do not necessarily refer to the same example, nor are they necessarily separate or alternative examples that are mutually exclusive with other examples.

[0063] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A current-mode sensing amplifier, characterized in that, include: The circuit consists of a first-stage positive feedback amplifier circuit, a second-stage comparator amplifier circuit, and an output shaping circuit. The first-stage positive feedback amplifier circuit includes a pair of cross-coupled first input transistors and second input transistors. The first input terminal and the second input terminal of the first-stage positive feedback amplifier circuit are respectively connected to the first input transistor and the second input transistor. The first input terminal and the second input terminal are respectively connected to the bit line signal terminal and the reference signal terminal of the memory cell array. The signals output by the bit line signal terminal and the reference signal terminal are current signals. The second-stage comparator amplifier circuit includes a pair of first differential input transistors and second differential input transistors with a differential input structure. The first differential input transistor and the second differential input transistor are respectively connected to the first output terminal and the second output terminal of the first-stage positive feedback amplifier circuit. The input terminal of the output shaping circuit is connected to the single-ended output terminal of the second-stage comparator amplifier circuit.

2. The current-mode sensing amplifier according to claim 1, characterized in that, The first-stage positive feedback amplifier circuit further includes a first load transistor and a second load transistor connected in a diode configuration. The source of the first load transistor is connected to the drain of the first input transistor, and the source of the second load transistor is connected to the drain of the second input transistor. The second-stage comparator amplifier circuit further includes a third load transistor and a fourth load transistor connected in a diode configuration. The source of the third load transistor is connected to the drain of the first differential input transistor, and the source of the fourth load transistor is connected to the drain of the second differential input transistor.

3. The current-mode sensing amplifier according to claim 2, characterized in that, The output shaping circuit is an inverter, which includes a fifth load transistor connected in the form of a diode and a driving transistor. The source of the fifth load transistor is connected to the drain of the driving transistor.

4. The current-mode sensing amplifier according to claim 3, characterized in that, The inverter also includes a pull-down transistor connected in parallel with the driving transistor. One of the source and drain terminals of the pull-down transistor is grounded, and the other terminal is directly connected to the single-ended output terminal of the inverter. The gate is controlled by the inverting clock signal.

5. The current-mode sensing amplifier according to claim 4, characterized in that, The first input transistor, the second input transistor, the first differential input transistor, the second differential input transistor, the first load transistor, the second load transistor, the third load transistor, the fourth load transistor, the fifth load transistor, the driving transistor, and the pull-down transistor are all N-type oxide thin-film transistors.

6. The current-mode sensing amplifier according to claim 5, characterized in that, The first-stage positive feedback amplifier circuit further includes a first bias current source transistor whose drain is connected to the source of the first input transistor and the second input transistor and whose source is grounded. The second-stage comparator amplifier circuit further includes a second bias current source transistor whose drain is connected to the source of the first differential input transistor and the second differential input transistor and whose source is grounded. The gates of the first bias current source transistor and the second bias current source transistor are controlled by a positive clock signal.

7. The current-mode sensing amplifier according to claim 6, characterized in that, The current-mode sensing amplifier is configured to include a non-readout reset phase, which is obtained through the following configuration: Set the positive phase clock signal to a low level; Set the inverted clock signal to a high level.

8. The current-mode sensing amplifier according to claim 6, characterized in that, The current-mode sensing amplifier is configured to include a phase for reading data "1", which is obtained through the following configuration: Set the positive phase clock signal to a high level; Set the inverted clock signal to a low level; The current signal corresponding to the data "1" causes the second input transistor and the first differential input transistor to turn off, and the first input transistor and the second differential input transistor to turn on.

9. The current-mode sensing amplifier according to claim 6, characterized in that, The current-mode sensing amplifier is configured to include a phase for reading data "0", which is obtained through the following configuration: Set the positive phase clock signal to a high level; Set the inverted clock signal to a low level; The current signal corresponding to the data "0" causes the second input transistor and the first differential input transistor to turn on, and the first input transistor and the second differential input transistor to turn off.

10. The current-mode sensing amplifier according to claim 6, characterized in that, The first bias current source transistor and the second bias current source transistor are used to provide stable operating current to the first stage positive feedback amplifier circuit and the second stage comparator amplifier circuit, respectively, and both the first bias current source transistor and the second bias current source transistor are N-type oxide thin film transistors.

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