Frequency multiplication method, device and system based on multi-ramp comparison

Abstract

The application discloses a frequency multiplication method, device and system based on multi-slope comparison, wherein the method comprises the following steps: generating an error voltage signal according to the difference between an output voltage and a reference voltage; generating multiple slope signals with different slopes and / or different initial values in parallel in different time periods of the same period, and generating multiple main control clock pulses in the same period based on the comparison between the error voltage signal and the multiple slope signals; wherein generating the multiple main control clock pulses in the same period at least comprises readjusting the slope of each slope signal based on the currently generated main control clock pulse. The application can effectively improve the MCLK frequency without significantly increasing the circuit complexity and power consumption.

Description

Technical Field

[0001] This invention relates to the field of controller clock frequency technology, and in particular to a frequency multiplication method, apparatus and system based on multi-slope comparison. Background Technology

[0002] In multiphase voltage regulators, increasing the Master Clock (MCLK) frequency is crucial for the system's transient response speed. Current multiphase controllers have up to 16 phases, with each phase having a steady-state frequency of 1MHz, resulting in an MCLK frequency of 16MHz. To achieve good transient performance, the highest frequency the MCLK needs to reach is 16MHz * 2.5 = 40MHz. If the highest frequency reaches 3MHz, the steady-state MCLK frequency would be 48MHz, requiring a maximum frequency of 120MHz. Future designs aim for a maximum frequency of 10MHz per phase, necessitating an MCLK frequency of 160MHz. However, the traditional COT (Constant On-Time) control method generates the MCLK by comparing the voltage loop's triangular wave voltage with a ramp signal. Its frequency is limited by the ramp signal generation rate and the comparator's response speed. Increasing the MCLK frequency often requires a larger ramp charging current and a faster comparator. With a fixed manufacturing process, this increases circuit power consumption and design complexity, and may introduce noise and stability issues. Therefore, how to effectively increase the MCLK frequency without significantly increasing circuit complexity and power consumption has become an urgent technical challenge. Summary of the Invention

[0003] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention proposes a frequency multiplication method, apparatus, and system based on multi-slope comparison, which can effectively increase the MCLK frequency without significantly increasing circuit complexity and power consumption.

[0004] Firstly, this application proposes a frequency multiplication method based on multi-slope comparison, including: An error voltage signal is generated based on the difference between the output voltage and the reference voltage; In different time periods of the same cycle, multiple ramp signals with different slopes and / or different starting values ​​are generated in parallel, and multiple main control clock pulses are generated in the same cycle based on the comparison of the error voltage signal and the multiple ramp signals; wherein, generating multiple main control clock pulses in the same cycle includes at least: readjusting the slope of each current ramp signal based on the currently generated main control clock pulse.

[0005] In one embodiment, multiple ramp signals with different slopes and / or different starting values ​​are generated in parallel during different time periods of the same cycle, and multiple master control clock pulses are generated within the same cycle based on the comparison of the error voltage signal and the multiple ramp signals, including: Generate M ramp signals, where M is an integer greater than or equal to 3; the M ramp signals have different voltage change slopes and / or different initial voltage values; M ramp signals are compared with the error voltage signal. When the level of any ramp signal reaches the level of the error voltage signal, a main control clock pulse is generated. In response to the generation of the main control clock pulse, the corresponding ramp signal that currently generates the main control clock pulse is reset, and the other ramp signals that have not triggered the main control clock pulse are allowed to ramp up according to a preset slope. Then, the process returns to the step of comparing the M ramp signals with the error voltage signal. When the level of any ramp signal reaches the level of the error voltage signal, a main control clock pulse is generated.

[0006] In one embodiment, M ramp signals are generated, including: A start-up trigger signal is issued based on the error voltage signal. The start-up trigger signal controls the on / off state of the reset switches of M parallel ramp generators, causing each ramp generator to simultaneously generate M ramp signals with different initial voltages and different initial slopes.

[0007] In one embodiment, M ramp generators are used to achieve frequency multiplication by N, where M = 2N-1; the slope of each ramp signal is determined based on the charging current of the corresponding ramp generator; the charging current of each ramp generator when the voltage of its respective ramp signal is 0 is determined based on the frequency multiplication factor N.

[0008] In one embodiment, the ramp signal includes a first ramp signal, a second ramp signal, and a third ramp signal; wherein the initial voltage of the first ramp signal and the third ramp signal is 0, the initial voltage of the second ramp signal is VCOMP / 2, where VCOMP is the voltage value of the error voltage signal; the initial slope of the first ramp signal is equal to the initial slope of the second ramp signal, and both are twice the initial slope of the third ramp signal.

[0009] In one embodiment, in response to the generation of a main control clock pulse, the ramp signal corresponding to the currently generated main control clock pulse is reset, and other ramp signals that have not triggered a main control clock pulse are allowed to voltage ramp up according to a preset slope, including: The first ramp signal is reset at the first moment when the corresponding main control clock pulse is generated, and the voltage is increased according to the preset ramp at other times except the first moment. The second ramp signal is kept in a reset state during the second moment when the corresponding main control clock pulse is generated, and during the first time period between the first moment and the second moment, which is the closest moment after the current second moment. The voltage is increased according to a preset ramp during the time other than the second moment and the first time period. The third ramp signal is kept in a reset state during the third moment when the corresponding main control clock pulse is generated, and during the second time period between the first moment and the third moment, which is the closest moment after the current third moment. The voltage is increased according to the preset ramp at times other than the second moment and the second time period.

[0010] Secondly, this application also proposes a frequency multiplication device based on multi-slope comparison, comprising: The error voltage output module is used to generate an error voltage signal based on the difference between the output voltage and the reference voltage. The main control clock pulse frequency multiplier output module is used to generate multiple ramp signals with different slopes and / or different starting values ​​in parallel within different time periods of the same cycle, and to generate multiple main control clock pulses within the same cycle based on the comparison between the error voltage signal and the multiple ramp signals; wherein, generating multiple main control clock pulses within the same cycle includes at least: readjusting the slope of each current ramp signal based on the currently generated main control clock pulse.

[0011] Thirdly, this application also proposes a frequency multiplication system based on multi-slope comparison, which implements the steps of any embodiment of the method in the first aspect above. The system includes multiple slope generation branches connected in parallel with an error amplifier, and each slope generation branch includes a slope generator and a PWM comparator connected to each other.

[0012] In one embodiment, the ramp generation branch further includes a trigger, the input of which is connected to the PWM comparator, and the output of which is connected to the control terminal of the ramp generator.

[0013] Fourthly, this application also proposes a controller, which includes the system of any one of the embodiments of the third aspect above.

[0014] According to the embodiments of this application, the frequency multiplication method, apparatus, and system based on multi-slope comparison generate an error voltage signal based on the difference between the output voltage and the reference voltage; generate multiple slope signals with different slopes and / or different starting values ​​in parallel within different time periods of the same cycle; and generate multiple main control clock pulses within the same cycle based on the comparison of the error voltage signal and the multiple slope signals; wherein, generating multiple main control clock pulses within the same cycle includes at least: readjusting the slope of each current slope signal based on the currently generated main control clock pulse, thereby generating multiple slope signals with different slopes in parallel and comparing them with the same control voltage, thereby generating multiple trigger signals within a single cycle, which can effectively increase the MCLK frequency without significantly increasing circuit complexity and power consumption, and achieve MCLK frequency multiplication.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present application. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 This is a flowchart illustrating the frequency multiplication method based on multi-slope comparison according to an embodiment of the present invention. Figure 2 This is an architecture diagram of a frequency multiplication system based on multi-slope comparison according to an embodiment of the present invention; Figure 3 This is a timing diagram of the MCLK generation scheme according to one embodiment of the present invention; Figure 4 This is a schematic diagram of an MCLK generation scheme according to another embodiment of the present invention; Figure 5 This is a schematic diagram of the internal structure of the frequency multiplication device based on multi-slope comparison according to an embodiment of the present invention. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0019] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0020] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0021] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0022] In multiphase voltage regulators, increasing the MCLK frequency is crucial for the system's transient response speed. Current multiphase controllers have up to 16 phases, with each phase having a steady-state frequency of 1MHz, resulting in an MCLK frequency of 16MHz. To achieve good transient performance, the highest frequency the MCLK needs to reach is 16MHz * 2.5 = 40MHz. If the highest frequency reaches 3MHz, the steady-state MCLK frequency would be 48MHz, requiring a maximum frequency of 120MHz. Future designs aim for a maximum frequency of 10MHz per phase, necessitating an MCLK frequency of 160MHz. However, traditional COT control methods generate the MCLK by comparing the voltage loop's triangular wave voltage with a ramp signal, a frequency limited by the ramp signal generation rate and comparator response speed. Increasing the MCLK frequency often requires a larger ramp charging current and a faster comparator. With a fixed manufacturing process, this increases circuit power consumption and design complexity, potentially introducing noise and stability issues. Therefore, effectively increasing the MCLK frequency without significantly increasing circuit complexity and power consumption has become a pressing technical challenge.

[0023] In existing technologies, several methods have been attempted to address the issue of increasing the MCLK frequency. One common approach is to increase the ramp signal rise rate by increasing the ramp charging current, thereby accelerating the comparator's trigger speed. However, this method leads to a significant increase in circuit power consumption, and the high current may cause electromagnetic interference (EMI) problems. Another approach is to use a faster comparator, but a faster comparator typically means higher power consumption or the use of a smaller process technology, which also implies a significant increase in cost. In summary, existing technologies have significant disadvantages in terms of power consumption and cost, making it difficult to meet customer needs. Specifically, due to process limitations, the RAMP rise rate, comparator delay time, and reset time Trst are restricted, thus limiting one complete cycle of MCLK (T0). MCLK The limit of MCLK is the maximum frequency that is restricted.

[0024] Based on this, this invention proposes a frequency multiplication method based on multi-slope comparison. By generating multiple slope signals with different slopes in parallel and comparing them with the same control voltage, multiple trigger signals are generated within a single cycle, thereby multiplying the MCLK frequency. This scheme employs multiple parallel slope generation branches (e.g., three branches: RAMP1, RAMP2, and RAMP3), each branch containing an independent slope generator and PWM comparator. The system achieves high-frequency response and automatic phase interleaving of the master clock (MCLK) through RS flip-flop logic and dynamic current source control.

[0025] In one exemplary embodiment, such as Figure 1As shown, a frequency multiplication method based on multi-slope comparison is provided, which is then applied to... Figure 2 The following explanation uses a frequency multiplication system based on multi-slope comparison as an example, including steps 302 to 304. Wherein: Step 302: Generate an error voltage signal based on the difference between the output voltage and the reference voltage.

[0026] Here, the output voltage refers to VOUT, the reference voltage refers to VREF, and the error voltage signal refers to VCOMP voltage.

[0027] For example, after the system is powered on, the error amplifier EA generates an initial VCOMP voltage based on the difference between VOUT and VREF, and sends out a main control clock pulse for startup, that is, to start MCLK1.

[0028] Step 304: In different time periods of the same cycle, multiple ramp signals with different slopes and / or different starting values ​​are generated in parallel, and multiple main control clock pulses are generated in the same cycle based on the comparison between the error voltage signal and the multiple ramp signals; wherein, generating multiple main control clock pulses in the same cycle includes at least: readjusting the slope of each ramp signal based on the currently generated main control clock pulse.

[0029] Optionally, a ramp generator (Ramp Generation), such as Ramp1 Generation, Ramp2 Generation, and Ramp3 Generation, connected in parallel with the error amplifier EA, generates multiple ramp signals (RAMPs) with different slopes and / or different starting values ​​in parallel via a parallel architecture. These RAMPs are named RAMP1, RAMP2, and RAMP3. A PWM comparator (e.g., PWM1 Comparator, PWM2 Comparator, and PWM3 Comparator) generates multiple master control clock pulses (MCLKs), such as MCLK1, MCLK2, and MCLK3, within the same cycle based on the comparison between the error voltage signal and the multiple ramp signals. The generation of multiple master control clock pulses within the same cycle includes at least: readjusting the slope of each ramp signal based on the currently generated master control clock pulse using current compensation.

[0030] Specifically, this application achieves higher latency tolerance for a single PWM comparator through parallel architecture and current compensation, enabling high-performance control without significantly increasing power consumption.

[0031] It is understood that this application generates an error voltage signal based on the difference between the output voltage and the reference voltage; generates multiple ramp signals (RAMP) with different slopes and / or different starting values ​​in parallel during different time periods of the same cycle; and generates multiple master control clock pulses (MCLK) in the same cycle based on the comparison of the error voltage signal and the multiple ramp signals. The generation of multiple master control clock pulses in the same cycle includes at least: readjusting the slope of each ramp signal based on the currently generated master control clock pulse, thereby generating multiple ramp signals with different slopes in parallel and comparing them with the same control voltage, thereby generating multiple trigger signals in a single cycle. This can effectively increase the MCLK frequency without significantly increasing circuit complexity and power consumption, achieving a doubling of the MCLK frequency.

[0032] In an exemplary embodiment, step 304 involves generating multiple ramp signals (RAMPs) with different slopes and / or different starting values ​​in parallel within different time periods of the same cycle, and generating multiple master control clock pulses (MCLKs) within the same cycle based on the comparison of the error voltage signal and the multiple ramp signals, including: Generate M ramp signals, where M is an integer greater than or equal to 3; the M ramp signals have different voltage change slopes and / or different initial voltage values; M ramp signals are compared with the error voltage signal. When the level of any ramp signal reaches the level of the error voltage signal, a main control clock pulse is generated. In response to the generation of the main control clock pulse, the corresponding ramp signal that currently generates the main control clock pulse is reset, and the other ramp signals that have not triggered the main control clock pulse are allowed to ramp up according to a preset slope. Then, the process returns to the step of comparing the M ramp signals with the error voltage signal. When the level of any ramp signal reaches the level of the error voltage signal, a main control clock pulse is generated.

[0033] Specifically, refer to Figure 2 and Figure 3Multiple parallel ramp generation branches simultaneously generate M ramp signals, where M is an integer greater than or equal to 3; the M ramp signals have different voltage change slopes and / or different initial voltage values; the M ramp signals are compared with an error voltage signal using a PWM comparator, and a main control clock pulse is generated when the level of any ramp signal reaches the level of the error voltage signal; in response to the generation of the main control clock pulse, the ramp signal corresponding to the current main control clock pulse is reset, and the other ramp signals that have not triggered the main control clock pulse are allowed to perform voltage ramping according to a preset slope, and the process returns to step: comparing the M ramp signals with the error voltage signal, and generating a main control clock pulse when the level of any ramp signal reaches the level of the error voltage signal.

[0034] Optionally, this application utilizes a multi-parallel architecture, where one path performs reset and comparison delays while another path uses a multiple current to accelerate charging in advance, i.e., voltage ramping according to a preset slope. This effectively masks the "reset dead zone" within the "charging time," significantly shortening the phase-to-phase interval and supporting higher system switching frequencies. Furthermore, this application also uses a large current for pre-charging in non-active phases and a standard current for precise timing in active phases. This mechanism ensures that even with extremely short on-times (Ton), the phases maintain a precise staggered distribution, avoiding phase collisions or overlaps.

[0035] In one exemplary embodiment, M ramp signals are generated, including: Based on the error voltage signal, a start trigger signal (MCLK1) is issued. Based on the start trigger signal, the reset switches (e.g., S11 / S21 / S22) of M parallel ramp generators are controlled to open and close, so that each ramp generator simultaneously generates M ramp signals with different initial voltages and different initial slopes.

[0036] In an exemplary embodiment, M ramp generators are used to achieve frequency multiplication by N, where M = 2N-1; the slope of each ramp signal is determined based on the charging current of the corresponding ramp generator; the charging current of each ramp generator when the voltage of its respective ramp signal is 0 is determined based on the frequency multiplication factor N.

[0037] For example, in addition to achieving a frequency multiplication of 2x, this application can also obtain frequency multiplication schemes of 3x, 4x, and Nx using a similar method. In the Nx frequency multiplication scheme, the number of ramp generators and PWM comparators required is 2N-1 each. The charging currents of RAMP1, RAMP2, RAMP3...Ramp(n-1), and RAMPn in the first stage are respectively... , , … , The charging current in the second stage is uniformly set as follows: .

[0038] Optionally, for the MCLK frequency multiplication scheme, substituting N into the above formula, we can obtain that in the frequency multiplication scheme, the number of ramp generators and PWM comparators required is 5 each. The charging currents of RAMP1, RAMP2, RAMP3, RAMP4, and RAMP5 in the first stage are respectively: (2 / 3) (1 / 3) (2 / 3) (1 / 3) The charging current in one stage refers to the initial charging current when the voltage is 0. The timing diagram is as follows: Figure 4 As shown.

[0039] In an exemplary embodiment, the ramp signal includes a first ramp signal RAMP1, a second ramp signal RAMP2, and a third ramp signal RAMP3; wherein the initial voltage of the first ramp signal and the third ramp signal is 0, the initial voltage of the second ramp signal is VCOMP / 2, where VCOMP is the voltage value of the error voltage signal; the initial slope of the first ramp signal is equal to the initial slope of the second ramp signal, and both are twice the initial slope of the third ramp signal.

[0040] For example, refer to Figure 2 and Figure 3 When this application is used to implement a frequency doubling scheme (2x frequency), its workflow includes: Initial state, generation of MCLK1 (t0): After the system powers on, the error amplifier generates the initial VCOMP voltage based on the difference between VOUT and VREF, and issues the start signal MCLK1. The generation of MCLK1 will cause S22A to go high through the D flip-flop, thus turning on S11 / S21 / S22 and turning off S31 / S32. The initial voltage of RAMP1 / RAMP3 is 0V, and the initial voltage of RAMP2 is VCOMP / 2.

[0041] MCLK2 Trigger (t0-t1): Reset switches S11 / S21 / S31 are open, C1 / C2 / C3 begin charging, and RAMP1 and RAMP3 signals rise linearly from zero, while Ramp2 rises linearly from VCOMP / 2. The charging current of C1 and C2 is I0, and the charging current of C3 is I0 / 2. Therefore, the rising slope of RAMP1 and RAMP2 is I0 / C1, and the rising slope of RAMP3 is I0 / 2C1 (C1=C2, so the rising slope of RAMP1 / RAMP2 is twice that of RAMP3). When the RAMP2 voltage exceeds VCOMP, the PWM2 comparator outputs a high level, generating MCLK2. Calculations show that the voltage values ​​of RAMP1 and RAMP3 at time t1 are VCOMP / 2 and VCOMP / 4, respectively.

[0042] In an exemplary embodiment, in response to the generation of a main control clock pulse, the ramp signal corresponding to the currently generated main control clock pulse is reset, and other ramp signals that have not triggered a main control clock pulse are allowed to voltage ramp up according to a preset slope, including: The first ramp signal is reset at the first moment when the corresponding main control clock pulse is generated, and the voltage is increased according to the preset ramp at other times except the first moment. The second ramp signal is kept in a reset state during the second moment when the corresponding main control clock pulse is generated, and during the first time period between the first moment and the second moment, which is the closest moment after the current second moment. The voltage is increased according to a preset ramp during the time other than the second moment and the first time period. The third ramp signal is kept in a reset state during the third moment when the corresponding main control clock pulse is generated, and during the second time period between the first moment and the third moment, which is the closest moment after the current third moment. The voltage is increased according to the preset ramp at times other than the second moment and the second time period.

[0043] Among them, reference Figure 3 The first time point includes t2 and t4, the second time point includes t1, and the third time point includes t3; the first time period includes t1 to t2, and the second time period includes t3 to t4.

[0044] For example, refer to Figure 2 and Figure 3 When this application is used to implement a frequency doubling scheme (2x frequency multiplication), its workflow further includes: MCLK1 trigger (t1-t2): The generation of MCLK2 will cause RS flip-flop 1 to set Rst2 high, turn on reset switch S21, and keep the RAMP2 voltage at 0V. RAMP1 and RAMP3 maintain a rising slope from t0 to t1. When the RAMP1 voltage exceeds VCOMP, the PWM1 comparator outputs a high level, generating MCLK1. MCLK1 will control reset switch S11 to reset the RAMP1 signal. The reset time of RAMP is Trst. Calculations show that at time t2, the voltage values ​​of RAMP2 and RAMP3 are 0V and VCOMP / 2, respectively.

[0045] MCLK3 Trigger (t2-t3): The generation of MCLK1 causes S32A to go high via the D flip-flop, and simultaneously causes Rst2 and Rst3 to go low via RS. Therefore, reset switches S11 / S21 / S31 open, C1 / C2 / C3 begin charging, and RAMP1 and RAMP2 signals rise linearly from zero, while Ramp3 rises linearly from VCAMP / 2. The charging current of C1 and C3 is I0, and the charging current of C2 is I0 / 2. Therefore, the rising slope of RAMP1 and RAMP3 is I0 / C1, and the rising slope of RAMP2 is I0 / 2C1. When the RAMP3 voltage exceeds VCOMP, the PWM3 comparator outputs a high level, generating MCLK3. Calculations show that at time t3, the voltage values ​​of RAMP1 and RAMP2 are VCOMP / 2 and VCOMP / 4, respectively. (The behavior from t2-t3 is similar to t0-t1, except that the behaviors of RAMP2 and RAMP3 are interchanged.) MCLK1 Re-trigger (t3-t4): The generation of MCLK3 will cause RS flip-flop 2 to set Rst3 high, turn on reset switch S31, and keep the RAMP3 voltage at 0V. RAMP1 and RAMP2 maintain the upward slope of t2-t3. When the RAMP1 voltage exceeds VCOMP, the PWM1 comparator outputs a high level, generating MCLK1. MCLK1 will control reset switch S11 to reset the RAMP1 signal. The reset time of RAMP1 is Trst. Calculations show that at time t2, the voltage values ​​of RAMP2 and RAMP3 are VCOMP / 2 and 0V, respectively. (The behavior of t3-t4 is similar to t1-t2, except that the behavior of RAMP2 and RAMP3 is interchanged.) Cyclic triggering: When the t4 state is consistent with the t0 state, a new cycle begins. This process repeats continuously. MCLKAllot distributes MCLK pulses in sequence (PWM1, PWM2, ..., PWM16) to ensure that the 16 phases are turned on sequentially and uniformly.

[0046] Therefore, in the scheme of this application embodiment, the period of MCLK is two complete cycles (T) of the master clock MCLK.MCLK It actually consists of three time components: Among them, T delay T is the comparator's comparison delay time. rst The reset time is determined by the on-resistance of switch S11 and capacitor C1. MCLK It is t0-t2. In this scheme, one MCLK1 cycle contains two MCLK cycles. One MCLK1 cycle (T MCLK It is actually composed of the three time components mentioned above.

[0047] It is understood that in the scheme of this application embodiment, the time component composition of two MCLK cycles is completely consistent with the time component composition of one MCLK cycle in the traditional scheme, but the extension from one cycle to two cycles is achieved. In other words, the embodiment of this application completes the doubling of MCLK frequency by using a PWM comparator and RAMP generator with the same performance.

[0048] Further, the embodiments of this application can achieve the following technical effects: Eliminating reset dead time and increasing maximum switching frequency: Utilizing a multi-parallel architecture, while one path performs reset and comparison delays, another path accelerates charging with double the current. This effectively masks the "reset dead time" within the "charging time," significantly shortening the phase-to-phase interval and supporting higher system switching frequencies.

[0049] Dynamic slope adjustment for compact interleaving: Dynamic adjustment of the ramp slope is achieved by introducing D flip-flops and current source switching switches (S22A / S32A). Inactive phases are pre-charged with a large current, while active phases are precisely timed using a standard current. This mechanism ensures that even with extremely short on-times (Ton), the phases maintain a precise interleaving distribution, avoiding phase collisions or overlaps.

[0050] Reducing the stringent requirements for comparator speed: In traditional high-frequency designs, extremely high-speed (high-power) comparators are typically required to minimize errors caused by Tdelay. The embodiments in this application, through parallel architecture and current compensation, offer higher tolerance for the delay of individual comparators, enabling high-performance control without significantly increasing power consumption.

[0051] In one exemplary embodiment, this application also proposes a frequency multiplication device 900 based on multi-slope comparison, comprising: Error voltage output module 901 is used to generate an error voltage signal based on the difference between the output voltage and the reference voltage; The main control clock pulse frequency multiplier output module 902 is used to generate multiple ramp signals (RAMP) with different slopes and / or different starting values ​​in parallel within different time periods of the same cycle, and to generate multiple main control clock pulses (MCLK) within the same cycle based on the comparison between the error voltage signal and the multiple ramp signals; wherein, generating multiple main control clock pulses within the same cycle includes at least: readjusting the slope of each ramp signal based on the currently generated main control clock pulse.

[0052] In one embodiment, the main control clock pulse frequency multiplier output module 902 is further configured to: Generate M ramp signals, where M is an integer greater than or equal to 3; the M ramp signals have different voltage change slopes and / or different initial voltage values; M ramp signals are compared with the error voltage signal. When the level of any ramp signal reaches the level of the error voltage signal, a main control clock pulse is generated. In response to the generation of the main control clock pulse, the corresponding ramp signal that currently generates the main control clock pulse is reset, and the other ramp signals that have not triggered the main control clock pulse are allowed to ramp up according to a preset slope. Then, the process returns to the step of comparing the M ramp signals with the error voltage signal. When the level of any ramp signal reaches the level of the error voltage signal, a main control clock pulse is generated.

[0053] In one embodiment, the main control clock pulse frequency multiplier output module 902 is further configured to: A start-up trigger signal is issued based on the error voltage signal. The start-up trigger signal controls the on / off state of the reset switches of M parallel ramp generators, causing each ramp generator to simultaneously generate M ramp signals with different initial voltages and different initial slopes.

[0054] In one embodiment, M ramp generators are used to achieve frequency multiplication by N, where M = 2N-1; the slope of each ramp signal is determined based on the charging current of the corresponding ramp generator; the charging current of each ramp generator when the voltage of its respective ramp signal is 0 is determined based on the frequency multiplication factor N.

[0055] In one embodiment, the ramp signal includes a first ramp signal, a second ramp signal, and a third ramp signal; wherein the initial voltage of the first ramp signal and the third ramp signal is 0, the initial voltage of the second ramp signal is VCOMP / 2, where VCOMP is the voltage value of the error voltage signal; the initial slope of the first ramp signal is equal to the initial slope of the second ramp signal, and both are twice the initial slope of the third ramp signal.

[0056] In one embodiment, the main control clock pulse frequency multiplier output module 902 is further configured to: The first ramp signal is reset at the first moment when the corresponding main control clock pulse is generated, and the voltage is increased according to the preset ramp at other times except the first moment. The second ramp signal is kept in a reset state during the second moment when the corresponding main control clock pulse is generated, and during the first time period between the first moment and the second moment, which is the closest moment after the current second moment. The voltage is increased according to a preset ramp during the time other than the second moment and the first time period. The third ramp signal is kept in a reset state during the third moment when the corresponding main control clock pulse is generated, and during the second time period between the first moment and the third moment, which is the closest moment after the current third moment. The voltage is increased according to the preset ramp at times other than the second moment and the second time period.

[0057] Each module in the aforementioned frequency multiplication device based on multi-slope comparison can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0058] In one exemplary embodiment, refer to Figure 2 This application also proposes a frequency multiplication system based on multi-slope comparison, which is used to implement the steps of any of the above-described methods. The system includes multiple slope generation branches connected in parallel with an error amplifier, and each slope generation branch includes a slope generator and a PWM comparator connected to each other.

[0059] In one embodiment, the ramp generation branch further includes a trigger, the input of which is connected to the PWM comparator, and the output of which is connected to the control terminal of the ramp generator.

[0060] In one exemplary embodiment, this application also proposes a controller that includes the above-described frequency multiplication system based on multi-slope comparison.

[0061] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0062] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

Claims

1. A frequency multiplication method based on multi-slope comparison, characterized in that, include: An error voltage signal is generated based on the difference between the output voltage and the reference voltage; In different time periods of the same cycle, multiple ramp signals with different slopes and / or different starting values ​​are generated in parallel, and multiple master control clock pulses are generated in the same cycle based on the comparison between the error voltage signal and the multiple ramp signals; wherein, generating multiple master control clock pulses in the same cycle includes at least: readjusting the slope of each of the current ramp signals based on the currently generated master control clock pulse.

2. The method according to claim 1, characterized in that, The method involves generating multiple ramp signals with different slopes and / or different initial values ​​in parallel within different time periods of the same cycle, and generating multiple main control clock pulses within the same cycle based on the comparison between the error voltage signal and the multiple ramp signals, including: M ramp signals are generated, where M is an integer greater than or equal to 3; the M ramp signals have different voltage change slopes and / or different initial voltage values; The M ramp signals are compared with the error voltage signal. When the level of any ramp signal reaches the level of the error voltage signal, a main control clock pulse is generated. In response to the generation of the main control clock pulse, the ramp signal corresponding to the current generation of the main control clock pulse is reset, and the other ramp signals that have not triggered the main control clock pulse are allowed to rise in voltage according to a preset slope, and the process returns to the step: comparing the M ramp signals with the error voltage signal, and generating a main control clock pulse when the level of any ramp signal reaches the level of the error voltage signal.

3. The method according to claim 2, characterized in that, The generation of M ramp signals includes: Based on the error voltage signal, a start trigger signal is issued, and based on the start trigger signal, the reset switches of M parallel ramp generators are controlled to open and close, so that each ramp generator simultaneously generates the M ramp signals with different initial voltages and different initial slopes.

4. The method according to claim 3, characterized in that, M ramp generators are used to achieve frequency multiplication by N, where M = 2N-1; the slope of each ramp signal is determined based on the charging current of the corresponding ramp generator; the charging current of each ramp generator when the voltage of its respective ramp signal is 0 is determined based on the frequency multiplication factor N.

5. The method according to claim 3, characterized in that, The ramp signal includes a first ramp signal, a second ramp signal, and a third ramp signal; wherein the initial voltage of the first ramp signal and the third ramp signal is 0, the initial voltage of the second ramp signal is VCOMP / 2, and VCOMP is the voltage value of the error voltage signal; the initial slope of the first ramp signal is equal to the initial slope of the second ramp signal, and both are twice the initial slope of the third ramp signal.

6. The method according to claim 5, characterized in that, The response to the generation of the main control clock pulse includes resetting the ramp signal corresponding to the current generation of the main control clock pulse, and causing other ramp signals that have not triggered the main control clock pulse to perform voltage ramp-up according to a preset slope, including: The first ramp signal is reset at the first moment when the corresponding main control clock pulse is generated, and the voltage is ramped up at times other than the first moment according to a preset slope. The second ramp signal is kept in a reset state during the second moment when the corresponding main control clock pulse is generated, and during the first time period between the first moment most recent after the current second moment and the second moment, and the voltage is ramped up according to a preset slope during the time other than the second moment and the first time period. The third ramp signal is kept in a reset state during the third moment when the corresponding main control clock pulse is generated, and during the second time period between the first moment most recent after the current third moment and the third moment. The voltage is ramped up according to a preset slope during the time other than the second moment and the second time period.

7. A frequency multiplier based on multi-slope comparison, characterized in that, include: The error voltage output module is used to generate an error voltage signal based on the difference between the output voltage and the reference voltage. The main control clock pulse frequency multiplier output module is used to generate multiple ramp signals with different slopes and / or different starting values ​​in parallel within different time periods of the same cycle, and to generate multiple main control clock pulses within the same cycle based on the comparison between the error voltage signal and the multiple ramp signals; wherein, generating multiple main control clock pulses within the same cycle includes at least: readjusting the slope of each of the current ramp signals based on the currently generated main control clock pulse.

8. A frequency multiplication system based on multi-slope comparison, characterized in that, The system is used to implement the method according to any one of claims 1 to 6, the system comprising a plurality of ramp generation branches connected in parallel with an error amplifier, each of the ramp generation branches comprising a ramp generator and a PWM comparator connected to each other.

9. The system according to claim 8, characterized in that, The ramp generation branch also includes a trigger, the input of which is connected to the PWM comparator, and the output of which is connected to the control terminal of the ramp generator.

10. A controller, characterized in that, The controller includes the system according to any one of claims 8 to 9.

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