An igbt drive pulse generating circuit

Abstract

The application discloses an IGBT driving pulse generation circuit, and relates to the technical field of power electronics and motor control.The circuit comprises an oscillation signal generation unit, a delay control unit, a first logic unit, a second logic unit, a third logic unit, a fourth logic unit and a power supply.When a fault signal is an invalid level, the output end of the delay control unit is a high level, the fourth logic unit directly transmits a pulse signal to the third logic unit, and the fourth logic unit outputs a pulse waveform same as the pulse signal to control the normal on-off of an IGBT.When the fault signal is a valid level, the fourth logic unit shields the pulse signal, the oscillation signal generation unit generates a high-frequency switching signal, the high-frequency switching signal is output to the IGBT driving circuit through the first, second and third logic units, and the IGBT driving circuit works in a linear region until the voltage of the output end of the delay control unit is lower than a preset threshold value, and the third logic unit outputs a constant IGBT off level.The application improves the reliability and stability of the driving pulse generation circuit.

Description

Technical Field

[0001] This application relates to the fields of power electronics and motor control technology, and in particular to an IGBT drive pulse generation circuit. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs), with their excellent conduction and switching characteristics, have been widely used in power electronics, industrial automation, new energy power generation, and rail transportation. In IGBT application systems, the design of the drive circuit is crucial; its core function is to amplify the control signal to ensure the safe and reliable turn-on and turn-off of the IGBT. With the increasing demands for safety and reliability in industrial systems, turn-off protection under fault conditions has become one of the key research directions in IGBT drive circuit design.

[0003] Currently, traditional IGBT drive circuits mostly employ a hard shutdown strategy for fault protection, which involves rapidly disconnecting the IGBT. However, this approach has inherent drawbacks: especially in the event of severe faults such as short circuits, rapid shutdown can induce high peak voltages on the stray inductance of the line, which may not only damage the IGBT itself but also compromise the system insulation and even jeopardize the safe operation of the entire device.

[0004] Therefore, it is necessary to provide an IGBT drive pulse generation circuit to solve the above problems. Summary of the Invention

[0005] The purpose of this application is to provide an IGBT drive pulse generation circuit to overcome the defects of IGBT damage and system safety caused by peak voltage generated by hard turn-off, and to improve the reliability and stability of the drive pulse generation circuit.

[0006] To achieve the above objectives, this application provides the following solution: This application provides an IGBT drive pulse generation circuit, which includes: an oscillation signal generation unit, a delay control unit, a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, and a power supply. The power supply terminal of the oscillation signal generating unit is connected to the power supply, the output terminal of the oscillation signal generating unit is connected to the first input terminal of the first logic unit, the input terminal of the delay control unit is connected to the power supply, the output terminal of the delay control unit is connected to the second input terminal of the first logic unit, the control terminal of the delay control unit is connected to the fault signal input terminal, the output terminal of the first logic unit is connected to the first input terminal of the second logic unit, the second input terminal of the second logic unit is connected to the fault signal input terminal, the output terminal of the second logic unit is connected to the first input terminal of the third logic unit, the second input terminal of the third logic unit is connected to the output terminal of the fourth logic unit, the output terminal of the third logic unit is connected to the external IGBT drive circuit, the first input terminal of the fourth logic unit is connected to the fault signal input terminal, and the second input terminal of the fourth logic unit is connected to the pulse signal input terminal. When the fault signal is invalid, the delay control unit is in the charging hold state, the output of the delay control unit is high, the first logic unit is turned on, the fourth logic unit directly passes the pulse signal received by the pulse signal input terminal to the third logic unit, and the third logic unit outputs the same pulse waveform as the pulse signal to control the IGBT to turn on and off normally. When the fault signal is at an effective level, the delay control unit starts to discharge. The fourth logic unit shields the pulse signal received at the pulse signal input terminal. The high-frequency switching signal generated by the oscillation signal generation unit is output to the external IGBT drive circuit through the first logic unit, the second logic unit, and the third logic unit in sequence, driving the IGBT to work in the linear region. After the output voltage of the delay control unit is lower than the preset threshold, the third logic unit outputs a constant IGBT turn-off level to control the IGBT to be completely turned off.

[0007] In one embodiment, the oscillation signal generating unit is a crystal oscillator; The positive terminal of the crystal oscillator is connected to the positive terminal of the power supply, the negative terminal of the crystal oscillator is grounded, and the output terminal of the crystal oscillator is connected to the first input terminal of the first logic unit.

[0008] In one embodiment, the delay control unit includes a first resistor, a second resistor, a capacitor, and a diode; The input terminal of the delay control unit is the first terminal of the second resistor, the output terminal of the delay control unit is the first node, and the control terminal of the delay control unit is the cathode of the diode. The first end of the second resistor is connected to the positive terminal of the power supply and the positive terminal of the crystal oscillator, respectively, and the second end of the second resistor is connected to the first node; the first end of the capacitor is connected to the first node, and the second end of the capacitor is grounded; the first end of the first resistor is connected to the first node, and the second end of the first resistor is connected to the anode of the diode, and the cathode of the diode is connected to the fault signal input terminal.

[0009] In one embodiment, the first logic unit is an AND gate logic circuit; The first input terminal of the first logic unit is the first input terminal of the AND gate logic circuit, the second input terminal of the first logic unit is the second input terminal of the AND gate logic circuit, and the output terminal of the first logic unit is the output terminal of the AND gate logic circuit. The first input terminal of the AND gate logic circuit is connected to the output terminal of the crystal oscillator, the second input terminal of the AND gate logic circuit is connected to the first node, and the output terminal of the AND gate logic circuit is connected to the first input terminal of the second logic unit.

[0010] In one embodiment, the second logic unit is an OR gate logic circuit; The first input terminal of the second logic unit is the first input terminal of the OR gate logic circuit, the second input terminal of the second logic unit is the second input terminal of the OR gate logic circuit, and the output terminal of the second logic unit is the output terminal of the OR gate logic circuit. The first input terminal of the OR gate logic circuit is connected to the output terminal of the first logic unit, and the second input terminal of the OR gate logic circuit is connected to the fault signal input terminal. The output terminal of the OR gate logic circuit is connected to the first input terminal of the third logic unit.

[0011] In one embodiment, the third logic unit is a first NAND gate logic circuit; The first input terminal of the third logic unit is the first input terminal of the first NAND gate logic circuit, the second input terminal of the third logic unit is the second input terminal of the first NAND gate logic circuit, and the output terminal of the third logic unit is the output terminal of the first NAND gate logic circuit. The first input terminal of the first NAND gate logic circuit is connected to the output terminal of the second logic unit, the second input terminal of the first NAND gate logic circuit is connected to the output terminal of the fourth logic unit, and the output terminal of the first NAND gate logic circuit is connected to the external IGBT driver circuit.

[0012] In one embodiment, the fourth logic unit is a second NAND gate logic circuit; The first input terminal of the fourth logic unit is the first input terminal of the second NAND gate logic circuit, the second input terminal of the fourth logic unit is the second input terminal of the second NAND gate logic circuit, and the output terminal of the fourth logic unit is the output terminal of the second NAND gate logic circuit. The first input terminal of the second NAND gate logic circuit is connected to the fault signal input terminal, the second input terminal of the second NAND gate logic circuit is connected to the pulse signal input terminal, and the output terminal of the second NAND gate logic circuit is connected to the second input terminal of the third logic unit.

[0013] In one embodiment, the preset threshold is 0.7V.

[0014] In one embodiment, the pulse signal is a PWM pulse signal.

[0015] In one implementation, when the fault signal is high, the fault signal is invalid. When the fault signal is low, the fault signal is active.

[0016] According to the specific embodiments provided in this application, this application has the following technical effects: This application discloses an IGBT drive pulse generation circuit. By setting an oscillation signal generation unit in the circuit to provide a high-frequency switching signal, setting a delay control unit to control the soft turn-off duration, and setting multiple logic units to realize normal / fault mode switching and signal path selection, an automatic timing control of "normal conduction - fault soft turn-off - complete turn-off" is constructed. When a fault occurs, the IGBT is driven to work in the linear region to slowly release stray inductance energy. After the energy is released, the IGBT is completely turned off, thereby avoiding the spike voltage generated by hard turn-off and solving the technical problems of damaging the IGBT, destroying insulation, and endangering system safety. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of an IGBT drive pulse generation circuit structure provided in an embodiment of this application; Figure 2 A schematic diagram of the working process of an IGBT drive pulse generation circuit in an embodiment of this application during normal operation; Figure 3 This is a schematic diagram of the working process of the IGBT drive pulse generation circuit provided in an embodiment of this application during the fault soft shutdown state.

[0019] Figure label: Oscillation signal generation unit 1, delay control unit 2, first logic unit 3, second logic unit 4, third logic unit 5, fourth logic unit 6, power supply E, crystal oscillator Q1, first resistor R1, second resistor R2, capacitor C1, diode D1, AND gate logic circuit Q2, OR gate logic circuit Q3, first NAND gate logic circuit Q4, and second NAND gate logic circuit Q5. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] In one exemplary embodiment, such as Figure 1 As shown, an IGBT drive pulse generation circuit is provided, including: an oscillation signal generation unit 1, a delay control unit 2, a first logic unit 3, a second logic unit 4, a third logic unit 5, a fourth logic unit 6, and a power supply E.

[0023] The power supply terminal of the oscillation signal generating unit 1 is connected to the power supply E. The output terminal of the oscillation signal generating unit 1 is connected to the first input terminal of the first logic unit 3. The input terminal of the delay control unit 2 is connected to the power supply E. The output terminal of the delay control unit 2 is connected to the second input terminal of the first logic unit 3. The control terminal of the delay control unit 2 is connected to the fault signal input terminal. The output terminal of the first logic unit 3 is connected to the first input terminal of the second logic unit 4. The second input terminal of the second logic unit 4 is connected to the fault signal input terminal. The output terminal of the second logic unit 4 is connected to the first input terminal of the third logic unit 5. The second input terminal of the third logic unit 5 is connected to the output terminal of the fourth logic unit 6. The output terminal of the third logic unit 5 is connected to the external IGBT drive circuit. The first input terminal of the fourth logic unit 6 is connected to the fault signal input terminal. The second input terminal of the fourth logic unit 6 is connected to the pulse signal input terminal.

[0024] When the fault signal is invalid, the delay control unit 2 is in the charging hold state, the output of the delay control unit 2 is high, the first logic unit 3 is turned on, the fourth logic unit 6 directly transmits the pulse signal received at the pulse signal input terminal to the third logic unit 5, and the third logic unit 5 outputs the same pulse waveform as the pulse signal to control the IGBT to turn on and off normally.

[0025] When the fault signal is at an effective level, the delay control unit 2 starts to discharge. The fourth logic unit 6 shields the pulse signal received at the pulse signal input terminal. The high-frequency switching signal generated by the oscillation signal generation unit 1 is sequentially output to the external IGBT drive circuit through the first logic unit 3, the second logic unit 4 and the third logic unit 5 to drive the IGBT to work in the linear region. After the output voltage of the delay control unit 2 is lower than the preset threshold, the third logic unit 5 outputs a constant IGBT turn-off level to control the IGBT to be completely turned off.

[0026] An automatic timing control mechanism of "normal conduction - soft shutdown - complete shutdown" is constructed by setting up an oscillation signal generation unit 1, a delay control unit 2, and multiple logic units in the circuit. During normal operation, the delay control unit 2 remains in a charging state, and the pulse signal is directly supplied to the IGBT drive circuit. The IGBT turns on and off normally according to the PWM signal. When a fault occurs, the delay control unit 2 begins to discharge, and simultaneously, the fourth logic unit 6 shields the normal pulse signal, allowing the high-frequency switching signal generated by the oscillation signal generation unit 1 to be output to the IGBT drive circuit through the first, second, and third logic units 5. This drives the IGBT to repeatedly turn on and off at high frequency in the linear region, gradually releasing the energy in the stray inductance and avoiding instantaneous energy release that could cause voltage spikes. When the delay control unit 2 discharges below a preset threshold, the third logic unit 5 outputs a constant shutdown level, and the IGBT is completely turned off. This pure logic device achieves timing control, solving the technical problem of voltage spikes caused by hard shutdown in a low-cost and highly reliable manner, and improving the safety of the drive circuit under fault conditions.

[0027] As an optional implementation method, such as Figure 1 As shown, the oscillation signal generation unit 1 is a crystal oscillator Q1.

[0028] The positive terminal of crystal oscillator Q1 is connected to the positive terminal of the power supply E, the negative terminal of crystal oscillator Q1 is grounded, and the output terminal of crystal oscillator Q1 is connected to the first input terminal of the first logic unit 3.

[0029] As an optional implementation method, such as Figure 1 As shown, the delay control unit 2 includes: a first resistor R1, a second resistor R2, a capacitor C1, and a diode D1.

[0030] The input terminal of the delay control unit 2 is the first terminal of the second resistor R2, the output terminal of the delay control unit 2 is the first node, and the control terminal of the delay control unit 2 is the cathode of the diode D1.

[0031] The first end of the second resistor R2 is connected to the positive terminal of the power supply E and the positive terminal of the crystal oscillator Q1, respectively. The second end of the second resistor R2 is connected to the first node. The first end of the capacitor C1 is connected to the first node, and the second end of the capacitor C1 is grounded. The first end of the first resistor R1 is connected to the first node, and the second end of the first resistor R1 is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the fault signal input terminal.

[0032] As an optional implementation method, such as Figure 1 As shown, the first logic unit 3 is an AND gate logic circuit Q2.

[0033] The first input terminal of the first logic unit 3 is the first input terminal of the AND gate logic circuit Q2, the second input terminal of the first logic unit 3 is the second input terminal of the AND gate logic circuit Q2, and the output terminal of the first logic unit 3 is the output terminal of the AND gate logic circuit Q2.

[0034] The first input terminal of the AND gate logic circuit Q2 is connected to the output terminal of the crystal oscillator Q1, the second input terminal of the AND gate logic circuit Q2 is connected to the first node, and the output terminal of the AND gate logic circuit Q2 is connected to the first input terminal of the second logic unit 4.

[0035] As an optional implementation method, such as Figure 1 As shown, the second logic unit 4 is an OR gate logic circuit Q3.

[0036] The first input terminal of the second logic unit 4 is the first input terminal of the OR gate logic circuit Q3, the second input terminal of the second logic unit 4 is the second input terminal of the OR gate logic circuit Q3, and the output terminal of the second logic unit 4 is the output terminal of the OR gate logic circuit Q3.

[0037] The first input terminal of the OR gate logic circuit Q3 is connected to the output terminal of the first logic unit 3, the second input terminal of the OR gate logic circuit Q3 is connected to the fault signal input terminal, and the output terminal of the OR gate logic circuit Q3 is connected to the first input terminal of the third logic unit 5.

[0038] As an optional implementation method, such as Figure 1 As shown, the third logic unit 5 is the first NAND gate logic circuit Q4.

[0039] The first input terminal of the third logic unit 5 is the first input terminal of the first NAND gate logic circuit Q4, the second input terminal of the third logic unit 5 is the second input terminal of the first NAND gate logic circuit Q4, and the output terminal of the third logic unit 5 is the output terminal of the first NAND gate logic circuit Q4.

[0040] The first input terminal of the first NAND gate logic circuit Q4 is connected to the output terminal of the second logic unit 4, the second input terminal of the first NAND gate logic circuit Q4 is connected to the output terminal of the fourth logic unit 6, and the output terminal of the first NAND gate logic circuit Q4 is connected to the external IGBT driver circuit.

[0041] As an optional implementation method, such as Figure 1 As shown, the fourth logic unit 6 is the second NAND gate logic circuit Q5.

[0042] The first input terminal of the fourth logic unit 6 is the first input terminal of the second NAND gate logic circuit Q5, the second input terminal of the fourth logic unit 6 is the second input terminal of the second NAND gate logic circuit Q5, and the output terminal of the fourth logic unit 6 is the output terminal of the second NAND gate logic circuit Q5.

[0043] The first input terminal of the second NAND gate logic circuit Q5 is connected to the fault signal input terminal, the second input terminal of the second NAND gate logic circuit Q5 is connected to the pulse signal input terminal, and the output terminal of the second NAND gate logic circuit Q5 is connected to the second input terminal of the third logic unit 5.

[0044] As an optional implementation, the preset threshold is 0.7V.

[0045] As an optional implementation, the pulse signal is a pulse width modulation (PWM) pulse signal.

[0046] As an optional implementation, when the fault signal is high, the fault signal is invalid. When the fault signal is low, the fault signal is active.

[0047] Specifically, the corresponding working principle is as follows: The central signal processing unit sends an input pulse signal (i.e., a PWM pulse signal), which, after passing through the first NAND gate logic circuit Q4 and the second NAND gate logic circuit Q5, outputs a pulse signal that is applied to the IGBT driver circuit to control the IGBT's turn-on and turn-off. Wherein: 1) such as Figure 2 As shown, when the fault signal from the central signal processing unit is high, it indicates that no fault has occurred. The crystal oscillator waveform is not added to the drive pulse signal, and the input pulse signal is directly given to the output pulse signal. The IGBT drive circuit normally controls the on / off state of the IGBT. The specific principle is as follows: The output signal of Q5 is determined solely by the input pulse signal. Diode D1 is reverse-biased and cut off. The power supply E charges capacitor C1 through the second resistor R2, causing the voltage of capacitor C1 to rise and stabilize at a high level. Due to the high voltage of capacitor C1, the AND gate Q2 outputs a high level, therefore the inputs of the OR gate Q3 are all high, resulting in a high output for Q3. At this point, the output of the first NAND gate Q4 is determined by the output signal of Q5, meaning it is uniquely determined by the input pulse signal (the inputs to the first NAND gate Q4 are the input pulse signal and the high level of the OR gate Q3, therefore the output of the first NAND gate Q4 is directly equal to the input pulse signal). The input pulse signal passes sequentially through the second NAND gate Q5 and the first NAND gate Q4 before being applied to the IGBT drive circuit, and the final output signal has the same logic level as the input signal: when the input pulse signal is high, the IGBT is off; when the input pulse signal is low, the IGBT is on. Therefore, the IGBT operates normally when there is no fault.

[0048] 2) such as Figure 3 As shown, when the central signal processing unit sends a low-level fault signal, it indicates that a fault has occurred. At this time, diode D1 is forward-biased, and the current from the power supply E and capacitor C1 will flow through diode D1. Capacitor C1 discharges through the first resistor R1 and diode D1, causing the voltage across capacitor C1 to gradually decrease. At the same time, the output signal of the second NAND gate logic circuit Q5 is constantly high, so that the output signal is no longer affected by the input pulse signal. At this time, the output signal of the first NAND gate logic circuit Q4 is determined by and only by the OR gate logic circuit Q3.

[0049] When the voltage across capacitor C1 exceeds a preset threshold of 0.7V, the output signal of AND gate circuit Q2 is the crystal waveform output by crystal oscillator Q1. Since the fault signal is low, the output of OR gate circuit Q3 is also a crystal waveform. At this time, one input signal of the first NAND gate circuit Q4 is the high-level signal output by the second NAND gate circuit Q5, and the other input signal is the crystal waveform output by OR gate circuit Q3. The output of the first NAND gate circuit Q4 is determined by both. At this time, the waveform of crystal oscillator Q1 is used to drive the IGBT to repeatedly turn on and off at high frequency, so that the IGBT works in the linear region, slowly releasing the energy in the stray parasitic inductance in the power circuit and avoiding voltage spikes in the line. Finally, the crystal waveform generated by crystal oscillator Q1 passes through AND gate circuit Q2, OR gate circuit Q3, and first NAND gate circuit Q4 in sequence, and is applied to the IGBT drive circuit to control the IGBT to work in the linear region and achieve soft turn-off.

[0050] As capacitor C1 continues to discharge until the voltage across C1 falls below a preset threshold of 0.7V, the output signal of AND gate Q2 is low, and the output of OR gate Q3 is also low. Therefore, the output of the first NAND gate Q4 remains high, and the IGBT is completely turned off. Thus, the circuit described above can automatically add a crystal-type waveform to the drive pulse, achieving soft turn-off of the IGBT under fault conditions.

[0051] Beneficial effects: 1) This application replaces the hard shutdown signal in traditional fault protection with a high-frequency switching signal generated by an oscillation signal generation unit. When a circuit fault occurs, the high-frequency switching signal is output to the IGBT drive circuit through each logic unit, driving the IGBT to operate in the linear region, gradually releasing the energy stored in the stray inductance of the line, avoiding the spike voltage generated by instantaneous energy release, thereby preventing IGBT damage and system insulation failure, and significantly improving the safety and reliability of the system under fault conditions.

[0052] 2) This application precisely controls the duration of the soft-shutdown drive pulse through a delay control unit (an RC discharge circuit composed of resistors, capacitors, and diodes). When a fault occurs, the capacitor discharges through the resistors and diodes. While the output voltage is above a preset threshold, a high-frequency switching signal is output to achieve soft shutdown. Once the voltage falls below the preset threshold, it automatically switches to a constant shutdown level for complete shutdown. The entire timing control requires no software intervention, resulting in rapid response and further enhancing the reliability and stability of the drive circuit.

[0053] 3) The driving pulse generation circuit proposed in this application consists only of resistors, capacitors, diodes, crystal oscillators and logic gates. It does not require the participation of microprocessors, digital signal processors or software. It has the outstanding advantages of fewer components, low cost, low power consumption and small size. It is also easy to combine or modify with existing IGBT driving pulse generation circuits and has good engineering application prospects.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the circuit and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. In summary, the content of this specification should not be construed as a limitation of this application.

Claims

1. An IGBT drive pulse generation circuit, characterized in that, The IGBT drive pulse generation circuit includes: an oscillation signal generation unit, a delay control unit, a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, and a power supply. The power supply terminal of the oscillation signal generating unit is connected to the power supply, the output terminal of the oscillation signal generating unit is connected to the first input terminal of the first logic unit, the input terminal of the delay control unit is connected to the power supply, the output terminal of the delay control unit is connected to the second input terminal of the first logic unit, the control terminal of the delay control unit is connected to the fault signal input terminal, the output terminal of the first logic unit is connected to the first input terminal of the second logic unit, the second input terminal of the second logic unit is connected to the fault signal input terminal, the output terminal of the second logic unit is connected to the first input terminal of the third logic unit, the second input terminal of the third logic unit is connected to the output terminal of the fourth logic unit, the output terminal of the third logic unit is connected to the external IGBT drive circuit, the first input terminal of the fourth logic unit is connected to the fault signal input terminal, and the second input terminal of the fourth logic unit is connected to the pulse signal input terminal. When the fault signal is invalid, the delay control unit is in the charging hold state, the output of the delay control unit is high, the first logic unit is turned on, the fourth logic unit directly passes the pulse signal received by the pulse signal input terminal to the third logic unit, and the third logic unit outputs the same pulse waveform as the pulse signal to control the IGBT to turn on and off normally. When the fault signal is at an effective level, the delay control unit starts to discharge. The fourth logic unit shields the pulse signal received at the pulse signal input terminal. The high-frequency switching signal generated by the oscillation signal generation unit is output to the external IGBT drive circuit through the first logic unit, the second logic unit, and the third logic unit in sequence, driving the IGBT to work in the linear region. After the output voltage of the delay control unit is lower than the preset threshold, the third logic unit outputs a constant IGBT turn-off level to control the IGBT to be completely turned off.

2. The IGBT drive pulse generation circuit according to claim 1, characterized in that, The oscillation signal generation unit is a crystal oscillator; The positive terminal of the crystal oscillator is connected to the positive terminal of the power supply, the negative terminal of the crystal oscillator is grounded, and the output terminal of the crystal oscillator is connected to the first input terminal of the first logic unit.

3. The IGBT drive pulse generation circuit according to claim 2, characterized in that, The delay control unit includes a first resistor, a second resistor, a capacitor, and a diode; The input terminal of the delay control unit is the first terminal of the second resistor, the output terminal of the delay control unit is the first node, and the control terminal of the delay control unit is the cathode of the diode. The first end of the second resistor is connected to the positive terminal of the power supply and the positive terminal of the crystal oscillator, respectively, and the second end of the second resistor is connected to the first node; the first end of the capacitor is connected to the first node, and the second end of the capacitor is grounded; the first end of the first resistor is connected to the first node, and the second end of the first resistor is connected to the anode of the diode, and the cathode of the diode is connected to the fault signal input terminal.

4. The IGBT drive pulse generation circuit according to claim 3, characterized in that, The first logic unit is an AND gate logic circuit; The first input terminal of the first logic unit is the first input terminal of the AND gate logic circuit, the second input terminal of the first logic unit is the second input terminal of the AND gate logic circuit, and the output terminal of the first logic unit is the output terminal of the AND gate logic circuit. The first input terminal of the AND gate logic circuit is connected to the output terminal of the crystal oscillator, the second input terminal of the AND gate logic circuit is connected to the first node, and the output terminal of the AND gate logic circuit is connected to the first input terminal of the second logic unit.

5. The IGBT drive pulse generation circuit according to claim 4, characterized in that, The second logic unit is an OR gate logic circuit; The first input terminal of the second logic unit is the first input terminal of the OR gate logic circuit, the second input terminal of the second logic unit is the second input terminal of the OR gate logic circuit, and the output terminal of the second logic unit is the output terminal of the OR gate logic circuit. The first input terminal of the OR gate logic circuit is connected to the output terminal of the first logic unit, and the second input terminal of the OR gate logic circuit is connected to the fault signal input terminal. The output terminal of the OR gate logic circuit is connected to the first input terminal of the third logic unit.

6. The IGBT drive pulse generation circuit according to claim 5, characterized in that, The third logic unit is a first NAND gate logic circuit; The first input terminal of the third logic unit is the first input terminal of the first NAND gate logic circuit, the second input terminal of the third logic unit is the second input terminal of the first NAND gate logic circuit, and the output terminal of the third logic unit is the output terminal of the first NAND gate logic circuit. The first input terminal of the first NAND gate logic circuit is connected to the output terminal of the second logic unit, the second input terminal of the first NAND gate logic circuit is connected to the output terminal of the fourth logic unit, and the output terminal of the first NAND gate logic circuit is connected to the external IGBT driver circuit.

7. The IGBT drive pulse generation circuit according to claim 6, characterized in that, The fourth logic unit is the second NAND gate logic circuit; The first input terminal of the fourth logic unit is the first input terminal of the second NAND gate logic circuit, the second input terminal of the fourth logic unit is the second input terminal of the second NAND gate logic circuit, and the output terminal of the fourth logic unit is the output terminal of the second NAND gate logic circuit. The first input terminal of the second NAND gate logic circuit is connected to the fault signal input terminal, the second input terminal of the second NAND gate logic circuit is connected to the pulse signal input terminal, and the output terminal of the second NAND gate logic circuit is connected to the second input terminal of the third logic unit.

8. The IGBT drive pulse generation circuit according to claim 1, characterized in that, The preset threshold is 0.7V.

9. The IGBT drive pulse generation circuit according to claim 1, characterized in that, The pulse signal is a PWM pulse signal.

10. The IGBT drive pulse generation circuit according to claim 1, characterized in that, When the fault signal is high, the fault signal is invalid. When the fault signal is low, the fault signal is active.

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