Tri-state output driver

Abstract

The application provides a tri-state output driving device, which comprises a latch protection circuit and a tri-state output driving circuit; a first input end of the latch protection circuit is connected with an output end of the tri-state output driving circuit, a second input end of the latch protection circuit is connected with a power supply, a first output end of the latch protection circuit is connected with a first input end of the tri-state output driving circuit, a second output end of the latch protection circuit is connected with a second input end of the tri-state output driving circuit, and a third output end of the latch protection circuit is connected with a third input end of the tri-state output driving circuit. The circuit can be prevented from being latched due to power failure or voltage change of an output port, and the tri-state output driving circuit can still output a high resistance state signal after power failure, so that the protection circuit is not damaged.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a three-state output driving device. Background Technology

[0002] A three-state output driver circuit is a commonly used circuit that can process and convert signals by controlling the output state.

[0003] The output stage of a traditional three-state output driver circuit consists of an output P-channel metal-oxide-semiconductor field-effect transistor (PMOS) and an output N-channel metal-oxide-semiconductor field-effect transistor (NMOS). The source and substrate of the PMOS transistor are connected to the power supply, and the drain is connected to the output terminal. The source and substrate of the NMOS transistor are grounded, and the drain is connected to the output terminal. The parasitic structures of the PMOS and NMOS transistors form an NPNP structure. When the power supply or output port voltage fluctuates, it is easy to cause device latch-up, burn out the chip, and fail to maintain the high impedance state of the output.

[0004] Therefore, there is an urgent need for a circuit that can prevent latch-up and maintain a high-impedance output state when there are voltage fluctuations at the power supply or output port. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a three-state output drive device that can prevent latch-up and maintain the output in a high-impedance state when there are voltage fluctuations in the power supply or output port.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a three-state output driving device, the device comprising: an anti-latch-up protection circuit and a three-state output driving circuit; The first input terminal of the anti-latch-up protection circuit is connected to the output terminal of the tri-state output drive circuit, the second input terminal of the anti-latch-up protection circuit is connected to the power supply, the first output terminal of the anti-latch-up protection circuit is connected to the first input terminal of the tri-state output drive circuit, the second output terminal of the anti-latch-up protection circuit is connected to the second input terminal of the tri-state output drive circuit, and the third output terminal of the anti-latch-up protection circuit is connected to the third input terminal of the tri-state output drive circuit. When the power supply is in normal operation, the anti-latch-up protection circuit is used to supply power to the tri-state output drive circuit. When the power supply fails or the output voltage of the tri-state output drive circuit changes, the anti-latch-up protection circuit provides a preset voltage to the tri-state output drive circuit via its third output terminal, causing each parasitic transistor in the tri-state output drive circuit to disconnect under the action of the preset voltage. When the power supply fails, the anti-latch-up protection circuit outputs a high level to the tri-state output drive circuit via its first output terminal and controls the second output terminal of the anti-latch-up protection circuit to have no output signal, so that the tri-state output drive circuit outputs a high-impedance signal through its output terminal.

[0007] Optionally, the anti-latch-up protection circuit includes: a power failure detection module, an output control module, and a power supply module; The input terminal of the power failure detection module is connected to the power supply, the output terminal of the power failure detection module is connected to the first input terminal of the output control module, and the ground terminal of the power failure detection module is grounded. The second input terminal of the output control module is connected to the first output terminal of the power supply module, the first output terminal of the output control module is connected to the first input terminal of the three-state output drive circuit, and the second output terminal of the output control module is connected to the second input terminal of the three-state output drive circuit. The first input terminal of the power supply module is connected to the power source, the second input terminal of the power supply module is connected to the output terminal of the tri-state output drive circuit, and the second output terminal of the power supply module is connected to the third input terminal of the tri-state output drive circuit. The power supply module is used to provide preset voltages to the three-state output drive circuit, the power failure detection module, and the output control module respectively when the power supply fails or the output voltage of the three-state output drive circuit changes; The power failure detection module is used to output a detection signal that changes with the power supply voltage to the output control module when the power supply fails. The output control module is used to respond to the detection signal by controlling the second output terminal of the output control module to have no output signal and to output a high level through the first output terminal of the output control module.

[0008] Optionally, the power failure detection module includes: a clamping protection submodule and a signal output submodule; The input terminal of the clamping protection submodule is connected to the power supply, and the output terminal of the clamping protection submodule is connected to the first input terminal of the signal output submodule. The second input terminal of the signal output submodule is connected to the power supply, and the output terminal of the signal output submodule is connected to the first input terminal of the output control module. The clamping protection submodule is used to clamp the voltage of the signal output submodule when the power supply fails; The signal output submodule outputs the detection signal to the output control module when the power is lost.

[0009] Optionally, the clamping protection submodule includes: a first diode and a second diode; The positive terminal of the first diode is connected to the power supply and the second input terminal of the signal output submodule, respectively, and the negative terminal of the first diode is connected to the negative terminal of the second diode. The positive terminal of the second diode is connected to the first input terminal of the signal output submodule.

[0010] Optionally, the signal output submodule includes: a first PMOS transistor and a first resistor; The first end of the first PMOS transistor is connected to one end of the first resistor and the output end of the clamping protection submodule. The second and third ends of the first PMOS transistor are both connected to the power supply. The fourth end of the first PMOS transistor is connected to the first input end of the output control module. The other end of the first resistor is grounded. When the power supply fails, the detection signal is output to the output control module through the first PMOS transistor.

[0011] Optionally, the output control module includes: a first inverting submodule, a second inverting submodule, and a third inverting submodule; The first input terminal of the first inverting submodule is connected to the output terminal of the power failure detection module, the second input terminal of the first inverting submodule is connected to the first output terminal of the power supply module, the output terminal of the first inverting submodule is connected to the first input terminal of the second inverting submodule, and the ground terminal of the first inverting submodule is grounded. The second input terminal of the second inverting submodule is connected to the first output terminal of the power supply module, the output terminal of the second inverting submodule is connected to the first input terminal of the third inverting submodule, and the ground terminal of the second inverting submodule is grounded. The second input terminal of the third inverting submodule is connected to the first output terminal of the power supply module, the first output terminal of the third inverting submodule is connected to the first input terminal of the tri-state output driving circuit, and the second output terminal of the third inverting submodule is connected to the second input terminal of the tri-state output driving circuit. The first inverting submodule is used to invert the detection signal when the level of the detection signal of the power-down detection module is less than the conduction threshold corresponding to the first inverting submodule, and output a high level to the second inverting submodule; The second inverting submodule is used to invert the high level and output a low level to the third inverting submodule; The third inverting submodule inverts the low level output by the second inverting submodule, outputs a high level to the tri-state output driving circuit via the first output terminal of the third inverting submodule, and controls the second output terminal of the third inverting submodule to have no output signal.

[0012] Optionally, the first inverting submodule includes: a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and a first NMOS transistor; The first terminal of the second PMOS transistor is connected to the first terminal of the third PMOS transistor, the first terminal of the fourth PMOS transistor, the first terminal of the fifth PMOS transistor, the first terminal of the sixth PMOS transistor, the first terminal of the seventh PMOS transistor, the first terminal of the first NMOS transistor, and the output terminal of the power-down detection module, respectively. The second terminal, the third terminal of the second PMOS transistor, the third terminal of the third PMOS transistor, the third terminal of the fourth PMOS transistor, the third terminal of the fifth PMOS transistor, the third terminal of the sixth PMOS transistor, and the third terminal of the seventh PMOS transistor are all connected to the first output terminal of the power supply module. The fourth terminal of the second PMOS transistor is connected to the second terminal of the third PMOS transistor, the fourth terminal of the third PMOS transistor is connected to the second terminal of the fourth PMOS transistor, the fourth terminal of the fourth PMOS transistor is connected to the second terminal of the fifth PMOS transistor, the fourth terminal of the fifth PMOS transistor is connected to the second terminal of the sixth PMOS transistor, the fourth terminal of the sixth PMOS transistor is connected to the second terminal of the seventh PMOS transistor, the fourth terminal of the seventh PMOS transistor is connected to the second terminal of the first NMOS transistor, the third terminal and the fourth terminal of the first NMOS transistor are both grounded, and the second terminal of the first NMOS transistor is connected to the second input terminal of the second inverting submodule.

[0013] Optionally, the second inverting submodule includes: an eighth PMOS transistor and a second NMOS transistor; The first end of the eighth PMOS transistor is connected to the output end of the first inverting submodule and the first end of the second NMOS transistor, respectively. The second end and the third end of the eighth PMOS transistor are both connected to the first output end of the power supply module. The fourth end of the eighth PMOS transistor is connected to the second end of the second NMOS transistor and the first input end of the third inverting submodule, respectively. The third and fourth terminals of the second NMOS transistor are both grounded.

[0014] Optionally, the third inverting submodule includes: a ninth PMOS transistor and a third NMOS transistor; The first terminal of the ninth PMOS transistor is connected to the first terminal of the third NMOS transistor and the output terminal of the second inverting submodule, the second terminal and the third terminal of the ninth PMOS transistor are both connected to the first output terminal of the power supply module, and the fourth terminal of the ninth PMOS transistor is connected to the first input terminal 11 of the tri-state output drive circuit. The second terminal of the third NMOS transistor is connected to the second input terminal 12 of the tri-state output drive circuit, and the third terminal and the fourth terminal of the third NMOS transistor are both grounded.

[0015] Optionally, the tri-state output driving circuit includes: a first logic circuit, a second logic circuit, a first driving circuit, a second driving circuit, an output PMOS transistor, and an output NMOS transistor; The first input terminal of the first logic circuit is used to input a first signal. The second input terminal of the first logic circuit is connected to the second output terminal 12 of the anti-latch-up protection circuit. The third input terminal of the first logic circuit is connected to the third output terminal 14 of the anti-latch-up protection circuit. The fourth input terminal of the first logic circuit is connected to the power supply. The fifth input terminal of the first logic circuit is connected to the first output terminal 11 of the anti-latch-up protection circuit. The first output terminal of the first logic circuit is connected to the first input terminal of the first drive circuit. The second output terminal of the first logic circuit is connected to the first input terminal of the second drive circuit. The second input terminal of the first driving circuit is connected to the third output terminal of the anti-latch-up protection circuit, and the output terminal of the first driving circuit is connected to the first terminal of the output PMOS transistor. The first input terminal and the second input terminal of the second driving circuit are respectively connected to the first output terminal 11 of the anti-latch-up protection circuit, the third input terminal of the second driving circuit is connected to the third output terminal 14 of the anti-latch-up protection circuit, and the output terminal of the second driving circuit is connected to the output NMOS transistor. The second and third terminals of the output PMOS transistor are both connected to the third output terminal of the latch-up protection circuit, and the fourth terminal of the output PMOS transistor is connected to the second terminal of the output NMOS transistor; the third and fourth terminals of the output NMOS transistor are both grounded. The first input terminal of the second logic circuit is used to input the second signal, the second input terminal of the second logic circuit is connected to the power supply, the ground terminal of the second logic circuit is grounded, and the output terminal of the second logic circuit is connected to the fourth input terminal of the second driving circuit and the third input terminal of the first driving circuit, respectively. The first logic circuit outputs a low level under the action of the high level output by the anti-latch-up protection circuit, and outputs the low level to the first driving circuit. The first driving circuit inverts the low level and outputs a high level by the output PMOS transistor. The output PMOS transistor is cut off under the action of the high level. The second driving circuit responds to the high level output by the anti-latch-up protection circuit by outputting a low level to the output NMOS transistor, and the output NMOS transistor is turned off under the action of the low level.

[0016] The beneficial effects of this application are: This application provides a tri-state output driving device. By connecting the first input terminal of the anti-latch-up protection circuit to the output terminal of the tri-state output driving circuit, and connecting the third output terminal of the anti-latch-up protection circuit to the third input terminal of the tri-state output driving circuit, a preset voltage can be provided to the tri-state output driving circuit through the third output terminal of the anti-latch-up protection circuit when the power supply fails or the voltage at the output terminal of the tri-state output driving circuit changes. This ensures that the tri-state output driving voltage not only functions normally but also disconnects the parasitic transistors of each transistor in the tri-state output driving circuit under the action of the preset voltage, preventing latch-up problems caused by the conduction of the parasitic transistors. By connecting the first output terminal of the anti-latch-up protection circuit to the first input terminal of the tri-state output driving circuit, a high level can be output to the tri-state output driving circuit through the first output terminal of the anti-latch-up protection circuit. Furthermore, by connecting the second output terminal of the anti-latch-up protection circuit to the first input terminal of the tri-state output driving circuit, the second output terminal of the anti-latch-up protection circuit can be controlled to have no output signal. Thus, when the power supply fails, the tri-state output driving circuit can output a high-impedance signal under the action of the high level output by the anti-latch-up protection circuit and the absence of an output signal at the second output terminal. It can prevent circuit latch-up problems caused by power failure or output port voltage changes, and can ensure that the tri-state output drive circuit can still maintain a high-impedance output signal after power failure, protecting the circuit from damage. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of a traditional three-state output driver; Figure 2 This is a schematic diagram of the parasitic tube structure; Figure 3 A schematic diagram of a three-state output driving device provided in an embodiment of this application; Figure 4 A circuit diagram of an anti-latch-up protection circuit provided in an embodiment of this application; Figure 5 A schematic diagram of another anti-latch-up protection circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an output control module provided in an embodiment of this application; Figure 7 A circuit diagram of another three-state output driving device provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0020] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0022] Figure 1This is a circuit diagram of a traditional tri-state output driver. The output stage of a traditional tri-state output driver circuit consists of an output PMOS transistor and an output NMOS transistor. The source and substrate of the output PMOS transistor are connected to the power supply, and the drain is connected to the output terminal. The source and substrate of the output NMOS transistor are grounded, and the drain is connected to the output terminal. The parasitic structure of the output PMOS transistor and the output NMOS transistor constitutes an NPNP structure. When the power supply or output port voltage fluctuates, it can easily cause device latch-up and burn out the chip.

[0023] When the output Y voltage or the power supply voltage fluctuates, it can cause the parasitic transistor to conduct, resulting in latch-up. Specifically, Figure 2 This is a schematic diagram of the parasitic tube structure. Figure 2 In this circuit, Q1 is the PNP parasitic transistor of the PMOS transistor, and Q2 is the NPN parasitic transistor of the NMOS transistor. When the output voltage Y is higher than the power supply voltage, the difference between the output voltage Y and the power supply voltage is greater than or equal to the turn-on voltage of the parasitic transistor Q1 of the output PMOS transistor. This causes Q1 to conduct, generating a large current from the power supply to ground. This, in turn, turns on the parasitic transistor Q2 of the output NMOS transistor, which in turn feeds back to Q1, creating a vicious cycle. This results in a large current flowing from the power supply to ground, generating a significant amount of heat and potentially burning out the chip. The principle is the same when the output voltage Y is lower than the power supply voltage, and will not be elaborated upon here.

[0024] Figure 3 This is a schematic diagram of the structure of a three-state output driving device provided in an embodiment of this application, as shown below. Figure 3 As shown, the tri-state output drive device may include: anti-latch-up protection circuit 10 and tri-state output drive circuit 11.

[0025] like Figure 3 As shown, the first input terminal of the anti-latch-up protection circuit 10 is connected to the output terminal of the tri-state output drive circuit 11, the second input terminal of the anti-latch-up protection circuit 10 is connected to the power supply, the first output terminal of the anti-latch-up protection circuit 10 is connected to the first input terminal of the tri-state output drive circuit 11, the second output terminal of the anti-latch-up protection circuit 10 is connected to the first input terminal of the tri-state output drive circuit 11, and the third output terminal of the anti-latch-up protection circuit 10 is connected to the third input terminal of the tri-state output drive circuit 11. The first output terminal of the anti-latch-up protection circuit 10 is as follows: Figure 3 Port A in the circuit, the second output terminal of the latch-up protection circuit 10 is as follows: Figure 3 Port B in the circuit, the third output terminal of the latch-up protection circuit 10, is as follows: Figure 3 Port C in the middle.

[0026] Optionally, when the power supply is normal, the anti-latch-up protection circuit 10 can supply power to the tri-state output drive circuit 11. When the power supply fails or the output voltage of the tri-state output drive circuit 11 changes, the anti-latch-up protection circuit 10 provides a preset voltage to the tri-state output drive circuit 11 through the third output terminal of the anti-latch-up protection circuit 10, so that each parasitic transistor in the tri-state output drive circuit 11 is disconnected under the action of the preset voltage.

[0027] Here, each parasitic transistor refers to the parasitic transistor of each PMOS transistor in the three-state output drive circuit. The preset voltage is the voltage that enables the three-state output drive circuit 11 to operate normally, and this preset voltage is sufficient to prevent the parasitic transistors of each transistor in the three-state output drive circuit from conducting; that is, the preset voltage is lower than the conduction threshold voltage of the parasitic transistor. For example, when the conduction threshold of the parasitic transistor is 0.7V, the preset voltage can be a voltage less than 0.7V, such as 0.3V or 0.4V.

[0028] Optionally, when the power is lost, the anti-latch-up protection circuit 10 outputs a high level to the tri-state output drive circuit 11 via the first output terminal of the anti-latch-up protection circuit 10 and controls the second output terminal of the anti-latch-up protection circuit 10 to have no output signal, so that the tri-state output drive circuit 11 outputs a high-impedance state signal through the output terminal of the tri-state output drive circuit 11.

[0029] In this embodiment, by connecting the first input terminal of the anti-latch-up protection circuit to the output terminal of the tri-state output drive circuit, and connecting the third output terminal of the anti-latch-up protection circuit to the third input terminal of the tri-state output drive circuit, a preset voltage can be provided to the tri-state output drive circuit through the third output terminal of the anti-latch-up protection circuit when the power supply fails or the voltage at the output terminal of the tri-state output drive circuit changes. This ensures that the tri-state output drive voltage not only functions normally but also disconnects the parasitic transistors of each transistor in the tri-state output drive circuit under the action of the preset voltage, preventing latch-up problems caused by the conduction of the parasitic transistors. By connecting the first output terminal of the anti-latch-up protection circuit to the first input terminal of the tri-state output drive circuit, a high level can be output to the tri-state output drive circuit through the first output terminal of the anti-latch-up protection circuit. Furthermore, by connecting the second output terminal of the anti-latch-up protection circuit to the first input terminal of the tri-state output drive circuit, the second output terminal of the anti-latch-up protection circuit can be controlled to have no output signal. Thus, when the power supply fails, the tri-state output drive circuit can output a high-impedance signal under the action of the high level output by the anti-latch-up protection circuit and the absence of an output signal at the second output terminal. It can prevent circuit latch-up problems caused by power failure or output port voltage changes, and can ensure that the tri-state output drive circuit can still maintain a high-impedance output signal after power failure, protecting the circuit from damage.

[0030] Figure 4 A circuit diagram of an anti-latch-up protection circuit provided in an embodiment of this application is shown below. Figure 4 As shown, the anti-latch-up protection circuit 10 may include: a power failure detection module 101, an output control module 102, and a power supply module 103.

[0031] like Figure 4 As shown, the input terminal of the power failure detection module 101 is connected to the power supply, the output terminal of the power failure detection module 101 is connected to the first input terminal of the output control module 102, and the ground terminal of the power failure detection module 101 is grounded.

[0032] Optionally, the second input terminal of the output control module 102 is connected to the first output terminal of the power supply module 103, the first output terminal of the output control module 102 is connected to the first input terminal of the tri-state output drive circuit 11, the second output terminal of the output control module 102 is connected to the second input terminal of the tri-state output drive circuit 11, and the ground terminal of the output control module 102 is grounded. The first output terminal of the output control module 102 is as follows: Figure 4 Port A in the output control module 102 is the second output terminal as shown in the example. Figure 4 Port B in the middle.

[0033] Optionally, the first input terminal of the power supply module 103 is connected to a power source, the second input terminal of the power supply module 103 is connected to the output terminal of the tri-state output drive circuit 11, and the second output terminal of the power supply module 103 is connected to the third input terminal of the tri-state output drive circuit 11. The second output terminal of the power supply module 103 is as follows: Figure 4 Port C in the middle.

[0034] Optionally, the power supply module 103 can provide preset voltages to the tri-state output drive circuit 11, the power failure detection module 101, and the output control module 102 respectively when the power supply fails or the output voltage of the tri-state output drive circuit 11 changes. Specifically, the power supply module 103 can provide preset voltages to the power failure detection module 101 and the output control module 102 respectively through the first output terminal of the power supply module 103, and the power supply module 103 can provide preset voltages to the tri-state output drive circuit 11 through the second output terminal of the power supply module 103.

[0035] Optionally, the power failure detection module 101 can output a detection signal that changes with the power supply voltage to the output control module 102 when the power supply fails. Specifically, since the first input terminal of the power failure detection module 101 is connected to the power supply, when the power supply fails, the detection signal output by the power failure detection module 101 also changes from high to low as the power supply voltage changes from high to low. When the output control module 102 receives the detection signal from high to low, it can respond to the received detection signal by controlling the second output terminal of the output control module 102 to have no output signal and outputting a high level through the first output terminal of the output control module 102, and outputting this high level to the first input terminal of the tri-state output drive circuit 11 connected to the output control module 102.

[0036] Figure 5 A schematic diagram of another anti-latch-up protection circuit provided in an embodiment of this application is shown below. Figure 5 As shown, the power failure detection module 101 may include a clamping protection submodule 1010 and a signal output submodule 1011.

[0037] like Figure 5 As shown, the input terminal of the clamping protection submodule 1010 is connected to the power supply, the output terminal of the clamping protection submodule 1010 is connected to the first input terminal of the signal output submodule 1011, the second input terminal of the signal output submodule 1011 is connected to the power supply, the output terminal of the signal output submodule 1011 is connected to the first input terminal of the output control module 102, and the ground terminal of the signal output submodule 1011 is grounded.

[0038] Optionally, the clamping protection submodule 1010 can clamp the voltage of the clamping signal output submodule when the power is off. The signal output submodule 1011 outputs a detection signal to the output control module 102 when the power is off.

[0039] Continue as Figure 5 As shown, the clamping protection submodule 1010 may include a first diode D1 and a second diode D2. The positive terminal of the first diode D1 can be connected to the second input terminal of the power supply and signal output submodule 1011, respectively. The negative terminal of the first diode D1 can be connected to the negative terminal of the second diode D2, and the positive terminal of the second diode D2 can be connected to the first input terminal of the signal output submodule 1011.

[0040] Continue as Figure 5 As shown, the signal output submodule 1011 may include a first PMOS transistor P1 and a first resistor R1.

[0041] Optionally, the first terminal of the first PMOS transistor P1 is connected to one end of the first resistor R1 and the output terminal of the clamping protection submodule 1010. Specifically, the first terminal of the first PMOS transistor P1 is connected to one end of the first resistor R1 and the positive terminal of the second diode D2 in the clamping protection submodule 1010. The second and third terminals of the first PMOS transistor P1 are both connected to the power supply, the fourth terminal of the first PMOS transistor is connected to the first input terminal of the output control module 102, and the other end of the first resistor R1 is grounded.

[0042] In this configuration, the first end of P1 is the gate of the PMOS transistor, the second end of P1 is the drain of the PMOS transistor, the third end of P1 is the substrate of the PMOS transistor, and the fourth end of P1 is the source of the PMOS transistor.

[0043] Optionally, when the power supply fails, a detection signal that changes with the power supply voltage can be output to the output control module 102 through the first PMOS transistor P1.

[0044] Figure 6 This is a schematic diagram of the structure of an output control module provided in an embodiment of this application, as shown below. Figure 6 As shown, the output control module 102 may include: a first inverting submodule 1021, a second inverting submodule 1022, and a third inverting submodule 1023.

[0045] like Figure 6 As shown, the first input terminal of the first inverting submodule 1021 is connected to the output terminal of the power failure detection module 101. Specifically, the first input terminal of the first inverting submodule 1021 is connected to the fourth terminal of the first PMOS transistor P1 in the power failure detection module 101. The second input terminal of the first inverting submodule 1021 is connected to the first output terminal of the power supply module 103. The output terminal of the first inverting submodule 1021 is connected to the first input terminal of the second inverting submodule 1022. The ground terminal of the first inverting submodule 1021 is grounded.

[0046] Optionally, the second input terminal of the second inverting submodule 1022 is connected to the first output terminal of the power supply module 103, the output terminal of the second inverting submodule 1022 is connected to the first input terminal of the third inverting submodule 1023, and the ground terminal of the second inverting submodule 1022 is grounded. The second input terminal of the third inverting submodule 1023 is connected to the first output terminal of the power supply module 103, the first output terminal of the third inverting submodule 1023 is connected to the first input terminal of the tri-state output driving circuit 11, and the second output terminal of the third inverting submodule 1023 is connected to the second input terminal of the tri-state output driving circuit 11.

[0047] Optionally, the first inverting submodule 1021 can invert the received detection signal and output a high level to the second inverting submodule 1022 when the level of the detection signal output by the power-down detection module 101 is less than the conduction threshold of the first inverting submodule 1021. The conduction threshold of the first inverting submodule 1022 is adjustable and can be determined based on the size, quantity, and model of each component in the first inverting submodule 1022. Different conduction thresholds can be set according to actual needs.

[0048] Optionally, when the second inverting submodule 1022 receives a high-level output from the first inverting submodule 1021, it inverts the high-level and outputs a low-level to the third inverting submodule 1023. When the third inverting submodule 1023 receives a low-level output from the second inverting submodule 1022, it inverts the low-level and outputs a high-level to the tri-state output driving circuit 11 via the first output terminal of the third inverting submodule 1023, and controls the second output terminal of the third inverting submodule 1023 to have no output signal. The first output port of the third inverting submodule 1023 is as follows: Figure 6 Port A in the diagram, the second output of the third inverting submodule 1023 is as follows: Figure 6 Port B in the middle.

[0049] Continue as Figure 6 As shown, the first inverting submodule 1021 may include: a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a first NMOS transistor N1.

[0050] Optionally, the first terminal of the second PMOS transistor P2 is connected to the first terminals of the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, the first terminal of the first NMOS transistor N1, and the output terminal of the power-down detection module 101, respectively. Specifically, it is connected to the fourth terminal of the first PMOS transistor P1 in the power-down detection module 101.

[0051] Optionally, the second terminal of the second PMOS transistor P2, the third terminal of the second PMOS transistor P2, the third terminal of the third PMOS transistor P3, the third terminal of the fourth PMOS transistor P4, the third terminal of the fifth PMOS transistor P5, the third terminal of the sixth PMOS transistor P6, and the third terminal of the seventh PMOS transistor P7 are all connected to the first output terminal of the power supply module 103.

[0052] Optionally, the fourth terminal of the second PMOS transistor P2 is connected to the second terminal of the third PMOS transistor P3, the fourth terminal of the third PMOS transistor P3 is connected to the second terminal of the fourth PMOS transistor P4, the fourth terminal of the fourth PMOS transistor P4 is connected to the second terminal of the fifth PMOS transistor P5, the fourth terminal of the fifth PMOS transistor P5 is connected to the second terminal of the sixth PMOS transistor P6, the fourth terminal of the sixth PMOS transistor P6 is connected to the second terminal of the seventh PMOS transistor P7, the fourth terminal of the seventh PMOS transistor P7 is connected to the second terminal of the first NMOS transistor N1, the third terminal and the fourth terminal of the first NMOS transistor N1 are both grounded, and the second terminal of the first NMOS transistor N1 is connected to the second input terminal of the second inverting submodule 1022.

[0053] Optionally, in the first inverting submodule 1021, P2~P7 and N1 form an inverter. The threshold of the inverter can be adjusted by adjusting the size of P2~P7 and N1. When the detection signal output by the power-down detection module 101 is less than or equal to the conduction threshold of the first inverting submodule 1021, P2~P7 are turned on and N1 is turned off. Then, the first inverting submodule 1021 outputs a high level to the second inverting submodule 1022.

[0054] Continue as Figure 6 As shown, the second inverting submodule 1022 may include an eighth PMOS transistor and a second NMOS transistor.

[0055] Optionally, the first terminal of the eighth PMOS transistor P8 is connected to the output terminal of the first inverting submodule 1021 and the first terminal of the second NMOS transistor N2, respectively. Specifically, the first terminal of the eighth PMOS transistor P8 is connected to the fourth terminal of the seventh PMOS transistor P7 in the first inverting submodule 1021. The second and third terminals of the eighth PMOS transistor P8 are both connected to the first output terminal of the power supply module 103, and the fourth terminal of the eighth PMOS transistor P8 is connected to the second terminal of the second NMOS transistor N2 and the first input terminal of the third inverting submodule 1023, respectively. The third and fourth terminals of the second NMOS transistor N2 are both grounded.

[0056] Optionally, when the first inverting submodule 1021 outputs a high level to the second inverting submodule 1022, the eighth PMOS transistor P8 in the second inverting submodule 1022 is turned off, the second NMOS transistor N2 is turned on, and the second inverting submodule 1022 outputs a low level to the third inverting submodule 1023.

[0057] Continue as Figure 6 As shown, the third inverting submodule 1023 may include: a ninth PMOS transistor P9 and a third NMOS transistor N3.

[0058] Optionally, the first terminal of the ninth PMOS transistor P9 is connected to the first terminal of the third NMOS transistor N3 and the output terminal of the second inverting submodule 1022, respectively. Specifically, the first terminal of the ninth PMOS transistor P9 is connected to the second terminal of the second NMOS transistor N2 in the second inverting submodule 1022. The second and third terminals of the ninth PMOS transistor P9 are both connected to the first output terminal of the power supply module 103, and the fourth terminal of the ninth PMOS transistor P9 is connected to the first input terminal of the tri-state output drive circuit 11. The fourth terminal of the ninth PMOS transistor P9 is as follows: Figure 6 Port A in the circuit. The second terminal of the third NMOS transistor N3 is connected to the second input terminal of the tri-state output driver circuit 11. The third and fourth terminals of the third NMOS transistor N3 are both grounded. The second terminal of the third NMOS transistor N3 is as follows: Figure 6 Port B in the middle.

[0059] Optionally, when the third inverting submodule 1023 receives the low level output from the second inverting submodule 1022, the ninth PMOS transistor P9 is turned on and outputs a high level to the tri-state output driving circuit 11 through the fourth terminal of the ninth PMOS transistor P9. At the same time, the third NMOS transistor N3 is turned off and there is no output signal at the second terminal of the third NMOS transistor N3.

[0060] Continue as Figure 6 As shown, the power supply module 103 may include a first Schottky diode DS1 and a second Schottky diode DS2.

[0061] Optionally, the positive terminal of the first Schottky diode DS1 is connected to the power supply, the negative terminal of the first Schottky diode DS1 is connected to the negative terminal of the second Schottky diode DS2 and the third input terminal of the tri-state output drive circuit 11, and the positive terminal of the second Schottky diode DS2 is connected to the output terminal of the tri-state output drive circuit 11.

[0062] Optionally, when the power supply fails or the voltage at the output terminal of the tri-state output drive circuit 11 changes, such as when the voltage at the output terminal of the tri-state output drive circuit 11 is higher than the power supply voltage, due to the small forward voltage drop of the Schottky diode, the voltage drop of the second Schottky diode DS2 can be used to output a preset voltage to the third input terminal of the tri-state output drive circuit 11. On the one hand, this allows the tri-state output drive circuit to work normally, and on the other hand, it ensures that the parasitic transistor in the tri-state output drive circuit does not meet the latch-up opening condition under the action of the preset voltage, thereby enhancing the anti-latch-up capability of the tri-state output drive circuit and preventing latch-up problems.

[0063] Figure 7 A circuit diagram of another three-state output driving device provided in the embodiments of this application is shown below. Figure 7As shown, the tri-state output driving circuit 11 in the tri-state output driving device may include: a first logic circuit, a first driving circuit, a second driving circuit, an output PMOS transistor, an output NMOS transistor, and a second logic circuit.

[0064] Optionally, the first input terminal of the first logic circuit is used to input the first signal, and the second input terminal of the first logic circuit is connected to the second output terminal of the anti-latch-up protection circuit 10. When the power is off, the circuit can be disconnected under the action of no output signal at the second output terminal of the anti-latch-up protection circuit 10, thereby preventing the transmission of the first signal.

[0065] Optionally, the third input terminal of the first logic circuit is connected to the third output terminal of the anti-latch-up protection circuit 10. When the power supply fails or the voltage at the output terminal of the tri-state output drive circuit changes, the third input terminal of the first logic circuit can receive the preset voltage output by the third output terminal of the anti-latch-up protection circuit 10, thereby ensuring the normal operation of the first logic circuit and preventing latch-up.

[0066] Optionally, the fourth input terminal of the first logic circuit is connected to the power supply, the fifth input terminal of the first logic circuit is connected to the first output terminal of the latch-up protection circuit 10, the first output terminal of the first logic circuit is connected to the first input terminal of the first drive circuit, and the second output terminal of the first logic circuit is connected to the first input terminal of the second drive circuit. This allows the fifth input terminal of the first logic circuit to receive a high-level signal output from the first output terminal of the latch-up protection circuit 10 after a power outage, and under the influence of the high-level signal, output a low-level signal to the first drive circuit through the first output terminal of the first logic circuit. The first drive circuit inverts the received low-level signal and outputs a high-level signal from the PMOS transistor, which is then cut off under the influence of the high-level signal.

[0067] Optionally, the second input terminal of the first driving circuit is connected to the third output terminal of the anti-latch-up protection circuit 10, the output terminal of the first driving circuit is connected to the first terminal of the output PMOS transistor, and the ground terminal of the first driving circuit is grounded. When the power supply fails or the voltage at the output terminal of the tri-state output driving circuit changes, the second input terminal of the first driving circuit can receive the preset voltage output by the third output terminal of the anti-latch-up protection circuit 10, thereby ensuring the normal operation of the first driving circuit and preventing latch-up.

[0068] Optionally, the first input terminal and the second input terminal of the second driving circuit are respectively connected to the first output terminal of the latch-up protection circuit 10, and the output terminal of the second driving circuit is connected to the output NMOS transistor. When the power is off, the first input terminal and the second input terminal of the second driving circuit can receive a high-level signal output from the latch-up protection circuit 10 via its first output terminal. Furthermore, under the influence of the high-level signal, the second driving circuit outputs a low-level signal to the output NMOS transistor, causing the output NMOS transistor to be turned off.

[0069] Optionally, the third input terminal of the second drive circuit is connected to the third output terminal of the anti-latch-up protection circuit 10. When the power supply fails or the voltage at the output terminal of the three-state output drive circuit changes, the third input terminal of the second drive circuit can receive the preset voltage output by the third output terminal of the anti-latch-up protection circuit 10, thereby ensuring the normal operation of the second drive circuit and preventing latch-up.

[0070] Optionally, the second and third terminals of the output PMOS transistor are both connected to the third output terminal of the anti-latch-up protection circuit 10, the fourth terminal of the output PMOS transistor is connected to the second terminal of the output NMOS transistor, and the third and fourth terminals of the output NMOS transistor are both grounded. When the power supply fails or the voltage at the output terminal of the tri-state output drive circuit changes, the output PMOS transistor can receive a preset voltage output from the third output terminal of the anti-latch-up protection circuit 10, thereby ensuring the normal operation of the output PMOS and preventing latch-up.

[0071] Optionally, the first input terminal of the second logic circuit is used to input the second signal, the second input terminal of the second logic circuit is connected to the power supply, the ground terminal of the second logic circuit is grounded, and the output terminal of the second logic circuit is connected to the fourth input terminal of the second driving circuit and the third input terminal of the first driving circuit, respectively. When the power supply fails, the second logic circuit disconnects and will not continue to transmit the second signal.

[0072] In this embodiment, when the power supply fails or the voltage at the output terminal of the tri-state output driving circuit changes, the first logic circuit, the first driving circuit, the second driving circuit, the output PMOS transistor, and the output NMOS transistor in the tri-state output driving circuit can all operate normally under the preset voltage output from the third terminal of the anti-latch-up protection circuit, and can also prevent latch-up. At the same time, when the power supply fails, the high level output from the first output terminal of the anti-latch-up protection circuit is output to the first logic circuit and the second driving circuit respectively, so that the first logic circuit outputs a low level under the action of the high level output by the anti-latch-up protection circuit, and outputs the low level to the first driving circuit. The first driving circuit inverts the low level and outputs a high level to the output PMOS transistor, which is cut off under the action of the high level. At the same time, the second driving circuit responds to the high level output by the anti-latch-up protection circuit and outputs a low level to the output NMOS transistor, which is cut off under the action of the low level. When both the output PMOS transistor and the output NMOS transistor are cut off, the tri-state output driving circuit outputs a high-impedance signal.

[0073] like Figure 7 As shown, the first logic circuit may include the tenth PMOS transistor P21, the eleventh PMOS transistor P23, the fourth NMOS transistor N21, and the fifth NMOS transistor N23.

[0074] The second logic circuit may include: the twelfth PMOS transistor P22 and the sixth NMOS transistor N22.

[0075] The first driving circuit may include: the thirteenth PMOS transistor P24, the fourteenth PMOS transistor P25, the seventh NMOS transistor N24, and the eighth NMOS transistor N25.

[0076] The second driving circuit may include: the fifteenth PMOS transistor P26, the sixteenth PMOS transistor P27, the ninth NMOS transistor N26, and the tenth NMOS transistor N27.

[0077] like Figure 7As shown, the first terminal of the tenth PMOS transistor P21 and the first terminal of the fourth NMOS transistor in the first logic circuit are both used to input the first signal. The second and third terminals of the tenth PMOS transistor P21 are both connected to the power supply. The fourth terminal of the tenth PMOS transistor P21 is connected to the second terminal of the fourth NMOS transistor, the first terminal of the eleventh PMOS transistor P23, and the first terminal of the fifth NMOS transistor N23, respectively. The first terminal of the eleventh PMOS transistor P23 is connected to the first output terminal of the latch-up protection circuit. The third terminal of the fourth NMOS transistor N21 is grounded. The fourth terminal of the fourth NMOS transistor N21 is connected to the second output terminal of the latch-up protection circuit. When the power supply is lost, the second output terminal of the latch-up protection circuit has no output signal. At this time, the fourth NMOS transistor N21 is turned off to prevent the first signal from continuing to be transmitted.

[0078] Optionally, the second and third terminals of the eleventh PMOS transistor P23 are both connected to the third output terminal of the latch-up protection circuit. The first terminals of the eleventh PMOS transistor P23 and the fifth NMOS transistor N23 are also connected to the first terminal of the fifteenth PMOS transistor P26. The fourth terminal of the eleventh PMOS transistor P23 is connected to the second terminal of the fifth NMOS transistor N23, the first terminal of the fourteenth PMOS transistor P25, and the first terminal of the eighth NMOS transistor N25, respectively. The fourth terminal of the eleventh PMOS transistor P23 is connected to the second terminal of the fifth NMOS transistor N23, and both the third and fourth terminals of the fifth NMOS transistor N23 are grounded.

[0079] Continue as Figure 7 As shown, the first terminal of the twelfth PMOS transistor P22 and the first terminal of the sixth NMOS transistor N22 are both used to input the second signal. The second terminal and the third terminal of the twelfth PMOS transistor P22 are both connected to the power supply. The fourth terminal of the twelfth PMOS transistor P22 is connected to the second terminal of the sixth NMOS transistor N22, the first terminal of the sixteenth PMOS transistor P27, the first terminal of the tenth NMOS transistor N27, the first terminal of the thirteenth PMOS transistor P24, and the first terminal of the seventh NMOS transistor N24, respectively. The third terminal and the fourth terminal of the sixth NMOS transistor N22 are both grounded.

[0080] Continue as Figure 7As shown, the second and third terminals of the thirteenth PMOS transistor P24, the second and third terminals of the fourteenth PMOS transistor P25, and the third terminal of the fourteenth PMOS transistor P25 are all connected to the third output terminal of the latch-up protection circuit. The fourth terminal of the thirteenth PMOS transistor P24 is connected to the second terminal of the seventh NMOS transistor N24, the fourth terminal of the fourteenth PMOS transistor P25, and the first terminal of the output PMOS transistor, respectively. The third terminal of the seventh NMOS transistor N24, the third terminal of the eighth NMOS transistor N25, and the fourth terminal of the eighth NMOS transistor N25 are all grounded. The fourth terminal of the seventh NMOS transistor N24 is connected to the second terminal of the eighth NMOS transistor N25.

[0081] Continue as Figure 7 As shown, the second and third terminals of the fifteenth PMOS transistor P26 and the sixteenth PMOS transistor P27 are all connected to the third output terminal of the latch-up protection circuit. The first terminal of the fifteenth PMOS transistor P26 is also connected to the first output terminal of the latch-up protection circuit. The fourth terminal of the fifteenth PMOS transistor P26 is connected to the second terminal of the sixteenth PMOS transistor P27. The fourth terminal of the sixteenth PMOS transistor P27 is connected to the second terminal of the tenth NMOS transistor N27, the second terminal of the ninth NMOS transistor N26, and the first terminal of the output NMOS transistor. The third and fourth terminals of the tenth NMOS transistor N27 are both grounded. The first terminal of the ninth NMOS transistor N26 is connected to the first output terminal of the latch-up protection circuit. The third and fourth terminals of the ninth NMOS transistor N26 are both grounded.

[0082] Then, based on Figure 7 The connection circuit diagram shows that when the power supply fails or the voltage at the output terminal of the three-state output circuit changes, the third output terminal of the anti-latch-up protection circuit outputs a preset voltage, so that the parasitic transistors P23, P24, P25, P26, and the output PMOS do not meet the latch-up opening conditions, thus avoiding the latch-up problem.

[0083] When the power fails, the first output of the latch-up protection circuit outputs a high level. The ninth NMOS transistor N26 conducts under the influence of the high level, outputting a low level to the output NMOS transistor, thus turning it off. The fifth NMOS transistor N23 conducts under the influence of the high level, outputting a low level. This low level is output to the fourteenth PMOS transistor P25 in the first drive circuit. The fourteenth PMOS transistor P25 conducts under the influence of the low level and outputs a high level to the output PMOS transistor, which then turns off. This ensures that the three-state output drive circuit can still output a high-impedance signal even when the power fails.

[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0085] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0086] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A three-state output drive device, characterized in that, The device includes: an anti-latch-off protection circuit and a three-state output drive circuit; The first input terminal of the anti-latch-up protection circuit is connected to the output terminal of the tri-state output drive circuit, the second input terminal of the anti-latch-up protection circuit is connected to the power supply, the first output terminal of the anti-latch-up protection circuit is connected to the first input terminal of the tri-state output drive circuit, the second output terminal of the anti-latch-up protection circuit is connected to the second input terminal of the tri-state output drive circuit, and the third output terminal of the anti-latch-up protection circuit is connected to the third input terminal of the tri-state output drive circuit. When the power supply is in normal operation, the anti-latch-up protection circuit is used to supply power to the tri-state output drive circuit. When the power supply fails or the output voltage of the tri-state output drive circuit changes, the anti-latch-up protection circuit provides a preset voltage to the tri-state output drive circuit via its third output terminal, causing each parasitic transistor in the tri-state output drive circuit to disconnect under the action of the preset voltage. When the power supply fails, the anti-latch-up protection circuit outputs a high level to the tri-state output drive circuit via its first output terminal and controls the second output terminal of the anti-latch-up protection circuit to have no output signal, so that the tri-state output drive circuit outputs a high-impedance signal through its output terminal.

2. The three-state output drive device according to claim 1, characterized in that, The anti-latch-off protection circuit includes: a power failure detection module, an output control module, and a power supply module; The input terminal of the power failure detection module is connected to the power supply, the output terminal of the power failure detection module is connected to the first input terminal of the output control module, and the ground terminal of the power failure detection module is grounded. The second input terminal of the output control module is connected to the first output terminal of the power supply module, the first output terminal of the output control module is connected to the first input terminal of the three-state output drive circuit, and the second output terminal of the output control module is connected to the second input terminal of the three-state output drive circuit. The first input terminal of the power supply module is connected to the power source, the second input terminal of the power supply module is connected to the output terminal of the tri-state output drive circuit, and the second output terminal of the power supply module is connected to the third input terminal of the tri-state output drive circuit. The power supply module is used to provide preset voltages to the three-state output drive circuit, the power failure detection module, and the output control module respectively when the power supply fails or the output voltage of the three-state output drive circuit changes; The power failure detection module is used to output a detection signal that changes with the power supply voltage to the output control module when the power supply fails. The output control module is used to respond to the detection signal by controlling the second output terminal of the output control module to have no output signal and to output a high level through the first output terminal of the output control module.

3. The three-state output drive device according to claim 2, characterized in that, The power failure detection module includes: a clamping protection submodule and a signal output submodule; The input terminal of the clamping protection submodule is connected to the power supply, and the output terminal of the clamping protection submodule is connected to the first input terminal of the signal output submodule. The second input terminal of the signal output submodule is connected to the power supply, and the output terminal of the signal output submodule is connected to the first input terminal of the output control module. The clamping protection submodule is used to clamp the voltage of the signal output submodule when the power supply fails; The signal output submodule outputs the detection signal to the output control module when the power is lost.

4. The three-state output drive device according to claim 3, characterized in that, The clamping protection submodule includes: a first diode and a second diode; The positive terminal of the first diode is connected to the power supply and the second input terminal of the signal output submodule, respectively, and the negative terminal of the first diode is connected to the negative terminal of the second diode. The positive terminal of the second diode is connected to the first input terminal of the signal output submodule.

5. The three-state output drive device according to claim 3, characterized in that, The signal output submodule includes: a first PMOS transistor and a first resistor; The first end of the first PMOS transistor is connected to one end of the first resistor and the output end of the clamping protection submodule. The second and third ends of the first PMOS transistor are both connected to the power supply. The fourth end of the first PMOS transistor is connected to the first input end of the output control module. The other end of the first resistor is grounded. When the power supply fails, the detection signal is output to the output control module through the first PMOS transistor.

6. The three-state output drive device according to claim 2, characterized in that, The output control module includes: a first inverting submodule, a second inverting submodule, and a third inverting submodule; The first input terminal of the first inverting submodule is connected to the output terminal of the power failure detection module, the second input terminal of the first inverting submodule is connected to the first output terminal of the power supply module, the output terminal of the first inverting submodule is connected to the first input terminal of the second inverting submodule, and the ground terminal of the first inverting submodule is grounded. The second input terminal of the second inverting submodule is connected to the first output terminal of the power supply module, the output terminal of the second inverting submodule is connected to the first input terminal of the third inverting submodule, and the ground terminal of the second inverting submodule is grounded. The second input terminal of the third inverting submodule is connected to the first output terminal of the power supply module, the first output terminal of the third inverting submodule is connected to the first input terminal of the tri-state output driving circuit, and the second output terminal of the third inverting submodule is connected to the second input terminal of the tri-state output driving circuit. The first inverting submodule is used to invert the detection signal when the level of the detection signal of the power-down detection module is less than the conduction threshold corresponding to the first inverting submodule, and output a high level to the second inverting submodule; The second inverting submodule is used to invert the high level and output a low level to the third inverting submodule; The third inverting submodule inverts the low level output by the second inverting submodule, outputs a high level to the tri-state output driving circuit via the first output terminal of the third inverting submodule, and controls the second output terminal of the third inverting submodule to have no output signal.

7. The three-state output drive device according to claim 6, characterized in that, The first inverting submodule includes: a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and a first NMOS transistor; The first terminal of the second PMOS transistor is connected to the first terminal of the third PMOS transistor, the first terminal of the fourth PMOS transistor, the first terminal of the fifth PMOS transistor, the first terminal of the sixth PMOS transistor, the first terminal of the seventh PMOS transistor, the first terminal of the first NMOS transistor, and the output terminal of the power-down detection module, respectively. The second terminal, the third terminal of the second PMOS transistor, the third terminal of the third PMOS transistor, the third terminal of the fourth PMOS transistor, the third terminal of the fifth PMOS transistor, the third terminal of the sixth PMOS transistor, and the third terminal of the seventh PMOS transistor are all connected to the first output terminal of the power supply module. The fourth terminal of the second PMOS transistor is connected to the second terminal of the third PMOS transistor, the fourth terminal of the third PMOS transistor is connected to the second terminal of the fourth PMOS transistor, the fourth terminal of the fourth PMOS transistor is connected to the second terminal of the fifth PMOS transistor, the fourth terminal of the fifth PMOS transistor is connected to the second terminal of the sixth PMOS transistor, the fourth terminal of the sixth PMOS transistor is connected to the second terminal of the seventh PMOS transistor, the fourth terminal of the seventh PMOS transistor is connected to the second terminal of the first NMOS transistor, the third terminal and the fourth terminal of the first NMOS transistor are both grounded, and the second terminal of the first NMOS transistor is connected to the second input terminal of the second inverting submodule.

8. The three-state output drive device according to claim 6, characterized in that, The second inverting submodule includes: an eighth PMOS transistor and a second NMOS transistor; The first end of the eighth PMOS transistor is connected to the output end of the first inverting submodule and the first end of the second NMOS transistor, respectively. The second end and the third end of the eighth PMOS transistor are both connected to the first output end of the power supply module. The fourth end of the eighth PMOS transistor is connected to the second end of the second NMOS transistor and the first input end of the third inverting submodule, respectively. The third and fourth terminals of the second NMOS transistor are both grounded.

9. The three-state output drive device according to claim 6, characterized in that, The third inverting submodule includes: a ninth PMOS transistor and a third NMOS transistor; The first terminal of the ninth PMOS transistor is connected to the first terminal of the third NMOS transistor and the output terminal of the second inverting submodule, the second terminal and the third terminal of the ninth PMOS transistor are both connected to the first output terminal of the power supply module, and the fourth terminal of the ninth PMOS transistor is connected to the first input terminal of the tri-state output drive circuit. The second terminal of the third NMOS transistor is connected to the second input terminal of the tri-state output drive circuit, and the third terminal and the fourth terminal of the third NMOS transistor are both grounded.

10. The three-state output drive device according to claim 1, characterized in that, The tri-state output driving circuit includes: a first logic circuit, a second logic circuit, a first driving circuit, a second driving circuit, an output PMOS transistor, and an output NMOS transistor; The first input terminal of the first logic circuit is used to input a first signal; the second input terminal of the first logic circuit is connected to the second output terminal of the anti-latch-up protection circuit; the third input terminal of the first logic circuit is connected to the third output terminal of the anti-latch-up protection circuit; the fourth input terminal of the first logic circuit is connected to the power supply; the fifth input terminal of the first logic circuit is connected to the first output terminal of the anti-latch-up protection circuit; the first output terminal of the first logic circuit is connected to the first input terminal of the first drive circuit; and the second output terminal of the first logic circuit is connected to the first input terminal of the second drive circuit. The second input terminal of the first driving circuit is connected to the third output terminal of the anti-latch-up protection circuit, and the output terminal of the first driving circuit is connected to the first terminal of the output PMOS transistor. The first input terminal and the second input terminal of the second driving circuit are respectively connected to the first output terminal of the anti-latch-up protection circuit, the third input terminal of the second driving circuit is connected to the third output terminal of the anti-latch-up protection circuit, and the output terminal of the second driving circuit is connected to the output NMOS transistor. The second and third terminals of the output PMOS transistor are both connected to the third output terminal of the latch-up protection circuit, and the fourth terminal of the output PMOS transistor is connected to the second terminal of the output NMOS transistor; the third and fourth terminals of the output NMOS transistor are both grounded. The first input terminal of the second logic circuit is used to input the second signal, the second input terminal of the second logic circuit is connected to the power supply, the ground terminal of the second logic circuit is grounded, and the output terminal of the second logic circuit is connected to the fourth input terminal of the second driving circuit and the third input terminal of the first driving circuit, respectively. The first logic circuit outputs a low level under the action of the high level output by the anti-latch-up protection circuit, and outputs the low level to the first driving circuit. The first driving circuit inverts the low level and outputs a high level by the output PMOS transistor. The output PMOS transistor is cut off under the action of the high level. The second driving circuit responds to the high level output by the anti-latch-up protection circuit by outputting a low level to the output NMOS transistor, and the output NMOS transistor is turned off under the action of the low level.

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