Charge pump and phase locked loop circuit

Abstract

The application discloses a charge pump and a phase-locked loop circuit, wherein the charge pump comprises a charge pump main body and a current compensation unit; the charge pump main body is provided with a pull-up current source and a pull-down current source connected with an output node of the charge pump; the pull-up current source and the pull-down current source are connected with the output node according to the control of a control signal. The current compensation unit is used for generating a compensation current, and performing current compensation on the pull-up current based on the compensation current; and the current compensation unit is used for adjusting the pull-down current based on the compensation current according to the control of the control signal. By introducing the current compensation unit in the charge pump, the application can dynamically compensate the difference between the pull-up current and the pull-down current in real time, and greatly weaken the deterministic jitter of the PLL output clock. Meanwhile, the application can track the current drift caused by low-frequency noise in real time, dynamically adjust the compensation current, and suppress the clock jitter converted by the low-frequency noise. The application supports an ultra-low working voltage of 0.7 V, and can be well adapted to the application scenarios of contemporary low-voltage high-frequency CPUs.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and specifically relates to a charge pump phase-locked loop circuit. Background Technology

[0002] As CMOS manufacturing processes continue to iterate, transistor feature sizes are constantly shrinking. Modern CPUs are consequently operating at lower voltages, significantly improving the energy efficiency and integrated functional density of digital chips. This allows CPUs to support higher operating frequencies and achieve high-speed computing capabilities.

[0003] Phase-locked loops (PLLs), as the core clock generation circuit of a CPU, are responsible for providing a stable and accurate synchronous clock signal for the chip system. The combined effect of continuously decreasing supply voltage and significantly increasing operating frequency presents a significant challenge to PLL circuit design. Traditional PLL circuit architectures are ill-suited to extreme low-voltage, high-frequency operating scenarios, and are prone to problems such as degraded output clock performance and failure to meet specifications.

[0004] Phase noise is a core indicator of PLL clock performance, manifesting as clock cycle jitter during CPU operation. Excessive clock jitter can trigger setup and hold time violations in the CPU's internal timing logic, leading to data sampling errors, timing operation anomalies, and in severe cases, program errors, system crashes, and significantly reducing the overall stability and reliability of the chip.

[0005] The phase noise of a PLL is inversely proportional to the square of its output clock frequency. Under high-frequency output conditions, the negative impacts of non-ideal characteristics of analog circuits, such as internal component mismatch and low-frequency noise, are further amplified, ultimately transforming into more severe phase noise and clock jitter. Specifically, traditional PLL charge pumps commonly suffer from pull-up and pull-down current mismatch. Furthermore, to enable PLLs to operate at lower voltages, the current source of the current mirror is implemented using low-voltage thin-gate oxide devices with even lower threshold voltages. These low-voltage thin-gate oxide devices have a higher defect concentration, making them more prone to noise generation, thus increasing the PLL's susceptibility to low-frequency noise interference. These problems introduce significant deterministic clock jitter, making it difficult to simultaneously meet the core design requirements of low-voltage operation, high-frequency output, and low jitter, severely restricting the realization of high-performance low-voltage PLLs.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a charge pump and phase-locked loop circuit that can balance low-voltage operation, high-frequency output, and low clock jitter.

[0008] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0009] A charge pump is used in a phase-locked loop (PLL) circuit, the PLL circuit including a frequency-phase detector that generates a control signal based on a phase difference and / or frequency difference between an output signal of the PLL circuit and a reference signal. The charge pump includes: a charge pump body having an up-current source and a down-current source connected to an output node of the charge pump, the up-current source and the down-current source being connected to the output node according to the control signal; and a current compensation unit connected to the charge pump body to generate a compensation current and perform current compensation on the up-current based on the compensation current, and to adjust the down-current based on the compensation current according to the control signal.

[0010] In one or more embodiments of the present invention, the current compensation unit includes: a current generating unit connected to the charge pump body to generate a compensation current; and a conduction control unit connected to the current generating unit and the pull-down current source, for controlling the conduction of the current generating unit and the pull-down current source according to a control signal.

[0011] In one or more embodiments of the present invention, the current generating unit includes a first amplifier and a first capacitor. The first input terminal of the first amplifier is connected to a conduction control unit, the second input terminal of the first amplifier is connected to a reference voltage, the output terminal of the first amplifier is used to generate a compensation current, the first terminal of the first capacitor is connected to the first input terminal of the first amplifier, and the second terminal of the first capacitor is connected to the output terminal of the first amplifier.

[0012] In one or more embodiments of the present invention, the first amplifier has a first amplification stage and a second amplification stage. The second amplification stage of the first amplifier includes a first transistor, a second transistor, and a second capacitor. A first terminal of the first transistor is connected to a power supply voltage. A second terminal of the first transistor and a first terminal of the second capacitor are connected to a second terminal of the second transistor to generate a compensation current. A control terminal of the first transistor and a second terminal of the second capacitor are connected to the first amplification stage of the first amplifier. A first terminal of the second transistor is connected to ground voltage. The control terminal of the second transistor is used to receive a bias voltage.

[0013] In one or more embodiments of the present invention, the conduction control unit includes a first switch and a second switch. The first end of the first switch is connected to a current generating unit, the second end of the first switch and the first end of the second switch are connected to the current generating unit, and the second end of the second switch is connected to a pull-down current source. The first switch and the second switch are turned on or off according to the control signal.

[0014] In one or more embodiments of the present invention, when the pull-up current source is connected to the output node, the first switch is open; when the pull-up current source is disconnected from the output node, the first switch is closed; when the pull-down current source is connected to the output node, the second switch is open; when the pull-down current source is disconnected from the output node, the second switch is closed.

[0015] A specific embodiment of the present invention also provides a phase-locked loop circuit, including the charge pump described above, and: a phase-frequency discriminator that generates a control signal based on the phase difference and / or frequency difference between the output signal of the phase-locked loop circuit and a reference signal; a loop filter connected to the output node of the charge pump to generate a voltage signal based on the current output by the charge pump; and a voltage-controlled oscillator connected to the loop filter to generate an output signal based on the voltage signal.

[0016] In one or more embodiments of the present invention, the loop filter includes a second amplifier and a filtering unit, wherein a first input terminal of the second amplifier is connected to the output node of the charge pump, a second input terminal of the second amplifier is connected to a reference voltage, and the filtering unit is connected to the first input terminal and the output terminal of the second amplifier.

[0017] In one or more embodiments of the present invention, the filtering unit includes a first resistor, a third capacitor and a fourth capacitor. The first terminal of the third capacitor and the first terminal of the fourth capacitor are connected to the first input terminal of the second amplifier. The second terminal of the third capacitor is connected to the first terminal of the first resistor. The second terminal of the fourth capacitor and the second terminal of the first resistor are connected to the output terminal of the second amplifier.

[0018] In one or more embodiments of the present invention, the second amplifier has a first amplification stage and a second amplification stage. The second amplification stage of the second amplifier includes a fifth capacitor, a third transistor, and a third amplifier. The first terminal of the third transistor is connected to a power supply voltage. The control terminal of the third transistor and the first terminal of the fifth capacitor are connected to the first amplification stage of the second amplifier. The second terminal of the third transistor and the second terminal of the fifth capacitor are connected to the power supply terminal of the third amplifier. The ground terminal of the third amplifier is connected to ground voltage. The input terminal of the third amplifier is connected to the output terminal of the third amplifier. Alternatively, the second amplifier has a first amplification stage and a second amplification stage. The second amplification stage of the second amplifier includes a fifth capacitor, a second resistor, a third transistor, and a third amplifier. The first terminal of the third transistor is connected to a power supply voltage. The control terminal of the third transistor is connected to the first amplification stage of the second amplifier. The second terminal of the third transistor is connected to the power supply terminal of the third amplifier. The fifth capacitor and the second resistor are connected in series between the control terminal and the second terminal of the third transistor. The ground terminal of the third amplifier is connected to ground voltage. The input terminal of the third amplifier is connected to the output terminal of the third amplifier.

[0019] Compared with existing technologies, the charge pump and phase-locked loop circuit of this invention, by introducing a current compensation unit into the charge pump, can dynamically compensate for the difference between the pull-up current and pull-down current in real time, significantly reducing the deterministic jitter of the PLL output clock. Simultaneously, it can track current drift caused by low-frequency noise in real time and dynamically adjust the compensation current to suppress clock jitter converted from low-frequency noise. This invention can achieve an ultra-low operating voltage as low as 0.7V, which is well-suited for the application scenarios of modern low-voltage, high-frequency CPUs, effectively solving the technical pain point of traditional PLLs in balancing low-voltage operation, high-frequency output, and low clock jitter. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a structural diagram of a phase-locked loop circuit in the prior art.

[0022] Figure 2 This is a waveform diagram of a phase-locked loop circuit in the prior art.

[0023] Figure 3 This is a schematic diagram of the current principle of a charge pump in one embodiment of the present invention.

[0024] Figure 4 This is a structural diagram of a phase-locked loop circuit in one embodiment of the present invention.

[0025] Figure 5 This is a partial current schematic diagram of a phase-locked loop circuit in one embodiment of the present invention.

[0026] Figure 6 This is a partial current schematic diagram of a phase-locked loop circuit in one embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0028] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0029] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0030] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0031] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0032] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.

[0033] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0034] Figure 1 The diagram illustrates a phase-locked loop (PLL) circuit structure in the prior art, which includes a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. Some PLL circuits also incorporate a high-order sigma-delta regulator to control the frequency divider, thereby achieving fractional division.

[0035] The charge pump receives the UP and DN control pulses output by the phase-frequency detector (PFD), performs charge and discharge regulation on the loop filter (LPF), and further changes the control voltage of the voltage-controlled oscillator (VCO) to achieve oscillation frequency adjustment and loop phase locking of the VCO.

[0036] In advanced submicron CMOS processes, transistor feature sizes are continuously shrinking, enhancing short-channel effects and exacerbating device mismatch issues. Meanwhile, low-voltage power supply conditions significantly compress the saturation conduction margin of MOSFETs, further worsening the current matching characteristics of the charge pump's upper and lower branches. In addition, the amplitude of the 1 / f low-frequency noise of the short-channel transistor itself increases significantly. The superposition of multiple factors leads to a significant mismatch in the pull-up and pull-down currents of the charge pump, and the low-frequency noise of the circuit is also more prominent.

[0037] Although the phase-locked loop (PLL) negative feedback loop can stabilize the average frequency of the output clock, charge pump current mismatch and low-frequency noise will still periodically introduce deterministic jitter. For example... Figure 2 As shown, the reference clock CK_REF frequency of a phase-locked loop circuit is 50MHz, corresponding to a period of 20ns. The shortest conduction time of the UP and DN pulses output by the frequency and phase detector is about 200ps.

[0038] If, due to device process mismatch or low-frequency noise interference from the MOSFET's 1 / f, the charge pump pull-up current is less than the pull-down current, then within the 200ps synchronous conduction window, the total charge charged by the loop filter is lower than the total charge discharged. This leads to continuous charge loss within the loop filter, causing a synchronous decrease in the voltage-controlled oscillator (VCO) control voltage, resulting in a brief drop in the VCO's instantaneous oscillation frequency. To compensate for the charge loss in the loop filter and maintain loop phase lock, the PLL negative feedback loop extends the effective conduction time of the UP pull-up pulse at the arrival of the next CK_REF cycle, replenishing the loop filter's charge, raising the VCO control voltage, and causing the VCO's oscillation frequency to recover. This cyclical frequency fluctuation in each reference clock cycle ultimately forms... Figure 2 The phase-locked loop output clock exhibits periodic deterministic jitter.

[0039] To address the above problems, the present invention provides a charge pump and a phase-locked loop circuit.

[0040] Example 1

[0041] like Figure 3 As shown, in one embodiment of the present invention, the charge pump 10 is used in a phase-locked loop circuit. The phase-locked loop circuit includes a frequency and phase detector, which generates a control signal based on the phase difference and / or frequency difference between the output signal of the phase-locked loop circuit and a reference signal.

[0042] The charge pump 10 includes a charge pump body 11 and a current compensation unit 12. The charge pump body 11 has an up-pull current source and a down-pull current source connected to the output node A of the charge pump 10. The up-pull current source and the down-pull current source are connected to the output node A according to the control of the control signal.

[0043] For example, the charge pump body 11 also includes a switching unit, which is connected to the output node A, the pull-up current source and the pull-down current source of the charge pump 10. The switching unit controls the connection and disconnection between the pull-up current source and the output node A according to the control signal, and controls the connection and disconnection between the pull-down current source and the output node A according to the control signal.

[0044] Specifically, the switching unit includes a third switch and a fourth switch. The third switch controls the connection between the pull-up current source and the output node A according to the control signal, and the fourth switch controls the connection between the pull-down current source and the output node A according to the control signal.

[0045] For example, the pull-up current source includes a fourth transistor PM12, the pull-down current source includes a fifth transistor NM7, and the charge pump body 11 also includes a first bias unit connected to the pull-up current source and the pull-down current source. The first bias unit is used to provide bias voltages for the pull-up current source and the pull-down current source. The first bias unit includes a first bias current source IB1, a sixth transistor NM5, a seventh transistor NM6, and an eighth transistor PM11.

[0046] Among them, the first terminal of the first bias current source IB1 is connected to the power supply voltage, the second terminal of the first bias current source IB1 is connected to the second terminal of the sixth transistor NM5, the control terminal of the sixth transistor NM5, and the control terminal of the seventh transistor NM6, the first terminal of the eighth transistor PM11 is connected to the power supply voltage, the control terminal of the eighth transistor PM11 and the second terminal of the eighth transistor PM11 are connected to the second terminal of the seventh transistor NM6, and the first terminal of the seventh transistor NM6 is connected to the ground voltage.

[0047] The first terminal of the fourth transistor PM12 is connected to the power supply voltage, the second terminal of the fourth transistor PM12 is connected to the first terminal of the third switch S3, the control terminal of the fourth transistor PM12 is connected to the control terminal of the eighth transistor PM11, and the second terminal of the third switch S3 is connected to the output node A.

[0048] The first terminal of the fifth transistor NM7 is connected to ground voltage, the second terminal of the fifth transistor NM7 is connected to the first terminal of the fourth switch S4, the control terminal of the fifth transistor NM7 is connected to the control terminal of the seventh transistor NM6, and the second terminal of the fourth switch S4 is connected to output node A.

[0049] The control signals generated by the frequency and phase detector include control signal UP and control signal DN. The third switch S3 is turned on or off based on the control signal UP, and the control terminal of the fourth switch S4 is turned on or off based on the control signal DN. For example, both the third switch S3 and the fourth switch S4 are turned on at a high level and off at a low level. The waveforms of control signals UP and DN are... Figure 2 As shown, the reference signal is at a low level for most of the clock cycle, with only very short high-level pulses (approximately 200 ps), and the high levels of control signals UP and DN almost overlap. The phase-frequency discriminator can actively adjust control signals UP and DN to regulate the current drawn and injected by charge pump 10 based on the phase difference and frequency difference between the output signal of the phase-locked loop circuit and the reference signal, thereby regulating the subsequent circuit.

[0050] like Figure 3 As shown, the current compensation unit 12 is connected to the charge pump body 11 to generate a compensation current and perform current compensation on the pull-up current based on the compensation current, and adjust the pull-down current based on the compensation current according to the control signal.

[0051] Specifically, the current compensation unit 12 includes a current generating unit and a conduction control unit. The current generating unit is connected to the charge pump body 11 to generate a compensation current. The conduction control unit is connected to the current generating unit and the pull-down current source, and is used to control the conduction of the current generating unit and the pull-down current source according to a control signal.

[0052] Furthermore, the current generating unit includes a first amplifier and a first capacitor C3. The first input terminal of the first amplifier is connected to the conduction control unit, the second input terminal of the first amplifier is connected to the reference voltage VCM, the output terminal of the first amplifier is used to generate a compensation current, the first terminal of the first capacitor C3 is connected to the first input terminal of the first amplifier, and the second terminal of the first capacitor C3 is connected to the output terminal of the first amplifier.

[0053] Furthermore, the first amplifier has a bias stage, a first amplification stage, and a second amplification stage, with the bias stage providing a bias voltage to the first and second amplification stages.

[0054] For example, the bias stage of the first amplifier includes a ninth transistor PM13 and a tenth transistor NM8. The first terminal of the ninth transistor PM13 is connected to the power supply voltage. The second terminals of the ninth transistor PM13 and the tenth transistor NM8 are connected to the control terminal of the tenth transistor NM8. The first terminal of the tenth transistor NM8 is connected to ground. The control terminal of the ninth transistor PM13 receives the bias voltage. For example, the control terminal of the ninth transistor PM13 is connected to the control terminal of the fourth transistor PM12.

[0055] The first amplification stage of the first amplifier includes the eleventh transistor PM14, the twelfth transistor PM15, the thirteenth transistor NM11, the fourteenth transistor NM12, and the fifteenth transistor NM9.

[0056] The first terminal of the eleventh transistor PM14 and the first terminal of the twelfth transistor PM15 are connected to the power supply voltage. The control terminals of the eleventh transistor PM14 and the twelfth transistor PM15 are connected to the second terminal of the thirteenth transistor NM11. The second terminal of the twelfth transistor PM15 is connected to the second terminal of the fourteenth transistor NM12 and serves as the output terminal of the first amplification stage of the first amplifier. The control terminal of the thirteenth transistor NM11 serves as the first input terminal of the first amplifier, and the control terminal of the fourteenth transistor NM12 serves as the second input terminal of the first amplifier. The first terminals of the thirteenth transistor NM11 and the fourteenth transistor NM12 are connected to the second terminal of the fifteenth transistor NM9. The first terminal of the fifteenth transistor NM9 is connected to ground, and the control terminal of the fifteenth transistor NM9 receives the bias voltage. For example, the control terminal of the fifteenth transistor NM9 is connected to the control terminal of the tenth transistor NM8.

[0057] The second amplification stage of the first amplifier includes a first transistor PM16, a second transistor NM10, and a second capacitor Ccmp2. The first terminal of the first transistor PM16 is connected to the power supply voltage. The second terminals of the first transistor PM16, the first terminal of the second capacitor Ccmp2, ​​and the second terminal of the second transistor NM10 are connected to generate a compensation current, which serves as the output terminal of the first amplifier. The control terminal of the first transistor PM16, the second terminal of the second capacitor Ccmp2, ​​and the second terminal of the twelfth transistor PM15 are connected. The first terminal of the second transistor NM10 is connected to ground. The control terminal of the second transistor NM10 is used to receive a bias voltage; exemplarily, the control terminal of the second transistor NM10 is connected to the control terminal of the fifteenth transistor NM9.

[0058] In other embodiments, the first amplifier may also be other amplifier circuit structures.

[0059] like Figure 3 As shown, the conduction control unit includes a first switch S1 and a second switch S2. The first end of the first switch S1 is connected to the second end of the first transistor PM16. The second ends of the first switch S1 and the first ends of the second switch S2 are connected to the control terminal of the thirteenth transistor NM11. The second end of the second switch S2 is connected to the second end of the fifth transistor NM7. The first switch S1 and the second switch S2 are turned on or off according to the control signal.

[0060] Specifically, when the pull-up current source is connected to the output node A, the first switch S1 is open; when the pull-up current source is disconnected from the output node A, the first switch S1 is closed.

[0061] When the pull-down current source is connected to the output node A, the second switch S2 is open; when the pull-down current source is disconnected from the output node A, the second switch S2 is closed.

[0062] For example, both the first switch S1 and the second switch S2 are turned on at a high level and turned off at a low level. The control signal UP_B of the first switch S1 is inverted with the control signal UP of the third switch S3, and the control signal DN_B of the second switch S2 is inverted with the control signal DN of the fourth switch S4. The control signals UP_B of the first switch S1 and DN_B of the second switch S2 can also be provided by a frequency and phase detector. Figure 2 It can be seen that the first switch S1 and the second switch S2 are turned on for most of the reference signal clock cycle.

[0063] In this embodiment, all transistors are MOS transistors. The transistor numbered PM is a P-channel MOS transistor, and the transistor numbered NM is an N-channel MOS transistor. The first terminal of each transistor refers to its source, the second terminal refers to its drain, and the control terminal refers to its gate.

[0064] In other embodiments, the P / N type of each transistor can be changed, and each transistor can be replaced with other devices, with the connection method adjusted accordingly.

[0065] In one embodiment, the first bias current source IB1 provides a nominal charging and discharging current of 8μA. The total pull-up current of the charge pump 10 is the sum of the two currents generated by the pull-up current source and the current compensation unit 12. The pull-up current source is configured to carry 75% of the nominal current (6μA), and the remaining 25% (2μA) adjustment margin is provided by the current compensation unit 12. This current matching scheme allows the correction loop to output only the pull-up compensation current in one direction, eliminating the need for an additional pull-down compensation path and significantly simplifying the design of the correction operational amplifier circuit. For example, if a process device deviation causes the basic pull-up current of the pull-up current source to rise by 20% to 7.2μA, the current compensation unit 12 outputs a compensation current of 8μA - 7.2μA = 0.8μA to offset the branch current difference, ensuring that the total pull-up current and pull-down current are equal.

[0066] When the charge pump 10 stops charging and discharging the subsequent circuit, the turn-on control unit short-circuits the pull-up and pull-down currents of the charge pump body 11 and automatically switches to the current self-calibration mode. It utilizes the idle window of the charge pump 10 during each reference clock cycle to complete the pull-up and pull-down current matching calibration in real time.

[0067] If there is a mismatch between the pull-up current source and the pull-down current source, the output node A potential will deviate from the common-mode reference voltage VCM. In correction mode, the first amplifier, relying on its virtual short characteristic, forces the potential of the first input terminal to equal the reference voltage VCM. The compensation current is dynamically adjusted via a negative feedback loop to replenish the current difference in the entire pull-up branch in real time. When the total pull-up and pull-down currents reach a perfect match, the potential of the first input terminal of the operational amplifier is stably clamped to the reference voltage VCM, thereby eliminating the deterministic jitter caused by the current mismatch of the charge pump 10. Simultaneously, this correction loop is a continuously conducting negative feedback closed loop, which can track the minute current drift induced by 1 / f low-frequency noise in real time and dynamically adjust the compensation current to synchronously suppress the periodic clock jitter caused by low-frequency noise.

[0068] Example 2

[0069] like Figure 4 As shown, this embodiment provides a phase-locked loop circuit, including the charge pump 10 described in any specific embodiment of Embodiment 1, as well as a frequency and phase detector 20, a loop filter 30, and a voltage-controlled oscillator 40.

[0070] The phase-frequency discriminator 20 generates control signals based on the phase difference and frequency difference between the output signal CLK OUT of the phase-locked loop circuit and the reference signal CK_REF. Specifically, the control signals include control signal UP, control signal DN, and their inverted signals: control signal UP_B and control signal DN_B.

[0071] Loop filter 30 is connected to the output node A of charge pump 10 to generate a voltage signal based on the current output by charge pump 10. Voltage-controlled oscillator 40 is connected to loop filter 30 to generate an output signal CLK OUT based on the voltage signal.

[0072] The frequency and phase detector 20 can be any existing frequency and phase detector product.

[0073] In one embodiment, the phase-locked loop circuit may further include a frequency divider 50, which is used to divide the output signal CLK OUT to generate a frequency-divided signal, and the frequency and phase detector 20 can generate a control signal based on the frequency-divided signal.

[0074] like Figure 5 As shown, the loop filter 30 includes a second amplifier and a filter unit 31. The first input terminal of the second amplifier is connected to the output node A of the charge pump 10, and the second input terminal of the second amplifier is connected to the reference voltage VCM. The filter unit 31 is connected to the first input terminal and the output terminal of the second amplifier.

[0075] The filter unit 31 includes a first resistor R1, a third capacitor C1, and a fourth capacitor C2. The first end of the third capacitor C1 and the first end of the fourth capacitor C2 are connected to the first input terminal of the second amplifier. The second end of the third capacitor C1 is connected to the first end of the first resistor R1. The second end of the fourth capacitor C2 and the second end of the first resistor R1 are connected to the output terminal of the second amplifier.

[0076] like Figure 5 As shown, the second amplifier has a bias stage, a first amplification stage, and a second amplification stage.

[0077] For example, the bias stage of the second amplifier includes a second bias current source IB2 and a sixteenth transistor NM4. The first terminal of the second bias current source IB2 is connected to the power supply voltage, the second terminal of the second bias current source IB2 is connected to the second terminal of the sixteenth transistor NM4 and the control terminal of the sixteenth transistor NM4, and the first terminal of the sixteenth transistor NM4 is connected to ground.

[0078] The first amplification stage of the second amplifier includes the seventeenth transistor PM1, the eighteenth transistor PM2, the nineteenth transistor NM1, the twentieth transistor NM2, and the twenty-first transistor NM3.

[0079] The first terminal of the seventeenth transistor PM1 and the first terminal of the eighteenth transistor PM2 are connected to the power supply voltage. The control terminals of the seventeenth transistor PM1 and the eighteenth transistor PM2 are connected to the second terminal of the seventeenth transistor PM1. The second terminal of the eighteenth transistor PM2 is connected to the second terminal of the twentieth transistor NM2 and serves as the output terminal of the first amplification stage of the second amplifier. The second terminal of the nineteenth transistor NM1 is connected to the second terminal of the seventeenth transistor PM1. The first terminal of the nineteenth transistor NM1 and the first terminal of the twenty-first transistor NM3 are connected to the second terminal of the twenty-first transistor NM3. The first terminal of the twenty-first transistor NM3 is connected to ground.

[0080] The control terminal of the nineteenth transistor NM1 is used as the first input terminal of the second amplifier, the control terminal of the twentieth transistor NM2 is used as the second input terminal of the second amplifier, and the control terminal of the twenty-first transistor NM3 is connected to the control terminal of the sixteenth transistor NM4 to receive the bias voltage.

[0081] The second amplification stage of the second amplifier includes a fifth capacitor Ccmp1, a second resistor R2, a third transistor PM3, and a third amplifier A1. The first terminal of the third transistor PM3 is connected to the power supply voltage. The control terminal of the third transistor PM3 is connected to the first amplification stage of the second amplifier and serves as the output terminal of the second amplifier. The second terminal of the third transistor PM3 is connected to the power supply terminal of the third amplifier A1. The fifth capacitor Ccmp1 and the second resistor R2 are connected in series between the control terminal and the second terminal of the third transistor. The ground terminal of the third amplifier A1 is connected to the ground voltage. The input terminal of the third amplifier A1 is connected to the output terminal of the third amplifier A1.

[0082] The fifth capacitor, Ccmp1, serves as a phase compensation device for the local feedback loop of the second amplification stage, ensuring the closed-loop stability of the second operational amplifier. The second resistor, R2, introduces the high-frequency poles of the zero-point cancellation circuit, further improving the phase margin of the local loop. In other embodiments, the second resistor R2 may not be included.

[0083] When the loop filter 30 is working, relying on the virtual short characteristic of the operational amplifier, the potential of the output node A of the charge pump 10 will be forcibly clamped to the reference voltage VCM. The first resistor R1, the third capacitor C1, and the fourth capacitor C2 in the filter unit 31 together form the second-order filter compensation network of the PLL loop.

[0084] like Figure 5 As shown, the voltage-controlled oscillator 40 includes multiple inverting units connected in series to form a loop.

[0085] For example, there are 5 inverting units. The circuit structure of one of the inverting units will be described below as an example.

[0086] Specifically, the inverting unit 41 includes a 22nd transistor PM4 and a 4th amplifier A2. The first terminal of the 22nd transistor PM4 is connected to the power supply voltage, the second terminal of the 22nd transistor PM4 is connected to the power supply terminal of the 4th amplifier A2, the control terminal of the 22nd transistor PM4 is connected to the output terminal of the loop filter 30 to receive a voltage signal, and the ground terminal of the 4th amplifier A2 is connected to ground. The output terminal of the 4th amplifier A2 is connected to the input terminal of the 4th amplifier A2 in the subsequent inverting unit, and the input terminal of the 4th amplifier A2 is connected to the output terminal of the 4th amplifier A2 in the preceding inverting unit.

[0087] like Figure 5 As shown, the circuit structure of other inverting units is the same as that of inverting unit 41, and the connection points of the input and output terminals of their internal amplifiers can be adjusted accordingly.

[0088] In one embodiment, the voltage-controlled oscillator 40 further includes an output unit. The output unit includes a 23rd transistor PM9 and a 5th amplifier A3. The first terminal of the 23rd transistor PM9 is connected to the power supply voltage, the second terminal of the 23rd transistor PM9 is connected to the power supply terminal of the 5th amplifier A3, the control terminal of the 23rd transistor PM9 is connected to the output terminal of the loop filter 30 to receive a voltage signal, and the ground terminal of the 5th amplifier A3 is connected to ground. The input terminal of the 5th amplifier A3 is connected to the output terminal of the 4th amplifier A2 in any of the inverting units, and the output terminal of the 5th amplifier A3 is used to generate the output signal CLKOUT.

[0089] The static bias current of the voltage-controlled oscillator 40 is determined by the gate-source voltage VGS of its internal transistors. To reduce the static power consumption of the loop filter 30 and the voltage-controlled oscillator 40, the aspect ratio of the third transistor PM3 and each transistor in the voltage-controlled oscillator 40 can be proportionally reduced to 1 / 2 or 1 / 4 of their original size; this optimization scheme can significantly reduce the static power consumption of this bias branch without reducing the current replication matching accuracy.

[0090] like Figure 6 The diagram illustrates one amplifier circuit. Exemplary examples show that the third amplifier A1, fourth amplifier A2, and fifth amplifier A3 can all utilize this circuit structure. Of course, other amplifier circuit structures can also be used for the third amplifier A1, fourth amplifier A2, and fifth amplifier A3.

[0091] In this embodiment, all transistors are MOS transistors. The transistor numbered PM is a P-channel MOS transistor, and the transistor numbered NM is an N-channel MOS transistor. The first terminal of each transistor refers to its source, the second terminal refers to its drain, and the control terminal refers to its gate.

[0092] In other embodiments, the P / N type of each transistor can be changed, and each transistor can be replaced with other devices, with the connection method adjusted accordingly.

[0093] When the frequency and phase detector 20 detects that the frequency of the output signal CLK OUT of the voltage-controlled oscillator 40 is lower than the frequency of the reference signal CK_REF, it generates a control signal pulse to control the charge pump 10 to output charging current. Because the potential of the output node A of the charge pump 10 is stably clamped at the reference voltage VCM by the feedback structure, the output current of the charge pump 10 will continuously charge the loop filter network, raising the voltage of the voltage signal, causing its static bias current to increase synchronously, and the charging and discharging operating current of each stage of the oscillation unit to increase synchronously, ultimately raising the oscillation frequency of the differential output signal CLK OUT, and relying on the negative feedback loop to complete the automatic frequency tracking and adjustment of the phase-locked loop.

[0094] When the chip's operating temperature drifts, the bias current of the PM3 branch of the third transistor will change synchronously with the temperature characteristics of the MOS transistor VGS, correcting the operating current of all subsequent inverting units in real time, and significantly reducing the output frequency drift caused by temperature fluctuations. Compared with the traditional fixed bias VCO architecture, this circuit can greatly reduce the loop unlock recovery time caused by temperature disturbances and improve the PLL's full-temperature-range operating stability.

[0095] Since the loop filter 30 and the charge pump 10 share the same common-mode reference voltage VCM, in addition to completing the pull-up and pull-down current matching calibration of the charge pump 10, the output node A of the charge pump 10 can be short-circuited to a common-mode voltage consistent with the output voltage of the charge pump 10 during the idle period. Therefore, when the charge pump 10 switches at each clock cycle, there is almost no potential difference across the parasitic capacitance of the current source branch, which can greatly reduce the charging and discharging behavior of the parasitic capacitance on the loop filter 30 and avoid the additional periodic clock jitter introduced by this effect.

[0096] The minimum supply voltage of the charge pump 10, loop filter 30, and voltage-controlled oscillator 40 in this phase-locked loop circuit only needs to meet the sum of the gate-source voltage VGS of one transistor (typically 0.35V) and the drain-source voltage drop of two saturation regions VDS (typically 0.15~0.2V). Compared with the traditional charge pump 10, the minimum operating voltage is greatly reduced, and it can work stably at an ultra-low supply voltage of 0.7V, which is suitable for the on-chip clock generation scenario of low-voltage high-frequency CPUs with advanced process technology.

[0097] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0098] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A charge pump for a phase-locked loop (PLL) circuit, the PLL circuit including a frequency-phase detector, the frequency-phase detector generating a control signal based on the phase difference and / or frequency difference between the output signal of the PLL circuit and a reference signal, characterized in that, The charge pump includes: The charge pump body has an up-pull current source and a down-pull current source connected to the output node of the charge pump. The up-pull current source and the down-pull current source are connected to the output node according to the control of the control signal. The current compensation unit is connected to the charge pump body to generate a compensation current and perform current compensation on the pull-up current based on the compensation current, and adjusts the pull-down current based on the compensation current according to the control signal.

2. The charge pump according to claim 1, characterized in that, The current compensation unit includes: A current generating unit is connected to the charge pump body to generate a compensation current; The conduction control unit, connected to the current generation unit and the pull-down current source, is used to control the conduction current generation unit and the pull-down current source according to the control signal.

3. The charge pump according to claim 2, characterized in that, The current generating unit includes a first amplifier and a first capacitor. The first input terminal of the first amplifier is connected to the conduction control unit, the second input terminal of the first amplifier is connected to the reference voltage, the output terminal of the first amplifier is used to generate a compensation current, the first terminal of the first capacitor is connected to the first input terminal of the first amplifier, and the second terminal of the first capacitor is connected to the output terminal of the first amplifier.

4. The charge pump according to claim 3, characterized in that, The first amplifier has a first amplification stage and a second amplification stage. The second amplification stage of the first amplifier includes a first transistor, a second transistor, and a second capacitor. The first terminal of the first transistor is connected to the power supply voltage. The second terminal of the first transistor, the first terminal of the second capacitor, and the second terminal of the second transistor are connected to generate a compensation current. The control terminal of the first transistor and the second terminal of the second capacitor are connected to the first amplification stage of the first amplifier. The first terminal of the second transistor is connected to the ground voltage. The control terminal of the second transistor is used to receive a bias voltage.

5. The charge pump according to claim 2, characterized in that, The conduction control unit includes a first switch and a second switch. The first end of the first switch is connected to the current generating unit. The second end of the first switch and the first end of the second switch are connected to the current generating unit. The second end of the second switch is connected to the pull-down current source. The first switch and the second switch are turned on or off according to the control signal.

6. The charge pump according to claim 5, characterized in that, When the pull-up current source is connected to the output node, the first switch is open; when the pull-up current source is disconnected from the output node, the first switch is closed. When the pull-down current source is connected to the output node, the second switch is open; when the pull-down current source is disconnected from the output node, the second switch is closed.

7. A phase-locked loop circuit, characterized in that, The charge pump comprising any one of claims 1 to 6, and: A frequency and phase detector generates a control signal based on the phase difference and / or frequency difference between the output signal of a phase-locked loop circuit and a reference signal. A loop filter is connected to the output node of the charge pump to generate a voltage signal based on the current output by the charge pump; A voltage-controlled oscillator, connected to a loop filter, generates an output signal based on a voltage signal.

8. The phase-locked loop circuit according to claim 7, characterized in that, The loop filter includes a second amplifier and a filtering unit. The first input terminal of the second amplifier is connected to the output node of the charge pump, and the second input terminal of the second amplifier is connected to a reference voltage. The filtering unit is connected to the first input terminal and the output terminal of the second amplifier.

9. The phase-locked loop circuit according to claim 8, characterized in that, The filtering unit includes a first resistor, a third capacitor, and a fourth capacitor. The first terminal of the third capacitor and the first terminal of the fourth capacitor are connected to the first input terminal of the second amplifier. The second terminal of the third capacitor is connected to the first terminal of the first resistor. The second terminal of the fourth capacitor and the second terminal of the first resistor are connected to the output terminal of the second amplifier.

10. The phase-locked loop circuit according to claim 8, characterized in that, The second amplifier has a first amplification stage and a second amplification stage. The second amplification stage of the second amplifier includes a fifth capacitor, a third transistor, and a third amplifier. The first terminal of the third transistor is connected to the power supply voltage. The control terminal of the third transistor and the first terminal of the fifth capacitor are connected to the first amplification stage of the second amplifier. The second terminal of the third transistor and the second terminal of the fifth capacitor are connected to the power supply terminal of the third amplifier. The ground terminal of the third amplifier is connected to ground voltage. The input terminal of the third amplifier is connected to the output terminal of the third amplifier; or... The second amplifier has a first amplification stage and a second amplification stage. The second amplification stage of the second amplifier includes a fifth capacitor, a second resistor, a third transistor, and a third amplifier. The first terminal of the third transistor is connected to the power supply voltage. The control terminal of the third transistor is connected to the first amplification stage of the second amplifier. The second terminal of the third transistor is connected to the power supply terminal of the third amplifier. The fifth capacitor and the second resistor are connected in series between the control terminal and the second terminal of the third transistor. The ground terminal of the third amplifier is connected to the ground voltage. The input terminal of the third amplifier is connected to the output terminal of the third amplifier.

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