A frequency locked loop circuit and processor

Abstract

The application discloses a kind of frequency-locked loop circuit and processor.The frequency-locked loop circuit includes: error amplifier, voltage-controlled oscillator, adaptive current charge-discharge circuit and voltage conversion detection circuit;Wherein, error amplifier connects adaptive current charge-discharge circuit, output control voltage and reference voltage to adaptive current;Adaptive current charge-discharge circuit connects voltage-controlled oscillator, compares input control voltage and reference voltage, generates control signal and is output to voltage-controlled oscillator;Voltage-controlled oscillator connects voltage conversion detection circuit, generates clock signal;Voltage conversion detection circuit is converted into feedback voltage according to input clock signal, and generates feedback signal, is output to error amplifier.The application can solve the technical problems of long recovery time and poor dynamic performance caused by control voltage saturation in traditional frequency-locked loop.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a frequency-locked loop circuit and a processor. Background Technology

[0002] As automotive electronics, communication systems, and high-performance computing chips place increasingly higher demands on clock signal stability and response speed, frequency-locked loops (LLLs), as a key frequency management and synchronization circuit, are becoming increasingly important in terms of dynamic performance and robustness.

[0003] In traditional frequency-locked loop (LLL) architectures, a frequency-to-voltage converter is typically used to convert the frequency signal into a voltage signal. An error amplifier compares the feedback voltage with a reference voltage to adjust the control voltage, which in turn adjusts the frequency of the voltage-controlled oscillator (VCO), ultimately locking the output frequency to the target value. However, in such integral-structure-based control loops, the control voltage output by the error amplifier is prone to saturation (reaching the power supply voltage) when encountering large initial frequency deviations, power-on transients, or strong external disturbances. Once saturated, the control voltage loses its regulatory capability, causing the entire LLL to lose lock. Furthermore, the recovery time from saturation to the normal linear regulation region is lengthy, severely limiting the system's locking speed and dynamic performance. Summary of the Invention

[0004] This invention provides a frequency-locked loop circuit and processor to solve the technical problems of long recovery time and poor dynamic performance caused by control voltage saturation in traditional frequency-locked loops.

[0005] In a first aspect, embodiments of the present invention provide a frequency-locked loop circuit, comprising: an error amplifier, a voltage-controlled oscillator (VCO), an adaptive current charging / discharging circuit, and a voltage conversion detection circuit; wherein, the error amplifier is connected to the adaptive current charging / discharging circuit and outputs a control voltage and a reference voltage to the adaptive current charging / discharging circuit; the adaptive current charging / discharging circuit is connected to the VCO, compares the input control voltage and the reference voltage, generates a control signal, and outputs it to the VCO; the VCO is connected to the voltage conversion detection circuit and generates a clock signal; the voltage conversion detection circuit converts the input clock signal into a feedback voltage, generates a feedback signal, and outputs it to the error amplifier.

[0006] Optionally, the adaptive current charging and discharging circuit includes a hysteresis comparator and a controllable charging and discharging branch. The hysteresis comparator compares the input control voltage and the reference voltage, and generates a comparison signal to the controllable charging and discharging branch. The controllable charging and discharging branch dynamically adjusts the current path according to the comparison signal to control the control voltage.

[0007] Optionally, the controllable charge / discharge branch dynamically adjusts the current path based on the comparison signal to control the control voltage, including: a reference voltage including a first reference voltage and a second reference voltage; control signals including a first control signal, a second control signal, and a third control signal; when the control voltage is greater than the first reference voltage threshold, the controllable charge / discharge branch pulls the control voltage down, generates the first control signal, and outputs it to the voltage-controlled oscillator; when the control voltage is less than the second reference voltage threshold, the controllable charge / discharge branch pulls the control voltage up, generates the second control signal, and outputs it to the voltage-controlled oscillator; when the control voltage is within the hysteresis window range of the hysteresis comparator, the controllable charge / discharge branch is turned off, generates the third control signal, and outputs it to the voltage-controlled oscillator.

[0008] Optionally, the voltage-controlled oscillator is connected to a voltage conversion and detection circuit to generate a clock signal, including: the voltage-controlled oscillator generates a clock signal based on the input control signal and linearly adjusts its oscillation frequency in accordance with the control voltage.

[0009] Optionally, the voltage conversion detection circuit converts the input clock signal into a feedback voltage and generates a feedback signal, which is then output to the error amplifier. This includes: the voltage conversion detection circuit converts the clock signal into complementary first and second clock signals, converts the first and second clock signals into a feedback voltage related to the output frequency, generates a feedback signal, and outputs it to the error amplifier.

[0010] Optionally, the hysteresis comparator includes an overvoltage hysteresis comparator and an undervoltage hysteresis comparator. The comparison signal includes a first comparison signal and a second comparison signal. The overvoltage hysteresis comparator compares the control voltage and the first reference voltage and outputs the first comparison signal to the controllable charge-discharge branch. The undervoltage hysteresis comparator compares the control voltage and the second reference voltage and outputs the second comparison signal to the controllable charge-discharge branch. The controllable charge-discharge branch dynamically adjusts the current path according to the first comparison signal and the second comparison signal to raise or lower the control voltage.

[0011] Optionally, the overvoltage hysteresis comparator compares the control voltage and the first reference voltage and outputs a first comparison signal to the controllable charge / discharge branch, including: the first comparison signal being an overvoltage indication signal; when the overvoltage hysteresis comparator adjusts the control voltage to be greater than the first reference voltage threshold, it outputs the overvoltage indication signal, and the controllable charge / discharge branch starts the discharge path, causing the control voltage to be pulled down through internal current discharge; when the control voltage is within the hysteresis window range of the overvoltage hysteresis comparator, the overvoltage hysteresis comparator outputs an overvoltage indication signal at a high level, and the controllable charge / discharge branch is turned off.

[0012] Optionally, the undervoltage hysteresis comparator compares the control voltage and the second reference voltage, and outputs a second comparison signal to the controllable charge / discharge branch, including: the second comparison signal being an undervoltage indication signal; when the undervoltage hysteresis comparator adjusts the control voltage to be less than the second reference voltage threshold, the output undervoltage indication signal is low, the controllable charge / discharge branch starts the charging path, causing the control voltage to rise; when the control voltage is within the hysteresis window range of the undervoltage hysteresis comparator, the undervoltage hysteresis comparator outputs an undervoltage indication signal high, and the controllable charge / discharge branch is turned off.

[0013] Optionally, the overvoltage hysteresis comparator includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the first current source is connected between the power supply voltage and the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded; the gate of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the fourth NMOS transistor is grounded; the gate of the second NMOS transistor is connected to the gate of the third NMOS transistor, and both the sources of the second and third NMOS transistors are grounded, and the drain of the second NMOS transistor is connected to its gate; the source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor; the gates of the second and third PMOS transistors are both connected to the first NMOS transistor. The gates of the PMOS transistors are connected together, and the sources of the second and third PMOS transistors are both connected to the power supply voltage. The gates of the fourth and fifth PMOS transistors are both connected to the gate of the sixth PMOS transistor, and the sources of the fourth and fifth PMOS transistors are both connected to the power supply voltage. The gate of the fifth NMOS transistor is used to connect to the control voltage, and the drain of the fifth NMOS transistor is connected to the drain of the second and fourth PMOS transistors. The source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the sixth PMOS transistor is connected to the power supply voltage, and the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor. The gate of the sixth NMOS transistor is used to connect to the first reference voltage, and the drain of the sixth NMOS transistor is connected to the drain of the third and fifth PMOS transistors. The source of the sixth NMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the sixth PMOS transistor serves as the output terminal of the overvoltage hysteresis comparator, used to output the first comparison signal.

[0014] Optionally, the undervoltage hysteresis comparator includes a second current source, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; the source of the seventh NMOS transistor and the source of the twelfth NMOS transistor are grounded; the gates of the eighth NMOS transistor and the ninth NMOS transistor are both connected to the gate of the seventh NMOS transistor, and the sources of the eighth NMOS transistor and the ninth NMOS transistor are both grounded; the gates of the tenth NMOS transistor and the eleventh NMOS transistor are both connected to the gate of the twelfth NMOS transistor, and the sources of the tenth NMOS transistor and the eleventh NMOS transistor are both grounded. The source of the seventh PMOS transistor is connected to the power supply voltage, and its drain is connected to the first terminal of the second current source and the gate of the seventh PMOS transistor. The second terminal of the second current source is grounded. The gate of the eighth PMOS transistor is connected to the gate of the seventh PMOS transistor, and its source is connected to the power supply voltage. The source of the ninth PMOS transistor is connected to the power supply voltage, and its drain is connected to the drain of the seventh NMOS transistor and the gate of the ninth PMOS transistor. The gate of the tenth PMOS transistor is connected to the gate of the ninth PMOS transistor, its source is connected to the power supply voltage, and its drain is connected to the tenth NMOS transistor. The drain of the second NMOS transistor; the gate of the twelfth PMOS transistor is used to connect the control voltage, the drain of the twelfth PMOS transistor is connected to the drain of the eleventh NMOS transistor and the drain of the ninth NMOS transistor, and the source of the twelfth PMOS transistor is connected to the drain of the eighth PMOS transistor; the gate of the eleventh PMOS transistor is used to connect the second reference voltage, the drain of the eleventh PMOS transistor is connected to the drain of the eighth NMOS transistor and the drain of the tenth NMOS transistor, and the source of the eleventh PMOS transistor is connected to the drain of the eighth PMOS transistor; the drain of the tenth PMOS transistor serves as the output terminal of the undervoltage hysteresis comparator, used to output the second comparison signal.

[0015] Optionally, the controllable charge / discharge branch includes: a third current source, an inverter, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor; the gate of the thirteenth PMOS transistor is connected to the gates of the fourteenth PMOS transistor and the fifteenth PMOS transistor, the drain of the thirteenth PMOS transistor is connected to the first terminal of the third current source, and the source of the thirteenth PMOS transistor is connected to the sources of the fourteenth PMOS transistor and the fifteenth PMOS transistor, and is connected to the power supply voltage; the fourteenth PMOS transistor... The drain of the 13th NMOS transistor is connected to the drain of the 15th PMOS transistor; the drain of the 15th PMOS transistor is connected to the source of the 16th PMOS transistor; the first terminal of the inverter is connected to the first comparison signal, and the second terminal of the inverter is connected to the gate of the 13th NMOS transistor; the source of the 13th NMOS transistor is connected to the drain of the 14th NMOS transistor, the source of the 14th NMOS transistor is connected to the source of the 15th NMOS transistor, and grounded; the gate of the 16th PMOS transistor is connected to the second comparison signal, the drain of the 16th PMOS transistor is connected to the drain of the 15th NMOS transistor, and serves as the output terminal of the controllable charge / discharge branch for outputting control signals.

[0016] Optionally, the voltage conversion detection circuit includes a non-interactive clock generation circuit and a frequency-voltage converter; wherein, the non-interactive clock generation circuit is used to convert the clock signal output by the voltage-controlled oscillator into a complementary first clock signal and a second clock signal; the frequency-voltage converter is used to receive the first clock signal and the second clock signal output by the non-interactive clock generation circuit and convert them into a feedback voltage related to the output frequency.

[0017] Secondly, embodiments of the present invention provide a processor including a frequency-locked loop circuit provided in any embodiment of the present invention.

[0018] The frequency-locked loop circuit provided in this invention includes an error amplifier, a voltage-controlled oscillator (VCO), an adaptive current charging / discharging circuit, and a voltage conversion detection circuit. The adaptive current charging / discharging circuit compares the input control voltage with a reference voltage, generates a control signal, and outputs it to the VCO. This ensures the control voltage is always limited to a reasonable range suitable for the normal operation of the VCO, avoiding control voltage saturation and ensuring the frequency-locked loop is always adjustable. Compared to traditional solutions that rely on error amplifier integration for charging / discharging recovery, this circuit significantly shortens the saturation recovery time through instantaneous charging / discharging actions, greatly improving the frequency-locked loop's response speed to dynamic scenarios. Simultaneously, the dual-threshold judgment design accurately distinguishes between overvoltage, undervoltage, and normal states, effectively avoiding misjudgments caused by a single threshold. The adaptive current charging / discharging circuit only initiates adjustment actions when needed, reducing unnecessary power consumption. This allows the frequency-locked loop to maintain stable performance even in complex environments, making it suitable for applications with extremely high requirements for clock stability and dynamic performance, such as automotive electronic chips and high-speed communication modules, significantly improving the robustness and reliability of the frequency-locked loop.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a frequency-locked loop circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of an adaptive current charging and discharging circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of an overvoltage hysteresis comparator provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of an undervoltage hysteresis comparator provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a controllable charge / discharge branch provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a processor provided in an embodiment of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0024] Figure 1 This is a schematic diagram of a frequency-locked loop circuit provided in an embodiment of the present invention. Figure 1 As shown, the frequency-locked loop circuit includes: an error amplifier 10, a voltage-controlled oscillator 30, an adaptive current charging / discharging circuit 20, and a voltage conversion detection circuit 40. The error amplifier 10 is connected to the adaptive current charging / discharging circuit 20, outputting a control voltage Vctrl and a reference voltage to the adaptive current charging / discharging circuit 20. The adaptive current charging / discharging circuit 20 is connected to the voltage-controlled oscillator 30, comparing the input control voltage Vctrl with the reference voltage, generating a control signal, and outputting it to the voltage-controlled oscillator 30. The voltage-controlled oscillator 30 is connected to the voltage conversion detection circuit 40, generating a clock signal. The voltage conversion detection circuit 40 converts the input clock signal CLK_VCO into a feedback voltage Vfb, generates a feedback signal, and outputs it to the error amplifier 10.

[0025] Specifically, the frequency-locked loop circuit provided in this embodiment includes an error amplifier 10, a voltage-controlled oscillator 30, an adaptive current charging / discharging circuit 20, and a voltage conversion detection circuit 40. The error amplifier 10 receives the reference voltage Vref and the feedback voltage Vfb, amplifies their difference, and outputs a control voltage Vctrl to the adaptive current charging / discharging circuit 20; this control voltage Vctrl reflects the error between the current output frequency and the target frequency. The voltage-controlled oscillator 30 generates a clock signal CLK_VCO of a corresponding frequency based on the input control signal (i.e., the control voltage adjusted by the adaptive current charging / discharging circuit 20), and its oscillation frequency is linearly adjusted with the change of the control voltage. The voltage conversion detection circuit 40 converts the clock signal CLK_VCO output by the voltage-controlled oscillator 30 into a feedback voltage Vfb and sends it back to the error amplifier 10, thereby forming a closed-loop frequency regulation loop.

[0026] The adaptive current charging / discharging circuit 20 is a key improvement of this invention. Its main function is to dynamically intervene before the control voltage Vctrl approaches the power supply voltage or ground voltage, so as to maintain the control voltage Vctrl within the voltage range that the voltage-controlled oscillator 30 can normally adjust. The adaptive current charging / discharging circuit 20 monitors the control voltage Vctrl output by the error amplifier 10 in real time and compares it with a preset reference voltage. When the control voltage Vctrl is too high or too low, it automatically initiates the corresponding charging / discharging action to quickly bring the control voltage Vctrl back to a reasonable range. Specifically, when the control voltage Vctrl is greater than the overvoltage threshold, the adaptive current charging / discharging circuit 20 starts the discharging mechanism to lower the control voltage; when the control voltage Vctrl is less than the undervoltage threshold, the adaptive current charging / discharging circuit 20 starts the charging mechanism to raise the control voltage Vctrl; if the control voltage Vctrl is in the normal range, the adaptive current charging / discharging circuit 20 is in the off state, and does not affect the steady-state regulation of the control voltage Vctrl by the error amplifier 10.

[0027] Through the above methods, the adaptive current charging and discharging circuit 20 effectively avoids the problems of loop unlocking and slow recovery caused by the output saturation of the error amplifier in traditional frequency-locked loops. It can respond quickly in dynamic scenarios such as system power-on, frequency sudden changes, or strong disturbances, significantly shortening the time required for the loop to recover from saturation to normal locking, thereby improving the overall dynamic performance and locking speed of the frequency-locked loop. While maintaining loop adjustment accuracy, it enhances the system's adaptability and robustness to changes in operating conditions, making it particularly suitable for applications with strict requirements for clock stability and fast response, such as automotive electronics and high-speed communications.

[0028] The frequency-locked loop circuit provided in this invention includes an error amplifier, a voltage-controlled oscillator (VCO), an adaptive current charging / discharging circuit, and a voltage conversion detection circuit. The adaptive current charging / discharging circuit compares the input control voltage with a reference voltage, generates a control signal, and outputs it to the VCO. This ensures the control voltage is always limited to a reasonable range suitable for the normal operation of the VCO, avoiding control voltage saturation and ensuring the frequency-locked loop is always adjustable. Compared to traditional solutions that rely on error amplifier integration for charging / discharging recovery, this circuit significantly shortens the saturation recovery time through instantaneous charging / discharging actions, greatly improving the frequency-locked loop's response speed to dynamic scenarios. Simultaneously, the dual-threshold judgment design accurately distinguishes between overvoltage, undervoltage, and normal states, effectively avoiding misjudgments caused by a single threshold. The adaptive current charging / discharging circuit only initiates adjustment actions when needed, reducing unnecessary power consumption. This allows the frequency-locked loop to maintain stable performance even in complex environments, making it suitable for applications with extremely high requirements for clock stability and dynamic performance, such as automotive electronic chips and high-speed communication modules, significantly improving the robustness and reliability of the frequency-locked loop.

[0029] In some embodiments, the voltage-controlled oscillator 30 generates a clock signal CLK_VCO based on the input control signal and linearly adjusts its oscillation frequency in accordance with the control voltage.

[0030] In some embodiments, the voltage conversion detection circuit 40 converts the clock signal CLK_VCO into complementary first clock signal CLK1 and second clock signal CLK2, and converts the first clock signal CLK1 and second clock signal CLK2 into a feedback voltage Vfb related to the output frequency, and generates a feedback signal, which is output to the error amplifier 10.

[0031] Specifically, complementarity means that within one clock cycle, the high-level pulses of the first clock signal CLK1 and the second clock signal CLK2 are completely out of time, do not overlap, and have opposite phases.

[0032] Continue to refer to Figure 1 Optionally, the voltage conversion detection circuit 40 includes a non-interactive clock generation circuit 401 and a frequency-voltage converter 402; The non-interactive clock generation circuit 401 is used to convert the clock signal CLK_VCO output by the voltage-controlled oscillator 30 into a complementary first clock signal CLK1 and a second clock signal CLK2. The frequency-to-voltage converter 402 is used to receive the first clock signal CLK1 and the second clock signal CLK2 output by the non-interactive clock generation circuit 401, and convert them into a feedback voltage Vfb related to the output frequency.

[0033] Figure 2This is a schematic diagram of an adaptive current charging and discharging circuit provided in an embodiment of the present invention. Figure 2 As shown, the adaptive current charging and discharging circuit 20 includes a hysteresis comparator 11 and a controllable charging and discharging branch 12. The hysteresis comparator 11 compares the input control voltage Vctrl with the reference voltage and generates a comparison signal to the controllable charging and discharging branch 12. The controllable charging and discharging branch 12 dynamically adjusts the current path according to the comparison signal to control the control voltage Vctrl.

[0034] In some embodiments, the hysteresis comparator 11 includes an overvoltage hysteresis comparator 111 and an undervoltage hysteresis comparator 112. The comparison signals include a first comparison signal VO and a second comparison signal VU, and the reference voltages include a first reference voltage VDD1 and a second reference voltage VDD2. The overvoltage hysteresis comparator 111 compares the control voltage Vctrl with the first reference voltage VDD1 and outputs the first comparison signal VO to the controllable charge / discharge branch 12. The undervoltage hysteresis comparator 112 compares the control voltage Vctrl with the second reference voltage VDD2 and outputs the second comparison signal VU to the controllable charge / discharge branch 12. The controllable charge / discharge branch 12 dynamically adjusts the current path according to the first comparison signal VO and the second comparison signal VU, thereby raising or lowering the control voltage Vctrl.

[0035] Specifically, the first reference voltage VDD1 is a reference voltage used to determine whether the control voltage Vctrl is overvoltage. Its value needs to be set according to the normal operating voltage range of the voltage-controlled oscillator in the frequency-locked loop. For example, the first reference voltage VDD1 is lower than the power supply voltage VDD to prevent the control voltage Vctrl from saturating to the power supply voltage VDD. When the control voltage Vctrl is greater than the first reference voltage VDD1, it is determined to be an overvoltage state.

[0036] The second reference voltage VDD2 is a reference voltage used to determine whether the control voltage Vctrl is undervoltage, and its value also matches the normal operating range of the voltage-controlled oscillator. For example, the second reference voltage is higher than the ground voltage to prevent the control voltage Vctrl from saturating to ground. When the control voltage Vctrl is less than the second reference voltage VDD2, it is determined to be undervoltage. Optionally, the first reference voltage VDD1 is the power supply voltage VDD minus a preset voltage, and the second reference voltage VDD2 is the ground voltage plus a preset voltage.

[0037] Optionally, the first comparison signal VO is an overvoltage indication signal, and the second comparison signal VU is an undervoltage indication signal.

[0038] When the overvoltage hysteresis comparator 111 adjusts the control voltage to be greater than the first reference voltage threshold (i.e., the overvoltage threshold), the output overvoltage indication signal is low, and the controllable charge-discharge branch 12 starts the discharge path, causing the control voltage Vctrl to be pulled low through internal current discharge; when the control voltage Vctrl is within the hysteresis window range of the overvoltage hysteresis comparator 111, the overvoltage hysteresis comparator 111 outputs the overvoltage indication signal to be high, and the controllable charge-discharge branch 12 is turned off.

[0039] When the undervoltage hysteresis comparator 112 adjusts the control voltage Vctrl to be less than the second reference voltage threshold (i.e., the undervoltage threshold), the output undervoltage indication signal is low, and the controllable charge / discharge branch 12 starts the charging path, causing the control voltage Vctrl to be pulled high; when the control voltage Vctrl is within the hysteresis window range of the undervoltage hysteresis comparator 112, the output undervoltage indication signal of the undervoltage hysteresis comparator 112 is high, and the controllable charge / discharge branch 12 is turned off.

[0040] In some embodiments, the control signal includes a first control signal, a second control signal, and a third control signal; when the control voltage Vctrl is greater than the first reference voltage threshold, the controllable charge / discharge branch 12 pulls the control voltage Vctrl low, generates the first control signal, and outputs it to the voltage-controlled oscillator 30; when the control voltage Vctrl is less than the second reference voltage threshold, the controllable charge / discharge branch 12 pulls the control voltage high, generates the second control signal, and outputs it to the voltage-controlled oscillator 30; when the control voltage Vctrl is within the hysteresis window range of the hysteresis comparator, the controllable charge / discharge branch 12 is turned off, generates the third control signal, and outputs it to the voltage-controlled oscillator 30.

[0041] refer to Figure 1 and Figure 2 The operation of this frequency-locked loop circuit is as follows: When the control voltage Vctrl exceeds the first reference voltage threshold, it indicates that the control voltage Vctrl is close to the power rail, posing a risk of driving the error amplifier 10 into positive saturation. At this time, the overvoltage hysteresis comparator 111 outputs a low-level undervoltage indication signal, triggering the controllable charge / discharge branch 12 to open its discharge path. The discharge path can be formed by a controllable current discharge channel connected to the control node VN1, which can actively pull down the control voltage, thereby generating the first control signal and outputting it to the voltage-controlled oscillator 30.

[0042] Conversely, when the control voltage Vctrl is less than the second reference voltage threshold, it indicates that it is close to ground potential, posing a risk of driving the error amplifier 10 into negative saturation. At this time, the undervoltage hysteresis comparator 112 outputs a low-level undervoltage indication signal, triggering the controllable charge / discharge branch 12 to open its charging path. The charging path can be formed by a controllable current injection channel connected to the control node VN1, which can actively pull up the control voltage Vctrl, thereby generating a second control signal and outputting it to the voltage-controlled oscillator 30.

[0043] If the control voltage Vctrl is within the normal operating window (i.e., the hysteresis window) defined by the first and second reference voltage thresholds, both hysteresis comparators output invalid signals (such as high level). At this time, the charging and discharging paths of the controllable charge / discharge branch are closed, preventing active charging / discharging interference to the control node VN1. The stable value of the control voltage is determined solely by the error amplifier 10, without introducing additional current interference. This maintains high-precision adjustment within the small error range of the frequency-locked loop while avoiding unnecessary noise and oscillations. In this state, the controllable charge / discharge branch 12 generates a third control signal and outputs it to the voltage-controlled oscillator 30.

[0044] As a preferred embodiment of the present invention, Figure 3 This is a schematic diagram of an overvoltage hysteresis comparator provided in an embodiment of the present invention. Figure 3 As shown, the overvoltage hysteresis comparator 111 includes: a first current source Iref1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6.

[0045] The first current source Iref1 is connected between the power supply voltage VDD and the drain of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded. The gate of the fourth NMOS transistor MN4 is connected to the gate of the first NMOS transistor MN1, and the source of the fourth NMOS transistor MN4 is grounded.

[0046] The gates of the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected, and the sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are both grounded; the drain of the second NMOS transistor MN2 is connected to its gate.

[0047] The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD, and the drain of the first PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2. The gates of the second PMOS transistor MP2 and the third PMOS transistor MP3 are both connected to the gate of the first PMOS transistor MP1, and the sources of the second PMOS transistor MP2 and the third PMOS transistor MP3 are both connected to the power supply voltage VDD; the gates of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are both connected to the gate of the sixth PMOS transistor MP6, and the sources of the second PMOS transistor MP2 and the third PMOS transistor MP3 are both connected to the power supply voltage VDD. The gate of the fifth NMOS transistor MN5 is used to connect to the control voltage Vctrl. The drain of the fifth NMOS transistor MN5 is connected to the drain of the second PMOS transistor MP2 and the drain of the fourth PMOS transistor MP4. The source of the fifth NMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS transistor MP6 is connected to the drain of the third NMOS transistor MN3. The gate of the sixth NMOS transistor MN6 is used to connect to the first reference voltage VDD1. The drain of the sixth NMOS transistor MN6 is connected to the drain of the third PMOS transistor MP3 and the drain of the fifth PMOS transistor MP5. The source of the sixth NMOS transistor MN6 is connected to the drain of the fourth NMOS transistor MN4. The drain of the sixth PMOS transistor MP6 serves as the output terminal of the overvoltage hysteresis comparator 111, outputting the first comparison signal VO.

[0048] Specifically, the overvoltage hysteresis comparator 111 is a precision analog comparator circuit based on a differential input and positive feedback structure. Its function is to detect whether the control voltage Vctrl exceeds the preset first reference voltage VDD1 and output the first comparison signal VO to drive the subsequent controllable charging and discharging branch 12.

[0049] The first current source Iref1 and the first NMOS transistor MN1 together establish the bias current for the entire overvoltage hysteresis comparator 111. The first NMOS transistor MN1 and the fourth NMOS transistor MN4 form a current mirror. The fourth NMOS transistor MN4 acts as a tail current source, providing a constant tail current for the input differential pair (the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6). The gate of the fifth NMOS transistor MN5 is connected to the control voltage Vctrl to be monitored, and the gate of the sixth NMOS transistor MN6 is connected to a fixed first reference voltage VDD1. The two form the differential input pair of the overvoltage hysteresis comparator 111. The gates of the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected, and together with the first PMOS transistor MP1, they form a startup and bias circuit. The first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 form a PMOS current mirror network, serving as the active load of the differential pair. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 constitute another PMOS current mirror and output stage. The drain of the sixth PMOS transistor MP6 is the output node of the overvoltage hysteresis comparator 111, which is used to generate the first comparison signal VO.

[0050] When the control voltage Vctrl is greater than the first reference voltage VDD1, the gate voltage of the fifth NMOS transistor MN5 in the input differential pair is greater than the gate voltage of the sixth NMOS transistor MN6. Since the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 share the tail current source of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 will conduct more current, while the current of the sixth NMOS transistor MN6 will decrease accordingly. This causes the current flowing through the second PMOS transistor MP2 (which acts as the load of the fifth NMOS transistor MN5) to increase, and its drain voltage is pulled low. This low-level signal is transmitted to the gate of the fourth PMOS transistor MP4 on the one hand, and affects the gate potential of the sixth PMOS transistor MP6 through internal connections on the other hand. Through positive feedback, the sixth PMOS transistor MP6 is finally fully turned on, strongly pulling the output node (drain of the sixth PMOS transistor) of the overvoltage hysteresis comparator 111 to the power supply voltage VDD. Therefore, the overvoltage hysteresis comparator 111 outputs a high-level first comparison signal VO.

[0051] When the control voltage Vctrl is within the hysteresis window of the overvoltage hysteresis comparator 111, the gate voltage of the sixth NMOS transistor MN6 in the input differential pair is higher than the gate voltage of the fifth NMOS transistor MN5, causing the sixth NMOS transistor MN6 to conduct more current. This increases the current flowing through the third PMOS transistor MP3 (which acts as the load of the sixth NMOS transistor MN6), pulling its drain voltage low. This low-level signal is transmitted to the gates of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, forcing the sixth PMOS transistor MP6 to turn off. Because the sixth PMOS transistor MP6 is off, the output node of the overvoltage hysteresis comparator 111 is pulled low (typically through an internal or subsequent circuit discharge path). Therefore, the overvoltage hysteresis comparator 111 outputs a low-level first comparison signal VO.

[0052] Figure 4 This is a schematic diagram of an undervoltage hysteresis comparator provided in an embodiment of the present invention. Figure 4 As shown, the undervoltage hysteresis comparator 112 includes a second current source Iref2, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, and a twelfth PMOS transistor MP12; Among them, the source of the seventh NMOS transistor MN7 and the source of the twelfth NMOS transistor MN12 are grounded; the gates of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are both connected to the gate of the seventh NMOS transistor MN7, and the sources of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are both grounded; the gates of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are both connected to the gate of the twelfth NMOS transistor MN10, and the sources of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are both grounded. The source of the seventh PMOS transistor MP7 is connected to the power supply voltage VDD, and the drain of the seventh PMOS transistor MP7 is connected to the first terminal of the second current source Iref2 and the gate of the seventh PMOS transistor MP7. The second terminal of the second current source Iref2 is grounded. The gate of the eighth PMOS transistor MP8 is connected to the gate of the seventh PMOS transistor MP7, and the source of the eighth PMOS transistor MP8 is connected to the power supply voltage VDD. The source of the ninth PMOS transistor MP9 is connected to the power supply voltage VDD, and the drain of the ninth PMOS transistor MP9 is connected to the drain of the seventh NMOS transistor MN7 and the gate of the ninth PMOS transistor MP9. The gate of the tenth PMOS transistor MP10 is connected to the gate of the ninth PMOS transistor MP9, the source of the tenth PMOS transistor MP10 is connected to the power supply voltage VDD, and the drain of the tenth PMOS transistor MP10 is connected to the drain of the twelfth NMOS transistor MN12. The gate of the twelfth PMOS transistor MP12 is used to connect to the control voltage Vctrl. The drain of the twelfth PMOS transistor MP12 is connected to the drain of the eleventh NMOS transistor MN11 and the drain of the ninth NMOS transistor MN9. The source is connected to the drain of the eighth PMOS transistor MP8. The gate of the eleventh PMOS transistor MP11 is used to connect to the second reference voltage VDD2. The drain of the eleventh PMOS transistor MP11 is connected to the drain of the eighth NMOS transistor MN8 and the drain of the tenth NMOS transistor MN10. The source of the eleventh PMOS transistor MP11 is connected to the drain of the eighth PMOS transistor MP8.

[0053] The drain of the tenth PMOS transistor MP10 serves as the output terminal of the undervoltage hysteresis comparator 112, outputting the second comparison signal VU.

[0054] Specifically, the undervoltage hysteresis comparator 112 also employs a differential input and positive feedback structure to ensure reliable hysteresis characteristics. The second current source Iref2, together with the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7, establishes the reference bias. The seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 form a current mirror, providing operating current to the input stage. The ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 form another current mirror, serving as the load and gain stage for the output stage.

[0055] The input stage consists of a differential pair of PMOS transistors: the gate of the twelfth PMOS transistor MP12 is connected to the control voltage Vctrl to be monitored, and the gate of the eleventh PMOS transistor MP11 is connected to a fixed second reference voltage VDD2. The eighth NMOS transistor MN8 and the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 respectively form two sets of current mirrors, which are used to conduct and mirror the output current of the differential pair and transmit the signal to the output node of the undervoltage hysteresis comparator 112.

[0056] When the control voltage Vctrl is less than the second reference voltage VDD2, in the input differential pair, the gate voltage of the twelfth PMOS transistor MP12 is lower than the gate voltage of the eleventh PMOS transistor MP11. Due to the characteristics of PMOS transistors, the twelfth PMOS transistor MP12 will conduct more strongly than the eleventh PMOS transistor MP11, thus allowing more current to flow through the twelfth PMOS transistor MP12, mirrored from the eighth PMOS transistor MP8. This current is then mirrored by the ninth NMOS transistor MN9 and affects the gate potential of the ninth PMOS transistor MP9. Through the internal positive feedback path, this ultimately causes the tenth PMOS transistor MP10 to turn off completely. With the tenth PMOS transistor MP10 off, its drain (i.e., the output node of the undervoltage hysteresis comparator 112) is pulled low by the pull-down path of the internal or subsequent circuitry. Therefore, the undervoltage hysteresis comparator 112 outputs a low-level second comparison signal VU.

[0057] When the control voltage Vctrl is within the hysteresis window of the undervoltage hysteresis comparator 112, the gate voltage of the eleventh PMOS transistor MP11 in the input differential pair is lower than that of the twelfth PMOS transistor MP12, resulting in stronger conduction of the eleventh PMOS transistor MP11. Current mainly flows through the eleventh PMOS transistor MP11 and is mirrored by the eighth NMOS transistor MN8, thus affecting the state of the internal nodes of the circuit. Through positive feedback, the tenth PMOS transistor MP10 is eventually fully turned on, pulling the output node up to the power supply voltage VDD. Therefore, the undervoltage hysteresis comparator 112 outputs a high-level second comparison signal VU.

[0058] Figure 5 This is a schematic diagram of a controllable charge / discharge branch provided in an embodiment of the present invention. Figure 5 As shown, optionally, the controllable charging and discharging branch 12 includes: a third current source Iref3, an inverter U1, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, and a fifteenth NMOS transistor MN15; The gate of the thirteenth PMOS transistor MP13 is connected to the gate of the fourteenth PMOS transistor MP14 and the gate of the fifteenth PMOS transistor MP15. The drain of the thirteenth PMOS transistor MP13 is connected to the first terminal of the third current source Iref3. The source of the thirteenth PMOS transistor MP13 is connected to the source of the fourteenth PMOS transistor MP14 and the source of the fifteenth PMOS transistor MP15, and is connected to the power supply voltage VDD. The drain of the fourteenth PMOS transistor MP14 is connected to the drain of the thirteenth NMOS transistor MN13; the drain of the fifteenth PMOS transistor MP15 is connected to the source of the sixteenth PMOS transistor MP16. The first terminal of inverter U1 is connected to the first comparison signal VO, and the second terminal of inverter U1 is connected to the gate of the thirteenth NMOS transistor MN13. The source of the thirteenth NMOS transistor MN13 is connected to the drain of the fourteenth NMOS transistor MN14, and the source of the fourteenth NMOS transistor MN14 is connected to the source of the fifteenth NMOS transistor MN15, and grounded. The gate of the sixteenth PMOS transistor MP16 is connected to the second comparison signal VU, and the drain of the sixteenth PMOS transistor MP16 is connected to the drain of the fifteenth NMOS transistor MN15, serving as the output terminal of the controllable charge-discharge branch 12 for outputting control signals.

[0059] Specifically, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, and the fifteenth PMOS transistor MP15 form a three-output PMOS current mirror. The thirteenth PMOS transistor MP13 acts as the input transistor, mirroring its drain current (i.e., the current of the third current source Iref3) to the drain branches of the fourteenth and fifteenth PMOS transistors MP14 and MP15. The gate of the sixteenth PMOS transistor MP16 is directly controlled by the second comparator signal VU, serving as the master switch for the charging path. The gate of the thirteenth NMOS transistor MN13 is controlled by the first comparator signal VO via an inverter U1, serving as the master switch for the discharging path. The fourteenth and fifteenth NMOS transistors MN14 and MN15 form an NMOS current mirror, with MN14 as the input transistor and MN15 as the output transistor, used to provide a controlled pull-down current proportional to the reference current during discharge.

[0060] When the control voltage Vctrl is greater than the first reference voltage threshold, the first comparison signal VO output by the overvoltage hysteresis comparator 111 is low. This signal is inverted by inverter U1 and becomes high, turning on the thirteenth NMOS transistor MN13. At this time, the current mirrored from the fourteenth PMOS transistor MP14 flows through the thirteenth NMOS transistor MN13 and acts as the input current for the fourteenth NMOS transistor MN14. This current is mirrored by the fifteenth NMOS transistor MN15, forming a discharge path from the control node VN1 (connected to the drain of the sixteenth PMOS transistor MP16 and the drain of the fifteenth NMOS transistor MN15) to ground, thereby actively and quickly pulling down the control voltage Vctrl, preventing it from continuously rising and causing the error amplifier to enter positive saturation.

[0061] When the control voltage Vctrl is less than the second reference voltage threshold, the second comparison signal VU output by the undervoltage hysteresis comparator 112 is low. This signal directly turns on the sixteenth PMOS transistor MP16. Simultaneously, the fifteenth PMOS transistor MP15 is normally on due to its gate potential being biased by the current mirror. At this time, the power supply voltage VDD injects current into the control node VN1 through the series path formed by the sixteenth PMOS transistor MP16 and the fifteenth PMOS transistor MP15, forming a charging path. This actively and quickly pulls the control voltage Vctrl high, preventing it from continuously decreasing and causing the error amplifier to enter negative saturation.

[0062] When the control voltage Vctrl is within the hysteresis window of the hysteresis comparator, both the first comparison signal VO and the second comparison signal VU are high. On one hand, the high-level first comparison signal VO is output as a low level after passing through the inverter U1, turning off the thirteenth NMOS transistor MN13 and disabling the discharge path. On the other hand, the high-level second comparison signal VU turns off the sixteenth PMOS transistor MP16, also disabling the charging path. Therefore, the output of the controllable charge / discharge branch 12 presents a high-impedance state, producing no active charging or discharging effect on the control node VN1. The frequency-locked loop is finely adjusted by the error amplifier 10 through its own negative feedback mechanism, ensuring high accuracy and low noise performance of the frequency-locked loop in a stable state.

[0063] Based on the same inventive concept, embodiments of the present invention also provide a processor. Figure 6 This is a schematic diagram of the structure of a processor provided in an embodiment of the present invention. Figure 6 As shown, the processor 600 includes a frequency-locked loop circuit 610 as provided in any embodiment of the present invention, and has the same functional modules and beneficial effects as the frequency-locked loop circuit 610. This embodiment will not be described in detail here.

[0064] The processor described here is a broad concept. Processor 600 is a circuit with signal processing capabilities. In one implementation, processor 600 can be a circuit with instruction read and execute capabilities, such as a central processing unit (CPU), microprocessor, graphics processing unit (GPU) (which can be understood as a type of microprocessor), or digital signal processor (DSP). In another implementation, processor 610 can implement certain functions through the logical relationships of hardware circuits. These logical relationships are fixed or reconfigurable. For example, processor 600 could be a hardware circuit implemented as an ASIC or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration file and configuring the hardware circuit can be understood as the processor loading instructions to implement the functions of some or all of the above modules. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), or deep learning processing unit (DPU). The processor 600 is used to execute related programs to implement the functions required by the units in the efficiency lane-changing capability assessment device of this application embodiment, or to execute the efficiency lane-changing capability assessment method of this application method embodiment.

[0065] As can be seen, each module in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor types.

[0066] Furthermore, the modules in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these modules are integrated together as a system-on-a-chip (SOC). The SOC may include at least one processor for implementing any of the above methods or for implementing the functions of the modules of the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0067] The frequency-locked loop circuit 610 significantly improves the clock stability, dynamic response, and overall reliability of the integrated processor under complex operating conditions through its anti-saturation self-recovery mechanism.

[0068] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

[0069] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0070] It should also be noted that, in this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified. The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A frequency-locked loop circuit, characterized in that, include: The circuit includes an error amplifier, a voltage-controlled oscillator, an adaptive current charging / discharging circuit, and a voltage conversion and detection circuit; the error amplifier is connected to the adaptive current charging / discharging circuit and outputs control voltage and reference voltage to the adaptive current charging / discharging circuit. The adaptive current charging and discharging circuit is connected to the voltage-controlled oscillator, compares the input control voltage with the reference voltage, generates a control signal, and outputs it to the voltage-controlled oscillator. A voltage-controlled oscillator is connected to a voltage conversion and detection circuit to generate a clock signal; The voltage conversion and detection circuit converts the input clock signal into a feedback voltage and generates a feedback signal, which is then output to the error amplifier.

2. The frequency-locked loop circuit according to claim 1, characterized in that, The adaptive current charging and discharging circuit includes a hysteresis comparator and a controllable charging and discharging branch. The hysteresis comparator compares the input control voltage and the reference voltage and generates a comparison signal to the controllable charging and discharging branch. The controllable charging and discharging branch dynamically adjusts the current path according to the comparison signal to control the control voltage.

3. The frequency-locked loop circuit according to claim 2, characterized in that, The controllable charge / discharge branch dynamically adjusts the current path based on the comparison signal to control the control voltage, including: The reference voltage includes a first reference voltage and a second reference voltage; the control signal includes a first control signal, a second control signal, and a third control signal; When the control voltage is greater than the first reference voltage threshold, the controllable charge and discharge branch pulls the control voltage down, generates the first control signal and outputs it to the voltage-controlled oscillator. When the control voltage is less than the second reference voltage threshold, the controllable charge and discharge branch pulls the control voltage up, generates a second control signal and outputs it to the voltage-controlled oscillator. When the control voltage is within the hysteresis window range of the hysteresis comparator, the controllable charge / discharge branch is closed, generating a third control signal and outputting it to the voltage-controlled oscillator.

4. The frequency-locked loop circuit according to claim 1, characterized in that, A voltage-controlled oscillator is connected to a voltage conversion and detection circuit to generate a clock signal, including: The voltage-controlled oscillator generates a clock signal based on the input control signal and adjusts its oscillation frequency linearly in accordance with the control voltage.

5. The frequency-locked loop circuit according to claim 1, characterized in that, The voltage conversion detection circuit converts the input clock signal into a feedback voltage and generates a feedback signal, which is then output to the error amplifier. The circuit includes: converting the clock signal into a complementary first clock signal and a second clock signal, converting the first clock signal and the second clock signal into a feedback voltage related to the output frequency, generating a feedback signal, and outputting it to the error amplifier.

6. The frequency-locked loop circuit according to claim 3, characterized in that, The hysteresis comparator includes an overvoltage hysteresis comparator and an undervoltage hysteresis comparator. The comparison signals include a first comparison signal and a second comparison signal. The overvoltage hysteresis comparator compares the control voltage and a first reference voltage and outputs the first comparison signal to the controllable charge-discharge branch. The undervoltage hysteresis comparator compares the control voltage and a second reference voltage and outputs the second comparison signal to the controllable charge-discharge branch. The controllable charge-discharge branch dynamically adjusts the current path according to the first comparison signal and the second comparison signal to raise or lower the control voltage.

7. The frequency-locked loop circuit according to claim 6, characterized in that, The overvoltage hysteresis comparator compares the control voltage and the first reference voltage, and outputs a first comparison signal to the controllable charge / discharge branch, including: The first comparison signal is an overvoltage indication signal; When the overvoltage hysteresis comparator adjusts the control voltage to be greater than the first reference voltage threshold, it outputs an overvoltage indication signal, and the controllable charge and discharge branch starts the discharge path, so that the control voltage is pulled down through internal current discharge. When the control voltage is within the hysteresis window range of the overvoltage hysteresis comparator, the overvoltage hysteresis comparator outputs an overvoltage indication signal at a high level, and the controllable charge and discharge branch is closed.

8. The frequency-locked loop circuit according to claim 6, characterized in that, The undervoltage hysteresis comparator compares the control voltage and the second reference voltage, and outputs a second comparison signal to the controllable charge / discharge branch, including: The second comparison signal is an undervoltage indication signal; When the undervoltage hysteresis comparator adjusts the control voltage to be less than the second reference voltage threshold, the output undervoltage indication signal is low, and the controllable charge and discharge branch starts the charging path, causing the control voltage to be pulled up. When the control voltage is within the hysteresis window range of the undervoltage hysteresis comparator, the undervoltage hysteresis comparator outputs an undervoltage indication signal at a high level, and the controllable charge and discharge branch is closed.

9. The frequency-locked loop circuit according to claim 6, characterized in that, The overvoltage hysteresis comparator includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The first current source is connected between the power supply voltage and the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded. The gate of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the fourth NMOS transistor is grounded. The gate of the second NMOS transistor is connected to the gate of the third NMOS transistor. The source of the second NMOS transistor and the source of the third NMOS transistor are both grounded. The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor. The gates of the second and third PMOS transistors are both connected to the gate of the first PMOS transistor, and the sources of the second and third PMOS transistors are both connected to the power supply voltage; the gates of the fourth and fifth PMOS transistors are both connected to the gate of the sixth PMOS transistor, and the sources of the fourth and fifth PMOS transistors are both connected to the power supply voltage. The gate of the fifth NMOS transistor is used to receive the control voltage. The drain of the fifth NMOS transistor is connected to the drain of the second PMOS transistor and the drain of the fourth PMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the sixth PMOS transistor is connected to the power supply voltage, and the drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor. The gate of the sixth NMOS transistor is used to connect to the first reference voltage. The drain of the sixth NMOS transistor is connected to the drain of the third PMOS transistor and the drain of the fifth PMOS transistor. The source of the sixth NMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the sixth PMOS transistor serves as the output terminal of the overvoltage hysteresis comparator, used to output the first comparison signal.

10. The frequency-locked loop circuit according to claim 6, characterized in that, The undervoltage hysteresis comparator includes a second current source, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; The source of the seventh NMOS transistor and the source of the twelfth NMOS transistor are grounded; the gates of the eighth and ninth NMOS transistors are connected to the gate of the seventh NMOS transistor, and the sources of the eighth and ninth NMOS transistors are grounded; the gates of the tenth and eleventh NMOS transistors are connected to the gate of the twelfth NMOS transistor, and the sources of the tenth and eleventh NMOS transistors are grounded. The source of the seventh PMOS transistor is connected to the power supply voltage, and the drain of the seventh PMOS transistor is connected to the first terminal of the second current source and the gate of the seventh PMOS transistor. The second terminal of the second current source is grounded. The gate of the eighth PMOS transistor is connected to the gate of the seventh PMOS transistor, and the source of the eighth PMOS transistor is connected to the power supply voltage. The source of the ninth PMOS transistor is connected to the power supply voltage, and the drain of the ninth PMOS transistor is connected to the drain of the seventh NMOS transistor and the gate of the ninth PMOS transistor. The gate of the tenth PMOS transistor is connected to the gate of the ninth PMOS transistor, the source of the tenth PMOS transistor is connected to the power supply voltage, and the drain of the tenth PMOS transistor is connected to the drain of the twelfth NMOS transistor. The gate of the twelfth PMOS transistor is used to receive the control voltage. The drain of the twelfth PMOS transistor is connected to the drain of the eleventh NMOS transistor and the drain of the ninth NMOS transistor. The source of the twelfth PMOS transistor is connected to the drain of the eighth PMOS transistor. The gate of the eleventh PMOS transistor is used to connect to the second reference voltage. The drain of the eleventh PMOS transistor is connected to the drain of the eighth NMOS transistor and the drain of the tenth NMOS transistor. The source of the eleventh PMOS transistor is connected to the drain of the eighth PMOS transistor. The drain of the tenth PMOS transistor serves as the output terminal of the undervoltage hysteresis comparator, used to output the second comparison signal.

11. The frequency-locked loop circuit according to claim 6, characterized in that, The controllable charging and discharging branch includes: a third current source, an inverter, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor; The gate of the thirteenth PMOS transistor is connected to the gate of the fourteenth PMOS transistor and the gate of the fifteenth PMOS transistor. The drain of the thirteenth PMOS transistor is connected to the first terminal of the third current source. The source of the thirteenth PMOS transistor is connected to the source of the fourteenth PMOS transistor and the source of the fifteenth PMOS transistor, and is connected to the power supply voltage. The drain of the fourteenth PMOS transistor is connected to the drain of the thirteenth NMOS transistor; the drain of the fifteenth PMOS transistor is connected to the source of the sixteenth PMOS transistor. The first terminal of the inverter is connected to the first comparison signal, and the second terminal of the inverter is connected to the gate of the thirteenth NMOS transistor. The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source of the fourteenth NMOS transistor is connected to the source of the fifteenth NMOS transistor and grounded. The gate of the sixteenth PMOS transistor is connected to the second comparison signal, and the drain of the sixteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor, serving as the output terminal of the controllable charge and discharge branch for outputting control signals.

12. The frequency-locked loop circuit according to claims 1-11, characterized in that, The voltage conversion detection circuit includes a non-interactive clock generation circuit and a frequency-to-voltage converter; The non-interactive clock generation circuit is used to convert the clock signal output by the voltage-controlled oscillator into a complementary first clock signal and a second clock signal. The frequency-to-voltage converter is used to receive the first clock signal and the second clock signal output by the non-interactive clock generation circuit and convert them into a feedback voltage related to the output frequency.

13. A processor, characterized in that, Includes the frequency-locked loop circuit as described in any one of claims 1-12.

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