A decoding method, program product, medium and electronic device
Patent Information
- Application Number
- CN202611055815.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-15
- Publication Date
- 2026-09-25
AI Technical Summary
[0004]本申请实施例提供了一种译码方法及装置、程序产品、存储介质，以至少解决现有技术中Chase译码算法运算量随符号数增加呈指数增长，导致终端实时处理计算量大、功耗较高的问题
[0026]应用本申请的技术方案，通过基于接收的符号软信息序列确定符号位置索引，并将该索引用于限定试探序列中需要翻转的位置，进而生成对应于特定翻转状态的试探序列集，从而将译码搜索范围从全量搜索缩减为基于符号位置索引确定的特定翻转状态；随后基于该试探序列集及符号软信息序列的硬判决序列确定得到候选码字，并通过计算每个候选码字与符号软信息序列的相关度量值，在有限的候选码字中选出最优解作为译码输出。该方案通过减少需要处理的试探序列数量，直接降低了计算量，从而解决了现有技术中Chase译码算法运算量随符号数增加呈指数增长，导致终端实时处理计算量大、功耗较高的技术问题，达到降低终端功耗、提升实时处理效率的效果。
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Figure CN122824232A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and more specifically, to a decoding method, program product, medium, and electronic device. Background Technology
[0002] In satellite mobile communication systems, the Broadcast Alarm Channel (BACH) typically employs Reed-Solomon codes (such as RS(15,9) codes) combined with soft-decision decoding techniques to enhance the system's anti-interference capability and reliability in complex channel environments. The Chase algorithm, a classic soft-decision decoding method, approximates maximum likelihood decoding performance by generating a finite number of trial sequences. When decoding in the GF(2^4) domain, the traditional Chase algorithm usually requires traversing and searching all possible flip states of unreliable symbols in the received sequence. For example, under certain configurations, it may be necessary to generate and process 2^6 = 64 trial sequences to find the candidate codeword with the smallest Euclidean distance as the final decoded output.
[0003] However, the aforementioned traditional technologies have significant drawbacks when applied to resource-constrained satellite communication terminals. Because the computational complexity of the Chase algorithm increases exponentially with the number of trial sequences to be traversed, the entire search process results in a massive real-time processing load for the terminal device, leading to high power consumption and long decoding latency. Especially in scenarios where BACH channels have high requirements for real-time performance and energy efficiency, this highly complex decoding method struggles to meet the terminal's low-power, low-latency processing needs. Therefore, an improved solution that can significantly reduce computational complexity while maintaining high decoding performance is urgently needed. Summary of the Invention
[0004] This application provides a decoding method, apparatus, program product, and storage medium to at least solve the problem that the computational workload of the Chase decoding algorithm in the prior art increases exponentially with the number of symbols, resulting in high computational workload and high power consumption in real-time terminal processing.
[0005] According to one embodiment of this application, a decoding method is provided, the method comprising:
[0006] The symbol position index is determined based on the received symbol soft information sequence;
[0007] Based on the symbol position index, a set of trial sequences is generated, wherein each trial sequence in the set corresponds to a flip state of the symbol position index;
[0008] Candidate codewords are determined based on the hard decision sequence of the set of trial sequences and the symbol soft information sequence;
[0009] Determine the correlation metric between each candidate codeword and the symbol soft information sequence, and determine the decoding output based on the correlation metric.
[0010] Further, determining the symbol position index based on the received symbol soft information sequence includes:
[0011] The reliability of each symbol is calculated based on the received symbol soft information sequence;
[0012] The symbols are sorted in ascending order according to their reliability, and the positions of a set number of symbols with the lowest reliability are selected as the symbol position indices.
[0013] Further, the step of determining candidate codewords based on the hard decision sequence of the trial sequence set and the symbol soft information sequence includes:
[0014] For each of the aforementioned trial sequences, an XOR operation is performed between it and the hard decision sequence of the received sequence to obtain the modified hard decision sequence;
[0015] The modified hard decision sequence is input into a hard decision decoder for decoding to obtain the candidate codeword.
[0016] Further, determining the decoding output based on the relevant metric value includes:
[0017] The candidate codeword with the largest value among the relevant metrics is selected as the decoding output.
[0018] Furthermore, the hard-decision decoder is constructed and generated on the Galois domain GF(2^4). The hard-decision decoder has 9 information symbols, a code length of 15 symbols, an error correction capability of 3, and a minimum distance of 7.
[0019] Furthermore, the formula for determining the relevant metric is as follows:
[0020]
[0021] in, Map the codewords to ±1. This represents the j-th bit of the i-th candidate codeword. This represents the symbol voltage value at the j-th bit in the symbol soft information sequence.
[0022] Furthermore, after inputting the modified hard decision sequence into the hard decision decoder for decoding, the method further includes: if the hard decision decoder fails to decode, the corresponding candidate codeword is discarded.
[0023] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.
[0024] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.
[0025] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.
[0026] By applying the technical solution of this application, a symbol position index is determined based on the received symbol soft information sequence, and this index is used to limit the positions that need to be flipped in the trial sequence, thereby generating a trial sequence set corresponding to a specific flip state. This reduces the decoding search range from a full search to a specific flip state determined based on the symbol position index. Subsequently, candidate codewords are determined based on the hard decision sequence of the trial sequence set and the symbol soft information sequence. By calculating the correlation metric between each candidate codeword and the symbol soft information sequence, the optimal solution is selected as the decoding output from the limited number of candidate codewords. This solution directly reduces the computational load by reducing the number of trial sequences that need to be processed, thus solving the technical problem in the prior art where the computational load of the Chase decoding algorithm increases exponentially with the number of symbols, resulting in high computational load and high power consumption in real-time terminal processing. This achieves the effect of reducing terminal power consumption and improving real-time processing efficiency. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of the hardware environment for a decoding method according to an embodiment of this application;
[0028] Figure 2 This is a flowchart of a decoding method according to an embodiment of this application;
[0029] Figure 3 This is a schematic diagram of the system structure of a decoding method according to an embodiment of this application;
[0030] Figure 4 This is a structural block diagram of an electronic device according to an embodiment of this application. Detailed Implementation
[0031] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.
[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0033] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a schematic diagram of the hardware environment for a decoding method according to an embodiment of this application. For example... Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.
[0034] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to a decoding method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
[0035] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.
[0036] This embodiment provides a decoding method. Figure 2 This is a flowchart of a decoding method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:
[0037] Step S202: Determine the symbol position index based on the received symbol soft information sequence;
[0038] In this embodiment, the symbol soft information sequence can be a sequence containing multiple symbol soft information output by the demodulator. The symbol position index is information output by the reliability sorting module that identifies the position of the symbol with the lowest reliability in the sequence.
[0039] In this embodiment, the first step is to process the received symbol soft information sequence. The core objective is to transform this continuous soft information data into symbol position indices with clear physical meaning. By analyzing the numerical characteristics of each symbol in the soft information sequence, the specific positions of symbols with low reliability or in a critical state are identified and located within the sequence, thus providing precise spatial coordinates for the subsequent generation of probe sequences. Here, the soft information sequence carries continuous domain data such as amplitude, phase, or voltage of symbols during channel transmission, reflecting the reliability of the received signal. By extracting these position indices, it is possible to identify which symbols are key nodes with significant interference or a high probability of demodulation error. This is the premise and foundation for subsequently generating targeted probe sequences with approximate maximum likelihood decoding performance.
[0040] Step S204: Based on the symbol position index, generate a set of trial sequences, wherein each trial sequence in the set corresponds to a flip state of the symbol position index.
[0041] In this embodiment, the trial sequence set is a collection of trial sequences generated by the trial sequence generator based on multiple symbol positions. A trial sequence is a single element constituting the trial sequence set. A flip state can be a 0 or 1 state change performed on the symbol positions with the lowest reliability (such as pos1, pos2, pos3) during the generation of the trial sequence. In the Chase algorithm, this corresponds to a bit-flipping operation on these least reliable symbols, thereby generating different candidate correction modes.
[0042] In this embodiment, based on the symbol position index determined in the preceding steps, a set containing multiple trial sequences is constructed, wherein each trial sequence in the set corresponds one-to-one with a specific flip combination state of a set of specific positions indicated by the symbol position index. Thus, by exhaustively enumerating the logical flip possibilities of these positions, a set of candidate correction sequences for subsequent decoding processing is generated.
[0043] Step S206: Based on the set of trial sequences and the hard decision sequence of symbol soft information sequence, candidate codewords are determined.
[0044] In this embodiment, the hard decision sequence is the binary sequence obtained after performing hard decision on the received soft information sequence. The candidate codeword can be the codeword that the decoder outputs after successfully decoding the modified hard decision sequence by inputting it into the hard decision decoder.
[0045] In this embodiment, the method utilizes a set of trial sequences generated from the low-reliability symbol positions determined by reliability ranking, combined with the hard decision result of the received signal, to generate a corrected sequence for decoding. Specifically, by performing a modulo-2 addition operation on each trial sequence and the hard decision sequence, a series of corrected hard decision sequences are obtained, and these corrected sequences are input one by one into the RS(15,9) hard decision decoder for decoding. This process aims to approximate the performance of maximum likelihood decoding with a limited number of trial corrections, and finally select a specific set of candidate codewords from the successful decoding results, providing basic data for subsequent soft distance measurement and final selection.
[0046] Step S208: Determine the correlation metric value between each candidate codeword and the symbol soft information sequence, and determine the decoding output based on the correlation metric value.
[0047] In this embodiment, the relevant metric can be an indicator used to evaluate the degree of matching between candidate codewords and the received soft sequence, wherein the codeword is mapped to ±1, multiplied by the soft information voltage value, and summed. The larger the value, the more likely the candidate codeword is to be the correct codeword.
[0048] In this embodiment, the correlation between multiple candidate codewords generated during the decoding process and the received symbol soft information sequence is evaluated. Specifically, the degree of matching or confidence between each candidate codeword and the symbol soft information sequence is quantified by calculating a correlation metric. Subsequently, based on the magnitude or order of the determined correlation metric, the optimal candidate codeword is selected and determined as the final decoding output, thereby completing the mapping process from soft information to the final hard decision codeword.
[0049] The technical solution of this embodiment first determines the symbol position index based on the received symbol soft information sequence. Then, based on the symbol position index, a set of trial sequences corresponding only to the flipped states of these index bits is generated, thereby narrowing the search range from the entire symbol space to specific local positions and directly reducing the number of trial sequences to be processed. Next, candidate codewords are determined based on the generated set of trial sequences and the hard decision sequence of the symbol soft information sequence. The correlation metric between each candidate codeword and the symbol soft information sequence is calculated, and finally, the decoding output is determined based on the correlation metric. This processing method, which generates trial sequences by locking key symbol positions and then filters the decoding output based on correlation metric, effectively avoids the situation in the traditional Chase decoding algorithm where the computational load increases exponentially with the number of symbols due to traversing all symbols. It significantly reduces the real-time processing computational load and power consumption of the terminal device, achieving the technical effect of improving decoding efficiency and optimizing terminal energy consumption.
[0050] Optionally, determining the symbol position index based on the received symbol soft information sequence includes: calculating the reliability of each symbol based on the received symbol soft information sequence; sorting each symbol in ascending order according to reliability; and selecting a set number of symbol positions with the lowest reliability as the symbol position index.
[0051] In this embodiment, the received soft information values representing the probability distribution of each symbol are quantified to determine the reliability of each symbol being correctly judged. For example, soft information values with smaller absolute values are considered to have low reliability. "Sorting the symbols in ascending order of reliability" means arranging all the calculated symbol reliability values from smallest to largest, so that the symbol with the worst reliability (i.e., the highest probability of error) is placed at the front. "Selecting a set number of symbol positions with the lowest reliability as symbol position indices" means extracting a set number of symbol positions from the head of the sorted sequence. These positions are determined as the target indices that need to be tested and flipped. Through this series of steps, the decoding process can accurately lock the symbol positions most likely to err. Only for these high-probability error symbols, a set of test sequences is generated for flipping and verification, rather than blindly traversing all symbol combinations. This significantly reduces unnecessary calculation steps while maintaining the original decoding framework, effectively reducing the real-time processing workload and power consumption of the terminal device, and improving error correction efficiency under resource-constrained conditions.
[0052] Optionally, the candidate codeword is determined based on the hard decision sequence of the set of trial sequences and the symbol soft information sequence, including: for each trial sequence, performing an XOR operation with the hard decision sequence of the received sequence to obtain a modified hard decision sequence; and inputting the modified hard decision sequence into a hard decision decoder for decoding to obtain the candidate codeword.
[0053] In this embodiment, by leveraging the logical characteristics of the XOR operation, the hard decision bits corresponding to the positions marked "1" in the trial sequence are precisely located and reversed, thereby constructing a corrected input sequence based on a specific error hypothesis. For example, if the trial sequence indicates that the 3rd and 5th bits may be flipped, the XOR operation will change the 0 in the 3rd and 5th bits of the hard decision sequence to 1 or the 1 to 0, while keeping the remaining bits unchanged, so that the corrected hard decision sequence can reflect the receiving state under this specific flipping mode. Subsequently, by using the feature of "inputting the corrected hard decision sequence into the hard decision decoder for decoding to obtain candidate codewords", the hard decision decoder is used to decode the targeted corrected sequence, directly generating a legal codeword that conforms to the current trial hypothesis, avoiding the exponential computational load caused by blind search in traditional Chase decoding. This implementation method, which combines XOR correction and hard decision decoding, enables the system to quickly generate multiple high-quality candidate codewords with lower computational complexity. Compared with the complex soft information iteration or full-space search in the prior art, it significantly reduces the computational load and power consumption of the terminal in real-time processing, while ensuring the accuracy of the decoded output.
[0054] Optionally, the decoding output can be determined based on relevant metrics, including: selecting the candidate codeword with the largest metric value among the relevant metrics as the decoding output.
[0055] Optionally, the hard-decision decoder is constructed and generated on the Galois field GF(2^4). The hard-decision decoder has 9 information symbols, a code length of 15 symbols, an error correction capability of 3, and a minimum distance of 7.
[0056] In this embodiment, the feature clarifies the specific algebraic structure and encoding parameters of the hard-decision decoder, namely, it is constructed on the Galois field GF(2^4), and the number of information symbols is set to 9, the code length to 15, the error correction capability to 3, and the minimum distance to 7, which specifically corresponds to the mathematical definition of RS(15,9) code. In actual operation, this constraint ensures that the logic of polynomial operations, synod calculations, and error position polynomial solutions within the decoder strictly follows the field operation rules of GF(2^4), making the "corrected hard decision" generated in the preceding steps... The sequence can be correctly mapped to the codeword space of the specific code length and trigger the corresponding error correction algorithm (such as the BM algorithm or the Euclidean algorithm) to locate up to 3 erroneous symbols, thereby outputting candidate codewords that conform to the RS(15,9) specification. Through this targeted parameter solidification, the scheme avoids decoding failure or resource waste caused by parameter mismatch in general decoders, significantly improves the processing accuracy and real-time performance of RS(15,9) code data in specific scenarios such as satellite communication, and achieves precise adaptation of hardware resources to specific channel coding requirements.
[0057] Optionally, the formula for determining the relevant metric is as follows:
[0058]
[0059] in, Map the codewords to ±1. This represents the j-th bit of the i-th candidate codeword. This represents the symbol voltage value at the j-th bit in the symbol soft information sequence.
[0060] Optionally, after inputting the modified hard decision sequence into the hard decision decoder for decoding, the method further includes: if the hard decision decoder fails to decode, discarding the corresponding candidate codeword.
[0061] In this embodiment, when the hard-decision decoder performs decoding logic on the corrected hard-decision sequence, if the internal verification mechanism (such as parity check or cyclic redundancy check) fails, it is determined that the sequence cannot be restored to a valid codeword structure. At this time, the system directly removes the invalid data generated by this operation and does not include it in the subsequent processing flow. This mechanism ensures that all candidate codewords entering the "determine relevant metric value" stage are valid results verified by the hard-decision decoder, avoiding interference with the calculation of relevant metric values based on soft information sequences due to erroneous sequences that have failed to be decoded, thereby improving the accuracy and reliability of the final decoded output.
[0062] For example, Figure 3 This is a schematic diagram of the system structure of a decoding method according to an embodiment of this application. The system structure for low-complexity Chase decoding adapted to RS(15,9) codes is as follows. Figure 3 As shown: Soft information processing module: receives symbol soft information (such as voltage value) output by the demodulator and calculates the reliability of each symbol; Reliability sorting module: sorts the reliability of 15 symbols and outputs the position indices of the 3 symbols with the lowest reliability; Probe sequence generator: generates 8 probe sequences based on the 3 symbol positions; Hard decision decoder: adds each probe sequence modulo 2 to the hard decision value of the received sequence to obtain a corrected sequence, and sends the corrected sequence to the hard decision decoder of RS(15,9) for decoding to obtain candidate codewords; Candidate codeword selector: calculates the soft distance between the candidate codeword and the received soft sequence, and selects the candidate codeword with the smallest soft distance as the final decoded output.
[0063] The implementation steps and calculation formulas for low-complexity Chase decoding adapted to RS(15,9) codes are as follows:
[0064] 1. Reliability Calculation and Ranking
[0065] Input received soft sequence ,in Symbolic voltage value;
[0066] Reliability of computational symbols: threshold V;
[0067] Sort by reliability in ascending order and obtain the three index positions pos1, pos2, and pos3 with the lowest reliability;
[0068] 2. Generate trial sequences
[0069] Define a set of trial sequences Each It is a 15-dimensional vector, with values of 0 or 1 only at the indices pos1, pos2, and pos3, and 0 for the rest; for example, All are 0. Only pos1 is 1. The three positions pos1, pos2, and pos3 are all 1;
[0070] 3. Hard decision decoding
[0071] For each Calculate the modified hard decision sequence: ,in It is a hard decision sequence; The hard-decision sequence is a binary sequence (vector) obtained by symbol decision from the soft sequence R_soft. For each symbol voltage value V_j, a decision is made according to the threshold V_threshold = 0V. If V_j > 0V, the corresponding bit in R_h is set to 1; otherwise, it is set to 0, resulting in a binary sequence R_h of length 15. The operator ⊕ used to calculate the corrected hard-decision sequence is the XOR operation, which represents a bitwise XOR operation between two vectors. A value of 0 indicates the vectors are the same, while a value of 1 indicates they are different. Input an RS(15,9) hard-decision decoder and decode to output candidate codewords. (Discard if it fails);
[0072] 4. Soft Distance Metrics and Selection
[0073] For each candidate codeword Calculate soft distance: ,in Map the codewords to ±1; select to make The largest candidate codeword is used as the final output.
[0074] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0075] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps in any of the above method embodiments.
[0076] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.
[0077] Figure 4 This is a structural block diagram of an electronic device according to an embodiment of this application, such as... Figure 4 As shown, embodiments of this application also provide an electronic device 400, including a processor 401 and a memory 402, wherein the memory 402 stores a computer program, and the processor 401 is configured to run the computer program to perform the steps in any of the above method embodiments.
[0078] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.
[0079] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.
[0080] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.
[0081] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.
[0082] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.
Claims
1. A decoding method, characterized in that, The method includes: The symbol position index is determined based on the received symbol soft information sequence; Based on the symbol position index, a set of trial sequences is generated, wherein each trial sequence in the set corresponds to a flip state of the symbol position index; Candidate codewords are determined based on the hard decision sequence of the set of trial sequences and the symbol soft information sequence; Determine the correlation metric between each candidate codeword and the symbol soft information sequence, and determine the decoding output based on the correlation metric.
2. The method according to claim 1, characterized in that, The determination of the symbol position index based on the received symbol soft information sequence includes: The reliability of each symbol is calculated based on the received symbol soft information sequence; The symbols are sorted in ascending order according to their reliability, and the positions of a set number of symbols with the lowest reliability are selected as the symbol position indices.
3. The method according to claim 1, characterized in that, The process of determining candidate codewords based on the hard decision sequence derived from the set of trial sequences and the symbol soft information sequence includes: For each of the aforementioned trial sequences, an XOR operation is performed between it and the hard decision sequence of the received sequence to obtain the modified hard decision sequence; The modified hard decision sequence is input into a hard decision decoder for decoding to obtain the candidate codeword.
4. The method according to claim 1, characterized in that, The step of determining the decoding output based on the relevant metric value includes: The candidate codeword with the largest value among the relevant metrics is selected as the decoding output.
5. The method according to claim 3, characterized in that, The hard-decision decoder is constructed and generated on the Galois domain GF(2^4). The hard-decision decoder has 9 information symbols, a code length of 15 symbols, an error correction capability of 3, and a minimum distance of 7.
6. The method according to claim 3, characterized in that, The formula for determining the relevant metric is as follows: in, Map the codewords to ±1. This represents the j-th bit of the i-th candidate codeword. This represents the symbol voltage value at the j-th bit in the symbol soft information sequence.
7. The method according to claim 3, characterized in that, After the modified hard-decision sequence is input into the hard-decision decoder for decoding, the process further includes: If the hard-decision decoder fails to decode, the corresponding candidate codeword is discarded.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 7.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 7.
10. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1 to 7.